1 /* 2 * Copyright (C) 2005 - 2014 Emulex 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation. The full GNU General 8 * Public License is included in this distribution in the file called COPYING. 9 * 10 * Contact Information: 11 * linux-drivers@emulex.com 12 * 13 * Emulex 14 * 3333 Susan Street 15 * Costa Mesa, CA 92626 16 */ 17 18 #ifndef BE_H 19 #define BE_H 20 21 #include <linux/pci.h> 22 #include <linux/etherdevice.h> 23 #include <linux/delay.h> 24 #include <net/tcp.h> 25 #include <net/ip.h> 26 #include <net/ipv6.h> 27 #include <linux/if_vlan.h> 28 #include <linux/workqueue.h> 29 #include <linux/interrupt.h> 30 #include <linux/firmware.h> 31 #include <linux/slab.h> 32 #include <linux/u64_stats_sync.h> 33 34 #include "be_hw.h" 35 #include "be_roce.h" 36 37 #define DRV_VER "10.4u" 38 #define DRV_NAME "be2net" 39 #define BE_NAME "Emulex BladeEngine2" 40 #define BE3_NAME "Emulex BladeEngine3" 41 #define OC_NAME "Emulex OneConnect" 42 #define OC_NAME_BE OC_NAME "(be3)" 43 #define OC_NAME_LANCER OC_NAME "(Lancer)" 44 #define OC_NAME_SH OC_NAME "(Skyhawk)" 45 #define DRV_DESC "Emulex OneConnect NIC Driver" 46 47 #define BE_VENDOR_ID 0x19a2 48 #define EMULEX_VENDOR_ID 0x10df 49 #define BE_DEVICE_ID1 0x211 50 #define BE_DEVICE_ID2 0x221 51 #define OC_DEVICE_ID1 0x700 /* Device Id for BE2 cards */ 52 #define OC_DEVICE_ID2 0x710 /* Device Id for BE3 cards */ 53 #define OC_DEVICE_ID3 0xe220 /* Device id for Lancer cards */ 54 #define OC_DEVICE_ID4 0xe228 /* Device id for VF in Lancer */ 55 #define OC_DEVICE_ID5 0x720 /* Device Id for Skyhawk cards */ 56 #define OC_DEVICE_ID6 0x728 /* Device id for VF in SkyHawk */ 57 #define OC_SUBSYS_DEVICE_ID1 0xE602 58 #define OC_SUBSYS_DEVICE_ID2 0xE642 59 #define OC_SUBSYS_DEVICE_ID3 0xE612 60 #define OC_SUBSYS_DEVICE_ID4 0xE652 61 62 /* Number of bytes of an RX frame that are copied to skb->data */ 63 #define BE_HDR_LEN ((u16) 64) 64 /* allocate extra space to allow tunneling decapsulation without head reallocation */ 65 #define BE_RX_SKB_ALLOC_SIZE (BE_HDR_LEN + 64) 66 67 #define BE_MAX_JUMBO_FRAME_SIZE 9018 68 #define BE_MIN_MTU 256 69 #define BE_MAX_MTU (BE_MAX_JUMBO_FRAME_SIZE - \ 70 (ETH_HLEN + ETH_FCS_LEN)) 71 72 #define BE_NUM_VLANS_SUPPORTED 64 73 #define BE_MAX_EQD 128u 74 #define BE_MAX_TX_FRAG_COUNT 30 75 76 #define EVNT_Q_LEN 1024 77 #define TX_Q_LEN 2048 78 #define TX_CQ_LEN 1024 79 #define RX_Q_LEN 1024 /* Does not support any other value */ 80 #define RX_CQ_LEN 1024 81 #define MCC_Q_LEN 128 /* total size not to exceed 8 pages */ 82 #define MCC_CQ_LEN 256 83 84 #define BE2_MAX_RSS_QS 4 85 #define BE3_MAX_RSS_QS 16 86 #define BE3_MAX_TX_QS 16 87 #define BE3_MAX_EVT_QS 16 88 #define BE3_SRIOV_MAX_EVT_QS 8 89 90 #define MAX_RSS_IFACES 15 91 #define MAX_RX_QS 32 92 #define MAX_EVT_QS 32 93 #define MAX_TX_QS 32 94 95 #define MAX_ROCE_EQS 5 96 #define MAX_MSIX_VECTORS 32 97 #define MIN_MSIX_VECTORS 1 98 #define BE_NAPI_WEIGHT 64 99 #define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */ 100 #define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST) 101 102 #define MAX_VFS 30 /* Max VFs supported by BE3 FW */ 103 #define FW_VER_LEN 32 104 105 #define RSS_INDIR_TABLE_LEN 128 106 #define RSS_HASH_KEY_LEN 40 107 108 struct be_dma_mem { 109 void *va; 110 dma_addr_t dma; 111 u32 size; 112 }; 113 114 struct be_queue_info { 115 struct be_dma_mem dma_mem; 116 u16 len; 117 u16 entry_size; /* Size of an element in the queue */ 118 u16 id; 119 u16 tail, head; 120 bool created; 121 atomic_t used; /* Number of valid elements in the queue */ 122 }; 123 124 static inline u32 MODULO(u16 val, u16 limit) 125 { 126 BUG_ON(limit & (limit - 1)); 127 return val & (limit - 1); 128 } 129 130 static inline void index_adv(u16 *index, u16 val, u16 limit) 131 { 132 *index = MODULO((*index + val), limit); 133 } 134 135 static inline void index_inc(u16 *index, u16 limit) 136 { 137 *index = MODULO((*index + 1), limit); 138 } 139 140 static inline void *queue_head_node(struct be_queue_info *q) 141 { 142 return q->dma_mem.va + q->head * q->entry_size; 143 } 144 145 static inline void *queue_tail_node(struct be_queue_info *q) 146 { 147 return q->dma_mem.va + q->tail * q->entry_size; 148 } 149 150 static inline void *queue_index_node(struct be_queue_info *q, u16 index) 151 { 152 return q->dma_mem.va + index * q->entry_size; 153 } 154 155 static inline void queue_head_inc(struct be_queue_info *q) 156 { 157 index_inc(&q->head, q->len); 158 } 159 160 static inline void index_dec(u16 *index, u16 limit) 161 { 162 *index = MODULO((*index - 1), limit); 163 } 164 165 static inline void queue_tail_inc(struct be_queue_info *q) 166 { 167 index_inc(&q->tail, q->len); 168 } 169 170 struct be_eq_obj { 171 struct be_queue_info q; 172 char desc[32]; 173 174 /* Adaptive interrupt coalescing (AIC) info */ 175 bool enable_aic; 176 u32 min_eqd; /* in usecs */ 177 u32 max_eqd; /* in usecs */ 178 u32 eqd; /* configured val when aic is off */ 179 u32 cur_eqd; /* in usecs */ 180 181 u8 idx; /* array index */ 182 u8 msix_idx; 183 u16 spurious_intr; 184 struct napi_struct napi; 185 struct be_adapter *adapter; 186 187 #ifdef CONFIG_NET_RX_BUSY_POLL 188 #define BE_EQ_IDLE 0 189 #define BE_EQ_NAPI 1 /* napi owns this EQ */ 190 #define BE_EQ_POLL 2 /* poll owns this EQ */ 191 #define BE_EQ_LOCKED (BE_EQ_NAPI | BE_EQ_POLL) 192 #define BE_EQ_NAPI_YIELD 4 /* napi yielded this EQ */ 193 #define BE_EQ_POLL_YIELD 8 /* poll yielded this EQ */ 194 #define BE_EQ_YIELD (BE_EQ_NAPI_YIELD | BE_EQ_POLL_YIELD) 195 #define BE_EQ_USER_PEND (BE_EQ_POLL | BE_EQ_POLL_YIELD) 196 unsigned int state; 197 spinlock_t lock; /* lock to serialize napi and busy-poll */ 198 #endif /* CONFIG_NET_RX_BUSY_POLL */ 199 } ____cacheline_aligned_in_smp; 200 201 struct be_aic_obj { /* Adaptive interrupt coalescing (AIC) info */ 202 bool enable; 203 u32 min_eqd; /* in usecs */ 204 u32 max_eqd; /* in usecs */ 205 u32 prev_eqd; /* in usecs */ 206 u32 et_eqd; /* configured val when aic is off */ 207 ulong jiffies; 208 u64 rx_pkts_prev; /* Used to calculate RX pps */ 209 u64 tx_reqs_prev; /* Used to calculate TX pps */ 210 }; 211 212 enum { 213 NAPI_POLLING, 214 BUSY_POLLING 215 }; 216 217 struct be_mcc_obj { 218 struct be_queue_info q; 219 struct be_queue_info cq; 220 bool rearm_cq; 221 }; 222 223 struct be_tx_stats { 224 u64 tx_bytes; 225 u64 tx_pkts; 226 u64 tx_reqs; 227 u64 tx_compl; 228 ulong tx_jiffies; 229 u32 tx_stops; 230 u32 tx_drv_drops; /* pkts dropped by driver */ 231 /* the error counters are described in be_ethtool.c */ 232 u32 tx_hdr_parse_err; 233 u32 tx_dma_err; 234 u32 tx_tso_err; 235 u32 tx_spoof_check_err; 236 u32 tx_qinq_err; 237 u32 tx_internal_parity_err; 238 struct u64_stats_sync sync; 239 struct u64_stats_sync sync_compl; 240 }; 241 242 /* Structure to hold some data of interest obtained from a TX CQE */ 243 struct be_tx_compl_info { 244 u8 status; /* Completion status */ 245 u16 end_index; /* Completed TXQ Index */ 246 }; 247 248 struct be_tx_obj { 249 u32 db_offset; 250 struct be_queue_info q; 251 struct be_queue_info cq; 252 struct be_tx_compl_info txcp; 253 /* Remember the skbs that were transmitted */ 254 struct sk_buff *sent_skb_list[TX_Q_LEN]; 255 struct be_tx_stats stats; 256 u16 pend_wrb_cnt; /* Number of WRBs yet to be given to HW */ 257 u16 last_req_wrb_cnt; /* wrb cnt of the last req in the Q */ 258 u16 last_req_hdr; /* index of the last req's hdr-wrb */ 259 } ____cacheline_aligned_in_smp; 260 261 /* Struct to remember the pages posted for rx frags */ 262 struct be_rx_page_info { 263 struct page *page; 264 /* set to page-addr for last frag of the page & frag-addr otherwise */ 265 DEFINE_DMA_UNMAP_ADDR(bus); 266 u16 page_offset; 267 bool last_frag; /* last frag of the page */ 268 }; 269 270 struct be_rx_stats { 271 u64 rx_bytes; 272 u64 rx_pkts; 273 u32 rx_drops_no_skbs; /* skb allocation errors */ 274 u32 rx_drops_no_frags; /* HW has no fetched frags */ 275 u32 rx_post_fail; /* page post alloc failures */ 276 u32 rx_compl; 277 u32 rx_mcast_pkts; 278 u32 rx_compl_err; /* completions with err set */ 279 struct u64_stats_sync sync; 280 }; 281 282 struct be_rx_compl_info { 283 u32 rss_hash; 284 u16 vlan_tag; 285 u16 pkt_size; 286 u16 port; 287 u8 vlanf; 288 u8 num_rcvd; 289 u8 err; 290 u8 ipf; 291 u8 tcpf; 292 u8 udpf; 293 u8 ip_csum; 294 u8 l4_csum; 295 u8 ipv6; 296 u8 qnq; 297 u8 pkt_type; 298 u8 ip_frag; 299 u8 tunneled; 300 }; 301 302 struct be_rx_obj { 303 struct be_adapter *adapter; 304 struct be_queue_info q; 305 struct be_queue_info cq; 306 struct be_rx_compl_info rxcp; 307 struct be_rx_page_info page_info_tbl[RX_Q_LEN]; 308 struct be_rx_stats stats; 309 u8 rss_id; 310 bool rx_post_starved; /* Zero rx frags have been posted to BE */ 311 } ____cacheline_aligned_in_smp; 312 313 struct be_drv_stats { 314 u32 be_on_die_temperature; 315 u32 eth_red_drops; 316 u32 dma_map_errors; 317 u32 rx_drops_no_pbuf; 318 u32 rx_drops_no_txpb; 319 u32 rx_drops_no_erx_descr; 320 u32 rx_drops_no_tpre_descr; 321 u32 rx_drops_too_many_frags; 322 u32 forwarded_packets; 323 u32 rx_drops_mtu; 324 u32 rx_crc_errors; 325 u32 rx_alignment_symbol_errors; 326 u32 rx_pause_frames; 327 u32 rx_priority_pause_frames; 328 u32 rx_control_frames; 329 u32 rx_in_range_errors; 330 u32 rx_out_range_errors; 331 u32 rx_frame_too_long; 332 u32 rx_address_filtered; 333 u32 rx_dropped_too_small; 334 u32 rx_dropped_too_short; 335 u32 rx_dropped_header_too_small; 336 u32 rx_dropped_tcp_length; 337 u32 rx_dropped_runt; 338 u32 rx_ip_checksum_errs; 339 u32 rx_tcp_checksum_errs; 340 u32 rx_udp_checksum_errs; 341 u32 tx_pauseframes; 342 u32 tx_priority_pauseframes; 343 u32 tx_controlframes; 344 u32 rxpp_fifo_overflow_drop; 345 u32 rx_input_fifo_overflow_drop; 346 u32 pmem_fifo_overflow_drop; 347 u32 jabber_events; 348 u32 rx_roce_bytes_lsd; 349 u32 rx_roce_bytes_msd; 350 u32 rx_roce_frames; 351 u32 roce_drops_payload_len; 352 u32 roce_drops_crc; 353 }; 354 355 /* A vlan-id of 0xFFFF must be used to clear transparent vlan-tagging */ 356 #define BE_RESET_VLAN_TAG_ID 0xFFFF 357 358 struct be_vf_cfg { 359 unsigned char mac_addr[ETH_ALEN]; 360 int if_handle; 361 int pmac_id; 362 u16 vlan_tag; 363 u32 tx_rate; 364 u32 plink_tracking; 365 }; 366 367 enum vf_state { 368 ENABLED = 0, 369 ASSIGNED = 1 370 }; 371 372 #define BE_FLAGS_LINK_STATUS_INIT BIT(1) 373 #define BE_FLAGS_SRIOV_ENABLED BIT(2) 374 #define BE_FLAGS_WORKER_SCHEDULED BIT(3) 375 #define BE_FLAGS_NAPI_ENABLED BIT(6) 376 #define BE_FLAGS_QNQ_ASYNC_EVT_RCVD BIT(7) 377 #define BE_FLAGS_VXLAN_OFFLOADS BIT(8) 378 #define BE_FLAGS_SETUP_DONE BIT(9) 379 #define BE_FLAGS_EVT_INCOMPATIBLE_SFP BIT(10) 380 #define BE_FLAGS_ERR_DETECTION_SCHEDULED BIT(11) 381 382 #define BE_UC_PMAC_COUNT 30 383 #define BE_VF_UC_PMAC_COUNT 2 384 385 /* Ethtool set_dump flags */ 386 #define LANCER_INITIATE_FW_DUMP 0x1 387 #define LANCER_DELETE_FW_DUMP 0x2 388 389 struct phy_info { 390 /* From SFF-8472 spec */ 391 #define SFP_VENDOR_NAME_LEN 17 392 u8 transceiver; 393 u8 autoneg; 394 u8 fc_autoneg; 395 u8 port_type; 396 u16 phy_type; 397 u16 interface_type; 398 u32 misc_params; 399 u16 auto_speeds_supported; 400 u16 fixed_speeds_supported; 401 int link_speed; 402 u32 advertising; 403 u32 supported; 404 u8 cable_type; 405 u8 vendor_name[SFP_VENDOR_NAME_LEN]; 406 u8 vendor_pn[SFP_VENDOR_NAME_LEN]; 407 }; 408 409 struct be_resources { 410 u16 max_vfs; /* Total VFs "really" supported by FW/HW */ 411 u16 max_mcast_mac; 412 u16 max_tx_qs; 413 u16 max_rss_qs; 414 u16 max_rx_qs; 415 u16 max_cq_count; 416 u16 max_uc_mac; /* Max UC MACs programmable */ 417 u16 max_vlans; /* Number of vlans supported */ 418 u16 max_iface_count; 419 u16 max_mcc_count; 420 u16 max_evt_qs; 421 u32 if_cap_flags; 422 u32 vf_if_cap_flags; /* VF if capability flags */ 423 }; 424 425 struct rss_info { 426 u64 rss_flags; 427 u8 rsstable[RSS_INDIR_TABLE_LEN]; 428 u8 rss_queue[RSS_INDIR_TABLE_LEN]; 429 u8 rss_hkey[RSS_HASH_KEY_LEN]; 430 }; 431 432 /* Macros to read/write the 'features' word of be_wrb_params structure. 433 */ 434 #define BE_WRB_F_BIT(name) BE_WRB_F_##name##_BIT 435 #define BE_WRB_F_MASK(name) BIT_MASK(BE_WRB_F_##name##_BIT) 436 437 #define BE_WRB_F_GET(word, name) \ 438 (((word) & (BE_WRB_F_MASK(name))) >> BE_WRB_F_BIT(name)) 439 440 #define BE_WRB_F_SET(word, name, val) \ 441 ((word) |= (((val) << BE_WRB_F_BIT(name)) & BE_WRB_F_MASK(name))) 442 443 /* Feature/offload bits */ 444 enum { 445 BE_WRB_F_CRC_BIT, /* Ethernet CRC */ 446 BE_WRB_F_IPCS_BIT, /* IP csum */ 447 BE_WRB_F_TCPCS_BIT, /* TCP csum */ 448 BE_WRB_F_UDPCS_BIT, /* UDP csum */ 449 BE_WRB_F_LSO_BIT, /* LSO */ 450 BE_WRB_F_LSO6_BIT, /* LSO6 */ 451 BE_WRB_F_VLAN_BIT, /* VLAN */ 452 BE_WRB_F_VLAN_SKIP_HW_BIT /* Skip VLAN tag (workaround) */ 453 }; 454 455 /* The structure below provides a HW-agnostic abstraction of WRB params 456 * retrieved from a TX skb. This is in turn passed to chip specific routines 457 * during transmit, to set the corresponding params in the WRB. 458 */ 459 struct be_wrb_params { 460 u32 features; /* Feature bits */ 461 u16 vlan_tag; /* VLAN tag */ 462 u16 lso_mss; /* MSS for LSO */ 463 }; 464 465 struct be_adapter { 466 struct pci_dev *pdev; 467 struct net_device *netdev; 468 469 u8 __iomem *csr; /* CSR BAR used only for BE2/3 */ 470 u8 __iomem *db; /* Door Bell */ 471 472 struct mutex mbox_lock; /* For serializing mbox cmds to BE card */ 473 struct be_dma_mem mbox_mem; 474 /* Mbox mem is adjusted to align to 16 bytes. The allocated addr 475 * is stored for freeing purpose */ 476 struct be_dma_mem mbox_mem_alloced; 477 478 struct be_mcc_obj mcc_obj; 479 spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */ 480 spinlock_t mcc_cq_lock; 481 482 u16 cfg_num_qs; /* configured via set-channels */ 483 u16 num_evt_qs; 484 u16 num_msix_vec; 485 struct be_eq_obj eq_obj[MAX_EVT_QS]; 486 struct msix_entry msix_entries[MAX_MSIX_VECTORS]; 487 bool isr_registered; 488 489 /* TX Rings */ 490 u16 num_tx_qs; 491 struct be_tx_obj tx_obj[MAX_TX_QS]; 492 493 /* Rx rings */ 494 u16 num_rx_qs; 495 u16 num_rss_qs; 496 u16 need_def_rxq; 497 struct be_rx_obj rx_obj[MAX_RX_QS]; 498 u32 big_page_size; /* Compounded page size shared by rx wrbs */ 499 500 struct be_drv_stats drv_stats; 501 struct be_aic_obj aic_obj[MAX_EVT_QS]; 502 u8 vlan_prio_bmap; /* Available Priority BitMap */ 503 u16 recommended_prio; /* Recommended Priority */ 504 struct be_dma_mem rx_filter; /* Cmd DMA mem for rx-filter */ 505 506 struct be_dma_mem stats_cmd; 507 /* Work queue used to perform periodic tasks like getting statistics */ 508 struct delayed_work work; 509 u16 work_counter; 510 511 struct delayed_work be_err_detection_work; 512 u32 flags; 513 u32 cmd_privileges; 514 /* Ethtool knobs and info */ 515 char fw_ver[FW_VER_LEN]; 516 char fw_on_flash[FW_VER_LEN]; 517 518 /* IFACE filtering fields */ 519 int if_handle; /* Used to configure filtering */ 520 u32 if_flags; /* Interface filtering flags */ 521 u32 *pmac_id; /* MAC addr handle used by BE card */ 522 u32 uc_macs; /* Count of secondary UC MAC programmed */ 523 unsigned long vids[BITS_TO_LONGS(VLAN_N_VID)]; 524 u16 vlans_added; 525 526 u32 beacon_state; /* for set_phys_id */ 527 528 bool eeh_error; 529 bool fw_timeout; 530 bool hw_error; 531 532 u32 port_num; 533 char port_name; 534 u8 mc_type; 535 u32 function_mode; 536 u32 function_caps; 537 u32 rx_fc; /* Rx flow control */ 538 u32 tx_fc; /* Tx flow control */ 539 bool stats_cmd_sent; 540 struct { 541 u32 size; 542 u32 total_size; 543 u64 io_addr; 544 } roce_db; 545 u32 num_msix_roce_vec; 546 struct ocrdma_dev *ocrdma_dev; 547 struct list_head entry; 548 549 u32 flash_status; 550 struct completion et_cmd_compl; 551 552 struct be_resources pool_res; /* resources available for the port */ 553 struct be_resources res; /* resources available for the func */ 554 u16 num_vfs; /* Number of VFs provisioned by PF */ 555 u8 virtfn; 556 struct be_vf_cfg *vf_cfg; 557 bool be3_native; 558 u32 sli_family; 559 u8 hba_port_num; 560 u16 pvid; 561 __be16 vxlan_port; 562 int vxlan_port_count; 563 struct phy_info phy; 564 u8 wol_cap; 565 bool wol_en; 566 u16 asic_rev; 567 u16 qnq_vid; 568 u32 msg_enable; 569 int be_get_temp_freq; 570 u8 pf_number; 571 struct rss_info rss_info; 572 }; 573 574 #define be_physfn(adapter) (!adapter->virtfn) 575 #define be_virtfn(adapter) (adapter->virtfn) 576 #define sriov_enabled(adapter) (adapter->flags & \ 577 BE_FLAGS_SRIOV_ENABLED) 578 579 #define for_all_vfs(adapter, vf_cfg, i) \ 580 for (i = 0, vf_cfg = &adapter->vf_cfg[i]; i < adapter->num_vfs; \ 581 i++, vf_cfg++) 582 583 #define ON 1 584 #define OFF 0 585 586 #define be_max_vlans(adapter) (adapter->res.max_vlans) 587 #define be_max_uc(adapter) (adapter->res.max_uc_mac) 588 #define be_max_mc(adapter) (adapter->res.max_mcast_mac) 589 #define be_max_vfs(adapter) (adapter->pool_res.max_vfs) 590 #define be_max_rss(adapter) (adapter->res.max_rss_qs) 591 #define be_max_txqs(adapter) (adapter->res.max_tx_qs) 592 #define be_max_prio_txqs(adapter) (adapter->res.max_prio_tx_qs) 593 #define be_max_rxqs(adapter) (adapter->res.max_rx_qs) 594 #define be_max_eqs(adapter) (adapter->res.max_evt_qs) 595 #define be_if_cap_flags(adapter) (adapter->res.if_cap_flags) 596 597 static inline u16 be_max_qs(struct be_adapter *adapter) 598 { 599 /* If no RSS, need atleast the one def RXQ */ 600 u16 num = max_t(u16, be_max_rss(adapter), 1); 601 602 num = min(num, be_max_eqs(adapter)); 603 return min_t(u16, num, num_online_cpus()); 604 } 605 606 /* Is BE in pvid_tagging mode */ 607 #define be_pvid_tagging_enabled(adapter) (adapter->pvid) 608 609 /* Is BE in QNQ multi-channel mode */ 610 #define be_is_qnq_mode(adapter) (adapter->function_mode & QNQ_MODE) 611 612 #define lancer_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID3 || \ 613 adapter->pdev->device == OC_DEVICE_ID4) 614 615 #define skyhawk_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID5 || \ 616 adapter->pdev->device == OC_DEVICE_ID6) 617 618 #define BE3_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID2 || \ 619 adapter->pdev->device == OC_DEVICE_ID2) 620 621 #define BE2_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID1 || \ 622 adapter->pdev->device == OC_DEVICE_ID1) 623 624 #define BEx_chip(adapter) (BE3_chip(adapter) || BE2_chip(adapter)) 625 626 #define be_roce_supported(adapter) (skyhawk_chip(adapter) && \ 627 (adapter->function_mode & RDMA_ENABLED)) 628 629 extern const struct ethtool_ops be_ethtool_ops; 630 631 #define msix_enabled(adapter) (adapter->num_msix_vec > 0) 632 #define num_irqs(adapter) (msix_enabled(adapter) ? \ 633 adapter->num_msix_vec : 1) 634 #define tx_stats(txo) (&(txo)->stats) 635 #define rx_stats(rxo) (&(rxo)->stats) 636 637 /* The default RXQ is the last RXQ */ 638 #define default_rxo(adpt) (&adpt->rx_obj[adpt->num_rx_qs - 1]) 639 640 #define for_all_rx_queues(adapter, rxo, i) \ 641 for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \ 642 i++, rxo++) 643 644 #define for_all_rss_queues(adapter, rxo, i) \ 645 for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rss_qs; \ 646 i++, rxo++) 647 648 #define for_all_tx_queues(adapter, txo, i) \ 649 for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs; \ 650 i++, txo++) 651 652 #define for_all_evt_queues(adapter, eqo, i) \ 653 for (i = 0, eqo = &adapter->eq_obj[i]; i < adapter->num_evt_qs; \ 654 i++, eqo++) 655 656 #define for_all_rx_queues_on_eq(adapter, eqo, rxo, i) \ 657 for (i = eqo->idx, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs;\ 658 i += adapter->num_evt_qs, rxo += adapter->num_evt_qs) 659 660 #define for_all_tx_queues_on_eq(adapter, eqo, txo, i) \ 661 for (i = eqo->idx, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs;\ 662 i += adapter->num_evt_qs, txo += adapter->num_evt_qs) 663 664 #define is_mcc_eqo(eqo) (eqo->idx == 0) 665 #define mcc_eqo(adapter) (&adapter->eq_obj[0]) 666 667 #define PAGE_SHIFT_4K 12 668 #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K) 669 670 /* Returns number of pages spanned by the data starting at the given addr */ 671 #define PAGES_4K_SPANNED(_address, size) \ 672 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \ 673 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K)) 674 675 /* Returns bit offset within a DWORD of a bitfield */ 676 #define AMAP_BIT_OFFSET(_struct, field) \ 677 (((size_t)&(((_struct *)0)->field))%32) 678 679 /* Returns the bit mask of the field that is NOT shifted into location. */ 680 static inline u32 amap_mask(u32 bitsize) 681 { 682 return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1); 683 } 684 685 static inline void 686 amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value) 687 { 688 u32 *dw = (u32 *) ptr + dw_offset; 689 *dw &= ~(mask << offset); 690 *dw |= (mask & value) << offset; 691 } 692 693 #define AMAP_SET_BITS(_struct, field, ptr, val) \ 694 amap_set(ptr, \ 695 offsetof(_struct, field)/32, \ 696 amap_mask(sizeof(((_struct *)0)->field)), \ 697 AMAP_BIT_OFFSET(_struct, field), \ 698 val) 699 700 static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset) 701 { 702 u32 *dw = (u32 *) ptr; 703 return mask & (*(dw + dw_offset) >> offset); 704 } 705 706 #define AMAP_GET_BITS(_struct, field, ptr) \ 707 amap_get(ptr, \ 708 offsetof(_struct, field)/32, \ 709 amap_mask(sizeof(((_struct *)0)->field)), \ 710 AMAP_BIT_OFFSET(_struct, field)) 711 712 #define GET_RX_COMPL_V0_BITS(field, ptr) \ 713 AMAP_GET_BITS(struct amap_eth_rx_compl_v0, field, ptr) 714 715 #define GET_RX_COMPL_V1_BITS(field, ptr) \ 716 AMAP_GET_BITS(struct amap_eth_rx_compl_v1, field, ptr) 717 718 #define GET_TX_COMPL_BITS(field, ptr) \ 719 AMAP_GET_BITS(struct amap_eth_tx_compl, field, ptr) 720 721 #define SET_TX_WRB_HDR_BITS(field, ptr, val) \ 722 AMAP_SET_BITS(struct amap_eth_hdr_wrb, field, ptr, val) 723 724 #define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len) 725 #define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len) 726 static inline void swap_dws(void *wrb, int len) 727 { 728 #ifdef __BIG_ENDIAN 729 u32 *dw = wrb; 730 BUG_ON(len % 4); 731 do { 732 *dw = cpu_to_le32(*dw); 733 dw++; 734 len -= 4; 735 } while (len); 736 #endif /* __BIG_ENDIAN */ 737 } 738 739 #define be_cmd_status(status) (status > 0 ? -EIO : status) 740 741 static inline u8 is_tcp_pkt(struct sk_buff *skb) 742 { 743 u8 val = 0; 744 745 if (ip_hdr(skb)->version == 4) 746 val = (ip_hdr(skb)->protocol == IPPROTO_TCP); 747 else if (ip_hdr(skb)->version == 6) 748 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP); 749 750 return val; 751 } 752 753 static inline u8 is_udp_pkt(struct sk_buff *skb) 754 { 755 u8 val = 0; 756 757 if (ip_hdr(skb)->version == 4) 758 val = (ip_hdr(skb)->protocol == IPPROTO_UDP); 759 else if (ip_hdr(skb)->version == 6) 760 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP); 761 762 return val; 763 } 764 765 static inline bool is_ipv4_pkt(struct sk_buff *skb) 766 { 767 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 768 } 769 770 static inline bool be_multi_rxq(const struct be_adapter *adapter) 771 { 772 return adapter->num_rx_qs > 1; 773 } 774 775 static inline bool be_error(struct be_adapter *adapter) 776 { 777 return adapter->eeh_error || adapter->hw_error || adapter->fw_timeout; 778 } 779 780 static inline bool be_hw_error(struct be_adapter *adapter) 781 { 782 return adapter->eeh_error || adapter->hw_error; 783 } 784 785 static inline void be_clear_all_error(struct be_adapter *adapter) 786 { 787 adapter->eeh_error = false; 788 adapter->hw_error = false; 789 adapter->fw_timeout = false; 790 } 791 792 void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, 793 u16 num_popped); 794 void be_link_status_update(struct be_adapter *adapter, u8 link_status); 795 void be_parse_stats(struct be_adapter *adapter); 796 int be_load_fw(struct be_adapter *adapter, u8 *func); 797 bool be_is_wol_supported(struct be_adapter *adapter); 798 bool be_pause_supported(struct be_adapter *adapter); 799 u32 be_get_fw_log_level(struct be_adapter *adapter); 800 int be_update_queues(struct be_adapter *adapter); 801 int be_poll(struct napi_struct *napi, int budget); 802 803 /* 804 * internal function to initialize-cleanup roce device. 805 */ 806 void be_roce_dev_add(struct be_adapter *); 807 void be_roce_dev_remove(struct be_adapter *); 808 809 /* 810 * internal function to open-close roce device during ifup-ifdown. 811 */ 812 void be_roce_dev_open(struct be_adapter *); 813 void be_roce_dev_close(struct be_adapter *); 814 void be_roce_dev_shutdown(struct be_adapter *); 815 816 #endif /* BE_H */ 817