1 /* 2 * Copyright (C) 2005 - 2015 Emulex 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation. The full GNU General 8 * Public License is included in this distribution in the file called COPYING. 9 * 10 * Contact Information: 11 * linux-drivers@emulex.com 12 * 13 * Emulex 14 * 3333 Susan Street 15 * Costa Mesa, CA 92626 16 */ 17 18 #ifndef BE_H 19 #define BE_H 20 21 #include <linux/pci.h> 22 #include <linux/etherdevice.h> 23 #include <linux/delay.h> 24 #include <net/tcp.h> 25 #include <net/ip.h> 26 #include <net/ipv6.h> 27 #include <linux/if_vlan.h> 28 #include <linux/workqueue.h> 29 #include <linux/interrupt.h> 30 #include <linux/firmware.h> 31 #include <linux/slab.h> 32 #include <linux/u64_stats_sync.h> 33 #include <linux/cpumask.h> 34 #include <linux/hwmon.h> 35 #include <linux/hwmon-sysfs.h> 36 37 #include "be_hw.h" 38 #include "be_roce.h" 39 40 #define DRV_VER "10.6.0.3" 41 #define DRV_NAME "be2net" 42 #define BE_NAME "Emulex BladeEngine2" 43 #define BE3_NAME "Emulex BladeEngine3" 44 #define OC_NAME "Emulex OneConnect" 45 #define OC_NAME_BE OC_NAME "(be3)" 46 #define OC_NAME_LANCER OC_NAME "(Lancer)" 47 #define OC_NAME_SH OC_NAME "(Skyhawk)" 48 #define DRV_DESC "Emulex OneConnect NIC Driver" 49 50 #define BE_VENDOR_ID 0x19a2 51 #define EMULEX_VENDOR_ID 0x10df 52 #define BE_DEVICE_ID1 0x211 53 #define BE_DEVICE_ID2 0x221 54 #define OC_DEVICE_ID1 0x700 /* Device Id for BE2 cards */ 55 #define OC_DEVICE_ID2 0x710 /* Device Id for BE3 cards */ 56 #define OC_DEVICE_ID3 0xe220 /* Device id for Lancer cards */ 57 #define OC_DEVICE_ID4 0xe228 /* Device id for VF in Lancer */ 58 #define OC_DEVICE_ID5 0x720 /* Device Id for Skyhawk cards */ 59 #define OC_DEVICE_ID6 0x728 /* Device id for VF in SkyHawk */ 60 #define OC_SUBSYS_DEVICE_ID1 0xE602 61 #define OC_SUBSYS_DEVICE_ID2 0xE642 62 #define OC_SUBSYS_DEVICE_ID3 0xE612 63 #define OC_SUBSYS_DEVICE_ID4 0xE652 64 65 /* Number of bytes of an RX frame that are copied to skb->data */ 66 #define BE_HDR_LEN ((u16) 64) 67 /* allocate extra space to allow tunneling decapsulation without head reallocation */ 68 #define BE_RX_SKB_ALLOC_SIZE (BE_HDR_LEN + 64) 69 70 #define BE_MAX_JUMBO_FRAME_SIZE 9018 71 #define BE_MIN_MTU 256 72 #define BE_MAX_MTU (BE_MAX_JUMBO_FRAME_SIZE - \ 73 (ETH_HLEN + ETH_FCS_LEN)) 74 75 #define BE_NUM_VLANS_SUPPORTED 64 76 #define BE_MAX_EQD 128u 77 #define BE_MAX_TX_FRAG_COUNT 30 78 79 #define EVNT_Q_LEN 1024 80 #define TX_Q_LEN 2048 81 #define TX_CQ_LEN 1024 82 #define RX_Q_LEN 1024 /* Does not support any other value */ 83 #define RX_CQ_LEN 1024 84 #define MCC_Q_LEN 128 /* total size not to exceed 8 pages */ 85 #define MCC_CQ_LEN 256 86 87 #define BE2_MAX_RSS_QS 4 88 #define BE3_MAX_RSS_QS 16 89 #define BE3_MAX_TX_QS 16 90 #define BE3_MAX_EVT_QS 16 91 #define BE3_SRIOV_MAX_EVT_QS 8 92 93 #define MAX_RSS_IFACES 15 94 #define MAX_RX_QS 32 95 #define MAX_EVT_QS 32 96 #define MAX_TX_QS 32 97 98 #define MAX_ROCE_EQS 5 99 #define MAX_MSIX_VECTORS 32 100 #define MIN_MSIX_VECTORS 1 101 #define BE_NAPI_WEIGHT 64 102 #define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */ 103 #define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST) 104 #define MAX_NUM_POST_ERX_DB 255u 105 106 #define MAX_VFS 30 /* Max VFs supported by BE3 FW */ 107 #define FW_VER_LEN 32 108 #define CNTL_SERIAL_NUM_WORDS 8 /* Controller serial number words */ 109 #define CNTL_SERIAL_NUM_WORD_SZ (sizeof(u16)) /* Byte-sz of serial num word */ 110 111 #define RSS_INDIR_TABLE_LEN 128 112 #define RSS_HASH_KEY_LEN 40 113 114 struct be_dma_mem { 115 void *va; 116 dma_addr_t dma; 117 u32 size; 118 }; 119 120 struct be_queue_info { 121 struct be_dma_mem dma_mem; 122 u16 len; 123 u16 entry_size; /* Size of an element in the queue */ 124 u16 id; 125 u16 tail, head; 126 bool created; 127 atomic_t used; /* Number of valid elements in the queue */ 128 }; 129 130 static inline u32 MODULO(u16 val, u16 limit) 131 { 132 BUG_ON(limit & (limit - 1)); 133 return val & (limit - 1); 134 } 135 136 static inline void index_adv(u16 *index, u16 val, u16 limit) 137 { 138 *index = MODULO((*index + val), limit); 139 } 140 141 static inline void index_inc(u16 *index, u16 limit) 142 { 143 *index = MODULO((*index + 1), limit); 144 } 145 146 static inline void *queue_head_node(struct be_queue_info *q) 147 { 148 return q->dma_mem.va + q->head * q->entry_size; 149 } 150 151 static inline void *queue_tail_node(struct be_queue_info *q) 152 { 153 return q->dma_mem.va + q->tail * q->entry_size; 154 } 155 156 static inline void *queue_index_node(struct be_queue_info *q, u16 index) 157 { 158 return q->dma_mem.va + index * q->entry_size; 159 } 160 161 static inline void queue_head_inc(struct be_queue_info *q) 162 { 163 index_inc(&q->head, q->len); 164 } 165 166 static inline void index_dec(u16 *index, u16 limit) 167 { 168 *index = MODULO((*index - 1), limit); 169 } 170 171 static inline void queue_tail_inc(struct be_queue_info *q) 172 { 173 index_inc(&q->tail, q->len); 174 } 175 176 struct be_eq_obj { 177 struct be_queue_info q; 178 char desc[32]; 179 180 /* Adaptive interrupt coalescing (AIC) info */ 181 bool enable_aic; 182 u32 min_eqd; /* in usecs */ 183 u32 max_eqd; /* in usecs */ 184 u32 eqd; /* configured val when aic is off */ 185 u32 cur_eqd; /* in usecs */ 186 187 u8 idx; /* array index */ 188 u8 msix_idx; 189 u16 spurious_intr; 190 struct napi_struct napi; 191 struct be_adapter *adapter; 192 cpumask_var_t affinity_mask; 193 194 #ifdef CONFIG_NET_RX_BUSY_POLL 195 #define BE_EQ_IDLE 0 196 #define BE_EQ_NAPI 1 /* napi owns this EQ */ 197 #define BE_EQ_POLL 2 /* poll owns this EQ */ 198 #define BE_EQ_LOCKED (BE_EQ_NAPI | BE_EQ_POLL) 199 #define BE_EQ_NAPI_YIELD 4 /* napi yielded this EQ */ 200 #define BE_EQ_POLL_YIELD 8 /* poll yielded this EQ */ 201 #define BE_EQ_YIELD (BE_EQ_NAPI_YIELD | BE_EQ_POLL_YIELD) 202 #define BE_EQ_USER_PEND (BE_EQ_POLL | BE_EQ_POLL_YIELD) 203 unsigned int state; 204 spinlock_t lock; /* lock to serialize napi and busy-poll */ 205 #endif /* CONFIG_NET_RX_BUSY_POLL */ 206 } ____cacheline_aligned_in_smp; 207 208 struct be_aic_obj { /* Adaptive interrupt coalescing (AIC) info */ 209 bool enable; 210 u32 min_eqd; /* in usecs */ 211 u32 max_eqd; /* in usecs */ 212 u32 prev_eqd; /* in usecs */ 213 u32 et_eqd; /* configured val when aic is off */ 214 ulong jiffies; 215 u64 rx_pkts_prev; /* Used to calculate RX pps */ 216 u64 tx_reqs_prev; /* Used to calculate TX pps */ 217 }; 218 219 enum { 220 NAPI_POLLING, 221 BUSY_POLLING 222 }; 223 224 struct be_mcc_obj { 225 struct be_queue_info q; 226 struct be_queue_info cq; 227 bool rearm_cq; 228 }; 229 230 struct be_tx_stats { 231 u64 tx_bytes; 232 u64 tx_pkts; 233 u64 tx_vxlan_offload_pkts; 234 u64 tx_reqs; 235 u64 tx_compl; 236 ulong tx_jiffies; 237 u32 tx_stops; 238 u32 tx_drv_drops; /* pkts dropped by driver */ 239 /* the error counters are described in be_ethtool.c */ 240 u32 tx_hdr_parse_err; 241 u32 tx_dma_err; 242 u32 tx_tso_err; 243 u32 tx_spoof_check_err; 244 u32 tx_qinq_err; 245 u32 tx_internal_parity_err; 246 struct u64_stats_sync sync; 247 struct u64_stats_sync sync_compl; 248 }; 249 250 /* Structure to hold some data of interest obtained from a TX CQE */ 251 struct be_tx_compl_info { 252 u8 status; /* Completion status */ 253 u16 end_index; /* Completed TXQ Index */ 254 }; 255 256 struct be_tx_obj { 257 u32 db_offset; 258 struct be_queue_info q; 259 struct be_queue_info cq; 260 struct be_tx_compl_info txcp; 261 /* Remember the skbs that were transmitted */ 262 struct sk_buff *sent_skb_list[TX_Q_LEN]; 263 struct be_tx_stats stats; 264 u16 pend_wrb_cnt; /* Number of WRBs yet to be given to HW */ 265 u16 last_req_wrb_cnt; /* wrb cnt of the last req in the Q */ 266 u16 last_req_hdr; /* index of the last req's hdr-wrb */ 267 } ____cacheline_aligned_in_smp; 268 269 /* Struct to remember the pages posted for rx frags */ 270 struct be_rx_page_info { 271 struct page *page; 272 /* set to page-addr for last frag of the page & frag-addr otherwise */ 273 DEFINE_DMA_UNMAP_ADDR(bus); 274 u16 page_offset; 275 bool last_frag; /* last frag of the page */ 276 }; 277 278 struct be_rx_stats { 279 u64 rx_bytes; 280 u64 rx_pkts; 281 u64 rx_vxlan_offload_pkts; 282 u32 rx_drops_no_skbs; /* skb allocation errors */ 283 u32 rx_drops_no_frags; /* HW has no fetched frags */ 284 u32 rx_post_fail; /* page post alloc failures */ 285 u32 rx_compl; 286 u32 rx_mcast_pkts; 287 u32 rx_compl_err; /* completions with err set */ 288 struct u64_stats_sync sync; 289 }; 290 291 struct be_rx_compl_info { 292 u32 rss_hash; 293 u16 vlan_tag; 294 u16 pkt_size; 295 u16 port; 296 u8 vlanf; 297 u8 num_rcvd; 298 u8 err; 299 u8 ipf; 300 u8 tcpf; 301 u8 udpf; 302 u8 ip_csum; 303 u8 l4_csum; 304 u8 ipv6; 305 u8 qnq; 306 u8 pkt_type; 307 u8 ip_frag; 308 u8 tunneled; 309 }; 310 311 struct be_rx_obj { 312 struct be_adapter *adapter; 313 struct be_queue_info q; 314 struct be_queue_info cq; 315 struct be_rx_compl_info rxcp; 316 struct be_rx_page_info page_info_tbl[RX_Q_LEN]; 317 struct be_rx_stats stats; 318 u8 rss_id; 319 bool rx_post_starved; /* Zero rx frags have been posted to BE */ 320 } ____cacheline_aligned_in_smp; 321 322 struct be_drv_stats { 323 u32 eth_red_drops; 324 u32 dma_map_errors; 325 u32 rx_drops_no_pbuf; 326 u32 rx_drops_no_txpb; 327 u32 rx_drops_no_erx_descr; 328 u32 rx_drops_no_tpre_descr; 329 u32 rx_drops_too_many_frags; 330 u32 forwarded_packets; 331 u32 rx_drops_mtu; 332 u32 rx_crc_errors; 333 u32 rx_alignment_symbol_errors; 334 u32 rx_pause_frames; 335 u32 rx_priority_pause_frames; 336 u32 rx_control_frames; 337 u32 rx_in_range_errors; 338 u32 rx_out_range_errors; 339 u32 rx_frame_too_long; 340 u32 rx_address_filtered; 341 u32 rx_dropped_too_small; 342 u32 rx_dropped_too_short; 343 u32 rx_dropped_header_too_small; 344 u32 rx_dropped_tcp_length; 345 u32 rx_dropped_runt; 346 u32 rx_ip_checksum_errs; 347 u32 rx_tcp_checksum_errs; 348 u32 rx_udp_checksum_errs; 349 u32 tx_pauseframes; 350 u32 tx_priority_pauseframes; 351 u32 tx_controlframes; 352 u32 rxpp_fifo_overflow_drop; 353 u32 rx_input_fifo_overflow_drop; 354 u32 pmem_fifo_overflow_drop; 355 u32 jabber_events; 356 u32 rx_roce_bytes_lsd; 357 u32 rx_roce_bytes_msd; 358 u32 rx_roce_frames; 359 u32 roce_drops_payload_len; 360 u32 roce_drops_crc; 361 }; 362 363 /* A vlan-id of 0xFFFF must be used to clear transparent vlan-tagging */ 364 #define BE_RESET_VLAN_TAG_ID 0xFFFF 365 366 struct be_vf_cfg { 367 unsigned char mac_addr[ETH_ALEN]; 368 int if_handle; 369 int pmac_id; 370 u16 vlan_tag; 371 u32 tx_rate; 372 u32 plink_tracking; 373 u32 privileges; 374 bool spoofchk; 375 }; 376 377 enum vf_state { 378 ENABLED = 0, 379 ASSIGNED = 1 380 }; 381 382 #define BE_FLAGS_LINK_STATUS_INIT BIT(1) 383 #define BE_FLAGS_SRIOV_ENABLED BIT(2) 384 #define BE_FLAGS_WORKER_SCHEDULED BIT(3) 385 #define BE_FLAGS_NAPI_ENABLED BIT(6) 386 #define BE_FLAGS_QNQ_ASYNC_EVT_RCVD BIT(7) 387 #define BE_FLAGS_VXLAN_OFFLOADS BIT(8) 388 #define BE_FLAGS_SETUP_DONE BIT(9) 389 #define BE_FLAGS_EVT_INCOMPATIBLE_SFP BIT(10) 390 #define BE_FLAGS_ERR_DETECTION_SCHEDULED BIT(11) 391 #define BE_FLAGS_OS2BMC BIT(12) 392 393 #define BE_UC_PMAC_COUNT 30 394 #define BE_VF_UC_PMAC_COUNT 2 395 396 /* Ethtool set_dump flags */ 397 #define LANCER_INITIATE_FW_DUMP 0x1 398 #define LANCER_DELETE_FW_DUMP 0x2 399 400 struct phy_info { 401 /* From SFF-8472 spec */ 402 #define SFP_VENDOR_NAME_LEN 17 403 u8 transceiver; 404 u8 autoneg; 405 u8 fc_autoneg; 406 u8 port_type; 407 u16 phy_type; 408 u16 interface_type; 409 u32 misc_params; 410 u16 auto_speeds_supported; 411 u16 fixed_speeds_supported; 412 int link_speed; 413 u32 advertising; 414 u32 supported; 415 u8 cable_type; 416 u8 vendor_name[SFP_VENDOR_NAME_LEN]; 417 u8 vendor_pn[SFP_VENDOR_NAME_LEN]; 418 }; 419 420 struct be_resources { 421 u16 max_vfs; /* Total VFs "really" supported by FW/HW */ 422 u16 max_mcast_mac; 423 u16 max_tx_qs; 424 u16 max_rss_qs; 425 u16 max_rx_qs; 426 u16 max_cq_count; 427 u16 max_uc_mac; /* Max UC MACs programmable */ 428 u16 max_vlans; /* Number of vlans supported */ 429 u16 max_iface_count; 430 u16 max_mcc_count; 431 u16 max_evt_qs; 432 u32 if_cap_flags; 433 u32 vf_if_cap_flags; /* VF if capability flags */ 434 }; 435 436 #define be_is_os2bmc_enabled(adapter) (adapter->flags & BE_FLAGS_OS2BMC) 437 438 struct rss_info { 439 u64 rss_flags; 440 u8 rsstable[RSS_INDIR_TABLE_LEN]; 441 u8 rss_queue[RSS_INDIR_TABLE_LEN]; 442 u8 rss_hkey[RSS_HASH_KEY_LEN]; 443 }; 444 445 #define BE_INVALID_DIE_TEMP 0xFF 446 struct be_hwmon { 447 struct device *hwmon_dev; 448 u8 be_on_die_temp; /* Unit: millidegree Celsius */ 449 }; 450 451 /* Macros to read/write the 'features' word of be_wrb_params structure. 452 */ 453 #define BE_WRB_F_BIT(name) BE_WRB_F_##name##_BIT 454 #define BE_WRB_F_MASK(name) BIT_MASK(BE_WRB_F_##name##_BIT) 455 456 #define BE_WRB_F_GET(word, name) \ 457 (((word) & (BE_WRB_F_MASK(name))) >> BE_WRB_F_BIT(name)) 458 459 #define BE_WRB_F_SET(word, name, val) \ 460 ((word) |= (((val) << BE_WRB_F_BIT(name)) & BE_WRB_F_MASK(name))) 461 462 /* Feature/offload bits */ 463 enum { 464 BE_WRB_F_CRC_BIT, /* Ethernet CRC */ 465 BE_WRB_F_IPCS_BIT, /* IP csum */ 466 BE_WRB_F_TCPCS_BIT, /* TCP csum */ 467 BE_WRB_F_UDPCS_BIT, /* UDP csum */ 468 BE_WRB_F_LSO_BIT, /* LSO */ 469 BE_WRB_F_LSO6_BIT, /* LSO6 */ 470 BE_WRB_F_VLAN_BIT, /* VLAN */ 471 BE_WRB_F_VLAN_SKIP_HW_BIT, /* Skip VLAN tag (workaround) */ 472 BE_WRB_F_OS2BMC_BIT /* Send packet to the management ring */ 473 }; 474 475 /* The structure below provides a HW-agnostic abstraction of WRB params 476 * retrieved from a TX skb. This is in turn passed to chip specific routines 477 * during transmit, to set the corresponding params in the WRB. 478 */ 479 struct be_wrb_params { 480 u32 features; /* Feature bits */ 481 u16 vlan_tag; /* VLAN tag */ 482 u16 lso_mss; /* MSS for LSO */ 483 }; 484 485 struct be_adapter { 486 struct pci_dev *pdev; 487 struct net_device *netdev; 488 489 u8 __iomem *csr; /* CSR BAR used only for BE2/3 */ 490 u8 __iomem *db; /* Door Bell */ 491 u8 __iomem *pcicfg; /* On SH,BEx only. Shadow of PCI config space */ 492 493 struct mutex mbox_lock; /* For serializing mbox cmds to BE card */ 494 struct be_dma_mem mbox_mem; 495 /* Mbox mem is adjusted to align to 16 bytes. The allocated addr 496 * is stored for freeing purpose */ 497 struct be_dma_mem mbox_mem_alloced; 498 499 struct be_mcc_obj mcc_obj; 500 spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */ 501 spinlock_t mcc_cq_lock; 502 503 u16 cfg_num_qs; /* configured via set-channels */ 504 u16 num_evt_qs; 505 u16 num_msix_vec; 506 struct be_eq_obj eq_obj[MAX_EVT_QS]; 507 struct msix_entry msix_entries[MAX_MSIX_VECTORS]; 508 bool isr_registered; 509 510 /* TX Rings */ 511 u16 num_tx_qs; 512 struct be_tx_obj tx_obj[MAX_TX_QS]; 513 514 /* Rx rings */ 515 u16 num_rx_qs; 516 u16 num_rss_qs; 517 u16 need_def_rxq; 518 struct be_rx_obj rx_obj[MAX_RX_QS]; 519 u32 big_page_size; /* Compounded page size shared by rx wrbs */ 520 521 struct be_drv_stats drv_stats; 522 struct be_aic_obj aic_obj[MAX_EVT_QS]; 523 u8 vlan_prio_bmap; /* Available Priority BitMap */ 524 u16 recommended_prio; /* Recommended Priority */ 525 struct be_dma_mem rx_filter; /* Cmd DMA mem for rx-filter */ 526 527 struct be_dma_mem stats_cmd; 528 /* Work queue used to perform periodic tasks like getting statistics */ 529 struct delayed_work work; 530 u16 work_counter; 531 532 struct delayed_work be_err_detection_work; 533 u8 err_flags; 534 u32 flags; 535 u32 cmd_privileges; 536 /* Ethtool knobs and info */ 537 char fw_ver[FW_VER_LEN]; 538 char fw_on_flash[FW_VER_LEN]; 539 540 /* IFACE filtering fields */ 541 int if_handle; /* Used to configure filtering */ 542 u32 if_flags; /* Interface filtering flags */ 543 u32 *pmac_id; /* MAC addr handle used by BE card */ 544 u32 uc_macs; /* Count of secondary UC MAC programmed */ 545 unsigned long vids[BITS_TO_LONGS(VLAN_N_VID)]; 546 u16 vlans_added; 547 548 u32 beacon_state; /* for set_phys_id */ 549 550 bool eeh_error; 551 bool fw_timeout; 552 bool hw_error; 553 554 u32 port_num; 555 char port_name; 556 u8 mc_type; 557 u32 function_mode; 558 u32 function_caps; 559 u32 rx_fc; /* Rx flow control */ 560 u32 tx_fc; /* Tx flow control */ 561 bool stats_cmd_sent; 562 struct { 563 u32 size; 564 u32 total_size; 565 u64 io_addr; 566 } roce_db; 567 u32 num_msix_roce_vec; 568 struct ocrdma_dev *ocrdma_dev; 569 struct list_head entry; 570 571 u32 flash_status; 572 struct completion et_cmd_compl; 573 574 struct be_resources pool_res; /* resources available for the port */ 575 struct be_resources res; /* resources available for the func */ 576 u16 num_vfs; /* Number of VFs provisioned by PF */ 577 u8 virtfn; 578 struct be_vf_cfg *vf_cfg; 579 bool be3_native; 580 u32 sli_family; 581 u8 hba_port_num; 582 u16 pvid; 583 __be16 vxlan_port; 584 int vxlan_port_count; 585 int vxlan_port_aliases; 586 struct phy_info phy; 587 u8 wol_cap; 588 bool wol_en; 589 u16 asic_rev; 590 u16 qnq_vid; 591 u32 msg_enable; 592 int be_get_temp_freq; 593 struct be_hwmon hwmon_info; 594 u8 pf_number; 595 u8 pci_func_num; 596 struct rss_info rss_info; 597 /* Filters for packets that need to be sent to BMC */ 598 u32 bmc_filt_mask; 599 u16 serial_num[CNTL_SERIAL_NUM_WORDS]; 600 }; 601 602 #define be_physfn(adapter) (!adapter->virtfn) 603 #define be_virtfn(adapter) (adapter->virtfn) 604 #define sriov_enabled(adapter) (adapter->flags & \ 605 BE_FLAGS_SRIOV_ENABLED) 606 607 #define for_all_vfs(adapter, vf_cfg, i) \ 608 for (i = 0, vf_cfg = &adapter->vf_cfg[i]; i < adapter->num_vfs; \ 609 i++, vf_cfg++) 610 611 #define ON 1 612 #define OFF 0 613 614 #define be_max_vlans(adapter) (adapter->res.max_vlans) 615 #define be_max_uc(adapter) (adapter->res.max_uc_mac) 616 #define be_max_mc(adapter) (adapter->res.max_mcast_mac) 617 #define be_max_vfs(adapter) (adapter->pool_res.max_vfs) 618 #define be_max_rss(adapter) (adapter->res.max_rss_qs) 619 #define be_max_txqs(adapter) (adapter->res.max_tx_qs) 620 #define be_max_prio_txqs(adapter) (adapter->res.max_prio_tx_qs) 621 #define be_max_rxqs(adapter) (adapter->res.max_rx_qs) 622 #define be_max_eqs(adapter) (adapter->res.max_evt_qs) 623 #define be_if_cap_flags(adapter) (adapter->res.if_cap_flags) 624 625 static inline u16 be_max_qs(struct be_adapter *adapter) 626 { 627 /* If no RSS, need atleast the one def RXQ */ 628 u16 num = max_t(u16, be_max_rss(adapter), 1); 629 630 num = min(num, be_max_eqs(adapter)); 631 return min_t(u16, num, num_online_cpus()); 632 } 633 634 /* Is BE in pvid_tagging mode */ 635 #define be_pvid_tagging_enabled(adapter) (adapter->pvid) 636 637 /* Is BE in QNQ multi-channel mode */ 638 #define be_is_qnq_mode(adapter) (adapter->function_mode & QNQ_MODE) 639 640 #define lancer_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID3 || \ 641 adapter->pdev->device == OC_DEVICE_ID4) 642 643 #define skyhawk_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID5 || \ 644 adapter->pdev->device == OC_DEVICE_ID6) 645 646 #define BE3_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID2 || \ 647 adapter->pdev->device == OC_DEVICE_ID2) 648 649 #define BE2_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID1 || \ 650 adapter->pdev->device == OC_DEVICE_ID1) 651 652 #define BEx_chip(adapter) (BE3_chip(adapter) || BE2_chip(adapter)) 653 654 #define be_roce_supported(adapter) (skyhawk_chip(adapter) && \ 655 (adapter->function_mode & RDMA_ENABLED)) 656 657 extern const struct ethtool_ops be_ethtool_ops; 658 659 #define msix_enabled(adapter) (adapter->num_msix_vec > 0) 660 #define num_irqs(adapter) (msix_enabled(adapter) ? \ 661 adapter->num_msix_vec : 1) 662 #define tx_stats(txo) (&(txo)->stats) 663 #define rx_stats(rxo) (&(rxo)->stats) 664 665 /* The default RXQ is the last RXQ */ 666 #define default_rxo(adpt) (&adpt->rx_obj[adpt->num_rx_qs - 1]) 667 668 #define for_all_rx_queues(adapter, rxo, i) \ 669 for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \ 670 i++, rxo++) 671 672 #define for_all_rss_queues(adapter, rxo, i) \ 673 for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rss_qs; \ 674 i++, rxo++) 675 676 #define for_all_tx_queues(adapter, txo, i) \ 677 for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs; \ 678 i++, txo++) 679 680 #define for_all_evt_queues(adapter, eqo, i) \ 681 for (i = 0, eqo = &adapter->eq_obj[i]; i < adapter->num_evt_qs; \ 682 i++, eqo++) 683 684 #define for_all_rx_queues_on_eq(adapter, eqo, rxo, i) \ 685 for (i = eqo->idx, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs;\ 686 i += adapter->num_evt_qs, rxo += adapter->num_evt_qs) 687 688 #define for_all_tx_queues_on_eq(adapter, eqo, txo, i) \ 689 for (i = eqo->idx, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs;\ 690 i += adapter->num_evt_qs, txo += adapter->num_evt_qs) 691 692 #define is_mcc_eqo(eqo) (eqo->idx == 0) 693 #define mcc_eqo(adapter) (&adapter->eq_obj[0]) 694 695 #define PAGE_SHIFT_4K 12 696 #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K) 697 698 /* Returns number of pages spanned by the data starting at the given addr */ 699 #define PAGES_4K_SPANNED(_address, size) \ 700 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \ 701 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K)) 702 703 /* Returns bit offset within a DWORD of a bitfield */ 704 #define AMAP_BIT_OFFSET(_struct, field) \ 705 (((size_t)&(((_struct *)0)->field))%32) 706 707 /* Returns the bit mask of the field that is NOT shifted into location. */ 708 static inline u32 amap_mask(u32 bitsize) 709 { 710 return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1); 711 } 712 713 static inline void 714 amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value) 715 { 716 u32 *dw = (u32 *) ptr + dw_offset; 717 *dw &= ~(mask << offset); 718 *dw |= (mask & value) << offset; 719 } 720 721 #define AMAP_SET_BITS(_struct, field, ptr, val) \ 722 amap_set(ptr, \ 723 offsetof(_struct, field)/32, \ 724 amap_mask(sizeof(((_struct *)0)->field)), \ 725 AMAP_BIT_OFFSET(_struct, field), \ 726 val) 727 728 static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset) 729 { 730 u32 *dw = (u32 *) ptr; 731 return mask & (*(dw + dw_offset) >> offset); 732 } 733 734 #define AMAP_GET_BITS(_struct, field, ptr) \ 735 amap_get(ptr, \ 736 offsetof(_struct, field)/32, \ 737 amap_mask(sizeof(((_struct *)0)->field)), \ 738 AMAP_BIT_OFFSET(_struct, field)) 739 740 #define GET_RX_COMPL_V0_BITS(field, ptr) \ 741 AMAP_GET_BITS(struct amap_eth_rx_compl_v0, field, ptr) 742 743 #define GET_RX_COMPL_V1_BITS(field, ptr) \ 744 AMAP_GET_BITS(struct amap_eth_rx_compl_v1, field, ptr) 745 746 #define GET_TX_COMPL_BITS(field, ptr) \ 747 AMAP_GET_BITS(struct amap_eth_tx_compl, field, ptr) 748 749 #define SET_TX_WRB_HDR_BITS(field, ptr, val) \ 750 AMAP_SET_BITS(struct amap_eth_hdr_wrb, field, ptr, val) 751 752 #define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len) 753 #define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len) 754 static inline void swap_dws(void *wrb, int len) 755 { 756 #ifdef __BIG_ENDIAN 757 u32 *dw = wrb; 758 BUG_ON(len % 4); 759 do { 760 *dw = cpu_to_le32(*dw); 761 dw++; 762 len -= 4; 763 } while (len); 764 #endif /* __BIG_ENDIAN */ 765 } 766 767 #define be_cmd_status(status) (status > 0 ? -EIO : status) 768 769 static inline u8 is_tcp_pkt(struct sk_buff *skb) 770 { 771 u8 val = 0; 772 773 if (ip_hdr(skb)->version == 4) 774 val = (ip_hdr(skb)->protocol == IPPROTO_TCP); 775 else if (ip_hdr(skb)->version == 6) 776 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP); 777 778 return val; 779 } 780 781 static inline u8 is_udp_pkt(struct sk_buff *skb) 782 { 783 u8 val = 0; 784 785 if (ip_hdr(skb)->version == 4) 786 val = (ip_hdr(skb)->protocol == IPPROTO_UDP); 787 else if (ip_hdr(skb)->version == 6) 788 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP); 789 790 return val; 791 } 792 793 static inline bool is_ipv4_pkt(struct sk_buff *skb) 794 { 795 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 796 } 797 798 #define BE_ERROR_EEH 1 799 #define BE_ERROR_UE BIT(1) 800 #define BE_ERROR_FW BIT(2) 801 #define BE_ERROR_HW (BE_ERROR_EEH | BE_ERROR_UE) 802 #define BE_ERROR_ANY (BE_ERROR_EEH | BE_ERROR_UE | BE_ERROR_FW) 803 #define BE_CLEAR_ALL 0xFF 804 805 static inline u8 be_check_error(struct be_adapter *adapter, u32 err_type) 806 { 807 return (adapter->err_flags & err_type); 808 } 809 810 static inline void be_set_error(struct be_adapter *adapter, int err_type) 811 { 812 struct net_device *netdev = adapter->netdev; 813 814 adapter->err_flags |= err_type; 815 netif_carrier_off(netdev); 816 817 dev_info(&adapter->pdev->dev, "%s: Link down\n", netdev->name); 818 } 819 820 static inline void be_clear_error(struct be_adapter *adapter, int err_type) 821 { 822 adapter->err_flags &= ~err_type; 823 } 824 825 static inline bool be_multi_rxq(const struct be_adapter *adapter) 826 { 827 return adapter->num_rx_qs > 1; 828 } 829 830 void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, 831 u16 num_popped); 832 void be_link_status_update(struct be_adapter *adapter, u8 link_status); 833 void be_parse_stats(struct be_adapter *adapter); 834 int be_load_fw(struct be_adapter *adapter, u8 *func); 835 bool be_is_wol_supported(struct be_adapter *adapter); 836 bool be_pause_supported(struct be_adapter *adapter); 837 u32 be_get_fw_log_level(struct be_adapter *adapter); 838 int be_update_queues(struct be_adapter *adapter); 839 int be_poll(struct napi_struct *napi, int budget); 840 void be_eqd_update(struct be_adapter *adapter, bool force_update); 841 842 /* 843 * internal function to initialize-cleanup roce device. 844 */ 845 void be_roce_dev_add(struct be_adapter *); 846 void be_roce_dev_remove(struct be_adapter *); 847 848 /* 849 * internal function to open-close roce device during ifup-ifdown. 850 */ 851 void be_roce_dev_open(struct be_adapter *); 852 void be_roce_dev_close(struct be_adapter *); 853 void be_roce_dev_shutdown(struct be_adapter *); 854 855 #endif /* BE_H */ 856