19aebddd1SJeff Kirsher /*
27dfbe7d7SSomnath Kotur  * Copyright (C) 2005 - 2016 Broadcom
39aebddd1SJeff Kirsher  * All rights reserved.
49aebddd1SJeff Kirsher  *
59aebddd1SJeff Kirsher  * This program is free software; you can redistribute it and/or
69aebddd1SJeff Kirsher  * modify it under the terms of the GNU General Public License version 2
79aebddd1SJeff Kirsher  * as published by the Free Software Foundation.  The full GNU General
89aebddd1SJeff Kirsher  * Public License is included in this distribution in the file called COPYING.
99aebddd1SJeff Kirsher  *
109aebddd1SJeff Kirsher  * Contact Information:
119aebddd1SJeff Kirsher  * linux-drivers@emulex.com
129aebddd1SJeff Kirsher  *
139aebddd1SJeff Kirsher  * Emulex
149aebddd1SJeff Kirsher  * 3333 Susan Street
159aebddd1SJeff Kirsher  * Costa Mesa, CA 92626
169aebddd1SJeff Kirsher  */
179aebddd1SJeff Kirsher 
189aebddd1SJeff Kirsher #ifndef BE_H
199aebddd1SJeff Kirsher #define BE_H
209aebddd1SJeff Kirsher 
219aebddd1SJeff Kirsher #include <linux/pci.h>
229aebddd1SJeff Kirsher #include <linux/etherdevice.h>
239aebddd1SJeff Kirsher #include <linux/delay.h>
249aebddd1SJeff Kirsher #include <net/tcp.h>
259aebddd1SJeff Kirsher #include <net/ip.h>
269aebddd1SJeff Kirsher #include <net/ipv6.h>
279aebddd1SJeff Kirsher #include <linux/if_vlan.h>
289aebddd1SJeff Kirsher #include <linux/workqueue.h>
299aebddd1SJeff Kirsher #include <linux/interrupt.h>
309aebddd1SJeff Kirsher #include <linux/firmware.h>
319aebddd1SJeff Kirsher #include <linux/slab.h>
329aebddd1SJeff Kirsher #include <linux/u64_stats_sync.h>
33d658d98aSPadmanabh Ratnakar #include <linux/cpumask.h>
3429e9122bSVenkata Duvvuru #include <linux/hwmon.h>
3529e9122bSVenkata Duvvuru #include <linux/hwmon-sysfs.h>
369aebddd1SJeff Kirsher 
379aebddd1SJeff Kirsher #include "be_hw.h"
38045508a8SParav Pandit #include "be_roce.h"
399aebddd1SJeff Kirsher 
40aab0830aSSuresh Reddy #define DRV_VER			"11.4.0.0"
419aebddd1SJeff Kirsher #define DRV_NAME		"be2net"
4200d3d51eSSarveshwar Bandi #define BE_NAME			"Emulex BladeEngine2"
4300d3d51eSSarveshwar Bandi #define BE3_NAME		"Emulex BladeEngine3"
4400d3d51eSSarveshwar Bandi #define OC_NAME			"Emulex OneConnect"
459aebddd1SJeff Kirsher #define OC_NAME_BE		OC_NAME	"(be3)"
469aebddd1SJeff Kirsher #define OC_NAME_LANCER		OC_NAME "(Lancer)"
47ecedb6aeSAjit Khaparde #define OC_NAME_SH		OC_NAME "(Skyhawk)"
48f3effb45SSuresh Reddy #define DRV_DESC		"Emulex OneConnect NIC Driver"
499aebddd1SJeff Kirsher 
509aebddd1SJeff Kirsher #define BE_VENDOR_ID 		0x19a2
519aebddd1SJeff Kirsher #define EMULEX_VENDOR_ID	0x10df
529aebddd1SJeff Kirsher #define BE_DEVICE_ID1		0x211
539aebddd1SJeff Kirsher #define BE_DEVICE_ID2		0x221
549aebddd1SJeff Kirsher #define OC_DEVICE_ID1		0x700	/* Device Id for BE2 cards */
559aebddd1SJeff Kirsher #define OC_DEVICE_ID2		0x710	/* Device Id for BE3 cards */
569aebddd1SJeff Kirsher #define OC_DEVICE_ID3		0xe220	/* Device id for Lancer cards */
579aebddd1SJeff Kirsher #define OC_DEVICE_ID4           0xe228   /* Device id for VF in Lancer */
58ecedb6aeSAjit Khaparde #define OC_DEVICE_ID5		0x720	/* Device Id for Skyhawk cards */
5976b73530SPadmanabh Ratnakar #define OC_DEVICE_ID6		0x728   /* Device id for VF in SkyHawk */
604762f6ceSAjit Khaparde #define OC_SUBSYS_DEVICE_ID1	0xE602
614762f6ceSAjit Khaparde #define OC_SUBSYS_DEVICE_ID2	0xE642
624762f6ceSAjit Khaparde #define OC_SUBSYS_DEVICE_ID3	0xE612
634762f6ceSAjit Khaparde #define OC_SUBSYS_DEVICE_ID4	0xE652
649aebddd1SJeff Kirsher 
659aebddd1SJeff Kirsher /* Number of bytes of an RX frame that are copied to skb->data */
669aebddd1SJeff Kirsher #define BE_HDR_LEN		((u16) 64)
67bb349bb4SEric Dumazet /* allocate extra space to allow tunneling decapsulation without head reallocation */
6876b15923SKalesh A P #define BE_RX_SKB_ALLOC_SIZE	256
69bb349bb4SEric Dumazet 
709aebddd1SJeff Kirsher #define BE_MAX_JUMBO_FRAME_SIZE	9018
719aebddd1SJeff Kirsher #define BE_MIN_MTU		256
720d3f5cceSKalesh AP #define BE_MAX_MTU              (BE_MAX_JUMBO_FRAME_SIZE -	\
730d3f5cceSKalesh AP 				 (ETH_HLEN + ETH_FCS_LEN))
749aebddd1SJeff Kirsher 
75127bfce5Sajit.khaparde@broadcom.com /* Accommodate for QnQ configurations where VLAN insertion is enabled in HW */
76127bfce5Sajit.khaparde@broadcom.com #define BE_MAX_GSO_SIZE		(65535 - 2 * VLAN_HLEN)
77127bfce5Sajit.khaparde@broadcom.com 
789aebddd1SJeff Kirsher #define BE_NUM_VLANS_SUPPORTED	64
792632bafdSSathya Perla #define BE_MAX_EQD		128u
809aebddd1SJeff Kirsher #define	BE_MAX_TX_FRAG_COUNT	30
819aebddd1SJeff Kirsher 
829aebddd1SJeff Kirsher #define EVNT_Q_LEN		1024
839aebddd1SJeff Kirsher #define TX_Q_LEN		2048
849aebddd1SJeff Kirsher #define TX_CQ_LEN		1024
859aebddd1SJeff Kirsher #define RX_Q_LEN		1024	/* Does not support any other value */
869aebddd1SJeff Kirsher #define RX_CQ_LEN		1024
879aebddd1SJeff Kirsher #define MCC_Q_LEN		128	/* total size not to exceed 8 pages */
889aebddd1SJeff Kirsher #define MCC_CQ_LEN		256
899aebddd1SJeff Kirsher 
9010ef9ab4SSathya Perla #define BE2_MAX_RSS_QS		4
9168d7bdcbSSathya Perla #define BE3_MAX_RSS_QS		16
9268d7bdcbSSathya Perla #define BE3_MAX_TX_QS		16
9368d7bdcbSSathya Perla #define BE3_MAX_EVT_QS		16
94e3dc867cSSuresh Reddy #define BE3_SRIOV_MAX_EVT_QS	8
95ee9ad280SSriharsha Basavapatna #define SH_VF_MAX_NIC_EQS	3	/* Skyhawk VFs can have a max of 4 EQs
96ee9ad280SSriharsha Basavapatna 					 * and at least 1 is granted to either
97ee9ad280SSriharsha Basavapatna 					 * SURF/DPDK
98ee9ad280SSriharsha Basavapatna 					 */
9910ef9ab4SSathya Perla 
100de2b1e03SSomnath Kotur #define MAX_PORT_RSS_TABLES	15
101de2b1e03SSomnath Kotur #define MAX_NIC_FUNCS		16
10268d7bdcbSSathya Perla #define MAX_RX_QS		32
10368d7bdcbSSathya Perla #define MAX_EVT_QS		32
10468d7bdcbSSathya Perla #define MAX_TX_QS		32
10568d7bdcbSSathya Perla 
106045508a8SParav Pandit #define MAX_ROCE_EQS		5
10768d7bdcbSSathya Perla #define MAX_MSIX_VECTORS	32
10892bf14abSSathya Perla #define MIN_MSIX_VECTORS	1
1099aebddd1SJeff Kirsher #define BE_NAPI_WEIGHT		64
1109aebddd1SJeff Kirsher #define MAX_RX_POST		BE_NAPI_WEIGHT /* Frags posted at a time */
1119aebddd1SJeff Kirsher #define RX_FRAGS_REFILL_WM	(RX_Q_LEN - MAX_RX_POST)
11269304cc9SAjit Khaparde #define MAX_NUM_POST_ERX_DB	255u
1139aebddd1SJeff Kirsher 
1147c5a5242SVasundhara Volam #define MAX_VFS			30 /* Max VFs supported by BE3 FW */
1159aebddd1SJeff Kirsher #define FW_VER_LEN		32
116a155a5dbSSriharsha Basavapatna #define	CNTL_SERIAL_NUM_WORDS	8  /* Controller serial number words */
117a155a5dbSSriharsha Basavapatna #define	CNTL_SERIAL_NUM_WORD_SZ	(sizeof(u16)) /* Byte-sz of serial num word */
1189aebddd1SJeff Kirsher 
119e2557877SVenkata Duvvuru #define	RSS_INDIR_TABLE_LEN	128
120e2557877SVenkata Duvvuru #define RSS_HASH_KEY_LEN	40
121e2557877SVenkata Duvvuru 
12251d1f98aSAjit Khaparde #define BE_UNKNOWN_PHY_STATE	0xFF
12351d1f98aSAjit Khaparde 
1249aebddd1SJeff Kirsher struct be_dma_mem {
1259aebddd1SJeff Kirsher 	void *va;
1269aebddd1SJeff Kirsher 	dma_addr_t dma;
1279aebddd1SJeff Kirsher 	u32 size;
1289aebddd1SJeff Kirsher };
1299aebddd1SJeff Kirsher 
1309aebddd1SJeff Kirsher struct be_queue_info {
131b0fd2eb2Sajit.khaparde@broadcom.com 	u32 len;
132b0fd2eb2Sajit.khaparde@broadcom.com 	u32 entry_size;	/* Size of an element in the queue */
133b0fd2eb2Sajit.khaparde@broadcom.com 	u32 tail, head;
1349aebddd1SJeff Kirsher 	atomic_t used;	/* Number of valid elements in the queue */
135b0fd2eb2Sajit.khaparde@broadcom.com 	u32 id;
136b0fd2eb2Sajit.khaparde@broadcom.com 	struct be_dma_mem dma_mem;
137b0fd2eb2Sajit.khaparde@broadcom.com 	bool created;
1389aebddd1SJeff Kirsher };
1399aebddd1SJeff Kirsher 
140b0fd2eb2Sajit.khaparde@broadcom.com static inline u32 MODULO(u32 val, u32 limit)
1419aebddd1SJeff Kirsher {
1429aebddd1SJeff Kirsher 	BUG_ON(limit & (limit - 1));
1439aebddd1SJeff Kirsher 	return val & (limit - 1);
1449aebddd1SJeff Kirsher }
1459aebddd1SJeff Kirsher 
146b0fd2eb2Sajit.khaparde@broadcom.com static inline void index_adv(u32 *index, u32 val, u32 limit)
1479aebddd1SJeff Kirsher {
1489aebddd1SJeff Kirsher 	*index = MODULO((*index + val), limit);
1499aebddd1SJeff Kirsher }
1509aebddd1SJeff Kirsher 
151b0fd2eb2Sajit.khaparde@broadcom.com static inline void index_inc(u32 *index, u32 limit)
1529aebddd1SJeff Kirsher {
1539aebddd1SJeff Kirsher 	*index = MODULO((*index + 1), limit);
1549aebddd1SJeff Kirsher }
1559aebddd1SJeff Kirsher 
1569aebddd1SJeff Kirsher static inline void *queue_head_node(struct be_queue_info *q)
1579aebddd1SJeff Kirsher {
1589aebddd1SJeff Kirsher 	return q->dma_mem.va + q->head * q->entry_size;
1599aebddd1SJeff Kirsher }
1609aebddd1SJeff Kirsher 
1619aebddd1SJeff Kirsher static inline void *queue_tail_node(struct be_queue_info *q)
1629aebddd1SJeff Kirsher {
1639aebddd1SJeff Kirsher 	return q->dma_mem.va + q->tail * q->entry_size;
1649aebddd1SJeff Kirsher }
1659aebddd1SJeff Kirsher 
1663de09455SSomnath Kotur static inline void *queue_index_node(struct be_queue_info *q, u16 index)
1673de09455SSomnath Kotur {
1683de09455SSomnath Kotur 	return q->dma_mem.va + index * q->entry_size;
1693de09455SSomnath Kotur }
1703de09455SSomnath Kotur 
1719aebddd1SJeff Kirsher static inline void queue_head_inc(struct be_queue_info *q)
1729aebddd1SJeff Kirsher {
1739aebddd1SJeff Kirsher 	index_inc(&q->head, q->len);
1749aebddd1SJeff Kirsher }
1759aebddd1SJeff Kirsher 
176b0fd2eb2Sajit.khaparde@broadcom.com static inline void index_dec(u32 *index, u32 limit)
177652bf646SPadmanabh Ratnakar {
178652bf646SPadmanabh Ratnakar 	*index = MODULO((*index - 1), limit);
179652bf646SPadmanabh Ratnakar }
180652bf646SPadmanabh Ratnakar 
1819aebddd1SJeff Kirsher static inline void queue_tail_inc(struct be_queue_info *q)
1829aebddd1SJeff Kirsher {
1839aebddd1SJeff Kirsher 	index_inc(&q->tail, q->len);
1849aebddd1SJeff Kirsher }
1859aebddd1SJeff Kirsher 
1869aebddd1SJeff Kirsher struct be_eq_obj {
1879aebddd1SJeff Kirsher 	struct be_queue_info q;
1889aebddd1SJeff Kirsher 
189e9c74cd8SIvan Vecera 	struct be_adapter *adapter;
190e9c74cd8SIvan Vecera 	struct napi_struct napi;
19110ef9ab4SSathya Perla 	u8 idx;			/* array index */
192f2f781a7SSathya Perla 	u8 msix_idx;
193d0b9cec3SSathya Perla 	u16 spurious_intr;
194d658d98aSPadmanabh Ratnakar 	cpumask_var_t  affinity_mask;
19510ef9ab4SSathya Perla } ____cacheline_aligned_in_smp;
1969aebddd1SJeff Kirsher 
1972632bafdSSathya Perla struct be_aic_obj {		/* Adaptive interrupt coalescing (AIC) info */
1982632bafdSSathya Perla 	bool enable;
1992632bafdSSathya Perla 	u32 min_eqd;		/* in usecs */
2002632bafdSSathya Perla 	u32 max_eqd;		/* in usecs */
2012632bafdSSathya Perla 	u32 prev_eqd;		/* in usecs */
2022632bafdSSathya Perla 	u32 et_eqd;		/* configured val when aic is off */
2032632bafdSSathya Perla 	ulong jiffies;
2042632bafdSSathya Perla 	u64 rx_pkts_prev;	/* Used to calculate RX pps */
2052632bafdSSathya Perla 	u64 tx_reqs_prev;	/* Used to calculate TX pps */
2062632bafdSSathya Perla };
2072632bafdSSathya Perla 
2089aebddd1SJeff Kirsher struct be_mcc_obj {
2099aebddd1SJeff Kirsher 	struct be_queue_info q;
2109aebddd1SJeff Kirsher 	struct be_queue_info cq;
2119aebddd1SJeff Kirsher 	bool rearm_cq;
2129aebddd1SJeff Kirsher };
2139aebddd1SJeff Kirsher 
2149aebddd1SJeff Kirsher struct be_tx_stats {
2159aebddd1SJeff Kirsher 	u64 tx_bytes;
2169aebddd1SJeff Kirsher 	u64 tx_pkts;
2178670f2a5SSriharsha Basavapatna 	u64 tx_vxlan_offload_pkts;
2189aebddd1SJeff Kirsher 	u64 tx_reqs;
2199aebddd1SJeff Kirsher 	u64 tx_compl;
2209aebddd1SJeff Kirsher 	ulong tx_jiffies;
2219aebddd1SJeff Kirsher 	u32 tx_stops;
222bc617526SSathya Perla 	u32 tx_drv_drops;	/* pkts dropped by driver */
223512bb8a2SKalesh AP 	/* the error counters are described in be_ethtool.c */
224512bb8a2SKalesh AP 	u32 tx_hdr_parse_err;
225512bb8a2SKalesh AP 	u32 tx_dma_err;
226512bb8a2SKalesh AP 	u32 tx_tso_err;
227512bb8a2SKalesh AP 	u32 tx_spoof_check_err;
228512bb8a2SKalesh AP 	u32 tx_qinq_err;
229512bb8a2SKalesh AP 	u32 tx_internal_parity_err;
230ffc39620SSuresh Reddy 	u32 tx_sge_err;
2319aebddd1SJeff Kirsher 	struct u64_stats_sync sync;
2329aebddd1SJeff Kirsher 	struct u64_stats_sync sync_compl;
2339aebddd1SJeff Kirsher };
2349aebddd1SJeff Kirsher 
235152ffe5bSSriharsha Basavapatna /* Structure to hold some data of interest obtained from a TX CQE */
236152ffe5bSSriharsha Basavapatna struct be_tx_compl_info {
237152ffe5bSSriharsha Basavapatna 	u8 status;		/* Completion status */
238152ffe5bSSriharsha Basavapatna 	u16 end_index;		/* Completed TXQ Index */
239152ffe5bSSriharsha Basavapatna };
240152ffe5bSSriharsha Basavapatna 
2419aebddd1SJeff Kirsher struct be_tx_obj {
24294d73aaaSVasundhara Volam 	u32 db_offset;
2439aebddd1SJeff Kirsher 	struct be_queue_info q;
2449aebddd1SJeff Kirsher 	struct be_queue_info cq;
245152ffe5bSSriharsha Basavapatna 	struct be_tx_compl_info txcp;
2469aebddd1SJeff Kirsher 	/* Remember the skbs that were transmitted */
2479aebddd1SJeff Kirsher 	struct sk_buff *sent_skb_list[TX_Q_LEN];
2489aebddd1SJeff Kirsher 	struct be_tx_stats stats;
2495f07b3c5SSathya Perla 	u16 pend_wrb_cnt;	/* Number of WRBs yet to be given to HW */
2505f07b3c5SSathya Perla 	u16 last_req_wrb_cnt;	/* wrb cnt of the last req in the Q */
2515f07b3c5SSathya Perla 	u16 last_req_hdr;	/* index of the last req's hdr-wrb */
25210ef9ab4SSathya Perla } ____cacheline_aligned_in_smp;
2539aebddd1SJeff Kirsher 
2549aebddd1SJeff Kirsher /* Struct to remember the pages posted for rx frags */
2559aebddd1SJeff Kirsher struct be_rx_page_info {
2569aebddd1SJeff Kirsher 	struct page *page;
257e50287beSSathya Perla 	/* set to page-addr for last frag of the page & frag-addr otherwise */
2589aebddd1SJeff Kirsher 	DEFINE_DMA_UNMAP_ADDR(bus);
2599aebddd1SJeff Kirsher 	u16 page_offset;
260e50287beSSathya Perla 	bool last_frag;		/* last frag of the page */
2619aebddd1SJeff Kirsher };
2629aebddd1SJeff Kirsher 
2639aebddd1SJeff Kirsher struct be_rx_stats {
2649aebddd1SJeff Kirsher 	u64 rx_bytes;
2659aebddd1SJeff Kirsher 	u64 rx_pkts;
2668670f2a5SSriharsha Basavapatna 	u64 rx_vxlan_offload_pkts;
2679aebddd1SJeff Kirsher 	u32 rx_drops_no_skbs;	/* skb allocation errors */
2689aebddd1SJeff Kirsher 	u32 rx_drops_no_frags;	/* HW has no fetched frags */
2699aebddd1SJeff Kirsher 	u32 rx_post_fail;	/* page post alloc failures */
2709aebddd1SJeff Kirsher 	u32 rx_compl;
2719aebddd1SJeff Kirsher 	u32 rx_mcast_pkts;
2729aebddd1SJeff Kirsher 	u32 rx_compl_err;	/* completions with err set */
2739aebddd1SJeff Kirsher 	struct u64_stats_sync sync;
2749aebddd1SJeff Kirsher };
2759aebddd1SJeff Kirsher 
2769aebddd1SJeff Kirsher struct be_rx_compl_info {
2779aebddd1SJeff Kirsher 	u32 rss_hash;
2789aebddd1SJeff Kirsher 	u16 vlan_tag;
2799aebddd1SJeff Kirsher 	u16 pkt_size;
2809aebddd1SJeff Kirsher 	u16 port;
2819aebddd1SJeff Kirsher 	u8 vlanf;
2829aebddd1SJeff Kirsher 	u8 num_rcvd;
2839aebddd1SJeff Kirsher 	u8 err;
2849aebddd1SJeff Kirsher 	u8 ipf;
2859aebddd1SJeff Kirsher 	u8 tcpf;
2869aebddd1SJeff Kirsher 	u8 udpf;
2879aebddd1SJeff Kirsher 	u8 ip_csum;
2889aebddd1SJeff Kirsher 	u8 l4_csum;
2899aebddd1SJeff Kirsher 	u8 ipv6;
290f93f160bSVasundhara Volam 	u8 qnq;
2919aebddd1SJeff Kirsher 	u8 pkt_type;
292e38b1706SSomnath Kotur 	u8 ip_frag;
293c9c47142SSathya Perla 	u8 tunneled;
2949aebddd1SJeff Kirsher };
2959aebddd1SJeff Kirsher 
2969aebddd1SJeff Kirsher struct be_rx_obj {
2979aebddd1SJeff Kirsher 	struct be_adapter *adapter;
2989aebddd1SJeff Kirsher 	struct be_queue_info q;
2999aebddd1SJeff Kirsher 	struct be_queue_info cq;
3009aebddd1SJeff Kirsher 	struct be_rx_compl_info rxcp;
3019aebddd1SJeff Kirsher 	struct be_rx_page_info page_info_tbl[RX_Q_LEN];
3029aebddd1SJeff Kirsher 	struct be_rx_stats stats;
3039aebddd1SJeff Kirsher 	u8 rss_id;
3049aebddd1SJeff Kirsher 	bool rx_post_starved;	/* Zero rx frags have been posted to BE */
30510ef9ab4SSathya Perla } ____cacheline_aligned_in_smp;
3069aebddd1SJeff Kirsher 
3079aebddd1SJeff Kirsher struct be_drv_stats {
3089aebddd1SJeff Kirsher 	u32 eth_red_drops;
309d3de1540SVasundhara Volam 	u32 dma_map_errors;
3109aebddd1SJeff Kirsher 	u32 rx_drops_no_pbuf;
3119aebddd1SJeff Kirsher 	u32 rx_drops_no_txpb;
3129aebddd1SJeff Kirsher 	u32 rx_drops_no_erx_descr;
3139aebddd1SJeff Kirsher 	u32 rx_drops_no_tpre_descr;
3149aebddd1SJeff Kirsher 	u32 rx_drops_too_many_frags;
3159aebddd1SJeff Kirsher 	u32 forwarded_packets;
3169aebddd1SJeff Kirsher 	u32 rx_drops_mtu;
3179aebddd1SJeff Kirsher 	u32 rx_crc_errors;
3189aebddd1SJeff Kirsher 	u32 rx_alignment_symbol_errors;
3199aebddd1SJeff Kirsher 	u32 rx_pause_frames;
3209aebddd1SJeff Kirsher 	u32 rx_priority_pause_frames;
3219aebddd1SJeff Kirsher 	u32 rx_control_frames;
3229aebddd1SJeff Kirsher 	u32 rx_in_range_errors;
3239aebddd1SJeff Kirsher 	u32 rx_out_range_errors;
3249aebddd1SJeff Kirsher 	u32 rx_frame_too_long;
32518fb06a1SSuresh Reddy 	u32 rx_address_filtered;
3269aebddd1SJeff Kirsher 	u32 rx_dropped_too_small;
3279aebddd1SJeff Kirsher 	u32 rx_dropped_too_short;
3289aebddd1SJeff Kirsher 	u32 rx_dropped_header_too_small;
3299aebddd1SJeff Kirsher 	u32 rx_dropped_tcp_length;
3309aebddd1SJeff Kirsher 	u32 rx_dropped_runt;
3319aebddd1SJeff Kirsher 	u32 rx_ip_checksum_errs;
3329aebddd1SJeff Kirsher 	u32 rx_tcp_checksum_errs;
3339aebddd1SJeff Kirsher 	u32 rx_udp_checksum_errs;
3349aebddd1SJeff Kirsher 	u32 tx_pauseframes;
3359aebddd1SJeff Kirsher 	u32 tx_priority_pauseframes;
3369aebddd1SJeff Kirsher 	u32 tx_controlframes;
3379aebddd1SJeff Kirsher 	u32 rxpp_fifo_overflow_drop;
3389aebddd1SJeff Kirsher 	u32 rx_input_fifo_overflow_drop;
3399aebddd1SJeff Kirsher 	u32 pmem_fifo_overflow_drop;
3409aebddd1SJeff Kirsher 	u32 jabber_events;
341461ae379SAjit Khaparde 	u32 rx_roce_bytes_lsd;
342461ae379SAjit Khaparde 	u32 rx_roce_bytes_msd;
343461ae379SAjit Khaparde 	u32 rx_roce_frames;
344461ae379SAjit Khaparde 	u32 roce_drops_payload_len;
345461ae379SAjit Khaparde 	u32 roce_drops_crc;
3469aebddd1SJeff Kirsher };
3479aebddd1SJeff Kirsher 
348c502224eSSomnath Kotur /* A vlan-id of 0xFFFF must be used to clear transparent vlan-tagging */
349c502224eSSomnath Kotur #define BE_RESET_VLAN_TAG_ID	0xFFFF
350c502224eSSomnath Kotur 
3519aebddd1SJeff Kirsher struct be_vf_cfg {
35211ac75edSSathya Perla 	unsigned char mac_addr[ETH_ALEN];
35311ac75edSSathya Perla 	int if_handle;
35411ac75edSSathya Perla 	int pmac_id;
35511ac75edSSathya Perla 	u16 vlan_tag;
35611ac75edSSathya Perla 	u32 tx_rate;
357bdce2ad7SSuresh Reddy 	u32 plink_tracking;
358435452aaSVasundhara Volam 	u32 privileges;
359e7bcbd7bSKalesh AP 	bool spoofchk;
3609aebddd1SJeff Kirsher };
3619aebddd1SJeff Kirsher 
36239f1d94dSSathya Perla enum vf_state {
36339f1d94dSSathya Perla 	ENABLED = 0,
36439f1d94dSSathya Perla 	ASSIGNED = 1
36539f1d94dSSathya Perla };
36639f1d94dSSathya Perla 
36783b06116SVasundhara Volam #define BE_FLAGS_LINK_STATUS_INIT		BIT(1)
36883b06116SVasundhara Volam #define BE_FLAGS_SRIOV_ENABLED			BIT(2)
36983b06116SVasundhara Volam #define BE_FLAGS_WORKER_SCHEDULED		BIT(3)
37083b06116SVasundhara Volam #define BE_FLAGS_NAPI_ENABLED			BIT(6)
37183b06116SVasundhara Volam #define BE_FLAGS_QNQ_ASYNC_EVT_RCVD		BIT(7)
37283b06116SVasundhara Volam #define BE_FLAGS_VXLAN_OFFLOADS			BIT(8)
37383b06116SVasundhara Volam #define BE_FLAGS_SETUP_DONE			BIT(9)
37451d1f98aSAjit Khaparde #define BE_FLAGS_PHY_MISCONFIGURED		BIT(10)
375eb7dd46cSSathya Perla #define BE_FLAGS_ERR_DETECTION_SCHEDULED	BIT(11)
376760c295eSVenkata Duvvuru #define BE_FLAGS_OS2BMC				BIT(12)
377710f3e59SSriharsha Basavapatna #define BE_FLAGS_TRY_RECOVERY			BIT(13)
378c9c47142SSathya Perla 
379fbc13f01SAjit Khaparde #define BE_UC_PMAC_COUNT			30
380fbc13f01SAjit Khaparde #define BE_VF_UC_PMAC_COUNT			2
381f0613380SKalesh AP 
382972f37b4SPadmanabh Ratnakar #define MAX_ERR_RECOVERY_RETRY_COUNT		3
383972f37b4SPadmanabh Ratnakar #define ERR_DETECTION_DELAY			1000
384972f37b4SPadmanabh Ratnakar 
3855c510811SSomnath Kotur /* Ethtool set_dump flags */
3865c510811SSomnath Kotur #define LANCER_INITIATE_FW_DUMP			0x1
387f0613380SKalesh AP #define LANCER_DELETE_FW_DUMP			0x2
3885c510811SSomnath Kotur 
38942f11cf2SAjit Khaparde struct phy_info {
39021252377SVasundhara Volam /* From SFF-8472 spec */
39121252377SVasundhara Volam #define SFP_VENDOR_NAME_LEN			17
39242f11cf2SAjit Khaparde 	u8 transceiver;
39342f11cf2SAjit Khaparde 	u8 autoneg;
39442f11cf2SAjit Khaparde 	u8 fc_autoneg;
39542f11cf2SAjit Khaparde 	u8 port_type;
39642f11cf2SAjit Khaparde 	u16 phy_type;
39742f11cf2SAjit Khaparde 	u16 interface_type;
39842f11cf2SAjit Khaparde 	u32 misc_params;
39942f11cf2SAjit Khaparde 	u16 auto_speeds_supported;
40042f11cf2SAjit Khaparde 	u16 fixed_speeds_supported;
40142f11cf2SAjit Khaparde 	int link_speed;
40242f11cf2SAjit Khaparde 	u32 advertising;
40342f11cf2SAjit Khaparde 	u32 supported;
4046809cee0SRavikumar Nelavelli 	u8 cable_type;
40521252377SVasundhara Volam 	u8 vendor_name[SFP_VENDOR_NAME_LEN];
40621252377SVasundhara Volam 	u8 vendor_pn[SFP_VENDOR_NAME_LEN];
40742f11cf2SAjit Khaparde };
40842f11cf2SAjit Khaparde 
40992bf14abSSathya Perla struct be_resources {
41092bf14abSSathya Perla 	u16 max_vfs;		/* Total VFs "really" supported by FW/HW */
41192bf14abSSathya Perla 	u16 max_mcast_mac;
41292bf14abSSathya Perla 	u16 max_tx_qs;
41392bf14abSSathya Perla 	u16 max_rss_qs;
41492bf14abSSathya Perla 	u16 max_rx_qs;
415f2858738SVasundhara Volam 	u16 max_cq_count;
41692bf14abSSathya Perla 	u16 max_uc_mac;		/* Max UC MACs programmable */
41792bf14abSSathya Perla 	u16 max_vlans;		/* Number of vlans supported */
418f2858738SVasundhara Volam 	u16 max_iface_count;
419f2858738SVasundhara Volam 	u16 max_mcc_count;
42092bf14abSSathya Perla 	u16 max_evt_qs;
421ce7faf0aSSathya Perla 	u16 max_nic_evt_qs;	/* NIC's share of evt qs */
42292bf14abSSathya Perla 	u32 if_cap_flags;
42310cccf60SVasundhara Volam 	u32 vf_if_cap_flags;	/* VF if capability flags */
424b9263cbfSSuresh Reddy 	u32 flags;
425de2b1e03SSomnath Kotur 	/* Calculated PF Pool's share of RSS Tables. This is not enforced by
426de2b1e03SSomnath Kotur 	 * the FW, but is a self-imposed driver limitation.
427de2b1e03SSomnath Kotur 	 */
428de2b1e03SSomnath Kotur 	u16 max_rss_tables;
429de2b1e03SSomnath Kotur };
430de2b1e03SSomnath Kotur 
431de2b1e03SSomnath Kotur /* These are port-wide values */
432de2b1e03SSomnath Kotur struct be_port_resources {
433de2b1e03SSomnath Kotur 	u16 max_vfs;
434de2b1e03SSomnath Kotur 	u16 nic_pfs;
43592bf14abSSathya Perla };
43692bf14abSSathya Perla 
437760c295eSVenkata Duvvuru #define be_is_os2bmc_enabled(adapter) (adapter->flags & BE_FLAGS_OS2BMC)
438760c295eSVenkata Duvvuru 
439e2557877SVenkata Duvvuru struct rss_info {
440e2557877SVenkata Duvvuru 	u64 rss_flags;
441e2557877SVenkata Duvvuru 	u8 rsstable[RSS_INDIR_TABLE_LEN];
442e2557877SVenkata Duvvuru 	u8 rss_queue[RSS_INDIR_TABLE_LEN];
443e2557877SVenkata Duvvuru 	u8 rss_hkey[RSS_HASH_KEY_LEN];
444e2557877SVenkata Duvvuru };
445e2557877SVenkata Duvvuru 
44629e9122bSVenkata Duvvuru #define BE_INVALID_DIE_TEMP	0xFF
44729e9122bSVenkata Duvvuru struct be_hwmon {
44829e9122bSVenkata Duvvuru 	struct device *hwmon_dev;
44929e9122bSVenkata Duvvuru 	u8 be_on_die_temp;  /* Unit: millidegree Celsius */
45029e9122bSVenkata Duvvuru };
45129e9122bSVenkata Duvvuru 
452804abcdbSSriharsha Basavapatna /* Macros to read/write the 'features' word of be_wrb_params structure.
453804abcdbSSriharsha Basavapatna  */
454804abcdbSSriharsha Basavapatna #define	BE_WRB_F_BIT(name)			BE_WRB_F_##name##_BIT
455804abcdbSSriharsha Basavapatna #define	BE_WRB_F_MASK(name)			BIT_MASK(BE_WRB_F_##name##_BIT)
456804abcdbSSriharsha Basavapatna 
457804abcdbSSriharsha Basavapatna #define	BE_WRB_F_GET(word, name)	\
458804abcdbSSriharsha Basavapatna 	(((word) & (BE_WRB_F_MASK(name))) >> BE_WRB_F_BIT(name))
459804abcdbSSriharsha Basavapatna 
460804abcdbSSriharsha Basavapatna #define	BE_WRB_F_SET(word, name, val)	\
461804abcdbSSriharsha Basavapatna 	((word) |= (((val) << BE_WRB_F_BIT(name)) & BE_WRB_F_MASK(name)))
462804abcdbSSriharsha Basavapatna 
463804abcdbSSriharsha Basavapatna /* Feature/offload bits */
464804abcdbSSriharsha Basavapatna enum {
465804abcdbSSriharsha Basavapatna 	BE_WRB_F_CRC_BIT,		/* Ethernet CRC */
466804abcdbSSriharsha Basavapatna 	BE_WRB_F_IPCS_BIT,		/* IP csum */
467804abcdbSSriharsha Basavapatna 	BE_WRB_F_TCPCS_BIT,		/* TCP csum */
468804abcdbSSriharsha Basavapatna 	BE_WRB_F_UDPCS_BIT,		/* UDP csum */
469804abcdbSSriharsha Basavapatna 	BE_WRB_F_LSO_BIT,		/* LSO */
470804abcdbSSriharsha Basavapatna 	BE_WRB_F_LSO6_BIT,		/* LSO6 */
471804abcdbSSriharsha Basavapatna 	BE_WRB_F_VLAN_BIT,		/* VLAN */
472760c295eSVenkata Duvvuru 	BE_WRB_F_VLAN_SKIP_HW_BIT,	/* Skip VLAN tag (workaround) */
473760c295eSVenkata Duvvuru 	BE_WRB_F_OS2BMC_BIT		/* Send packet to the management ring */
474804abcdbSSriharsha Basavapatna };
475804abcdbSSriharsha Basavapatna 
476804abcdbSSriharsha Basavapatna /* The structure below provides a HW-agnostic abstraction of WRB params
477804abcdbSSriharsha Basavapatna  * retrieved from a TX skb. This is in turn passed to chip specific routines
478804abcdbSSriharsha Basavapatna  * during transmit, to set the corresponding params in the WRB.
479804abcdbSSriharsha Basavapatna  */
480804abcdbSSriharsha Basavapatna struct be_wrb_params {
481804abcdbSSriharsha Basavapatna 	u32 features;	/* Feature bits */
482804abcdbSSriharsha Basavapatna 	u16 vlan_tag;	/* VLAN tag */
483804abcdbSSriharsha Basavapatna 	u16 lso_mss;	/* MSS for LSO */
484804abcdbSSriharsha Basavapatna };
485804abcdbSSriharsha Basavapatna 
486b7172414SSathya Perla struct be_eth_addr {
487b7172414SSathya Perla 	unsigned char mac[ETH_ALEN];
488b7172414SSathya Perla };
489b7172414SSathya Perla 
490710f3e59SSriharsha Basavapatna #define BE_SEC	1000			/* in msec */
491710f3e59SSriharsha Basavapatna #define BE_MIN	(60 * BE_SEC)		/* in msec */
492710f3e59SSriharsha Basavapatna #define BE_HOUR	(60 * BE_MIN)		/* in msec */
493710f3e59SSriharsha Basavapatna 
494710f3e59SSriharsha Basavapatna #define ERR_RECOVERY_MAX_RETRY_COUNT		3
495710f3e59SSriharsha Basavapatna #define ERR_RECOVERY_DETECTION_DELAY		BE_SEC
496710f3e59SSriharsha Basavapatna #define ERR_RECOVERY_RETRY_DELAY		(30 * BE_SEC)
497710f3e59SSriharsha Basavapatna 
498710f3e59SSriharsha Basavapatna /* UE-detection-duration in BEx/Skyhawk:
499710f3e59SSriharsha Basavapatna  * All PFs must wait for this duration after they detect UE before reading
500710f3e59SSriharsha Basavapatna  * SLIPORT_SEMAPHORE register. At the end of this duration, the Firmware
501710f3e59SSriharsha Basavapatna  * guarantees that the SLIPORT_SEMAPHORE register is updated to indicate
502710f3e59SSriharsha Basavapatna  * if the UE is recoverable.
503710f3e59SSriharsha Basavapatna  */
504710f3e59SSriharsha Basavapatna #define ERR_RECOVERY_UE_DETECT_DURATION			BE_SEC
505710f3e59SSriharsha Basavapatna 
506710f3e59SSriharsha Basavapatna /* Initial idle time (in msec) to elapse after driver load,
507710f3e59SSriharsha Basavapatna  * before UE recovery is allowed.
508710f3e59SSriharsha Basavapatna  */
509710f3e59SSriharsha Basavapatna #define ERR_IDLE_HR			24
510710f3e59SSriharsha Basavapatna #define ERR_RECOVERY_IDLE_TIME		(ERR_IDLE_HR * BE_HOUR)
511710f3e59SSriharsha Basavapatna 
512710f3e59SSriharsha Basavapatna /* Time interval (in msec) after which UE recovery can be repeated */
513710f3e59SSriharsha Basavapatna #define ERR_INTERVAL_HR			72
514710f3e59SSriharsha Basavapatna #define ERR_RECOVERY_INTERVAL		(ERR_INTERVAL_HR * BE_HOUR)
515710f3e59SSriharsha Basavapatna 
516710f3e59SSriharsha Basavapatna /* BEx/SH UE recovery state machine */
517710f3e59SSriharsha Basavapatna enum {
518710f3e59SSriharsha Basavapatna 	ERR_RECOVERY_ST_NONE = 0,		/* No Recovery */
519710f3e59SSriharsha Basavapatna 	ERR_RECOVERY_ST_DETECT = 1,		/* UE detection duration */
520710f3e59SSriharsha Basavapatna 	ERR_RECOVERY_ST_RESET = 2,		/* Reset Phase (PF0 only) */
521710f3e59SSriharsha Basavapatna 	ERR_RECOVERY_ST_PRE_POLL = 3,		/* Pre-Poll Phase (all PFs) */
522710f3e59SSriharsha Basavapatna 	ERR_RECOVERY_ST_REINIT = 4		/* Re-initialize Phase */
523710f3e59SSriharsha Basavapatna };
524710f3e59SSriharsha Basavapatna 
525710f3e59SSriharsha Basavapatna struct be_error_recovery {
526710f3e59SSriharsha Basavapatna 	/* Lancer error recovery variables */
527710f3e59SSriharsha Basavapatna 	u8 recovery_retries;
528710f3e59SSriharsha Basavapatna 
529710f3e59SSriharsha Basavapatna 	/* BEx/Skyhawk error recovery variables */
530710f3e59SSriharsha Basavapatna 	u8 recovery_state;
531710f3e59SSriharsha Basavapatna 	u16 ue_to_reset_time;		/* Time after UE, to soft reset
532710f3e59SSriharsha Basavapatna 					 * the chip - PF0 only
533710f3e59SSriharsha Basavapatna 					 */
534710f3e59SSriharsha Basavapatna 	u16 ue_to_poll_time;		/* Time after UE, to Restart Polling
535710f3e59SSriharsha Basavapatna 					 * of SLIPORT_SEMAPHORE reg
536710f3e59SSriharsha Basavapatna 					 */
537710f3e59SSriharsha Basavapatna 	u16 last_err_code;
538710f3e59SSriharsha Basavapatna 	bool recovery_supported;
539710f3e59SSriharsha Basavapatna 	unsigned long probe_time;
540710f3e59SSriharsha Basavapatna 	unsigned long last_recovery_time;
541710f3e59SSriharsha Basavapatna 
542710f3e59SSriharsha Basavapatna 	/* Common to both Lancer & BEx/SH error recovery */
543710f3e59SSriharsha Basavapatna 	u32 resched_delay;
544710f3e59SSriharsha Basavapatna 	struct delayed_work err_detection_work;
545710f3e59SSriharsha Basavapatna };
546710f3e59SSriharsha Basavapatna 
547710f3e59SSriharsha Basavapatna /* Ethtool priv_flags */
548710f3e59SSriharsha Basavapatna #define	BE_DISABLE_TPE_RECOVERY	0x1
549710f3e59SSriharsha Basavapatna 
550bf8d9dfbSSriharsha Basavapatna struct be_vxlan_port {
551bf8d9dfbSSriharsha Basavapatna 	struct list_head list;
552bf8d9dfbSSriharsha Basavapatna 	__be16 port;		/* VxLAN UDP dst port */
553bf8d9dfbSSriharsha Basavapatna 	int port_aliases;	/* alias count */
554bf8d9dfbSSriharsha Basavapatna };
555bf8d9dfbSSriharsha Basavapatna 
5569aebddd1SJeff Kirsher struct be_adapter {
5579aebddd1SJeff Kirsher 	struct pci_dev *pdev;
5589aebddd1SJeff Kirsher 	struct net_device *netdev;
5599aebddd1SJeff Kirsher 
560c5b3ad4cSSathya Perla 	u8 __iomem *csr;	/* CSR BAR used only for BE2/3 */
5619aebddd1SJeff Kirsher 	u8 __iomem *db;		/* Door Bell */
56225848c90SSuresh Reddy 	u8 __iomem *pcicfg;	/* On SH,BEx only. Shadow of PCI config space */
5639aebddd1SJeff Kirsher 
5649aebddd1SJeff Kirsher 	struct mutex mbox_lock; /* For serializing mbox cmds to BE card */
5659aebddd1SJeff Kirsher 	struct be_dma_mem mbox_mem;
5669aebddd1SJeff Kirsher 	/* Mbox mem is adjusted to align to 16 bytes. The allocated addr
5679aebddd1SJeff Kirsher 	 * is stored for freeing purpose */
5689aebddd1SJeff Kirsher 	struct be_dma_mem mbox_mem_alloced;
5699aebddd1SJeff Kirsher 
5709aebddd1SJeff Kirsher 	struct be_mcc_obj mcc_obj;
571b7172414SSathya Perla 	struct mutex mcc_lock;	/* For serializing mcc cmds to BE card */
5729aebddd1SJeff Kirsher 	spinlock_t mcc_cq_lock;
5739aebddd1SJeff Kirsher 
574e261768eSSathya Perla 	u16 cfg_num_rx_irqs;		/* configured via set-channels */
575e261768eSSathya Perla 	u16 cfg_num_tx_irqs;		/* configured via set-channels */
57692bf14abSSathya Perla 	u16 num_evt_qs;
57792bf14abSSathya Perla 	u16 num_msix_vec;
57892bf14abSSathya Perla 	struct be_eq_obj eq_obj[MAX_EVT_QS];
57910ef9ab4SSathya Perla 	struct msix_entry msix_entries[MAX_MSIX_VECTORS];
5809aebddd1SJeff Kirsher 	bool isr_registered;
5819aebddd1SJeff Kirsher 
5829aebddd1SJeff Kirsher 	/* TX Rings */
58392bf14abSSathya Perla 	u16 num_tx_qs;
5849aebddd1SJeff Kirsher 	struct be_tx_obj tx_obj[MAX_TX_QS];
5859aebddd1SJeff Kirsher 
5869aebddd1SJeff Kirsher 	/* Rx rings */
58792bf14abSSathya Perla 	u16 num_rx_qs;
58871bb8bd0SVasundhara Volam 	u16 num_rss_qs;
58971bb8bd0SVasundhara Volam 	u16 need_def_rxq;
59010ef9ab4SSathya Perla 	struct be_rx_obj rx_obj[MAX_RX_QS];
5919aebddd1SJeff Kirsher 	u32 big_page_size;	/* Compounded page size shared by rx wrbs */
5929aebddd1SJeff Kirsher 
5939aebddd1SJeff Kirsher 	struct be_drv_stats drv_stats;
5942632bafdSSathya Perla 	struct be_aic_obj aic_obj[MAX_EVT_QS];
5959aebddd1SJeff Kirsher 	u8 vlan_prio_bmap;	/* Available Priority BitMap */
596fdf81bfbSSathya Perla 	u16 recommended_prio_bits;/* Recommended Priority bits in vlan tag */
5979aebddd1SJeff Kirsher 	struct be_dma_mem rx_filter; /* Cmd DMA mem for rx-filter */
5989aebddd1SJeff Kirsher 
5999aebddd1SJeff Kirsher 	struct be_dma_mem stats_cmd;
6009aebddd1SJeff Kirsher 	/* Work queue used to perform periodic tasks like getting statistics */
6019aebddd1SJeff Kirsher 	struct delayed_work work;
6029aebddd1SJeff Kirsher 	u16 work_counter;
6039aebddd1SJeff Kirsher 
604972f37b4SPadmanabh Ratnakar 	u8 recovery_retries;
605954f6825SVenkata Duvvuru 	u8 err_flags;
606a69bf3c5SDouglas Miller 	bool pcicfg_mapped;	/* pcicfg obtained via pci_iomap() */
607b236916aSAjit Khaparde 	u32 flags;
608f25b119cSPadmanabh Ratnakar 	u32 cmd_privileges;
6099aebddd1SJeff Kirsher 	/* Ethtool knobs and info */
6109aebddd1SJeff Kirsher 	char fw_ver[FW_VER_LEN];
611eeb65cedSSomnath Kotur 	char fw_on_flash[FW_VER_LEN];
612f66b7cfdSSathya Perla 
613f66b7cfdSSathya Perla 	/* IFACE filtering fields */
61430128031SSathya Perla 	int if_handle;		/* Used to configure filtering */
615f66b7cfdSSathya Perla 	u32 if_flags;		/* Interface filtering flags */
616fbc13f01SAjit Khaparde 	u32 *pmac_id;		/* MAC addr handle used by BE card */
617b7172414SSathya Perla 	struct be_eth_addr *uc_list;/* list of uc-addrs programmed (not perm) */
618f66b7cfdSSathya Perla 	u32 uc_macs;		/* Count of secondary UC MAC programmed */
619b7172414SSathya Perla 	struct be_eth_addr *mc_list;/* list of mcast addrs programmed */
620b7172414SSathya Perla 	u32 mc_count;
621f66b7cfdSSathya Perla 	unsigned long vids[BITS_TO_LONGS(VLAN_N_VID)];
622f66b7cfdSSathya Perla 	u16 vlans_added;
62392fbb1dfSSriharsha Basavapatna 	bool update_uc_list;
62492fbb1dfSSriharsha Basavapatna 	bool update_mc_list;
625b7172414SSathya Perla 	struct mutex rx_filter_lock;/* For protecting vids[] & mc/uc_list[] */
626f66b7cfdSSathya Perla 
6279aebddd1SJeff Kirsher 	u32 beacon_state;	/* for set_phys_id */
6289aebddd1SJeff Kirsher 
6299aebddd1SJeff Kirsher 	u32 port_num;
63021252377SVasundhara Volam 	char port_name;
631f93f160bSVasundhara Volam 	u8 mc_type;
6329aebddd1SJeff Kirsher 	u32 function_mode;
6339aebddd1SJeff Kirsher 	u32 function_caps;
6349aebddd1SJeff Kirsher 	u32 rx_fc;		/* Rx flow control */
6359aebddd1SJeff Kirsher 	u32 tx_fc;		/* Tx flow control */
6369aebddd1SJeff Kirsher 	bool stats_cmd_sent;
637045508a8SParav Pandit 	struct {
638045508a8SParav Pandit 		u32 size;
639045508a8SParav Pandit 		u32 total_size;
640045508a8SParav Pandit 		u64 io_addr;
641045508a8SParav Pandit 	} roce_db;
642045508a8SParav Pandit 	u32 num_msix_roce_vec;
643045508a8SParav Pandit 	struct ocrdma_dev *ocrdma_dev;
644045508a8SParav Pandit 	struct list_head entry;
645045508a8SParav Pandit 
6469aebddd1SJeff Kirsher 	u32 flash_status;
6475eeff635SSuresh Reddy 	struct completion et_cmd_compl;
6489aebddd1SJeff Kirsher 
649bec84e6bSVasundhara Volam 	struct be_resources pool_res;	/* resources available for the port */
65092bf14abSSathya Perla 	struct be_resources res;	/* resources available for the func */
65192bf14abSSathya Perla 	u16 num_vfs;			/* Number of VFs provisioned by PF */
652980df249SSuresh Reddy 	u8 pf_num;			/* Numbering used by FW, starts at 0 */
653980df249SSuresh Reddy 	u8 vf_num;			/* Numbering used by FW, starts at 1 */
65439f1d94dSSathya Perla 	u8 virtfn;
65511ac75edSSathya Perla 	struct be_vf_cfg *vf_cfg;
65611ac75edSSathya Perla 	bool be3_native;
6579aebddd1SJeff Kirsher 	u32 sli_family;
6589aebddd1SJeff Kirsher 	u8 hba_port_num;
6599aebddd1SJeff Kirsher 	u16 pvid;
660bf8d9dfbSSriharsha Basavapatna 	__be16 vxlan_port;		/* offloaded vxlan port num */
661bf8d9dfbSSriharsha Basavapatna 	int vxlan_port_count;		/* active vxlan port count */
662bf8d9dfbSSriharsha Basavapatna 	struct list_head vxlan_port_list;	/* vxlan port list */
66342f11cf2SAjit Khaparde 	struct phy_info phy;
6644762f6ceSAjit Khaparde 	u8 wol_cap;
66576a9e08eSSuresh Reddy 	bool wol_en;
6660ad3157eSVasundhara Volam 	u16 asic_rev;
667bc0c3405SAjit Khaparde 	u16 qnq_vid;
668941a77d5SSomnath Kotur 	u32 msg_enable;
6697aeb2156SPadmanabh Ratnakar 	int be_get_temp_freq;
67029e9122bSVenkata Duvvuru 	struct be_hwmon hwmon_info;
671e2557877SVenkata Duvvuru 	struct rss_info rss_info;
672760c295eSVenkata Duvvuru 	/* Filters for packets that need to be sent to BMC */
673760c295eSVenkata Duvvuru 	u32 bmc_filt_mask;
674fd7ff6f0SVenkat Duvvuru 	u32 fat_dump_len;
675a155a5dbSSriharsha Basavapatna 	u16 serial_num[CNTL_SERIAL_NUM_WORDS];
67651d1f98aSAjit Khaparde 	u8 phy_state; /* state of sfp optics (functional, faulted, etc.,) */
677c27ebf58SSuresh Reddy 	u8 dev_mac[ETH_ALEN];
678710f3e59SSriharsha Basavapatna 	u32 priv_flags; /* ethtool get/set_priv_flags() */
679710f3e59SSriharsha Basavapatna 	struct be_error_recovery error_recovery;
6809aebddd1SJeff Kirsher };
6819aebddd1SJeff Kirsher 
682b7172414SSathya Perla /* Used for defered FW config cmds. Add fields to this struct as reqd */
683b7172414SSathya Perla struct be_cmd_work {
684b7172414SSathya Perla 	struct work_struct work;
685b7172414SSathya Perla 	struct be_adapter *adapter;
686b7172414SSathya Perla 	union {
687b7172414SSathya Perla 		__be16 vxlan_port;
688b7172414SSathya Perla 	} info;
689b7172414SSathya Perla };
690b7172414SSathya Perla 
69139f1d94dSSathya Perla #define be_physfn(adapter)		(!adapter->virtfn)
6922c7a9dc1SAjit Khaparde #define be_virtfn(adapter)		(adapter->virtfn)
693f174c7ecSVasundhara Volam #define sriov_enabled(adapter)		(adapter->flags &	\
694f174c7ecSVasundhara Volam 					 BE_FLAGS_SRIOV_ENABLED)
695bec84e6bSVasundhara Volam 
69611ac75edSSathya Perla #define for_all_vfs(adapter, vf_cfg, i)					\
69711ac75edSSathya Perla 	for (i = 0, vf_cfg = &adapter->vf_cfg[i]; i < adapter->num_vfs;	\
69811ac75edSSathya Perla 		i++, vf_cfg++)
6999aebddd1SJeff Kirsher 
7009aebddd1SJeff Kirsher #define ON				1
7019aebddd1SJeff Kirsher #define OFF				0
702ca34fe38SSathya Perla 
70392bf14abSSathya Perla #define be_max_vlans(adapter)		(adapter->res.max_vlans)
70492bf14abSSathya Perla #define be_max_uc(adapter)		(adapter->res.max_uc_mac)
70592bf14abSSathya Perla #define be_max_mc(adapter)		(adapter->res.max_mcast_mac)
706bec84e6bSVasundhara Volam #define be_max_vfs(adapter)		(adapter->pool_res.max_vfs)
70792bf14abSSathya Perla #define be_max_rss(adapter)		(adapter->res.max_rss_qs)
70892bf14abSSathya Perla #define be_max_txqs(adapter)		(adapter->res.max_tx_qs)
70992bf14abSSathya Perla #define be_max_prio_txqs(adapter)	(adapter->res.max_prio_tx_qs)
71092bf14abSSathya Perla #define be_max_rxqs(adapter)		(adapter->res.max_rx_qs)
711ce7faf0aSSathya Perla /* Max number of EQs available for the function (NIC + RoCE (if enabled)) */
712ce7faf0aSSathya Perla #define be_max_func_eqs(adapter)	(adapter->res.max_evt_qs)
713ce7faf0aSSathya Perla /* Max number of EQs available avaialble only for NIC */
714ce7faf0aSSathya Perla #define be_max_nic_eqs(adapter)		(adapter->res.max_nic_evt_qs)
71592bf14abSSathya Perla #define be_if_cap_flags(adapter)	(adapter->res.if_cap_flags)
716de2b1e03SSomnath Kotur #define be_max_pf_pool_rss_tables(adapter)	\
717de2b1e03SSomnath Kotur 				(adapter->pool_res.max_rss_tables)
718e261768eSSathya Perla /* Max irqs avaialble for NIC */
719e261768eSSathya Perla #define be_max_irqs(adapter)		\
720e261768eSSathya Perla 			(min_t(u16, be_max_nic_eqs(adapter), num_online_cpus()))
72192bf14abSSathya Perla 
722e261768eSSathya Perla /* Max irqs *needed* for RX queues */
723e261768eSSathya Perla static inline u16 be_max_rx_irqs(struct be_adapter *adapter)
72492bf14abSSathya Perla {
725e261768eSSathya Perla 	/* If no RSS, need atleast one irq for def-RXQ */
72692bf14abSSathya Perla 	u16 num = max_t(u16, be_max_rss(adapter), 1);
72792bf14abSSathya Perla 
728e261768eSSathya Perla 	return min_t(u16, num, be_max_irqs(adapter));
729e261768eSSathya Perla }
730e261768eSSathya Perla 
731e261768eSSathya Perla /* Max irqs *needed* for TX queues */
732e261768eSSathya Perla static inline u16 be_max_tx_irqs(struct be_adapter *adapter)
733e261768eSSathya Perla {
734e261768eSSathya Perla 	return min_t(u16, be_max_txqs(adapter), be_max_irqs(adapter));
735e261768eSSathya Perla }
736e261768eSSathya Perla 
737e261768eSSathya Perla /* Max irqs *needed* for combined queues */
738e261768eSSathya Perla static inline u16 be_max_qp_irqs(struct be_adapter *adapter)
739e261768eSSathya Perla {
740e261768eSSathya Perla 	return min(be_max_tx_irqs(adapter), be_max_rx_irqs(adapter));
741e261768eSSathya Perla }
742e261768eSSathya Perla 
743e261768eSSathya Perla /* Max irqs *needed* for RX and TX queues together */
744e261768eSSathya Perla static inline u16 be_max_any_irqs(struct be_adapter *adapter)
745e261768eSSathya Perla {
746e261768eSSathya Perla 	return max(be_max_tx_irqs(adapter), be_max_rx_irqs(adapter));
74792bf14abSSathya Perla }
74892bf14abSSathya Perla 
749f93f160bSVasundhara Volam /* Is BE in pvid_tagging mode */
750f93f160bSVasundhara Volam #define be_pvid_tagging_enabled(adapter)	(adapter->pvid)
751f93f160bSVasundhara Volam 
752f93f160bSVasundhara Volam /* Is BE in QNQ multi-channel mode */
75366064dbcSSuresh Reddy #define be_is_qnq_mode(adapter)		(adapter->function_mode & QNQ_MODE)
754f93f160bSVasundhara Volam 
755ca34fe38SSathya Perla #define lancer_chip(adapter)	(adapter->pdev->device == OC_DEVICE_ID3 || \
756ca34fe38SSathya Perla 				 adapter->pdev->device == OC_DEVICE_ID4)
7579aebddd1SJeff Kirsher 
75876b73530SPadmanabh Ratnakar #define skyhawk_chip(adapter)	(adapter->pdev->device == OC_DEVICE_ID5 || \
75976b73530SPadmanabh Ratnakar 				 adapter->pdev->device == OC_DEVICE_ID6)
760d3bd3a5eSPadmanabh Ratnakar 
761ca34fe38SSathya Perla #define BE3_chip(adapter)	(adapter->pdev->device == BE_DEVICE_ID2 || \
762ca34fe38SSathya Perla 				 adapter->pdev->device == OC_DEVICE_ID2)
763ca34fe38SSathya Perla 
764ca34fe38SSathya Perla #define BE2_chip(adapter)	(adapter->pdev->device == BE_DEVICE_ID1 || \
765ca34fe38SSathya Perla 				 adapter->pdev->device == OC_DEVICE_ID1)
766ca34fe38SSathya Perla 
767ca34fe38SSathya Perla #define BEx_chip(adapter)	(BE3_chip(adapter) || BE2_chip(adapter))
768d3bd3a5eSPadmanabh Ratnakar 
769dbf0f2a7SSathya Perla #define be_roce_supported(adapter)	(skyhawk_chip(adapter) && \
770045508a8SParav Pandit 					(adapter->function_mode & RDMA_ENABLED))
771045508a8SParav Pandit 
7729aebddd1SJeff Kirsher extern const struct ethtool_ops be_ethtool_ops;
7739aebddd1SJeff Kirsher 
7749aebddd1SJeff Kirsher #define msix_enabled(adapter)		(adapter->num_msix_vec > 0)
77510ef9ab4SSathya Perla #define num_irqs(adapter)		(msix_enabled(adapter) ?	\
77610ef9ab4SSathya Perla 						adapter->num_msix_vec : 1)
77710ef9ab4SSathya Perla #define tx_stats(txo)			(&(txo)->stats)
77810ef9ab4SSathya Perla #define rx_stats(rxo)			(&(rxo)->stats)
7799aebddd1SJeff Kirsher 
78010ef9ab4SSathya Perla /* The default RXQ is the last RXQ */
78110ef9ab4SSathya Perla #define default_rxo(adpt)		(&adpt->rx_obj[adpt->num_rx_qs - 1])
7829aebddd1SJeff Kirsher 
7839aebddd1SJeff Kirsher #define for_all_rx_queues(adapter, rxo, i)				\
7849aebddd1SJeff Kirsher 	for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs;	\
7859aebddd1SJeff Kirsher 		i++, rxo++)
7869aebddd1SJeff Kirsher 
7879aebddd1SJeff Kirsher #define for_all_rss_queues(adapter, rxo, i)				\
78871bb8bd0SVasundhara Volam 	for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rss_qs;	\
7899aebddd1SJeff Kirsher 		i++, rxo++)
7909aebddd1SJeff Kirsher 
7919aebddd1SJeff Kirsher #define for_all_tx_queues(adapter, txo, i)				\
7929aebddd1SJeff Kirsher 	for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs;	\
7939aebddd1SJeff Kirsher 		i++, txo++)
7949aebddd1SJeff Kirsher 
79510ef9ab4SSathya Perla #define for_all_evt_queues(adapter, eqo, i)				\
79610ef9ab4SSathya Perla 	for (i = 0, eqo = &adapter->eq_obj[i]; i < adapter->num_evt_qs; \
79710ef9ab4SSathya Perla 		i++, eqo++)
79810ef9ab4SSathya Perla 
7996384a4d0SSathya Perla #define for_all_rx_queues_on_eq(adapter, eqo, rxo, i)			\
8006384a4d0SSathya Perla 	for (i = eqo->idx, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs;\
8016384a4d0SSathya Perla 		 i += adapter->num_evt_qs, rxo += adapter->num_evt_qs)
8026384a4d0SSathya Perla 
803a4906ea0SSathya Perla #define for_all_tx_queues_on_eq(adapter, eqo, txo, i)			\
804a4906ea0SSathya Perla 	for (i = eqo->idx, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs;\
805a4906ea0SSathya Perla 		i += adapter->num_evt_qs, txo += adapter->num_evt_qs)
806a4906ea0SSathya Perla 
80710ef9ab4SSathya Perla #define is_mcc_eqo(eqo)			(eqo->idx == 0)
80810ef9ab4SSathya Perla #define mcc_eqo(adapter)		(&adapter->eq_obj[0])
80910ef9ab4SSathya Perla 
8109aebddd1SJeff Kirsher #define PAGE_SHIFT_4K		12
8119aebddd1SJeff Kirsher #define PAGE_SIZE_4K		(1 << PAGE_SHIFT_4K)
8129aebddd1SJeff Kirsher 
8139aebddd1SJeff Kirsher /* Returns number of pages spanned by the data starting at the given addr */
8149aebddd1SJeff Kirsher #define PAGES_4K_SPANNED(_address, size) 				\
8159aebddd1SJeff Kirsher 		((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + 	\
8169aebddd1SJeff Kirsher 			(size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
8179aebddd1SJeff Kirsher 
8189aebddd1SJeff Kirsher /* Returns bit offset within a DWORD of a bitfield */
8199aebddd1SJeff Kirsher #define AMAP_BIT_OFFSET(_struct, field)  				\
8209aebddd1SJeff Kirsher 		(((size_t)&(((_struct *)0)->field))%32)
8219aebddd1SJeff Kirsher 
8229aebddd1SJeff Kirsher /* Returns the bit mask of the field that is NOT shifted into location. */
8239aebddd1SJeff Kirsher static inline u32 amap_mask(u32 bitsize)
8249aebddd1SJeff Kirsher {
8259aebddd1SJeff Kirsher 	return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
8269aebddd1SJeff Kirsher }
8279aebddd1SJeff Kirsher 
8289aebddd1SJeff Kirsher static inline void
8299aebddd1SJeff Kirsher amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
8309aebddd1SJeff Kirsher {
8319aebddd1SJeff Kirsher 	u32 *dw = (u32 *) ptr + dw_offset;
8329aebddd1SJeff Kirsher 	*dw &= ~(mask << offset);
8339aebddd1SJeff Kirsher 	*dw |= (mask & value) << offset;
8349aebddd1SJeff Kirsher }
8359aebddd1SJeff Kirsher 
8369aebddd1SJeff Kirsher #define AMAP_SET_BITS(_struct, field, ptr, val)				\
8379aebddd1SJeff Kirsher 		amap_set(ptr,						\
8389aebddd1SJeff Kirsher 			offsetof(_struct, field)/32,			\
8399aebddd1SJeff Kirsher 			amap_mask(sizeof(((_struct *)0)->field)),	\
8409aebddd1SJeff Kirsher 			AMAP_BIT_OFFSET(_struct, field),		\
8419aebddd1SJeff Kirsher 			val)
8429aebddd1SJeff Kirsher 
8439aebddd1SJeff Kirsher static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
8449aebddd1SJeff Kirsher {
8459aebddd1SJeff Kirsher 	u32 *dw = (u32 *) ptr;
8469aebddd1SJeff Kirsher 	return mask & (*(dw + dw_offset) >> offset);
8479aebddd1SJeff Kirsher }
8489aebddd1SJeff Kirsher 
8499aebddd1SJeff Kirsher #define AMAP_GET_BITS(_struct, field, ptr)				\
8509aebddd1SJeff Kirsher 		amap_get(ptr,						\
8519aebddd1SJeff Kirsher 			offsetof(_struct, field)/32,			\
8529aebddd1SJeff Kirsher 			amap_mask(sizeof(((_struct *)0)->field)),	\
8539aebddd1SJeff Kirsher 			AMAP_BIT_OFFSET(_struct, field))
8549aebddd1SJeff Kirsher 
855c3c18bc1SSathya Perla #define GET_RX_COMPL_V0_BITS(field, ptr)				\
856c3c18bc1SSathya Perla 		AMAP_GET_BITS(struct amap_eth_rx_compl_v0, field, ptr)
857c3c18bc1SSathya Perla 
858c3c18bc1SSathya Perla #define GET_RX_COMPL_V1_BITS(field, ptr)				\
859c3c18bc1SSathya Perla 		AMAP_GET_BITS(struct amap_eth_rx_compl_v1, field, ptr)
860c3c18bc1SSathya Perla 
861c3c18bc1SSathya Perla #define GET_TX_COMPL_BITS(field, ptr)					\
862c3c18bc1SSathya Perla 		AMAP_GET_BITS(struct amap_eth_tx_compl, field, ptr)
863c3c18bc1SSathya Perla 
864c3c18bc1SSathya Perla #define SET_TX_WRB_HDR_BITS(field, ptr, val)				\
865c3c18bc1SSathya Perla 		AMAP_SET_BITS(struct amap_eth_hdr_wrb, field, ptr, val)
866c3c18bc1SSathya Perla 
8679aebddd1SJeff Kirsher #define be_dws_cpu_to_le(wrb, len)	swap_dws(wrb, len)
8689aebddd1SJeff Kirsher #define be_dws_le_to_cpu(wrb, len)	swap_dws(wrb, len)
8699aebddd1SJeff Kirsher static inline void swap_dws(void *wrb, int len)
8709aebddd1SJeff Kirsher {
8719aebddd1SJeff Kirsher #ifdef __BIG_ENDIAN
8729aebddd1SJeff Kirsher 	u32 *dw = wrb;
8739aebddd1SJeff Kirsher 	BUG_ON(len % 4);
8749aebddd1SJeff Kirsher 	do {
8759aebddd1SJeff Kirsher 		*dw = cpu_to_le32(*dw);
8769aebddd1SJeff Kirsher 		dw++;
8779aebddd1SJeff Kirsher 		len -= 4;
8789aebddd1SJeff Kirsher 	} while (len);
8799aebddd1SJeff Kirsher #endif				/* __BIG_ENDIAN */
8809aebddd1SJeff Kirsher }
8819aebddd1SJeff Kirsher 
8820532d4e3SKalesh AP #define be_cmd_status(status)		(status > 0 ? -EIO : status)
8830532d4e3SKalesh AP 
8849aebddd1SJeff Kirsher static inline u8 is_tcp_pkt(struct sk_buff *skb)
8859aebddd1SJeff Kirsher {
8869aebddd1SJeff Kirsher 	u8 val = 0;
8879aebddd1SJeff Kirsher 
8889aebddd1SJeff Kirsher 	if (ip_hdr(skb)->version == 4)
8899aebddd1SJeff Kirsher 		val = (ip_hdr(skb)->protocol == IPPROTO_TCP);
8909aebddd1SJeff Kirsher 	else if (ip_hdr(skb)->version == 6)
8919aebddd1SJeff Kirsher 		val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP);
8929aebddd1SJeff Kirsher 
8939aebddd1SJeff Kirsher 	return val;
8949aebddd1SJeff Kirsher }
8959aebddd1SJeff Kirsher 
8969aebddd1SJeff Kirsher static inline u8 is_udp_pkt(struct sk_buff *skb)
8979aebddd1SJeff Kirsher {
8989aebddd1SJeff Kirsher 	u8 val = 0;
8999aebddd1SJeff Kirsher 
9009aebddd1SJeff Kirsher 	if (ip_hdr(skb)->version == 4)
9019aebddd1SJeff Kirsher 		val = (ip_hdr(skb)->protocol == IPPROTO_UDP);
9029aebddd1SJeff Kirsher 	else if (ip_hdr(skb)->version == 6)
9039aebddd1SJeff Kirsher 		val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP);
9049aebddd1SJeff Kirsher 
9059aebddd1SJeff Kirsher 	return val;
9069aebddd1SJeff Kirsher }
9079aebddd1SJeff Kirsher 
90893040ae5SSomnath Kotur static inline bool is_ipv4_pkt(struct sk_buff *skb)
90993040ae5SSomnath Kotur {
910e8efcec5SLi RongQing 	return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
91193040ae5SSomnath Kotur }
91293040ae5SSomnath Kotur 
913822f8565SSuresh Reddy static inline bool is_ipv6_ext_hdr(struct sk_buff *skb)
914822f8565SSuresh Reddy {
915822f8565SSuresh Reddy 	if (ip_hdr(skb)->version == 6)
916822f8565SSuresh Reddy 		return ipv6_ext_hdr(ipv6_hdr(skb)->nexthdr);
917822f8565SSuresh Reddy 	else
918822f8565SSuresh Reddy 		return false;
919822f8565SSuresh Reddy }
920822f8565SSuresh Reddy 
921710f3e59SSriharsha Basavapatna #define be_error_recovering(adapter)	\
922710f3e59SSriharsha Basavapatna 		(adapter->flags & BE_FLAGS_TRY_RECOVERY)
923710f3e59SSriharsha Basavapatna 
924954f6825SVenkata Duvvuru #define BE_ERROR_EEH		1
925954f6825SVenkata Duvvuru #define BE_ERROR_UE		BIT(1)
926954f6825SVenkata Duvvuru #define BE_ERROR_FW		BIT(2)
927ffc39620SSuresh Reddy #define BE_ERROR_TX		BIT(3)
928ffc39620SSuresh Reddy #define BE_ERROR_HW		(BE_ERROR_EEH | BE_ERROR_UE | BE_ERROR_TX)
929ffc39620SSuresh Reddy #define BE_ERROR_ANY		(BE_ERROR_EEH | BE_ERROR_UE | BE_ERROR_FW | \
930ffc39620SSuresh Reddy 				 BE_ERROR_TX)
931954f6825SVenkata Duvvuru #define BE_CLEAR_ALL		0xFF
932954f6825SVenkata Duvvuru 
933954f6825SVenkata Duvvuru static inline u8 be_check_error(struct be_adapter *adapter, u32 err_type)
934954f6825SVenkata Duvvuru {
935954f6825SVenkata Duvvuru 	return (adapter->err_flags & err_type);
936954f6825SVenkata Duvvuru }
937954f6825SVenkata Duvvuru 
938954f6825SVenkata Duvvuru static inline void be_set_error(struct be_adapter *adapter, int err_type)
939954f6825SVenkata Duvvuru {
940954f6825SVenkata Duvvuru 	struct net_device *netdev = adapter->netdev;
941954f6825SVenkata Duvvuru 
942954f6825SVenkata Duvvuru 	adapter->err_flags |= err_type;
943954f6825SVenkata Duvvuru 	netif_carrier_off(netdev);
944954f6825SVenkata Duvvuru 
945954f6825SVenkata Duvvuru 	dev_info(&adapter->pdev->dev, "%s: Link down\n", netdev->name);
946954f6825SVenkata Duvvuru }
947954f6825SVenkata Duvvuru 
948954f6825SVenkata Duvvuru static inline void  be_clear_error(struct be_adapter *adapter, int err_type)
949954f6825SVenkata Duvvuru {
950954f6825SVenkata Duvvuru 	adapter->err_flags &= ~err_type;
951954f6825SVenkata Duvvuru }
952954f6825SVenkata Duvvuru 
9539aebddd1SJeff Kirsher static inline bool be_multi_rxq(const struct be_adapter *adapter)
9549aebddd1SJeff Kirsher {
9559aebddd1SJeff Kirsher 	return adapter->num_rx_qs > 1;
9569aebddd1SJeff Kirsher }
9579aebddd1SJeff Kirsher 
95831886e87SJoe Perches void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm,
9599aebddd1SJeff Kirsher 		  u16 num_popped);
96031886e87SJoe Perches void be_link_status_update(struct be_adapter *adapter, u8 link_status);
96131886e87SJoe Perches void be_parse_stats(struct be_adapter *adapter);
96231886e87SJoe Perches int be_load_fw(struct be_adapter *adapter, u8 *func);
96331886e87SJoe Perches bool be_is_wol_supported(struct be_adapter *adapter);
96431886e87SJoe Perches bool be_pause_supported(struct be_adapter *adapter);
96531886e87SJoe Perches u32 be_get_fw_log_level(struct be_adapter *adapter);
96668d7bdcbSSathya Perla int be_update_queues(struct be_adapter *adapter);
96768d7bdcbSSathya Perla int be_poll(struct napi_struct *napi, int budget);
96820947770SPadmanabh Ratnakar void be_eqd_update(struct be_adapter *adapter, bool force_update);
969941a77d5SSomnath Kotur 
970045508a8SParav Pandit /*
971045508a8SParav Pandit  * internal function to initialize-cleanup roce device.
972045508a8SParav Pandit  */
97331886e87SJoe Perches void be_roce_dev_add(struct be_adapter *);
97431886e87SJoe Perches void be_roce_dev_remove(struct be_adapter *);
975045508a8SParav Pandit 
976045508a8SParav Pandit /*
977045508a8SParav Pandit  * internal function to open-close roce device during ifup-ifdown.
978045508a8SParav Pandit  */
979d114f99aSDevesh Sharma void be_roce_dev_shutdown(struct be_adapter *);
980045508a8SParav Pandit 
9819aebddd1SJeff Kirsher #endif				/* BE_H */
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