19aebddd1SJeff Kirsher /* 2d19261b8SVasundhara Volam * Copyright (C) 2005 - 2015 Emulex 39aebddd1SJeff Kirsher * All rights reserved. 49aebddd1SJeff Kirsher * 59aebddd1SJeff Kirsher * This program is free software; you can redistribute it and/or 69aebddd1SJeff Kirsher * modify it under the terms of the GNU General Public License version 2 79aebddd1SJeff Kirsher * as published by the Free Software Foundation. The full GNU General 89aebddd1SJeff Kirsher * Public License is included in this distribution in the file called COPYING. 99aebddd1SJeff Kirsher * 109aebddd1SJeff Kirsher * Contact Information: 119aebddd1SJeff Kirsher * linux-drivers@emulex.com 129aebddd1SJeff Kirsher * 139aebddd1SJeff Kirsher * Emulex 149aebddd1SJeff Kirsher * 3333 Susan Street 159aebddd1SJeff Kirsher * Costa Mesa, CA 92626 169aebddd1SJeff Kirsher */ 179aebddd1SJeff Kirsher 189aebddd1SJeff Kirsher #ifndef BE_H 199aebddd1SJeff Kirsher #define BE_H 209aebddd1SJeff Kirsher 219aebddd1SJeff Kirsher #include <linux/pci.h> 229aebddd1SJeff Kirsher #include <linux/etherdevice.h> 239aebddd1SJeff Kirsher #include <linux/delay.h> 249aebddd1SJeff Kirsher #include <net/tcp.h> 259aebddd1SJeff Kirsher #include <net/ip.h> 269aebddd1SJeff Kirsher #include <net/ipv6.h> 279aebddd1SJeff Kirsher #include <linux/if_vlan.h> 289aebddd1SJeff Kirsher #include <linux/workqueue.h> 299aebddd1SJeff Kirsher #include <linux/interrupt.h> 309aebddd1SJeff Kirsher #include <linux/firmware.h> 319aebddd1SJeff Kirsher #include <linux/slab.h> 329aebddd1SJeff Kirsher #include <linux/u64_stats_sync.h> 33d658d98aSPadmanabh Ratnakar #include <linux/cpumask.h> 349aebddd1SJeff Kirsher 359aebddd1SJeff Kirsher #include "be_hw.h" 36045508a8SParav Pandit #include "be_roce.h" 379aebddd1SJeff Kirsher 38265ec927SSathya Perla #define DRV_VER "10.6.0.1" 399aebddd1SJeff Kirsher #define DRV_NAME "be2net" 4000d3d51eSSarveshwar Bandi #define BE_NAME "Emulex BladeEngine2" 4100d3d51eSSarveshwar Bandi #define BE3_NAME "Emulex BladeEngine3" 4200d3d51eSSarveshwar Bandi #define OC_NAME "Emulex OneConnect" 439aebddd1SJeff Kirsher #define OC_NAME_BE OC_NAME "(be3)" 449aebddd1SJeff Kirsher #define OC_NAME_LANCER OC_NAME "(Lancer)" 45ecedb6aeSAjit Khaparde #define OC_NAME_SH OC_NAME "(Skyhawk)" 46f3effb45SSuresh Reddy #define DRV_DESC "Emulex OneConnect NIC Driver" 479aebddd1SJeff Kirsher 489aebddd1SJeff Kirsher #define BE_VENDOR_ID 0x19a2 499aebddd1SJeff Kirsher #define EMULEX_VENDOR_ID 0x10df 509aebddd1SJeff Kirsher #define BE_DEVICE_ID1 0x211 519aebddd1SJeff Kirsher #define BE_DEVICE_ID2 0x221 529aebddd1SJeff Kirsher #define OC_DEVICE_ID1 0x700 /* Device Id for BE2 cards */ 539aebddd1SJeff Kirsher #define OC_DEVICE_ID2 0x710 /* Device Id for BE3 cards */ 549aebddd1SJeff Kirsher #define OC_DEVICE_ID3 0xe220 /* Device id for Lancer cards */ 559aebddd1SJeff Kirsher #define OC_DEVICE_ID4 0xe228 /* Device id for VF in Lancer */ 56ecedb6aeSAjit Khaparde #define OC_DEVICE_ID5 0x720 /* Device Id for Skyhawk cards */ 5776b73530SPadmanabh Ratnakar #define OC_DEVICE_ID6 0x728 /* Device id for VF in SkyHawk */ 584762f6ceSAjit Khaparde #define OC_SUBSYS_DEVICE_ID1 0xE602 594762f6ceSAjit Khaparde #define OC_SUBSYS_DEVICE_ID2 0xE642 604762f6ceSAjit Khaparde #define OC_SUBSYS_DEVICE_ID3 0xE612 614762f6ceSAjit Khaparde #define OC_SUBSYS_DEVICE_ID4 0xE652 629aebddd1SJeff Kirsher 639aebddd1SJeff Kirsher /* Number of bytes of an RX frame that are copied to skb->data */ 649aebddd1SJeff Kirsher #define BE_HDR_LEN ((u16) 64) 65bb349bb4SEric Dumazet /* allocate extra space to allow tunneling decapsulation without head reallocation */ 66bb349bb4SEric Dumazet #define BE_RX_SKB_ALLOC_SIZE (BE_HDR_LEN + 64) 67bb349bb4SEric Dumazet 689aebddd1SJeff Kirsher #define BE_MAX_JUMBO_FRAME_SIZE 9018 699aebddd1SJeff Kirsher #define BE_MIN_MTU 256 700d3f5cceSKalesh AP #define BE_MAX_MTU (BE_MAX_JUMBO_FRAME_SIZE - \ 710d3f5cceSKalesh AP (ETH_HLEN + ETH_FCS_LEN)) 729aebddd1SJeff Kirsher 739aebddd1SJeff Kirsher #define BE_NUM_VLANS_SUPPORTED 64 742632bafdSSathya Perla #define BE_MAX_EQD 128u 759aebddd1SJeff Kirsher #define BE_MAX_TX_FRAG_COUNT 30 769aebddd1SJeff Kirsher 779aebddd1SJeff Kirsher #define EVNT_Q_LEN 1024 789aebddd1SJeff Kirsher #define TX_Q_LEN 2048 799aebddd1SJeff Kirsher #define TX_CQ_LEN 1024 809aebddd1SJeff Kirsher #define RX_Q_LEN 1024 /* Does not support any other value */ 819aebddd1SJeff Kirsher #define RX_CQ_LEN 1024 829aebddd1SJeff Kirsher #define MCC_Q_LEN 128 /* total size not to exceed 8 pages */ 839aebddd1SJeff Kirsher #define MCC_CQ_LEN 256 849aebddd1SJeff Kirsher 8510ef9ab4SSathya Perla #define BE2_MAX_RSS_QS 4 8668d7bdcbSSathya Perla #define BE3_MAX_RSS_QS 16 8768d7bdcbSSathya Perla #define BE3_MAX_TX_QS 16 8868d7bdcbSSathya Perla #define BE3_MAX_EVT_QS 16 89e3dc867cSSuresh Reddy #define BE3_SRIOV_MAX_EVT_QS 8 9010ef9ab4SSathya Perla 91f2858738SVasundhara Volam #define MAX_RSS_IFACES 15 9268d7bdcbSSathya Perla #define MAX_RX_QS 32 9368d7bdcbSSathya Perla #define MAX_EVT_QS 32 9468d7bdcbSSathya Perla #define MAX_TX_QS 32 9568d7bdcbSSathya Perla 96045508a8SParav Pandit #define MAX_ROCE_EQS 5 9768d7bdcbSSathya Perla #define MAX_MSIX_VECTORS 32 9892bf14abSSathya Perla #define MIN_MSIX_VECTORS 1 999aebddd1SJeff Kirsher #define BE_NAPI_WEIGHT 64 1009aebddd1SJeff Kirsher #define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */ 1019aebddd1SJeff Kirsher #define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST) 10269304cc9SAjit Khaparde #define MAX_NUM_POST_ERX_DB 255u 1039aebddd1SJeff Kirsher 1047c5a5242SVasundhara Volam #define MAX_VFS 30 /* Max VFs supported by BE3 FW */ 1059aebddd1SJeff Kirsher #define FW_VER_LEN 32 1069aebddd1SJeff Kirsher 107e2557877SVenkata Duvvuru #define RSS_INDIR_TABLE_LEN 128 108e2557877SVenkata Duvvuru #define RSS_HASH_KEY_LEN 40 109e2557877SVenkata Duvvuru 1109aebddd1SJeff Kirsher struct be_dma_mem { 1119aebddd1SJeff Kirsher void *va; 1129aebddd1SJeff Kirsher dma_addr_t dma; 1139aebddd1SJeff Kirsher u32 size; 1149aebddd1SJeff Kirsher }; 1159aebddd1SJeff Kirsher 1169aebddd1SJeff Kirsher struct be_queue_info { 1179aebddd1SJeff Kirsher struct be_dma_mem dma_mem; 1189aebddd1SJeff Kirsher u16 len; 1199aebddd1SJeff Kirsher u16 entry_size; /* Size of an element in the queue */ 1209aebddd1SJeff Kirsher u16 id; 1219aebddd1SJeff Kirsher u16 tail, head; 1229aebddd1SJeff Kirsher bool created; 1239aebddd1SJeff Kirsher atomic_t used; /* Number of valid elements in the queue */ 1249aebddd1SJeff Kirsher }; 1259aebddd1SJeff Kirsher 1269aebddd1SJeff Kirsher static inline u32 MODULO(u16 val, u16 limit) 1279aebddd1SJeff Kirsher { 1289aebddd1SJeff Kirsher BUG_ON(limit & (limit - 1)); 1299aebddd1SJeff Kirsher return val & (limit - 1); 1309aebddd1SJeff Kirsher } 1319aebddd1SJeff Kirsher 1329aebddd1SJeff Kirsher static inline void index_adv(u16 *index, u16 val, u16 limit) 1339aebddd1SJeff Kirsher { 1349aebddd1SJeff Kirsher *index = MODULO((*index + val), limit); 1359aebddd1SJeff Kirsher } 1369aebddd1SJeff Kirsher 1379aebddd1SJeff Kirsher static inline void index_inc(u16 *index, u16 limit) 1389aebddd1SJeff Kirsher { 1399aebddd1SJeff Kirsher *index = MODULO((*index + 1), limit); 1409aebddd1SJeff Kirsher } 1419aebddd1SJeff Kirsher 1429aebddd1SJeff Kirsher static inline void *queue_head_node(struct be_queue_info *q) 1439aebddd1SJeff Kirsher { 1449aebddd1SJeff Kirsher return q->dma_mem.va + q->head * q->entry_size; 1459aebddd1SJeff Kirsher } 1469aebddd1SJeff Kirsher 1479aebddd1SJeff Kirsher static inline void *queue_tail_node(struct be_queue_info *q) 1489aebddd1SJeff Kirsher { 1499aebddd1SJeff Kirsher return q->dma_mem.va + q->tail * q->entry_size; 1509aebddd1SJeff Kirsher } 1519aebddd1SJeff Kirsher 1523de09455SSomnath Kotur static inline void *queue_index_node(struct be_queue_info *q, u16 index) 1533de09455SSomnath Kotur { 1543de09455SSomnath Kotur return q->dma_mem.va + index * q->entry_size; 1553de09455SSomnath Kotur } 1563de09455SSomnath Kotur 1579aebddd1SJeff Kirsher static inline void queue_head_inc(struct be_queue_info *q) 1589aebddd1SJeff Kirsher { 1599aebddd1SJeff Kirsher index_inc(&q->head, q->len); 1609aebddd1SJeff Kirsher } 1619aebddd1SJeff Kirsher 162652bf646SPadmanabh Ratnakar static inline void index_dec(u16 *index, u16 limit) 163652bf646SPadmanabh Ratnakar { 164652bf646SPadmanabh Ratnakar *index = MODULO((*index - 1), limit); 165652bf646SPadmanabh Ratnakar } 166652bf646SPadmanabh Ratnakar 1679aebddd1SJeff Kirsher static inline void queue_tail_inc(struct be_queue_info *q) 1689aebddd1SJeff Kirsher { 1699aebddd1SJeff Kirsher index_inc(&q->tail, q->len); 1709aebddd1SJeff Kirsher } 1719aebddd1SJeff Kirsher 1729aebddd1SJeff Kirsher struct be_eq_obj { 1739aebddd1SJeff Kirsher struct be_queue_info q; 1749aebddd1SJeff Kirsher char desc[32]; 1759aebddd1SJeff Kirsher 1769aebddd1SJeff Kirsher /* Adaptive interrupt coalescing (AIC) info */ 1779aebddd1SJeff Kirsher bool enable_aic; 17810ef9ab4SSathya Perla u32 min_eqd; /* in usecs */ 17910ef9ab4SSathya Perla u32 max_eqd; /* in usecs */ 18010ef9ab4SSathya Perla u32 eqd; /* configured val when aic is off */ 18110ef9ab4SSathya Perla u32 cur_eqd; /* in usecs */ 1829aebddd1SJeff Kirsher 18310ef9ab4SSathya Perla u8 idx; /* array index */ 184f2f781a7SSathya Perla u8 msix_idx; 185d0b9cec3SSathya Perla u16 spurious_intr; 1869aebddd1SJeff Kirsher struct napi_struct napi; 18710ef9ab4SSathya Perla struct be_adapter *adapter; 188d658d98aSPadmanabh Ratnakar cpumask_var_t affinity_mask; 1896384a4d0SSathya Perla 1906384a4d0SSathya Perla #ifdef CONFIG_NET_RX_BUSY_POLL 1916384a4d0SSathya Perla #define BE_EQ_IDLE 0 1926384a4d0SSathya Perla #define BE_EQ_NAPI 1 /* napi owns this EQ */ 1936384a4d0SSathya Perla #define BE_EQ_POLL 2 /* poll owns this EQ */ 1946384a4d0SSathya Perla #define BE_EQ_LOCKED (BE_EQ_NAPI | BE_EQ_POLL) 1956384a4d0SSathya Perla #define BE_EQ_NAPI_YIELD 4 /* napi yielded this EQ */ 1966384a4d0SSathya Perla #define BE_EQ_POLL_YIELD 8 /* poll yielded this EQ */ 1976384a4d0SSathya Perla #define BE_EQ_YIELD (BE_EQ_NAPI_YIELD | BE_EQ_POLL_YIELD) 1986384a4d0SSathya Perla #define BE_EQ_USER_PEND (BE_EQ_POLL | BE_EQ_POLL_YIELD) 1996384a4d0SSathya Perla unsigned int state; 2006384a4d0SSathya Perla spinlock_t lock; /* lock to serialize napi and busy-poll */ 2016384a4d0SSathya Perla #endif /* CONFIG_NET_RX_BUSY_POLL */ 20210ef9ab4SSathya Perla } ____cacheline_aligned_in_smp; 2039aebddd1SJeff Kirsher 2042632bafdSSathya Perla struct be_aic_obj { /* Adaptive interrupt coalescing (AIC) info */ 2052632bafdSSathya Perla bool enable; 2062632bafdSSathya Perla u32 min_eqd; /* in usecs */ 2072632bafdSSathya Perla u32 max_eqd; /* in usecs */ 2082632bafdSSathya Perla u32 prev_eqd; /* in usecs */ 2092632bafdSSathya Perla u32 et_eqd; /* configured val when aic is off */ 2102632bafdSSathya Perla ulong jiffies; 2112632bafdSSathya Perla u64 rx_pkts_prev; /* Used to calculate RX pps */ 2122632bafdSSathya Perla u64 tx_reqs_prev; /* Used to calculate TX pps */ 2132632bafdSSathya Perla }; 2142632bafdSSathya Perla 2156384a4d0SSathya Perla enum { 2166384a4d0SSathya Perla NAPI_POLLING, 2176384a4d0SSathya Perla BUSY_POLLING 2186384a4d0SSathya Perla }; 2196384a4d0SSathya Perla 2209aebddd1SJeff Kirsher struct be_mcc_obj { 2219aebddd1SJeff Kirsher struct be_queue_info q; 2229aebddd1SJeff Kirsher struct be_queue_info cq; 2239aebddd1SJeff Kirsher bool rearm_cq; 2249aebddd1SJeff Kirsher }; 2259aebddd1SJeff Kirsher 2269aebddd1SJeff Kirsher struct be_tx_stats { 2279aebddd1SJeff Kirsher u64 tx_bytes; 2289aebddd1SJeff Kirsher u64 tx_pkts; 2299aebddd1SJeff Kirsher u64 tx_reqs; 2309aebddd1SJeff Kirsher u64 tx_compl; 2319aebddd1SJeff Kirsher ulong tx_jiffies; 2329aebddd1SJeff Kirsher u32 tx_stops; 233bc617526SSathya Perla u32 tx_drv_drops; /* pkts dropped by driver */ 234512bb8a2SKalesh AP /* the error counters are described in be_ethtool.c */ 235512bb8a2SKalesh AP u32 tx_hdr_parse_err; 236512bb8a2SKalesh AP u32 tx_dma_err; 237512bb8a2SKalesh AP u32 tx_tso_err; 238512bb8a2SKalesh AP u32 tx_spoof_check_err; 239512bb8a2SKalesh AP u32 tx_qinq_err; 240512bb8a2SKalesh AP u32 tx_internal_parity_err; 2419aebddd1SJeff Kirsher struct u64_stats_sync sync; 2429aebddd1SJeff Kirsher struct u64_stats_sync sync_compl; 2439aebddd1SJeff Kirsher }; 2449aebddd1SJeff Kirsher 245152ffe5bSSriharsha Basavapatna /* Structure to hold some data of interest obtained from a TX CQE */ 246152ffe5bSSriharsha Basavapatna struct be_tx_compl_info { 247152ffe5bSSriharsha Basavapatna u8 status; /* Completion status */ 248152ffe5bSSriharsha Basavapatna u16 end_index; /* Completed TXQ Index */ 249152ffe5bSSriharsha Basavapatna }; 250152ffe5bSSriharsha Basavapatna 2519aebddd1SJeff Kirsher struct be_tx_obj { 25294d73aaaSVasundhara Volam u32 db_offset; 2539aebddd1SJeff Kirsher struct be_queue_info q; 2549aebddd1SJeff Kirsher struct be_queue_info cq; 255152ffe5bSSriharsha Basavapatna struct be_tx_compl_info txcp; 2569aebddd1SJeff Kirsher /* Remember the skbs that were transmitted */ 2579aebddd1SJeff Kirsher struct sk_buff *sent_skb_list[TX_Q_LEN]; 2589aebddd1SJeff Kirsher struct be_tx_stats stats; 2595f07b3c5SSathya Perla u16 pend_wrb_cnt; /* Number of WRBs yet to be given to HW */ 2605f07b3c5SSathya Perla u16 last_req_wrb_cnt; /* wrb cnt of the last req in the Q */ 2615f07b3c5SSathya Perla u16 last_req_hdr; /* index of the last req's hdr-wrb */ 26210ef9ab4SSathya Perla } ____cacheline_aligned_in_smp; 2639aebddd1SJeff Kirsher 2649aebddd1SJeff Kirsher /* Struct to remember the pages posted for rx frags */ 2659aebddd1SJeff Kirsher struct be_rx_page_info { 2669aebddd1SJeff Kirsher struct page *page; 267e50287beSSathya Perla /* set to page-addr for last frag of the page & frag-addr otherwise */ 2689aebddd1SJeff Kirsher DEFINE_DMA_UNMAP_ADDR(bus); 2699aebddd1SJeff Kirsher u16 page_offset; 270e50287beSSathya Perla bool last_frag; /* last frag of the page */ 2719aebddd1SJeff Kirsher }; 2729aebddd1SJeff Kirsher 2739aebddd1SJeff Kirsher struct be_rx_stats { 2749aebddd1SJeff Kirsher u64 rx_bytes; 2759aebddd1SJeff Kirsher u64 rx_pkts; 2769aebddd1SJeff Kirsher u32 rx_drops_no_skbs; /* skb allocation errors */ 2779aebddd1SJeff Kirsher u32 rx_drops_no_frags; /* HW has no fetched frags */ 2789aebddd1SJeff Kirsher u32 rx_post_fail; /* page post alloc failures */ 2799aebddd1SJeff Kirsher u32 rx_compl; 2809aebddd1SJeff Kirsher u32 rx_mcast_pkts; 2819aebddd1SJeff Kirsher u32 rx_compl_err; /* completions with err set */ 2829aebddd1SJeff Kirsher struct u64_stats_sync sync; 2839aebddd1SJeff Kirsher }; 2849aebddd1SJeff Kirsher 2859aebddd1SJeff Kirsher struct be_rx_compl_info { 2869aebddd1SJeff Kirsher u32 rss_hash; 2879aebddd1SJeff Kirsher u16 vlan_tag; 2889aebddd1SJeff Kirsher u16 pkt_size; 2899aebddd1SJeff Kirsher u16 port; 2909aebddd1SJeff Kirsher u8 vlanf; 2919aebddd1SJeff Kirsher u8 num_rcvd; 2929aebddd1SJeff Kirsher u8 err; 2939aebddd1SJeff Kirsher u8 ipf; 2949aebddd1SJeff Kirsher u8 tcpf; 2959aebddd1SJeff Kirsher u8 udpf; 2969aebddd1SJeff Kirsher u8 ip_csum; 2979aebddd1SJeff Kirsher u8 l4_csum; 2989aebddd1SJeff Kirsher u8 ipv6; 299f93f160bSVasundhara Volam u8 qnq; 3009aebddd1SJeff Kirsher u8 pkt_type; 301e38b1706SSomnath Kotur u8 ip_frag; 302c9c47142SSathya Perla u8 tunneled; 3039aebddd1SJeff Kirsher }; 3049aebddd1SJeff Kirsher 3059aebddd1SJeff Kirsher struct be_rx_obj { 3069aebddd1SJeff Kirsher struct be_adapter *adapter; 3079aebddd1SJeff Kirsher struct be_queue_info q; 3089aebddd1SJeff Kirsher struct be_queue_info cq; 3099aebddd1SJeff Kirsher struct be_rx_compl_info rxcp; 3109aebddd1SJeff Kirsher struct be_rx_page_info page_info_tbl[RX_Q_LEN]; 3119aebddd1SJeff Kirsher struct be_rx_stats stats; 3129aebddd1SJeff Kirsher u8 rss_id; 3139aebddd1SJeff Kirsher bool rx_post_starved; /* Zero rx frags have been posted to BE */ 31410ef9ab4SSathya Perla } ____cacheline_aligned_in_smp; 3159aebddd1SJeff Kirsher 3169aebddd1SJeff Kirsher struct be_drv_stats { 3179ae081c6SSomnath Kotur u32 be_on_die_temperature; 3189aebddd1SJeff Kirsher u32 eth_red_drops; 319d3de1540SVasundhara Volam u32 dma_map_errors; 3209aebddd1SJeff Kirsher u32 rx_drops_no_pbuf; 3219aebddd1SJeff Kirsher u32 rx_drops_no_txpb; 3229aebddd1SJeff Kirsher u32 rx_drops_no_erx_descr; 3239aebddd1SJeff Kirsher u32 rx_drops_no_tpre_descr; 3249aebddd1SJeff Kirsher u32 rx_drops_too_many_frags; 3259aebddd1SJeff Kirsher u32 forwarded_packets; 3269aebddd1SJeff Kirsher u32 rx_drops_mtu; 3279aebddd1SJeff Kirsher u32 rx_crc_errors; 3289aebddd1SJeff Kirsher u32 rx_alignment_symbol_errors; 3299aebddd1SJeff Kirsher u32 rx_pause_frames; 3309aebddd1SJeff Kirsher u32 rx_priority_pause_frames; 3319aebddd1SJeff Kirsher u32 rx_control_frames; 3329aebddd1SJeff Kirsher u32 rx_in_range_errors; 3339aebddd1SJeff Kirsher u32 rx_out_range_errors; 3349aebddd1SJeff Kirsher u32 rx_frame_too_long; 33518fb06a1SSuresh Reddy u32 rx_address_filtered; 3369aebddd1SJeff Kirsher u32 rx_dropped_too_small; 3379aebddd1SJeff Kirsher u32 rx_dropped_too_short; 3389aebddd1SJeff Kirsher u32 rx_dropped_header_too_small; 3399aebddd1SJeff Kirsher u32 rx_dropped_tcp_length; 3409aebddd1SJeff Kirsher u32 rx_dropped_runt; 3419aebddd1SJeff Kirsher u32 rx_ip_checksum_errs; 3429aebddd1SJeff Kirsher u32 rx_tcp_checksum_errs; 3439aebddd1SJeff Kirsher u32 rx_udp_checksum_errs; 3449aebddd1SJeff Kirsher u32 tx_pauseframes; 3459aebddd1SJeff Kirsher u32 tx_priority_pauseframes; 3469aebddd1SJeff Kirsher u32 tx_controlframes; 3479aebddd1SJeff Kirsher u32 rxpp_fifo_overflow_drop; 3489aebddd1SJeff Kirsher u32 rx_input_fifo_overflow_drop; 3499aebddd1SJeff Kirsher u32 pmem_fifo_overflow_drop; 3509aebddd1SJeff Kirsher u32 jabber_events; 351461ae379SAjit Khaparde u32 rx_roce_bytes_lsd; 352461ae379SAjit Khaparde u32 rx_roce_bytes_msd; 353461ae379SAjit Khaparde u32 rx_roce_frames; 354461ae379SAjit Khaparde u32 roce_drops_payload_len; 355461ae379SAjit Khaparde u32 roce_drops_crc; 3569aebddd1SJeff Kirsher }; 3579aebddd1SJeff Kirsher 358c502224eSSomnath Kotur /* A vlan-id of 0xFFFF must be used to clear transparent vlan-tagging */ 359c502224eSSomnath Kotur #define BE_RESET_VLAN_TAG_ID 0xFFFF 360c502224eSSomnath Kotur 3619aebddd1SJeff Kirsher struct be_vf_cfg { 36211ac75edSSathya Perla unsigned char mac_addr[ETH_ALEN]; 36311ac75edSSathya Perla int if_handle; 36411ac75edSSathya Perla int pmac_id; 36511ac75edSSathya Perla u16 vlan_tag; 36611ac75edSSathya Perla u32 tx_rate; 367bdce2ad7SSuresh Reddy u32 plink_tracking; 368435452aaSVasundhara Volam u32 privileges; 369e7bcbd7bSKalesh AP bool spoofchk; 3709aebddd1SJeff Kirsher }; 3719aebddd1SJeff Kirsher 37239f1d94dSSathya Perla enum vf_state { 37339f1d94dSSathya Perla ENABLED = 0, 37439f1d94dSSathya Perla ASSIGNED = 1 37539f1d94dSSathya Perla }; 37639f1d94dSSathya Perla 37783b06116SVasundhara Volam #define BE_FLAGS_LINK_STATUS_INIT BIT(1) 37883b06116SVasundhara Volam #define BE_FLAGS_SRIOV_ENABLED BIT(2) 37983b06116SVasundhara Volam #define BE_FLAGS_WORKER_SCHEDULED BIT(3) 38083b06116SVasundhara Volam #define BE_FLAGS_NAPI_ENABLED BIT(6) 38183b06116SVasundhara Volam #define BE_FLAGS_QNQ_ASYNC_EVT_RCVD BIT(7) 38283b06116SVasundhara Volam #define BE_FLAGS_VXLAN_OFFLOADS BIT(8) 38383b06116SVasundhara Volam #define BE_FLAGS_SETUP_DONE BIT(9) 38421252377SVasundhara Volam #define BE_FLAGS_EVT_INCOMPATIBLE_SFP BIT(10) 385eb7dd46cSSathya Perla #define BE_FLAGS_ERR_DETECTION_SCHEDULED BIT(11) 386c9c47142SSathya Perla 387fbc13f01SAjit Khaparde #define BE_UC_PMAC_COUNT 30 388fbc13f01SAjit Khaparde #define BE_VF_UC_PMAC_COUNT 2 389f0613380SKalesh AP 3905c510811SSomnath Kotur /* Ethtool set_dump flags */ 3915c510811SSomnath Kotur #define LANCER_INITIATE_FW_DUMP 0x1 392f0613380SKalesh AP #define LANCER_DELETE_FW_DUMP 0x2 3935c510811SSomnath Kotur 39442f11cf2SAjit Khaparde struct phy_info { 39521252377SVasundhara Volam /* From SFF-8472 spec */ 39621252377SVasundhara Volam #define SFP_VENDOR_NAME_LEN 17 39742f11cf2SAjit Khaparde u8 transceiver; 39842f11cf2SAjit Khaparde u8 autoneg; 39942f11cf2SAjit Khaparde u8 fc_autoneg; 40042f11cf2SAjit Khaparde u8 port_type; 40142f11cf2SAjit Khaparde u16 phy_type; 40242f11cf2SAjit Khaparde u16 interface_type; 40342f11cf2SAjit Khaparde u32 misc_params; 40442f11cf2SAjit Khaparde u16 auto_speeds_supported; 40542f11cf2SAjit Khaparde u16 fixed_speeds_supported; 40642f11cf2SAjit Khaparde int link_speed; 40742f11cf2SAjit Khaparde u32 advertising; 40842f11cf2SAjit Khaparde u32 supported; 4096809cee0SRavikumar Nelavelli u8 cable_type; 41021252377SVasundhara Volam u8 vendor_name[SFP_VENDOR_NAME_LEN]; 41121252377SVasundhara Volam u8 vendor_pn[SFP_VENDOR_NAME_LEN]; 41242f11cf2SAjit Khaparde }; 41342f11cf2SAjit Khaparde 41492bf14abSSathya Perla struct be_resources { 41592bf14abSSathya Perla u16 max_vfs; /* Total VFs "really" supported by FW/HW */ 41692bf14abSSathya Perla u16 max_mcast_mac; 41792bf14abSSathya Perla u16 max_tx_qs; 41892bf14abSSathya Perla u16 max_rss_qs; 41992bf14abSSathya Perla u16 max_rx_qs; 420f2858738SVasundhara Volam u16 max_cq_count; 42192bf14abSSathya Perla u16 max_uc_mac; /* Max UC MACs programmable */ 42292bf14abSSathya Perla u16 max_vlans; /* Number of vlans supported */ 423f2858738SVasundhara Volam u16 max_iface_count; 424f2858738SVasundhara Volam u16 max_mcc_count; 42592bf14abSSathya Perla u16 max_evt_qs; 42692bf14abSSathya Perla u32 if_cap_flags; 42710cccf60SVasundhara Volam u32 vf_if_cap_flags; /* VF if capability flags */ 42892bf14abSSathya Perla }; 42992bf14abSSathya Perla 430e2557877SVenkata Duvvuru struct rss_info { 431e2557877SVenkata Duvvuru u64 rss_flags; 432e2557877SVenkata Duvvuru u8 rsstable[RSS_INDIR_TABLE_LEN]; 433e2557877SVenkata Duvvuru u8 rss_queue[RSS_INDIR_TABLE_LEN]; 434e2557877SVenkata Duvvuru u8 rss_hkey[RSS_HASH_KEY_LEN]; 435e2557877SVenkata Duvvuru }; 436e2557877SVenkata Duvvuru 437804abcdbSSriharsha Basavapatna /* Macros to read/write the 'features' word of be_wrb_params structure. 438804abcdbSSriharsha Basavapatna */ 439804abcdbSSriharsha Basavapatna #define BE_WRB_F_BIT(name) BE_WRB_F_##name##_BIT 440804abcdbSSriharsha Basavapatna #define BE_WRB_F_MASK(name) BIT_MASK(BE_WRB_F_##name##_BIT) 441804abcdbSSriharsha Basavapatna 442804abcdbSSriharsha Basavapatna #define BE_WRB_F_GET(word, name) \ 443804abcdbSSriharsha Basavapatna (((word) & (BE_WRB_F_MASK(name))) >> BE_WRB_F_BIT(name)) 444804abcdbSSriharsha Basavapatna 445804abcdbSSriharsha Basavapatna #define BE_WRB_F_SET(word, name, val) \ 446804abcdbSSriharsha Basavapatna ((word) |= (((val) << BE_WRB_F_BIT(name)) & BE_WRB_F_MASK(name))) 447804abcdbSSriharsha Basavapatna 448804abcdbSSriharsha Basavapatna /* Feature/offload bits */ 449804abcdbSSriharsha Basavapatna enum { 450804abcdbSSriharsha Basavapatna BE_WRB_F_CRC_BIT, /* Ethernet CRC */ 451804abcdbSSriharsha Basavapatna BE_WRB_F_IPCS_BIT, /* IP csum */ 452804abcdbSSriharsha Basavapatna BE_WRB_F_TCPCS_BIT, /* TCP csum */ 453804abcdbSSriharsha Basavapatna BE_WRB_F_UDPCS_BIT, /* UDP csum */ 454804abcdbSSriharsha Basavapatna BE_WRB_F_LSO_BIT, /* LSO */ 455804abcdbSSriharsha Basavapatna BE_WRB_F_LSO6_BIT, /* LSO6 */ 456804abcdbSSriharsha Basavapatna BE_WRB_F_VLAN_BIT, /* VLAN */ 457804abcdbSSriharsha Basavapatna BE_WRB_F_VLAN_SKIP_HW_BIT /* Skip VLAN tag (workaround) */ 458804abcdbSSriharsha Basavapatna }; 459804abcdbSSriharsha Basavapatna 460804abcdbSSriharsha Basavapatna /* The structure below provides a HW-agnostic abstraction of WRB params 461804abcdbSSriharsha Basavapatna * retrieved from a TX skb. This is in turn passed to chip specific routines 462804abcdbSSriharsha Basavapatna * during transmit, to set the corresponding params in the WRB. 463804abcdbSSriharsha Basavapatna */ 464804abcdbSSriharsha Basavapatna struct be_wrb_params { 465804abcdbSSriharsha Basavapatna u32 features; /* Feature bits */ 466804abcdbSSriharsha Basavapatna u16 vlan_tag; /* VLAN tag */ 467804abcdbSSriharsha Basavapatna u16 lso_mss; /* MSS for LSO */ 468804abcdbSSriharsha Basavapatna }; 469804abcdbSSriharsha Basavapatna 4709aebddd1SJeff Kirsher struct be_adapter { 4719aebddd1SJeff Kirsher struct pci_dev *pdev; 4729aebddd1SJeff Kirsher struct net_device *netdev; 4739aebddd1SJeff Kirsher 474c5b3ad4cSSathya Perla u8 __iomem *csr; /* CSR BAR used only for BE2/3 */ 4759aebddd1SJeff Kirsher u8 __iomem *db; /* Door Bell */ 47625848c90SSuresh Reddy u8 __iomem *pcicfg; /* On SH,BEx only. Shadow of PCI config space */ 4779aebddd1SJeff Kirsher 4789aebddd1SJeff Kirsher struct mutex mbox_lock; /* For serializing mbox cmds to BE card */ 4799aebddd1SJeff Kirsher struct be_dma_mem mbox_mem; 4809aebddd1SJeff Kirsher /* Mbox mem is adjusted to align to 16 bytes. The allocated addr 4819aebddd1SJeff Kirsher * is stored for freeing purpose */ 4829aebddd1SJeff Kirsher struct be_dma_mem mbox_mem_alloced; 4839aebddd1SJeff Kirsher 4849aebddd1SJeff Kirsher struct be_mcc_obj mcc_obj; 4859aebddd1SJeff Kirsher spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */ 4869aebddd1SJeff Kirsher spinlock_t mcc_cq_lock; 4879aebddd1SJeff Kirsher 48892bf14abSSathya Perla u16 cfg_num_qs; /* configured via set-channels */ 48992bf14abSSathya Perla u16 num_evt_qs; 49092bf14abSSathya Perla u16 num_msix_vec; 49192bf14abSSathya Perla struct be_eq_obj eq_obj[MAX_EVT_QS]; 49210ef9ab4SSathya Perla struct msix_entry msix_entries[MAX_MSIX_VECTORS]; 4939aebddd1SJeff Kirsher bool isr_registered; 4949aebddd1SJeff Kirsher 4959aebddd1SJeff Kirsher /* TX Rings */ 49692bf14abSSathya Perla u16 num_tx_qs; 4979aebddd1SJeff Kirsher struct be_tx_obj tx_obj[MAX_TX_QS]; 4989aebddd1SJeff Kirsher 4999aebddd1SJeff Kirsher /* Rx rings */ 50092bf14abSSathya Perla u16 num_rx_qs; 50171bb8bd0SVasundhara Volam u16 num_rss_qs; 50271bb8bd0SVasundhara Volam u16 need_def_rxq; 50310ef9ab4SSathya Perla struct be_rx_obj rx_obj[MAX_RX_QS]; 5049aebddd1SJeff Kirsher u32 big_page_size; /* Compounded page size shared by rx wrbs */ 5059aebddd1SJeff Kirsher 5069aebddd1SJeff Kirsher struct be_drv_stats drv_stats; 5072632bafdSSathya Perla struct be_aic_obj aic_obj[MAX_EVT_QS]; 5089aebddd1SJeff Kirsher u8 vlan_prio_bmap; /* Available Priority BitMap */ 5099aebddd1SJeff Kirsher u16 recommended_prio; /* Recommended Priority */ 5109aebddd1SJeff Kirsher struct be_dma_mem rx_filter; /* Cmd DMA mem for rx-filter */ 5119aebddd1SJeff Kirsher 5129aebddd1SJeff Kirsher struct be_dma_mem stats_cmd; 5139aebddd1SJeff Kirsher /* Work queue used to perform periodic tasks like getting statistics */ 5149aebddd1SJeff Kirsher struct delayed_work work; 5159aebddd1SJeff Kirsher u16 work_counter; 5169aebddd1SJeff Kirsher 517eb7dd46cSSathya Perla struct delayed_work be_err_detection_work; 518b236916aSAjit Khaparde u32 flags; 519f25b119cSPadmanabh Ratnakar u32 cmd_privileges; 5209aebddd1SJeff Kirsher /* Ethtool knobs and info */ 5219aebddd1SJeff Kirsher char fw_ver[FW_VER_LEN]; 522eeb65cedSSomnath Kotur char fw_on_flash[FW_VER_LEN]; 523f66b7cfdSSathya Perla 524f66b7cfdSSathya Perla /* IFACE filtering fields */ 52530128031SSathya Perla int if_handle; /* Used to configure filtering */ 526f66b7cfdSSathya Perla u32 if_flags; /* Interface filtering flags */ 527fbc13f01SAjit Khaparde u32 *pmac_id; /* MAC addr handle used by BE card */ 528f66b7cfdSSathya Perla u32 uc_macs; /* Count of secondary UC MAC programmed */ 529f66b7cfdSSathya Perla unsigned long vids[BITS_TO_LONGS(VLAN_N_VID)]; 530f66b7cfdSSathya Perla u16 vlans_added; 531f66b7cfdSSathya Perla 5329aebddd1SJeff Kirsher u32 beacon_state; /* for set_phys_id */ 5339aebddd1SJeff Kirsher 534f67ef7baSPadmanabh Ratnakar bool eeh_error; 5356589ade0SSathya Perla bool fw_timeout; 536f67ef7baSPadmanabh Ratnakar bool hw_error; 537f67ef7baSPadmanabh Ratnakar 5389aebddd1SJeff Kirsher u32 port_num; 53921252377SVasundhara Volam char port_name; 540f93f160bSVasundhara Volam u8 mc_type; 5419aebddd1SJeff Kirsher u32 function_mode; 5429aebddd1SJeff Kirsher u32 function_caps; 5439aebddd1SJeff Kirsher u32 rx_fc; /* Rx flow control */ 5449aebddd1SJeff Kirsher u32 tx_fc; /* Tx flow control */ 5459aebddd1SJeff Kirsher bool stats_cmd_sent; 546045508a8SParav Pandit struct { 547045508a8SParav Pandit u32 size; 548045508a8SParav Pandit u32 total_size; 549045508a8SParav Pandit u64 io_addr; 550045508a8SParav Pandit } roce_db; 551045508a8SParav Pandit u32 num_msix_roce_vec; 552045508a8SParav Pandit struct ocrdma_dev *ocrdma_dev; 553045508a8SParav Pandit struct list_head entry; 554045508a8SParav Pandit 5559aebddd1SJeff Kirsher u32 flash_status; 5565eeff635SSuresh Reddy struct completion et_cmd_compl; 5579aebddd1SJeff Kirsher 558bec84e6bSVasundhara Volam struct be_resources pool_res; /* resources available for the port */ 55992bf14abSSathya Perla struct be_resources res; /* resources available for the func */ 56092bf14abSSathya Perla u16 num_vfs; /* Number of VFs provisioned by PF */ 56139f1d94dSSathya Perla u8 virtfn; 56211ac75edSSathya Perla struct be_vf_cfg *vf_cfg; 56311ac75edSSathya Perla bool be3_native; 5649aebddd1SJeff Kirsher u32 sli_family; 5659aebddd1SJeff Kirsher u8 hba_port_num; 5669aebddd1SJeff Kirsher u16 pvid; 567c9c47142SSathya Perla __be16 vxlan_port; 568630f4b70SSriharsha Basavapatna int vxlan_port_count; 56942f11cf2SAjit Khaparde struct phy_info phy; 5704762f6ceSAjit Khaparde u8 wol_cap; 57176a9e08eSSuresh Reddy bool wol_en; 5720ad3157eSVasundhara Volam u16 asic_rev; 573bc0c3405SAjit Khaparde u16 qnq_vid; 574941a77d5SSomnath Kotur u32 msg_enable; 5757aeb2156SPadmanabh Ratnakar int be_get_temp_freq; 576d5c18473SPadmanabh Ratnakar u8 pf_number; 577e2557877SVenkata Duvvuru struct rss_info rss_info; 5789aebddd1SJeff Kirsher }; 5799aebddd1SJeff Kirsher 58039f1d94dSSathya Perla #define be_physfn(adapter) (!adapter->virtfn) 5812c7a9dc1SAjit Khaparde #define be_virtfn(adapter) (adapter->virtfn) 582f174c7ecSVasundhara Volam #define sriov_enabled(adapter) (adapter->flags & \ 583f174c7ecSVasundhara Volam BE_FLAGS_SRIOV_ENABLED) 584bec84e6bSVasundhara Volam 58511ac75edSSathya Perla #define for_all_vfs(adapter, vf_cfg, i) \ 58611ac75edSSathya Perla for (i = 0, vf_cfg = &adapter->vf_cfg[i]; i < adapter->num_vfs; \ 58711ac75edSSathya Perla i++, vf_cfg++) 5889aebddd1SJeff Kirsher 5899aebddd1SJeff Kirsher #define ON 1 5909aebddd1SJeff Kirsher #define OFF 0 591ca34fe38SSathya Perla 59292bf14abSSathya Perla #define be_max_vlans(adapter) (adapter->res.max_vlans) 59392bf14abSSathya Perla #define be_max_uc(adapter) (adapter->res.max_uc_mac) 59492bf14abSSathya Perla #define be_max_mc(adapter) (adapter->res.max_mcast_mac) 595bec84e6bSVasundhara Volam #define be_max_vfs(adapter) (adapter->pool_res.max_vfs) 59692bf14abSSathya Perla #define be_max_rss(adapter) (adapter->res.max_rss_qs) 59792bf14abSSathya Perla #define be_max_txqs(adapter) (adapter->res.max_tx_qs) 59892bf14abSSathya Perla #define be_max_prio_txqs(adapter) (adapter->res.max_prio_tx_qs) 59992bf14abSSathya Perla #define be_max_rxqs(adapter) (adapter->res.max_rx_qs) 60092bf14abSSathya Perla #define be_max_eqs(adapter) (adapter->res.max_evt_qs) 60192bf14abSSathya Perla #define be_if_cap_flags(adapter) (adapter->res.if_cap_flags) 60292bf14abSSathya Perla 60392bf14abSSathya Perla static inline u16 be_max_qs(struct be_adapter *adapter) 60492bf14abSSathya Perla { 60592bf14abSSathya Perla /* If no RSS, need atleast the one def RXQ */ 60692bf14abSSathya Perla u16 num = max_t(u16, be_max_rss(adapter), 1); 60792bf14abSSathya Perla 60892bf14abSSathya Perla num = min(num, be_max_eqs(adapter)); 60992bf14abSSathya Perla return min_t(u16, num, num_online_cpus()); 61092bf14abSSathya Perla } 61192bf14abSSathya Perla 612f93f160bSVasundhara Volam /* Is BE in pvid_tagging mode */ 613f93f160bSVasundhara Volam #define be_pvid_tagging_enabled(adapter) (adapter->pvid) 614f93f160bSVasundhara Volam 615f93f160bSVasundhara Volam /* Is BE in QNQ multi-channel mode */ 61666064dbcSSuresh Reddy #define be_is_qnq_mode(adapter) (adapter->function_mode & QNQ_MODE) 617f93f160bSVasundhara Volam 618ca34fe38SSathya Perla #define lancer_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID3 || \ 619ca34fe38SSathya Perla adapter->pdev->device == OC_DEVICE_ID4) 6209aebddd1SJeff Kirsher 62176b73530SPadmanabh Ratnakar #define skyhawk_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID5 || \ 62276b73530SPadmanabh Ratnakar adapter->pdev->device == OC_DEVICE_ID6) 623d3bd3a5eSPadmanabh Ratnakar 624ca34fe38SSathya Perla #define BE3_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID2 || \ 625ca34fe38SSathya Perla adapter->pdev->device == OC_DEVICE_ID2) 626ca34fe38SSathya Perla 627ca34fe38SSathya Perla #define BE2_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID1 || \ 628ca34fe38SSathya Perla adapter->pdev->device == OC_DEVICE_ID1) 629ca34fe38SSathya Perla 630ca34fe38SSathya Perla #define BEx_chip(adapter) (BE3_chip(adapter) || BE2_chip(adapter)) 631d3bd3a5eSPadmanabh Ratnakar 632dbf0f2a7SSathya Perla #define be_roce_supported(adapter) (skyhawk_chip(adapter) && \ 633045508a8SParav Pandit (adapter->function_mode & RDMA_ENABLED)) 634045508a8SParav Pandit 6359aebddd1SJeff Kirsher extern const struct ethtool_ops be_ethtool_ops; 6369aebddd1SJeff Kirsher 6379aebddd1SJeff Kirsher #define msix_enabled(adapter) (adapter->num_msix_vec > 0) 63810ef9ab4SSathya Perla #define num_irqs(adapter) (msix_enabled(adapter) ? \ 63910ef9ab4SSathya Perla adapter->num_msix_vec : 1) 64010ef9ab4SSathya Perla #define tx_stats(txo) (&(txo)->stats) 64110ef9ab4SSathya Perla #define rx_stats(rxo) (&(rxo)->stats) 6429aebddd1SJeff Kirsher 64310ef9ab4SSathya Perla /* The default RXQ is the last RXQ */ 64410ef9ab4SSathya Perla #define default_rxo(adpt) (&adpt->rx_obj[adpt->num_rx_qs - 1]) 6459aebddd1SJeff Kirsher 6469aebddd1SJeff Kirsher #define for_all_rx_queues(adapter, rxo, i) \ 6479aebddd1SJeff Kirsher for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \ 6489aebddd1SJeff Kirsher i++, rxo++) 6499aebddd1SJeff Kirsher 6509aebddd1SJeff Kirsher #define for_all_rss_queues(adapter, rxo, i) \ 65171bb8bd0SVasundhara Volam for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rss_qs; \ 6529aebddd1SJeff Kirsher i++, rxo++) 6539aebddd1SJeff Kirsher 6549aebddd1SJeff Kirsher #define for_all_tx_queues(adapter, txo, i) \ 6559aebddd1SJeff Kirsher for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs; \ 6569aebddd1SJeff Kirsher i++, txo++) 6579aebddd1SJeff Kirsher 65810ef9ab4SSathya Perla #define for_all_evt_queues(adapter, eqo, i) \ 65910ef9ab4SSathya Perla for (i = 0, eqo = &adapter->eq_obj[i]; i < adapter->num_evt_qs; \ 66010ef9ab4SSathya Perla i++, eqo++) 66110ef9ab4SSathya Perla 6626384a4d0SSathya Perla #define for_all_rx_queues_on_eq(adapter, eqo, rxo, i) \ 6636384a4d0SSathya Perla for (i = eqo->idx, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs;\ 6646384a4d0SSathya Perla i += adapter->num_evt_qs, rxo += adapter->num_evt_qs) 6656384a4d0SSathya Perla 666a4906ea0SSathya Perla #define for_all_tx_queues_on_eq(adapter, eqo, txo, i) \ 667a4906ea0SSathya Perla for (i = eqo->idx, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs;\ 668a4906ea0SSathya Perla i += adapter->num_evt_qs, txo += adapter->num_evt_qs) 669a4906ea0SSathya Perla 67010ef9ab4SSathya Perla #define is_mcc_eqo(eqo) (eqo->idx == 0) 67110ef9ab4SSathya Perla #define mcc_eqo(adapter) (&adapter->eq_obj[0]) 67210ef9ab4SSathya Perla 6739aebddd1SJeff Kirsher #define PAGE_SHIFT_4K 12 6749aebddd1SJeff Kirsher #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K) 6759aebddd1SJeff Kirsher 6769aebddd1SJeff Kirsher /* Returns number of pages spanned by the data starting at the given addr */ 6779aebddd1SJeff Kirsher #define PAGES_4K_SPANNED(_address, size) \ 6789aebddd1SJeff Kirsher ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \ 6799aebddd1SJeff Kirsher (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K)) 6809aebddd1SJeff Kirsher 6819aebddd1SJeff Kirsher /* Returns bit offset within a DWORD of a bitfield */ 6829aebddd1SJeff Kirsher #define AMAP_BIT_OFFSET(_struct, field) \ 6839aebddd1SJeff Kirsher (((size_t)&(((_struct *)0)->field))%32) 6849aebddd1SJeff Kirsher 6859aebddd1SJeff Kirsher /* Returns the bit mask of the field that is NOT shifted into location. */ 6869aebddd1SJeff Kirsher static inline u32 amap_mask(u32 bitsize) 6879aebddd1SJeff Kirsher { 6889aebddd1SJeff Kirsher return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1); 6899aebddd1SJeff Kirsher } 6909aebddd1SJeff Kirsher 6919aebddd1SJeff Kirsher static inline void 6929aebddd1SJeff Kirsher amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value) 6939aebddd1SJeff Kirsher { 6949aebddd1SJeff Kirsher u32 *dw = (u32 *) ptr + dw_offset; 6959aebddd1SJeff Kirsher *dw &= ~(mask << offset); 6969aebddd1SJeff Kirsher *dw |= (mask & value) << offset; 6979aebddd1SJeff Kirsher } 6989aebddd1SJeff Kirsher 6999aebddd1SJeff Kirsher #define AMAP_SET_BITS(_struct, field, ptr, val) \ 7009aebddd1SJeff Kirsher amap_set(ptr, \ 7019aebddd1SJeff Kirsher offsetof(_struct, field)/32, \ 7029aebddd1SJeff Kirsher amap_mask(sizeof(((_struct *)0)->field)), \ 7039aebddd1SJeff Kirsher AMAP_BIT_OFFSET(_struct, field), \ 7049aebddd1SJeff Kirsher val) 7059aebddd1SJeff Kirsher 7069aebddd1SJeff Kirsher static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset) 7079aebddd1SJeff Kirsher { 7089aebddd1SJeff Kirsher u32 *dw = (u32 *) ptr; 7099aebddd1SJeff Kirsher return mask & (*(dw + dw_offset) >> offset); 7109aebddd1SJeff Kirsher } 7119aebddd1SJeff Kirsher 7129aebddd1SJeff Kirsher #define AMAP_GET_BITS(_struct, field, ptr) \ 7139aebddd1SJeff Kirsher amap_get(ptr, \ 7149aebddd1SJeff Kirsher offsetof(_struct, field)/32, \ 7159aebddd1SJeff Kirsher amap_mask(sizeof(((_struct *)0)->field)), \ 7169aebddd1SJeff Kirsher AMAP_BIT_OFFSET(_struct, field)) 7179aebddd1SJeff Kirsher 718c3c18bc1SSathya Perla #define GET_RX_COMPL_V0_BITS(field, ptr) \ 719c3c18bc1SSathya Perla AMAP_GET_BITS(struct amap_eth_rx_compl_v0, field, ptr) 720c3c18bc1SSathya Perla 721c3c18bc1SSathya Perla #define GET_RX_COMPL_V1_BITS(field, ptr) \ 722c3c18bc1SSathya Perla AMAP_GET_BITS(struct amap_eth_rx_compl_v1, field, ptr) 723c3c18bc1SSathya Perla 724c3c18bc1SSathya Perla #define GET_TX_COMPL_BITS(field, ptr) \ 725c3c18bc1SSathya Perla AMAP_GET_BITS(struct amap_eth_tx_compl, field, ptr) 726c3c18bc1SSathya Perla 727c3c18bc1SSathya Perla #define SET_TX_WRB_HDR_BITS(field, ptr, val) \ 728c3c18bc1SSathya Perla AMAP_SET_BITS(struct amap_eth_hdr_wrb, field, ptr, val) 729c3c18bc1SSathya Perla 7309aebddd1SJeff Kirsher #define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len) 7319aebddd1SJeff Kirsher #define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len) 7329aebddd1SJeff Kirsher static inline void swap_dws(void *wrb, int len) 7339aebddd1SJeff Kirsher { 7349aebddd1SJeff Kirsher #ifdef __BIG_ENDIAN 7359aebddd1SJeff Kirsher u32 *dw = wrb; 7369aebddd1SJeff Kirsher BUG_ON(len % 4); 7379aebddd1SJeff Kirsher do { 7389aebddd1SJeff Kirsher *dw = cpu_to_le32(*dw); 7399aebddd1SJeff Kirsher dw++; 7409aebddd1SJeff Kirsher len -= 4; 7419aebddd1SJeff Kirsher } while (len); 7429aebddd1SJeff Kirsher #endif /* __BIG_ENDIAN */ 7439aebddd1SJeff Kirsher } 7449aebddd1SJeff Kirsher 7450532d4e3SKalesh AP #define be_cmd_status(status) (status > 0 ? -EIO : status) 7460532d4e3SKalesh AP 7479aebddd1SJeff Kirsher static inline u8 is_tcp_pkt(struct sk_buff *skb) 7489aebddd1SJeff Kirsher { 7499aebddd1SJeff Kirsher u8 val = 0; 7509aebddd1SJeff Kirsher 7519aebddd1SJeff Kirsher if (ip_hdr(skb)->version == 4) 7529aebddd1SJeff Kirsher val = (ip_hdr(skb)->protocol == IPPROTO_TCP); 7539aebddd1SJeff Kirsher else if (ip_hdr(skb)->version == 6) 7549aebddd1SJeff Kirsher val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP); 7559aebddd1SJeff Kirsher 7569aebddd1SJeff Kirsher return val; 7579aebddd1SJeff Kirsher } 7589aebddd1SJeff Kirsher 7599aebddd1SJeff Kirsher static inline u8 is_udp_pkt(struct sk_buff *skb) 7609aebddd1SJeff Kirsher { 7619aebddd1SJeff Kirsher u8 val = 0; 7629aebddd1SJeff Kirsher 7639aebddd1SJeff Kirsher if (ip_hdr(skb)->version == 4) 7649aebddd1SJeff Kirsher val = (ip_hdr(skb)->protocol == IPPROTO_UDP); 7659aebddd1SJeff Kirsher else if (ip_hdr(skb)->version == 6) 7669aebddd1SJeff Kirsher val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP); 7679aebddd1SJeff Kirsher 7689aebddd1SJeff Kirsher return val; 7699aebddd1SJeff Kirsher } 7709aebddd1SJeff Kirsher 77193040ae5SSomnath Kotur static inline bool is_ipv4_pkt(struct sk_buff *skb) 77293040ae5SSomnath Kotur { 773e8efcec5SLi RongQing return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 77493040ae5SSomnath Kotur } 77593040ae5SSomnath Kotur 7769aebddd1SJeff Kirsher static inline bool be_multi_rxq(const struct be_adapter *adapter) 7779aebddd1SJeff Kirsher { 7789aebddd1SJeff Kirsher return adapter->num_rx_qs > 1; 7799aebddd1SJeff Kirsher } 7809aebddd1SJeff Kirsher 7816589ade0SSathya Perla static inline bool be_error(struct be_adapter *adapter) 7826589ade0SSathya Perla { 783f67ef7baSPadmanabh Ratnakar return adapter->eeh_error || adapter->hw_error || adapter->fw_timeout; 784f67ef7baSPadmanabh Ratnakar } 785f67ef7baSPadmanabh Ratnakar 786d23e946cSSathya Perla static inline bool be_hw_error(struct be_adapter *adapter) 787f67ef7baSPadmanabh Ratnakar { 788f67ef7baSPadmanabh Ratnakar return adapter->eeh_error || adapter->hw_error; 789f67ef7baSPadmanabh Ratnakar } 790f67ef7baSPadmanabh Ratnakar 791f67ef7baSPadmanabh Ratnakar static inline void be_clear_all_error(struct be_adapter *adapter) 792f67ef7baSPadmanabh Ratnakar { 793f67ef7baSPadmanabh Ratnakar adapter->eeh_error = false; 794f67ef7baSPadmanabh Ratnakar adapter->hw_error = false; 795f67ef7baSPadmanabh Ratnakar adapter->fw_timeout = false; 7966589ade0SSathya Perla } 7976589ade0SSathya Perla 79831886e87SJoe Perches void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, 7999aebddd1SJeff Kirsher u16 num_popped); 80031886e87SJoe Perches void be_link_status_update(struct be_adapter *adapter, u8 link_status); 80131886e87SJoe Perches void be_parse_stats(struct be_adapter *adapter); 80231886e87SJoe Perches int be_load_fw(struct be_adapter *adapter, u8 *func); 80331886e87SJoe Perches bool be_is_wol_supported(struct be_adapter *adapter); 80431886e87SJoe Perches bool be_pause_supported(struct be_adapter *adapter); 80531886e87SJoe Perches u32 be_get_fw_log_level(struct be_adapter *adapter); 80668d7bdcbSSathya Perla int be_update_queues(struct be_adapter *adapter); 80768d7bdcbSSathya Perla int be_poll(struct napi_struct *napi, int budget); 80820947770SPadmanabh Ratnakar void be_eqd_update(struct be_adapter *adapter, bool force_update); 809941a77d5SSomnath Kotur 810045508a8SParav Pandit /* 811045508a8SParav Pandit * internal function to initialize-cleanup roce device. 812045508a8SParav Pandit */ 81331886e87SJoe Perches void be_roce_dev_add(struct be_adapter *); 81431886e87SJoe Perches void be_roce_dev_remove(struct be_adapter *); 815045508a8SParav Pandit 816045508a8SParav Pandit /* 817045508a8SParav Pandit * internal function to open-close roce device during ifup-ifdown. 818045508a8SParav Pandit */ 81931886e87SJoe Perches void be_roce_dev_open(struct be_adapter *); 82031886e87SJoe Perches void be_roce_dev_close(struct be_adapter *); 821d114f99aSDevesh Sharma void be_roce_dev_shutdown(struct be_adapter *); 822045508a8SParav Pandit 8239aebddd1SJeff Kirsher #endif /* BE_H */ 824