19aebddd1SJeff Kirsher /* 27dfbe7d7SSomnath Kotur * Copyright (C) 2005 - 2016 Broadcom 39aebddd1SJeff Kirsher * All rights reserved. 49aebddd1SJeff Kirsher * 59aebddd1SJeff Kirsher * This program is free software; you can redistribute it and/or 69aebddd1SJeff Kirsher * modify it under the terms of the GNU General Public License version 2 79aebddd1SJeff Kirsher * as published by the Free Software Foundation. The full GNU General 89aebddd1SJeff Kirsher * Public License is included in this distribution in the file called COPYING. 99aebddd1SJeff Kirsher * 109aebddd1SJeff Kirsher * Contact Information: 119aebddd1SJeff Kirsher * linux-drivers@emulex.com 129aebddd1SJeff Kirsher * 139aebddd1SJeff Kirsher * Emulex 149aebddd1SJeff Kirsher * 3333 Susan Street 159aebddd1SJeff Kirsher * Costa Mesa, CA 92626 169aebddd1SJeff Kirsher */ 179aebddd1SJeff Kirsher 189aebddd1SJeff Kirsher #ifndef BE_H 199aebddd1SJeff Kirsher #define BE_H 209aebddd1SJeff Kirsher 219aebddd1SJeff Kirsher #include <linux/pci.h> 229aebddd1SJeff Kirsher #include <linux/etherdevice.h> 239aebddd1SJeff Kirsher #include <linux/delay.h> 249aebddd1SJeff Kirsher #include <net/tcp.h> 259aebddd1SJeff Kirsher #include <net/ip.h> 269aebddd1SJeff Kirsher #include <net/ipv6.h> 279aebddd1SJeff Kirsher #include <linux/if_vlan.h> 289aebddd1SJeff Kirsher #include <linux/workqueue.h> 299aebddd1SJeff Kirsher #include <linux/interrupt.h> 309aebddd1SJeff Kirsher #include <linux/firmware.h> 319aebddd1SJeff Kirsher #include <linux/slab.h> 329aebddd1SJeff Kirsher #include <linux/u64_stats_sync.h> 33d658d98aSPadmanabh Ratnakar #include <linux/cpumask.h> 3429e9122bSVenkata Duvvuru #include <linux/hwmon.h> 3529e9122bSVenkata Duvvuru #include <linux/hwmon-sysfs.h> 369aebddd1SJeff Kirsher 379aebddd1SJeff Kirsher #include "be_hw.h" 38045508a8SParav Pandit #include "be_roce.h" 399aebddd1SJeff Kirsher 40aab0830aSSuresh Reddy #define DRV_VER "11.4.0.0" 419aebddd1SJeff Kirsher #define DRV_NAME "be2net" 4200d3d51eSSarveshwar Bandi #define BE_NAME "Emulex BladeEngine2" 4300d3d51eSSarveshwar Bandi #define BE3_NAME "Emulex BladeEngine3" 4400d3d51eSSarveshwar Bandi #define OC_NAME "Emulex OneConnect" 459aebddd1SJeff Kirsher #define OC_NAME_BE OC_NAME "(be3)" 469aebddd1SJeff Kirsher #define OC_NAME_LANCER OC_NAME "(Lancer)" 47ecedb6aeSAjit Khaparde #define OC_NAME_SH OC_NAME "(Skyhawk)" 48f3effb45SSuresh Reddy #define DRV_DESC "Emulex OneConnect NIC Driver" 499aebddd1SJeff Kirsher 509aebddd1SJeff Kirsher #define BE_VENDOR_ID 0x19a2 519aebddd1SJeff Kirsher #define EMULEX_VENDOR_ID 0x10df 529aebddd1SJeff Kirsher #define BE_DEVICE_ID1 0x211 539aebddd1SJeff Kirsher #define BE_DEVICE_ID2 0x221 549aebddd1SJeff Kirsher #define OC_DEVICE_ID1 0x700 /* Device Id for BE2 cards */ 559aebddd1SJeff Kirsher #define OC_DEVICE_ID2 0x710 /* Device Id for BE3 cards */ 569aebddd1SJeff Kirsher #define OC_DEVICE_ID3 0xe220 /* Device id for Lancer cards */ 579aebddd1SJeff Kirsher #define OC_DEVICE_ID4 0xe228 /* Device id for VF in Lancer */ 58ecedb6aeSAjit Khaparde #define OC_DEVICE_ID5 0x720 /* Device Id for Skyhawk cards */ 5976b73530SPadmanabh Ratnakar #define OC_DEVICE_ID6 0x728 /* Device id for VF in SkyHawk */ 604762f6ceSAjit Khaparde #define OC_SUBSYS_DEVICE_ID1 0xE602 614762f6ceSAjit Khaparde #define OC_SUBSYS_DEVICE_ID2 0xE642 624762f6ceSAjit Khaparde #define OC_SUBSYS_DEVICE_ID3 0xE612 634762f6ceSAjit Khaparde #define OC_SUBSYS_DEVICE_ID4 0xE652 649aebddd1SJeff Kirsher 659aebddd1SJeff Kirsher /* Number of bytes of an RX frame that are copied to skb->data */ 669aebddd1SJeff Kirsher #define BE_HDR_LEN ((u16) 64) 67bb349bb4SEric Dumazet /* allocate extra space to allow tunneling decapsulation without head reallocation */ 6876b15923SKalesh A P #define BE_RX_SKB_ALLOC_SIZE 256 69bb349bb4SEric Dumazet 709aebddd1SJeff Kirsher #define BE_MAX_JUMBO_FRAME_SIZE 9018 719aebddd1SJeff Kirsher #define BE_MIN_MTU 256 720d3f5cceSKalesh AP #define BE_MAX_MTU (BE_MAX_JUMBO_FRAME_SIZE - \ 730d3f5cceSKalesh AP (ETH_HLEN + ETH_FCS_LEN)) 749aebddd1SJeff Kirsher 75127bfce5Sajit.khaparde@broadcom.com /* Accommodate for QnQ configurations where VLAN insertion is enabled in HW */ 76127bfce5Sajit.khaparde@broadcom.com #define BE_MAX_GSO_SIZE (65535 - 2 * VLAN_HLEN) 77127bfce5Sajit.khaparde@broadcom.com 789aebddd1SJeff Kirsher #define BE_NUM_VLANS_SUPPORTED 64 792632bafdSSathya Perla #define BE_MAX_EQD 128u 809aebddd1SJeff Kirsher #define BE_MAX_TX_FRAG_COUNT 30 819aebddd1SJeff Kirsher 829aebddd1SJeff Kirsher #define EVNT_Q_LEN 1024 839aebddd1SJeff Kirsher #define TX_Q_LEN 2048 849aebddd1SJeff Kirsher #define TX_CQ_LEN 1024 859aebddd1SJeff Kirsher #define RX_Q_LEN 1024 /* Does not support any other value */ 869aebddd1SJeff Kirsher #define RX_CQ_LEN 1024 879aebddd1SJeff Kirsher #define MCC_Q_LEN 128 /* total size not to exceed 8 pages */ 889aebddd1SJeff Kirsher #define MCC_CQ_LEN 256 899aebddd1SJeff Kirsher 9010ef9ab4SSathya Perla #define BE2_MAX_RSS_QS 4 9168d7bdcbSSathya Perla #define BE3_MAX_RSS_QS 16 9268d7bdcbSSathya Perla #define BE3_MAX_TX_QS 16 9368d7bdcbSSathya Perla #define BE3_MAX_EVT_QS 16 94e3dc867cSSuresh Reddy #define BE3_SRIOV_MAX_EVT_QS 8 95ee9ad280SSriharsha Basavapatna #define SH_VF_MAX_NIC_EQS 3 /* Skyhawk VFs can have a max of 4 EQs 96ee9ad280SSriharsha Basavapatna * and at least 1 is granted to either 97ee9ad280SSriharsha Basavapatna * SURF/DPDK 98ee9ad280SSriharsha Basavapatna */ 9910ef9ab4SSathya Perla 100de2b1e03SSomnath Kotur #define MAX_PORT_RSS_TABLES 15 101de2b1e03SSomnath Kotur #define MAX_NIC_FUNCS 16 10268d7bdcbSSathya Perla #define MAX_RX_QS 32 10368d7bdcbSSathya Perla #define MAX_EVT_QS 32 10468d7bdcbSSathya Perla #define MAX_TX_QS 32 10568d7bdcbSSathya Perla 106045508a8SParav Pandit #define MAX_ROCE_EQS 5 10768d7bdcbSSathya Perla #define MAX_MSIX_VECTORS 32 10892bf14abSSathya Perla #define MIN_MSIX_VECTORS 1 1099aebddd1SJeff Kirsher #define BE_NAPI_WEIGHT 64 1109aebddd1SJeff Kirsher #define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */ 1119aebddd1SJeff Kirsher #define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST) 11269304cc9SAjit Khaparde #define MAX_NUM_POST_ERX_DB 255u 1139aebddd1SJeff Kirsher 1147c5a5242SVasundhara Volam #define MAX_VFS 30 /* Max VFs supported by BE3 FW */ 1159aebddd1SJeff Kirsher #define FW_VER_LEN 32 116a155a5dbSSriharsha Basavapatna #define CNTL_SERIAL_NUM_WORDS 8 /* Controller serial number words */ 117a155a5dbSSriharsha Basavapatna #define CNTL_SERIAL_NUM_WORD_SZ (sizeof(u16)) /* Byte-sz of serial num word */ 1189aebddd1SJeff Kirsher 119e2557877SVenkata Duvvuru #define RSS_INDIR_TABLE_LEN 128 120e2557877SVenkata Duvvuru #define RSS_HASH_KEY_LEN 40 121e2557877SVenkata Duvvuru 12251d1f98aSAjit Khaparde #define BE_UNKNOWN_PHY_STATE 0xFF 12351d1f98aSAjit Khaparde 1249aebddd1SJeff Kirsher struct be_dma_mem { 1259aebddd1SJeff Kirsher void *va; 1269aebddd1SJeff Kirsher dma_addr_t dma; 1279aebddd1SJeff Kirsher u32 size; 1289aebddd1SJeff Kirsher }; 1299aebddd1SJeff Kirsher 1309aebddd1SJeff Kirsher struct be_queue_info { 131b0fd2eb2Sajit.khaparde@broadcom.com u32 len; 132b0fd2eb2Sajit.khaparde@broadcom.com u32 entry_size; /* Size of an element in the queue */ 133b0fd2eb2Sajit.khaparde@broadcom.com u32 tail, head; 1349aebddd1SJeff Kirsher atomic_t used; /* Number of valid elements in the queue */ 135b0fd2eb2Sajit.khaparde@broadcom.com u32 id; 136b0fd2eb2Sajit.khaparde@broadcom.com struct be_dma_mem dma_mem; 137b0fd2eb2Sajit.khaparde@broadcom.com bool created; 1389aebddd1SJeff Kirsher }; 1399aebddd1SJeff Kirsher 140b0fd2eb2Sajit.khaparde@broadcom.com static inline u32 MODULO(u32 val, u32 limit) 1419aebddd1SJeff Kirsher { 1429aebddd1SJeff Kirsher BUG_ON(limit & (limit - 1)); 1439aebddd1SJeff Kirsher return val & (limit - 1); 1449aebddd1SJeff Kirsher } 1459aebddd1SJeff Kirsher 146b0fd2eb2Sajit.khaparde@broadcom.com static inline void index_adv(u32 *index, u32 val, u32 limit) 1479aebddd1SJeff Kirsher { 1489aebddd1SJeff Kirsher *index = MODULO((*index + val), limit); 1499aebddd1SJeff Kirsher } 1509aebddd1SJeff Kirsher 151b0fd2eb2Sajit.khaparde@broadcom.com static inline void index_inc(u32 *index, u32 limit) 1529aebddd1SJeff Kirsher { 1539aebddd1SJeff Kirsher *index = MODULO((*index + 1), limit); 1549aebddd1SJeff Kirsher } 1559aebddd1SJeff Kirsher 1569aebddd1SJeff Kirsher static inline void *queue_head_node(struct be_queue_info *q) 1579aebddd1SJeff Kirsher { 1589aebddd1SJeff Kirsher return q->dma_mem.va + q->head * q->entry_size; 1599aebddd1SJeff Kirsher } 1609aebddd1SJeff Kirsher 1619aebddd1SJeff Kirsher static inline void *queue_tail_node(struct be_queue_info *q) 1629aebddd1SJeff Kirsher { 1639aebddd1SJeff Kirsher return q->dma_mem.va + q->tail * q->entry_size; 1649aebddd1SJeff Kirsher } 1659aebddd1SJeff Kirsher 1663de09455SSomnath Kotur static inline void *queue_index_node(struct be_queue_info *q, u16 index) 1673de09455SSomnath Kotur { 1683de09455SSomnath Kotur return q->dma_mem.va + index * q->entry_size; 1693de09455SSomnath Kotur } 1703de09455SSomnath Kotur 1719aebddd1SJeff Kirsher static inline void queue_head_inc(struct be_queue_info *q) 1729aebddd1SJeff Kirsher { 1739aebddd1SJeff Kirsher index_inc(&q->head, q->len); 1749aebddd1SJeff Kirsher } 1759aebddd1SJeff Kirsher 176b0fd2eb2Sajit.khaparde@broadcom.com static inline void index_dec(u32 *index, u32 limit) 177652bf646SPadmanabh Ratnakar { 178652bf646SPadmanabh Ratnakar *index = MODULO((*index - 1), limit); 179652bf646SPadmanabh Ratnakar } 180652bf646SPadmanabh Ratnakar 1819aebddd1SJeff Kirsher static inline void queue_tail_inc(struct be_queue_info *q) 1829aebddd1SJeff Kirsher { 1839aebddd1SJeff Kirsher index_inc(&q->tail, q->len); 1849aebddd1SJeff Kirsher } 1859aebddd1SJeff Kirsher 1869aebddd1SJeff Kirsher struct be_eq_obj { 1879aebddd1SJeff Kirsher struct be_queue_info q; 1889aebddd1SJeff Kirsher char desc[32]; 1899aebddd1SJeff Kirsher 1909aebddd1SJeff Kirsher /* Adaptive interrupt coalescing (AIC) info */ 1919aebddd1SJeff Kirsher bool enable_aic; 19210ef9ab4SSathya Perla u32 min_eqd; /* in usecs */ 19310ef9ab4SSathya Perla u32 max_eqd; /* in usecs */ 19410ef9ab4SSathya Perla u32 eqd; /* configured val when aic is off */ 19510ef9ab4SSathya Perla u32 cur_eqd; /* in usecs */ 1969aebddd1SJeff Kirsher 19710ef9ab4SSathya Perla u8 idx; /* array index */ 198f2f781a7SSathya Perla u8 msix_idx; 199d0b9cec3SSathya Perla u16 spurious_intr; 2009aebddd1SJeff Kirsher struct napi_struct napi; 20110ef9ab4SSathya Perla struct be_adapter *adapter; 202d658d98aSPadmanabh Ratnakar cpumask_var_t affinity_mask; 2036384a4d0SSathya Perla 2046384a4d0SSathya Perla #ifdef CONFIG_NET_RX_BUSY_POLL 2056384a4d0SSathya Perla #define BE_EQ_IDLE 0 2066384a4d0SSathya Perla #define BE_EQ_NAPI 1 /* napi owns this EQ */ 2076384a4d0SSathya Perla #define BE_EQ_POLL 2 /* poll owns this EQ */ 2086384a4d0SSathya Perla #define BE_EQ_LOCKED (BE_EQ_NAPI | BE_EQ_POLL) 2096384a4d0SSathya Perla #define BE_EQ_NAPI_YIELD 4 /* napi yielded this EQ */ 2106384a4d0SSathya Perla #define BE_EQ_POLL_YIELD 8 /* poll yielded this EQ */ 2116384a4d0SSathya Perla #define BE_EQ_YIELD (BE_EQ_NAPI_YIELD | BE_EQ_POLL_YIELD) 2126384a4d0SSathya Perla #define BE_EQ_USER_PEND (BE_EQ_POLL | BE_EQ_POLL_YIELD) 2136384a4d0SSathya Perla unsigned int state; 2146384a4d0SSathya Perla spinlock_t lock; /* lock to serialize napi and busy-poll */ 2156384a4d0SSathya Perla #endif /* CONFIG_NET_RX_BUSY_POLL */ 21610ef9ab4SSathya Perla } ____cacheline_aligned_in_smp; 2179aebddd1SJeff Kirsher 2182632bafdSSathya Perla struct be_aic_obj { /* Adaptive interrupt coalescing (AIC) info */ 2192632bafdSSathya Perla bool enable; 2202632bafdSSathya Perla u32 min_eqd; /* in usecs */ 2212632bafdSSathya Perla u32 max_eqd; /* in usecs */ 2222632bafdSSathya Perla u32 prev_eqd; /* in usecs */ 2232632bafdSSathya Perla u32 et_eqd; /* configured val when aic is off */ 2242632bafdSSathya Perla ulong jiffies; 2252632bafdSSathya Perla u64 rx_pkts_prev; /* Used to calculate RX pps */ 2262632bafdSSathya Perla u64 tx_reqs_prev; /* Used to calculate TX pps */ 2272632bafdSSathya Perla }; 2282632bafdSSathya Perla 2299aebddd1SJeff Kirsher struct be_mcc_obj { 2309aebddd1SJeff Kirsher struct be_queue_info q; 2319aebddd1SJeff Kirsher struct be_queue_info cq; 2329aebddd1SJeff Kirsher bool rearm_cq; 2339aebddd1SJeff Kirsher }; 2349aebddd1SJeff Kirsher 2359aebddd1SJeff Kirsher struct be_tx_stats { 2369aebddd1SJeff Kirsher u64 tx_bytes; 2379aebddd1SJeff Kirsher u64 tx_pkts; 2388670f2a5SSriharsha Basavapatna u64 tx_vxlan_offload_pkts; 2399aebddd1SJeff Kirsher u64 tx_reqs; 2409aebddd1SJeff Kirsher u64 tx_compl; 2419aebddd1SJeff Kirsher ulong tx_jiffies; 2429aebddd1SJeff Kirsher u32 tx_stops; 243bc617526SSathya Perla u32 tx_drv_drops; /* pkts dropped by driver */ 244512bb8a2SKalesh AP /* the error counters are described in be_ethtool.c */ 245512bb8a2SKalesh AP u32 tx_hdr_parse_err; 246512bb8a2SKalesh AP u32 tx_dma_err; 247512bb8a2SKalesh AP u32 tx_tso_err; 248512bb8a2SKalesh AP u32 tx_spoof_check_err; 249512bb8a2SKalesh AP u32 tx_qinq_err; 250512bb8a2SKalesh AP u32 tx_internal_parity_err; 2519aebddd1SJeff Kirsher struct u64_stats_sync sync; 2529aebddd1SJeff Kirsher struct u64_stats_sync sync_compl; 2539aebddd1SJeff Kirsher }; 2549aebddd1SJeff Kirsher 255152ffe5bSSriharsha Basavapatna /* Structure to hold some data of interest obtained from a TX CQE */ 256152ffe5bSSriharsha Basavapatna struct be_tx_compl_info { 257152ffe5bSSriharsha Basavapatna u8 status; /* Completion status */ 258152ffe5bSSriharsha Basavapatna u16 end_index; /* Completed TXQ Index */ 259152ffe5bSSriharsha Basavapatna }; 260152ffe5bSSriharsha Basavapatna 2619aebddd1SJeff Kirsher struct be_tx_obj { 26294d73aaaSVasundhara Volam u32 db_offset; 2639aebddd1SJeff Kirsher struct be_queue_info q; 2649aebddd1SJeff Kirsher struct be_queue_info cq; 265152ffe5bSSriharsha Basavapatna struct be_tx_compl_info txcp; 2669aebddd1SJeff Kirsher /* Remember the skbs that were transmitted */ 2679aebddd1SJeff Kirsher struct sk_buff *sent_skb_list[TX_Q_LEN]; 2689aebddd1SJeff Kirsher struct be_tx_stats stats; 2695f07b3c5SSathya Perla u16 pend_wrb_cnt; /* Number of WRBs yet to be given to HW */ 2705f07b3c5SSathya Perla u16 last_req_wrb_cnt; /* wrb cnt of the last req in the Q */ 2715f07b3c5SSathya Perla u16 last_req_hdr; /* index of the last req's hdr-wrb */ 27210ef9ab4SSathya Perla } ____cacheline_aligned_in_smp; 2739aebddd1SJeff Kirsher 2749aebddd1SJeff Kirsher /* Struct to remember the pages posted for rx frags */ 2759aebddd1SJeff Kirsher struct be_rx_page_info { 2769aebddd1SJeff Kirsher struct page *page; 277e50287beSSathya Perla /* set to page-addr for last frag of the page & frag-addr otherwise */ 2789aebddd1SJeff Kirsher DEFINE_DMA_UNMAP_ADDR(bus); 2799aebddd1SJeff Kirsher u16 page_offset; 280e50287beSSathya Perla bool last_frag; /* last frag of the page */ 2819aebddd1SJeff Kirsher }; 2829aebddd1SJeff Kirsher 2839aebddd1SJeff Kirsher struct be_rx_stats { 2849aebddd1SJeff Kirsher u64 rx_bytes; 2859aebddd1SJeff Kirsher u64 rx_pkts; 2868670f2a5SSriharsha Basavapatna u64 rx_vxlan_offload_pkts; 2879aebddd1SJeff Kirsher u32 rx_drops_no_skbs; /* skb allocation errors */ 2889aebddd1SJeff Kirsher u32 rx_drops_no_frags; /* HW has no fetched frags */ 2899aebddd1SJeff Kirsher u32 rx_post_fail; /* page post alloc failures */ 2909aebddd1SJeff Kirsher u32 rx_compl; 2919aebddd1SJeff Kirsher u32 rx_mcast_pkts; 2929aebddd1SJeff Kirsher u32 rx_compl_err; /* completions with err set */ 2939aebddd1SJeff Kirsher struct u64_stats_sync sync; 2949aebddd1SJeff Kirsher }; 2959aebddd1SJeff Kirsher 2969aebddd1SJeff Kirsher struct be_rx_compl_info { 2979aebddd1SJeff Kirsher u32 rss_hash; 2989aebddd1SJeff Kirsher u16 vlan_tag; 2999aebddd1SJeff Kirsher u16 pkt_size; 3009aebddd1SJeff Kirsher u16 port; 3019aebddd1SJeff Kirsher u8 vlanf; 3029aebddd1SJeff Kirsher u8 num_rcvd; 3039aebddd1SJeff Kirsher u8 err; 3049aebddd1SJeff Kirsher u8 ipf; 3059aebddd1SJeff Kirsher u8 tcpf; 3069aebddd1SJeff Kirsher u8 udpf; 3079aebddd1SJeff Kirsher u8 ip_csum; 3089aebddd1SJeff Kirsher u8 l4_csum; 3099aebddd1SJeff Kirsher u8 ipv6; 310f93f160bSVasundhara Volam u8 qnq; 3119aebddd1SJeff Kirsher u8 pkt_type; 312e38b1706SSomnath Kotur u8 ip_frag; 313c9c47142SSathya Perla u8 tunneled; 3149aebddd1SJeff Kirsher }; 3159aebddd1SJeff Kirsher 3169aebddd1SJeff Kirsher struct be_rx_obj { 3179aebddd1SJeff Kirsher struct be_adapter *adapter; 3189aebddd1SJeff Kirsher struct be_queue_info q; 3199aebddd1SJeff Kirsher struct be_queue_info cq; 3209aebddd1SJeff Kirsher struct be_rx_compl_info rxcp; 3219aebddd1SJeff Kirsher struct be_rx_page_info page_info_tbl[RX_Q_LEN]; 3229aebddd1SJeff Kirsher struct be_rx_stats stats; 3239aebddd1SJeff Kirsher u8 rss_id; 3249aebddd1SJeff Kirsher bool rx_post_starved; /* Zero rx frags have been posted to BE */ 32510ef9ab4SSathya Perla } ____cacheline_aligned_in_smp; 3269aebddd1SJeff Kirsher 3279aebddd1SJeff Kirsher struct be_drv_stats { 3289aebddd1SJeff Kirsher u32 eth_red_drops; 329d3de1540SVasundhara Volam u32 dma_map_errors; 3309aebddd1SJeff Kirsher u32 rx_drops_no_pbuf; 3319aebddd1SJeff Kirsher u32 rx_drops_no_txpb; 3329aebddd1SJeff Kirsher u32 rx_drops_no_erx_descr; 3339aebddd1SJeff Kirsher u32 rx_drops_no_tpre_descr; 3349aebddd1SJeff Kirsher u32 rx_drops_too_many_frags; 3359aebddd1SJeff Kirsher u32 forwarded_packets; 3369aebddd1SJeff Kirsher u32 rx_drops_mtu; 3379aebddd1SJeff Kirsher u32 rx_crc_errors; 3389aebddd1SJeff Kirsher u32 rx_alignment_symbol_errors; 3399aebddd1SJeff Kirsher u32 rx_pause_frames; 3409aebddd1SJeff Kirsher u32 rx_priority_pause_frames; 3419aebddd1SJeff Kirsher u32 rx_control_frames; 3429aebddd1SJeff Kirsher u32 rx_in_range_errors; 3439aebddd1SJeff Kirsher u32 rx_out_range_errors; 3449aebddd1SJeff Kirsher u32 rx_frame_too_long; 34518fb06a1SSuresh Reddy u32 rx_address_filtered; 3469aebddd1SJeff Kirsher u32 rx_dropped_too_small; 3479aebddd1SJeff Kirsher u32 rx_dropped_too_short; 3489aebddd1SJeff Kirsher u32 rx_dropped_header_too_small; 3499aebddd1SJeff Kirsher u32 rx_dropped_tcp_length; 3509aebddd1SJeff Kirsher u32 rx_dropped_runt; 3519aebddd1SJeff Kirsher u32 rx_ip_checksum_errs; 3529aebddd1SJeff Kirsher u32 rx_tcp_checksum_errs; 3539aebddd1SJeff Kirsher u32 rx_udp_checksum_errs; 3549aebddd1SJeff Kirsher u32 tx_pauseframes; 3559aebddd1SJeff Kirsher u32 tx_priority_pauseframes; 3569aebddd1SJeff Kirsher u32 tx_controlframes; 3579aebddd1SJeff Kirsher u32 rxpp_fifo_overflow_drop; 3589aebddd1SJeff Kirsher u32 rx_input_fifo_overflow_drop; 3599aebddd1SJeff Kirsher u32 pmem_fifo_overflow_drop; 3609aebddd1SJeff Kirsher u32 jabber_events; 361461ae379SAjit Khaparde u32 rx_roce_bytes_lsd; 362461ae379SAjit Khaparde u32 rx_roce_bytes_msd; 363461ae379SAjit Khaparde u32 rx_roce_frames; 364461ae379SAjit Khaparde u32 roce_drops_payload_len; 365461ae379SAjit Khaparde u32 roce_drops_crc; 3669aebddd1SJeff Kirsher }; 3679aebddd1SJeff Kirsher 368c502224eSSomnath Kotur /* A vlan-id of 0xFFFF must be used to clear transparent vlan-tagging */ 369c502224eSSomnath Kotur #define BE_RESET_VLAN_TAG_ID 0xFFFF 370c502224eSSomnath Kotur 3719aebddd1SJeff Kirsher struct be_vf_cfg { 37211ac75edSSathya Perla unsigned char mac_addr[ETH_ALEN]; 37311ac75edSSathya Perla int if_handle; 37411ac75edSSathya Perla int pmac_id; 37511ac75edSSathya Perla u16 vlan_tag; 37611ac75edSSathya Perla u32 tx_rate; 377bdce2ad7SSuresh Reddy u32 plink_tracking; 378435452aaSVasundhara Volam u32 privileges; 379e7bcbd7bSKalesh AP bool spoofchk; 3809aebddd1SJeff Kirsher }; 3819aebddd1SJeff Kirsher 38239f1d94dSSathya Perla enum vf_state { 38339f1d94dSSathya Perla ENABLED = 0, 38439f1d94dSSathya Perla ASSIGNED = 1 38539f1d94dSSathya Perla }; 38639f1d94dSSathya Perla 38783b06116SVasundhara Volam #define BE_FLAGS_LINK_STATUS_INIT BIT(1) 38883b06116SVasundhara Volam #define BE_FLAGS_SRIOV_ENABLED BIT(2) 38983b06116SVasundhara Volam #define BE_FLAGS_WORKER_SCHEDULED BIT(3) 39083b06116SVasundhara Volam #define BE_FLAGS_NAPI_ENABLED BIT(6) 39183b06116SVasundhara Volam #define BE_FLAGS_QNQ_ASYNC_EVT_RCVD BIT(7) 39283b06116SVasundhara Volam #define BE_FLAGS_VXLAN_OFFLOADS BIT(8) 39383b06116SVasundhara Volam #define BE_FLAGS_SETUP_DONE BIT(9) 39451d1f98aSAjit Khaparde #define BE_FLAGS_PHY_MISCONFIGURED BIT(10) 395eb7dd46cSSathya Perla #define BE_FLAGS_ERR_DETECTION_SCHEDULED BIT(11) 396760c295eSVenkata Duvvuru #define BE_FLAGS_OS2BMC BIT(12) 397710f3e59SSriharsha Basavapatna #define BE_FLAGS_TRY_RECOVERY BIT(13) 398c9c47142SSathya Perla 399fbc13f01SAjit Khaparde #define BE_UC_PMAC_COUNT 30 400fbc13f01SAjit Khaparde #define BE_VF_UC_PMAC_COUNT 2 401f0613380SKalesh AP 402972f37b4SPadmanabh Ratnakar #define MAX_ERR_RECOVERY_RETRY_COUNT 3 403972f37b4SPadmanabh Ratnakar #define ERR_DETECTION_DELAY 1000 404972f37b4SPadmanabh Ratnakar 4055c510811SSomnath Kotur /* Ethtool set_dump flags */ 4065c510811SSomnath Kotur #define LANCER_INITIATE_FW_DUMP 0x1 407f0613380SKalesh AP #define LANCER_DELETE_FW_DUMP 0x2 4085c510811SSomnath Kotur 40942f11cf2SAjit Khaparde struct phy_info { 41021252377SVasundhara Volam /* From SFF-8472 spec */ 41121252377SVasundhara Volam #define SFP_VENDOR_NAME_LEN 17 41242f11cf2SAjit Khaparde u8 transceiver; 41342f11cf2SAjit Khaparde u8 autoneg; 41442f11cf2SAjit Khaparde u8 fc_autoneg; 41542f11cf2SAjit Khaparde u8 port_type; 41642f11cf2SAjit Khaparde u16 phy_type; 41742f11cf2SAjit Khaparde u16 interface_type; 41842f11cf2SAjit Khaparde u32 misc_params; 41942f11cf2SAjit Khaparde u16 auto_speeds_supported; 42042f11cf2SAjit Khaparde u16 fixed_speeds_supported; 42142f11cf2SAjit Khaparde int link_speed; 42242f11cf2SAjit Khaparde u32 advertising; 42342f11cf2SAjit Khaparde u32 supported; 4246809cee0SRavikumar Nelavelli u8 cable_type; 42521252377SVasundhara Volam u8 vendor_name[SFP_VENDOR_NAME_LEN]; 42621252377SVasundhara Volam u8 vendor_pn[SFP_VENDOR_NAME_LEN]; 42742f11cf2SAjit Khaparde }; 42842f11cf2SAjit Khaparde 42992bf14abSSathya Perla struct be_resources { 43092bf14abSSathya Perla u16 max_vfs; /* Total VFs "really" supported by FW/HW */ 43192bf14abSSathya Perla u16 max_mcast_mac; 43292bf14abSSathya Perla u16 max_tx_qs; 43392bf14abSSathya Perla u16 max_rss_qs; 43492bf14abSSathya Perla u16 max_rx_qs; 435f2858738SVasundhara Volam u16 max_cq_count; 43692bf14abSSathya Perla u16 max_uc_mac; /* Max UC MACs programmable */ 43792bf14abSSathya Perla u16 max_vlans; /* Number of vlans supported */ 438f2858738SVasundhara Volam u16 max_iface_count; 439f2858738SVasundhara Volam u16 max_mcc_count; 44092bf14abSSathya Perla u16 max_evt_qs; 441ce7faf0aSSathya Perla u16 max_nic_evt_qs; /* NIC's share of evt qs */ 44292bf14abSSathya Perla u32 if_cap_flags; 44310cccf60SVasundhara Volam u32 vf_if_cap_flags; /* VF if capability flags */ 444b9263cbfSSuresh Reddy u32 flags; 445de2b1e03SSomnath Kotur /* Calculated PF Pool's share of RSS Tables. This is not enforced by 446de2b1e03SSomnath Kotur * the FW, but is a self-imposed driver limitation. 447de2b1e03SSomnath Kotur */ 448de2b1e03SSomnath Kotur u16 max_rss_tables; 449de2b1e03SSomnath Kotur }; 450de2b1e03SSomnath Kotur 451de2b1e03SSomnath Kotur /* These are port-wide values */ 452de2b1e03SSomnath Kotur struct be_port_resources { 453de2b1e03SSomnath Kotur u16 max_vfs; 454de2b1e03SSomnath Kotur u16 nic_pfs; 45592bf14abSSathya Perla }; 45692bf14abSSathya Perla 457760c295eSVenkata Duvvuru #define be_is_os2bmc_enabled(adapter) (adapter->flags & BE_FLAGS_OS2BMC) 458760c295eSVenkata Duvvuru 459e2557877SVenkata Duvvuru struct rss_info { 460e2557877SVenkata Duvvuru u64 rss_flags; 461e2557877SVenkata Duvvuru u8 rsstable[RSS_INDIR_TABLE_LEN]; 462e2557877SVenkata Duvvuru u8 rss_queue[RSS_INDIR_TABLE_LEN]; 463e2557877SVenkata Duvvuru u8 rss_hkey[RSS_HASH_KEY_LEN]; 464e2557877SVenkata Duvvuru }; 465e2557877SVenkata Duvvuru 46629e9122bSVenkata Duvvuru #define BE_INVALID_DIE_TEMP 0xFF 46729e9122bSVenkata Duvvuru struct be_hwmon { 46829e9122bSVenkata Duvvuru struct device *hwmon_dev; 46929e9122bSVenkata Duvvuru u8 be_on_die_temp; /* Unit: millidegree Celsius */ 47029e9122bSVenkata Duvvuru }; 47129e9122bSVenkata Duvvuru 472804abcdbSSriharsha Basavapatna /* Macros to read/write the 'features' word of be_wrb_params structure. 473804abcdbSSriharsha Basavapatna */ 474804abcdbSSriharsha Basavapatna #define BE_WRB_F_BIT(name) BE_WRB_F_##name##_BIT 475804abcdbSSriharsha Basavapatna #define BE_WRB_F_MASK(name) BIT_MASK(BE_WRB_F_##name##_BIT) 476804abcdbSSriharsha Basavapatna 477804abcdbSSriharsha Basavapatna #define BE_WRB_F_GET(word, name) \ 478804abcdbSSriharsha Basavapatna (((word) & (BE_WRB_F_MASK(name))) >> BE_WRB_F_BIT(name)) 479804abcdbSSriharsha Basavapatna 480804abcdbSSriharsha Basavapatna #define BE_WRB_F_SET(word, name, val) \ 481804abcdbSSriharsha Basavapatna ((word) |= (((val) << BE_WRB_F_BIT(name)) & BE_WRB_F_MASK(name))) 482804abcdbSSriharsha Basavapatna 483804abcdbSSriharsha Basavapatna /* Feature/offload bits */ 484804abcdbSSriharsha Basavapatna enum { 485804abcdbSSriharsha Basavapatna BE_WRB_F_CRC_BIT, /* Ethernet CRC */ 486804abcdbSSriharsha Basavapatna BE_WRB_F_IPCS_BIT, /* IP csum */ 487804abcdbSSriharsha Basavapatna BE_WRB_F_TCPCS_BIT, /* TCP csum */ 488804abcdbSSriharsha Basavapatna BE_WRB_F_UDPCS_BIT, /* UDP csum */ 489804abcdbSSriharsha Basavapatna BE_WRB_F_LSO_BIT, /* LSO */ 490804abcdbSSriharsha Basavapatna BE_WRB_F_LSO6_BIT, /* LSO6 */ 491804abcdbSSriharsha Basavapatna BE_WRB_F_VLAN_BIT, /* VLAN */ 492760c295eSVenkata Duvvuru BE_WRB_F_VLAN_SKIP_HW_BIT, /* Skip VLAN tag (workaround) */ 493760c295eSVenkata Duvvuru BE_WRB_F_OS2BMC_BIT /* Send packet to the management ring */ 494804abcdbSSriharsha Basavapatna }; 495804abcdbSSriharsha Basavapatna 496804abcdbSSriharsha Basavapatna /* The structure below provides a HW-agnostic abstraction of WRB params 497804abcdbSSriharsha Basavapatna * retrieved from a TX skb. This is in turn passed to chip specific routines 498804abcdbSSriharsha Basavapatna * during transmit, to set the corresponding params in the WRB. 499804abcdbSSriharsha Basavapatna */ 500804abcdbSSriharsha Basavapatna struct be_wrb_params { 501804abcdbSSriharsha Basavapatna u32 features; /* Feature bits */ 502804abcdbSSriharsha Basavapatna u16 vlan_tag; /* VLAN tag */ 503804abcdbSSriharsha Basavapatna u16 lso_mss; /* MSS for LSO */ 504804abcdbSSriharsha Basavapatna }; 505804abcdbSSriharsha Basavapatna 506b7172414SSathya Perla struct be_eth_addr { 507b7172414SSathya Perla unsigned char mac[ETH_ALEN]; 508b7172414SSathya Perla }; 509b7172414SSathya Perla 510710f3e59SSriharsha Basavapatna #define BE_SEC 1000 /* in msec */ 511710f3e59SSriharsha Basavapatna #define BE_MIN (60 * BE_SEC) /* in msec */ 512710f3e59SSriharsha Basavapatna #define BE_HOUR (60 * BE_MIN) /* in msec */ 513710f3e59SSriharsha Basavapatna 514710f3e59SSriharsha Basavapatna #define ERR_RECOVERY_MAX_RETRY_COUNT 3 515710f3e59SSriharsha Basavapatna #define ERR_RECOVERY_DETECTION_DELAY BE_SEC 516710f3e59SSriharsha Basavapatna #define ERR_RECOVERY_RETRY_DELAY (30 * BE_SEC) 517710f3e59SSriharsha Basavapatna 518710f3e59SSriharsha Basavapatna /* UE-detection-duration in BEx/Skyhawk: 519710f3e59SSriharsha Basavapatna * All PFs must wait for this duration after they detect UE before reading 520710f3e59SSriharsha Basavapatna * SLIPORT_SEMAPHORE register. At the end of this duration, the Firmware 521710f3e59SSriharsha Basavapatna * guarantees that the SLIPORT_SEMAPHORE register is updated to indicate 522710f3e59SSriharsha Basavapatna * if the UE is recoverable. 523710f3e59SSriharsha Basavapatna */ 524710f3e59SSriharsha Basavapatna #define ERR_RECOVERY_UE_DETECT_DURATION BE_SEC 525710f3e59SSriharsha Basavapatna 526710f3e59SSriharsha Basavapatna /* Initial idle time (in msec) to elapse after driver load, 527710f3e59SSriharsha Basavapatna * before UE recovery is allowed. 528710f3e59SSriharsha Basavapatna */ 529710f3e59SSriharsha Basavapatna #define ERR_IDLE_HR 24 530710f3e59SSriharsha Basavapatna #define ERR_RECOVERY_IDLE_TIME (ERR_IDLE_HR * BE_HOUR) 531710f3e59SSriharsha Basavapatna 532710f3e59SSriharsha Basavapatna /* Time interval (in msec) after which UE recovery can be repeated */ 533710f3e59SSriharsha Basavapatna #define ERR_INTERVAL_HR 72 534710f3e59SSriharsha Basavapatna #define ERR_RECOVERY_INTERVAL (ERR_INTERVAL_HR * BE_HOUR) 535710f3e59SSriharsha Basavapatna 536710f3e59SSriharsha Basavapatna /* BEx/SH UE recovery state machine */ 537710f3e59SSriharsha Basavapatna enum { 538710f3e59SSriharsha Basavapatna ERR_RECOVERY_ST_NONE = 0, /* No Recovery */ 539710f3e59SSriharsha Basavapatna ERR_RECOVERY_ST_DETECT = 1, /* UE detection duration */ 540710f3e59SSriharsha Basavapatna ERR_RECOVERY_ST_RESET = 2, /* Reset Phase (PF0 only) */ 541710f3e59SSriharsha Basavapatna ERR_RECOVERY_ST_PRE_POLL = 3, /* Pre-Poll Phase (all PFs) */ 542710f3e59SSriharsha Basavapatna ERR_RECOVERY_ST_REINIT = 4 /* Re-initialize Phase */ 543710f3e59SSriharsha Basavapatna }; 544710f3e59SSriharsha Basavapatna 545710f3e59SSriharsha Basavapatna struct be_error_recovery { 546710f3e59SSriharsha Basavapatna /* Lancer error recovery variables */ 547710f3e59SSriharsha Basavapatna u8 recovery_retries; 548710f3e59SSriharsha Basavapatna 549710f3e59SSriharsha Basavapatna /* BEx/Skyhawk error recovery variables */ 550710f3e59SSriharsha Basavapatna u8 recovery_state; 551710f3e59SSriharsha Basavapatna u16 ue_to_reset_time; /* Time after UE, to soft reset 552710f3e59SSriharsha Basavapatna * the chip - PF0 only 553710f3e59SSriharsha Basavapatna */ 554710f3e59SSriharsha Basavapatna u16 ue_to_poll_time; /* Time after UE, to Restart Polling 555710f3e59SSriharsha Basavapatna * of SLIPORT_SEMAPHORE reg 556710f3e59SSriharsha Basavapatna */ 557710f3e59SSriharsha Basavapatna u16 last_err_code; 558710f3e59SSriharsha Basavapatna bool recovery_supported; 559710f3e59SSriharsha Basavapatna unsigned long probe_time; 560710f3e59SSriharsha Basavapatna unsigned long last_recovery_time; 561710f3e59SSriharsha Basavapatna 562710f3e59SSriharsha Basavapatna /* Common to both Lancer & BEx/SH error recovery */ 563710f3e59SSriharsha Basavapatna u32 resched_delay; 564710f3e59SSriharsha Basavapatna struct delayed_work err_detection_work; 565710f3e59SSriharsha Basavapatna }; 566710f3e59SSriharsha Basavapatna 567710f3e59SSriharsha Basavapatna /* Ethtool priv_flags */ 568710f3e59SSriharsha Basavapatna #define BE_DISABLE_TPE_RECOVERY 0x1 569710f3e59SSriharsha Basavapatna 570bf8d9dfbSSriharsha Basavapatna struct be_vxlan_port { 571bf8d9dfbSSriharsha Basavapatna struct list_head list; 572bf8d9dfbSSriharsha Basavapatna __be16 port; /* VxLAN UDP dst port */ 573bf8d9dfbSSriharsha Basavapatna int port_aliases; /* alias count */ 574bf8d9dfbSSriharsha Basavapatna }; 575bf8d9dfbSSriharsha Basavapatna 5769aebddd1SJeff Kirsher struct be_adapter { 5779aebddd1SJeff Kirsher struct pci_dev *pdev; 5789aebddd1SJeff Kirsher struct net_device *netdev; 5799aebddd1SJeff Kirsher 580c5b3ad4cSSathya Perla u8 __iomem *csr; /* CSR BAR used only for BE2/3 */ 5819aebddd1SJeff Kirsher u8 __iomem *db; /* Door Bell */ 58225848c90SSuresh Reddy u8 __iomem *pcicfg; /* On SH,BEx only. Shadow of PCI config space */ 5839aebddd1SJeff Kirsher 5849aebddd1SJeff Kirsher struct mutex mbox_lock; /* For serializing mbox cmds to BE card */ 5859aebddd1SJeff Kirsher struct be_dma_mem mbox_mem; 5869aebddd1SJeff Kirsher /* Mbox mem is adjusted to align to 16 bytes. The allocated addr 5879aebddd1SJeff Kirsher * is stored for freeing purpose */ 5889aebddd1SJeff Kirsher struct be_dma_mem mbox_mem_alloced; 5899aebddd1SJeff Kirsher 5909aebddd1SJeff Kirsher struct be_mcc_obj mcc_obj; 591b7172414SSathya Perla struct mutex mcc_lock; /* For serializing mcc cmds to BE card */ 5929aebddd1SJeff Kirsher spinlock_t mcc_cq_lock; 5939aebddd1SJeff Kirsher 594e261768eSSathya Perla u16 cfg_num_rx_irqs; /* configured via set-channels */ 595e261768eSSathya Perla u16 cfg_num_tx_irqs; /* configured via set-channels */ 59692bf14abSSathya Perla u16 num_evt_qs; 59792bf14abSSathya Perla u16 num_msix_vec; 59892bf14abSSathya Perla struct be_eq_obj eq_obj[MAX_EVT_QS]; 59910ef9ab4SSathya Perla struct msix_entry msix_entries[MAX_MSIX_VECTORS]; 6009aebddd1SJeff Kirsher bool isr_registered; 6019aebddd1SJeff Kirsher 6029aebddd1SJeff Kirsher /* TX Rings */ 60392bf14abSSathya Perla u16 num_tx_qs; 6049aebddd1SJeff Kirsher struct be_tx_obj tx_obj[MAX_TX_QS]; 6059aebddd1SJeff Kirsher 6069aebddd1SJeff Kirsher /* Rx rings */ 60792bf14abSSathya Perla u16 num_rx_qs; 60871bb8bd0SVasundhara Volam u16 num_rss_qs; 60971bb8bd0SVasundhara Volam u16 need_def_rxq; 61010ef9ab4SSathya Perla struct be_rx_obj rx_obj[MAX_RX_QS]; 6119aebddd1SJeff Kirsher u32 big_page_size; /* Compounded page size shared by rx wrbs */ 6129aebddd1SJeff Kirsher 6139aebddd1SJeff Kirsher struct be_drv_stats drv_stats; 6142632bafdSSathya Perla struct be_aic_obj aic_obj[MAX_EVT_QS]; 6159aebddd1SJeff Kirsher u8 vlan_prio_bmap; /* Available Priority BitMap */ 616fdf81bfbSSathya Perla u16 recommended_prio_bits;/* Recommended Priority bits in vlan tag */ 6179aebddd1SJeff Kirsher struct be_dma_mem rx_filter; /* Cmd DMA mem for rx-filter */ 6189aebddd1SJeff Kirsher 6199aebddd1SJeff Kirsher struct be_dma_mem stats_cmd; 6209aebddd1SJeff Kirsher /* Work queue used to perform periodic tasks like getting statistics */ 6219aebddd1SJeff Kirsher struct delayed_work work; 6229aebddd1SJeff Kirsher u16 work_counter; 6239aebddd1SJeff Kirsher 624972f37b4SPadmanabh Ratnakar u8 recovery_retries; 625954f6825SVenkata Duvvuru u8 err_flags; 626a69bf3c5SDouglas Miller bool pcicfg_mapped; /* pcicfg obtained via pci_iomap() */ 627b236916aSAjit Khaparde u32 flags; 628f25b119cSPadmanabh Ratnakar u32 cmd_privileges; 6299aebddd1SJeff Kirsher /* Ethtool knobs and info */ 6309aebddd1SJeff Kirsher char fw_ver[FW_VER_LEN]; 631eeb65cedSSomnath Kotur char fw_on_flash[FW_VER_LEN]; 632f66b7cfdSSathya Perla 633f66b7cfdSSathya Perla /* IFACE filtering fields */ 63430128031SSathya Perla int if_handle; /* Used to configure filtering */ 635f66b7cfdSSathya Perla u32 if_flags; /* Interface filtering flags */ 636fbc13f01SAjit Khaparde u32 *pmac_id; /* MAC addr handle used by BE card */ 637b7172414SSathya Perla struct be_eth_addr *uc_list;/* list of uc-addrs programmed (not perm) */ 638f66b7cfdSSathya Perla u32 uc_macs; /* Count of secondary UC MAC programmed */ 639b7172414SSathya Perla struct be_eth_addr *mc_list;/* list of mcast addrs programmed */ 640b7172414SSathya Perla u32 mc_count; 641f66b7cfdSSathya Perla unsigned long vids[BITS_TO_LONGS(VLAN_N_VID)]; 642f66b7cfdSSathya Perla u16 vlans_added; 64392fbb1dfSSriharsha Basavapatna bool update_uc_list; 64492fbb1dfSSriharsha Basavapatna bool update_mc_list; 645b7172414SSathya Perla struct mutex rx_filter_lock;/* For protecting vids[] & mc/uc_list[] */ 646f66b7cfdSSathya Perla 6479aebddd1SJeff Kirsher u32 beacon_state; /* for set_phys_id */ 6489aebddd1SJeff Kirsher 6499aebddd1SJeff Kirsher u32 port_num; 65021252377SVasundhara Volam char port_name; 651f93f160bSVasundhara Volam u8 mc_type; 6529aebddd1SJeff Kirsher u32 function_mode; 6539aebddd1SJeff Kirsher u32 function_caps; 6549aebddd1SJeff Kirsher u32 rx_fc; /* Rx flow control */ 6559aebddd1SJeff Kirsher u32 tx_fc; /* Tx flow control */ 6569aebddd1SJeff Kirsher bool stats_cmd_sent; 657045508a8SParav Pandit struct { 658045508a8SParav Pandit u32 size; 659045508a8SParav Pandit u32 total_size; 660045508a8SParav Pandit u64 io_addr; 661045508a8SParav Pandit } roce_db; 662045508a8SParav Pandit u32 num_msix_roce_vec; 663045508a8SParav Pandit struct ocrdma_dev *ocrdma_dev; 664045508a8SParav Pandit struct list_head entry; 665045508a8SParav Pandit 6669aebddd1SJeff Kirsher u32 flash_status; 6675eeff635SSuresh Reddy struct completion et_cmd_compl; 6689aebddd1SJeff Kirsher 669bec84e6bSVasundhara Volam struct be_resources pool_res; /* resources available for the port */ 67092bf14abSSathya Perla struct be_resources res; /* resources available for the func */ 67192bf14abSSathya Perla u16 num_vfs; /* Number of VFs provisioned by PF */ 672980df249SSuresh Reddy u8 pf_num; /* Numbering used by FW, starts at 0 */ 673980df249SSuresh Reddy u8 vf_num; /* Numbering used by FW, starts at 1 */ 67439f1d94dSSathya Perla u8 virtfn; 67511ac75edSSathya Perla struct be_vf_cfg *vf_cfg; 67611ac75edSSathya Perla bool be3_native; 6779aebddd1SJeff Kirsher u32 sli_family; 6789aebddd1SJeff Kirsher u8 hba_port_num; 6799aebddd1SJeff Kirsher u16 pvid; 680bf8d9dfbSSriharsha Basavapatna __be16 vxlan_port; /* offloaded vxlan port num */ 681bf8d9dfbSSriharsha Basavapatna int vxlan_port_count; /* active vxlan port count */ 682bf8d9dfbSSriharsha Basavapatna struct list_head vxlan_port_list; /* vxlan port list */ 68342f11cf2SAjit Khaparde struct phy_info phy; 6844762f6ceSAjit Khaparde u8 wol_cap; 68576a9e08eSSuresh Reddy bool wol_en; 6860ad3157eSVasundhara Volam u16 asic_rev; 687bc0c3405SAjit Khaparde u16 qnq_vid; 688941a77d5SSomnath Kotur u32 msg_enable; 6897aeb2156SPadmanabh Ratnakar int be_get_temp_freq; 69029e9122bSVenkata Duvvuru struct be_hwmon hwmon_info; 691e2557877SVenkata Duvvuru struct rss_info rss_info; 692760c295eSVenkata Duvvuru /* Filters for packets that need to be sent to BMC */ 693760c295eSVenkata Duvvuru u32 bmc_filt_mask; 694fd7ff6f0SVenkat Duvvuru u32 fat_dump_len; 695a155a5dbSSriharsha Basavapatna u16 serial_num[CNTL_SERIAL_NUM_WORDS]; 69651d1f98aSAjit Khaparde u8 phy_state; /* state of sfp optics (functional, faulted, etc.,) */ 697c27ebf58SSuresh Reddy u8 dev_mac[ETH_ALEN]; 698710f3e59SSriharsha Basavapatna u32 priv_flags; /* ethtool get/set_priv_flags() */ 699710f3e59SSriharsha Basavapatna struct be_error_recovery error_recovery; 7009aebddd1SJeff Kirsher }; 7019aebddd1SJeff Kirsher 702b7172414SSathya Perla /* Used for defered FW config cmds. Add fields to this struct as reqd */ 703b7172414SSathya Perla struct be_cmd_work { 704b7172414SSathya Perla struct work_struct work; 705b7172414SSathya Perla struct be_adapter *adapter; 706b7172414SSathya Perla union { 707b7172414SSathya Perla __be16 vxlan_port; 708b7172414SSathya Perla } info; 709b7172414SSathya Perla }; 710b7172414SSathya Perla 71139f1d94dSSathya Perla #define be_physfn(adapter) (!adapter->virtfn) 7122c7a9dc1SAjit Khaparde #define be_virtfn(adapter) (adapter->virtfn) 713f174c7ecSVasundhara Volam #define sriov_enabled(adapter) (adapter->flags & \ 714f174c7ecSVasundhara Volam BE_FLAGS_SRIOV_ENABLED) 715bec84e6bSVasundhara Volam 71611ac75edSSathya Perla #define for_all_vfs(adapter, vf_cfg, i) \ 71711ac75edSSathya Perla for (i = 0, vf_cfg = &adapter->vf_cfg[i]; i < adapter->num_vfs; \ 71811ac75edSSathya Perla i++, vf_cfg++) 7199aebddd1SJeff Kirsher 7209aebddd1SJeff Kirsher #define ON 1 7219aebddd1SJeff Kirsher #define OFF 0 722ca34fe38SSathya Perla 72392bf14abSSathya Perla #define be_max_vlans(adapter) (adapter->res.max_vlans) 72492bf14abSSathya Perla #define be_max_uc(adapter) (adapter->res.max_uc_mac) 72592bf14abSSathya Perla #define be_max_mc(adapter) (adapter->res.max_mcast_mac) 726bec84e6bSVasundhara Volam #define be_max_vfs(adapter) (adapter->pool_res.max_vfs) 72792bf14abSSathya Perla #define be_max_rss(adapter) (adapter->res.max_rss_qs) 72892bf14abSSathya Perla #define be_max_txqs(adapter) (adapter->res.max_tx_qs) 72992bf14abSSathya Perla #define be_max_prio_txqs(adapter) (adapter->res.max_prio_tx_qs) 73092bf14abSSathya Perla #define be_max_rxqs(adapter) (adapter->res.max_rx_qs) 731ce7faf0aSSathya Perla /* Max number of EQs available for the function (NIC + RoCE (if enabled)) */ 732ce7faf0aSSathya Perla #define be_max_func_eqs(adapter) (adapter->res.max_evt_qs) 733ce7faf0aSSathya Perla /* Max number of EQs available avaialble only for NIC */ 734ce7faf0aSSathya Perla #define be_max_nic_eqs(adapter) (adapter->res.max_nic_evt_qs) 73592bf14abSSathya Perla #define be_if_cap_flags(adapter) (adapter->res.if_cap_flags) 736de2b1e03SSomnath Kotur #define be_max_pf_pool_rss_tables(adapter) \ 737de2b1e03SSomnath Kotur (adapter->pool_res.max_rss_tables) 738e261768eSSathya Perla /* Max irqs avaialble for NIC */ 739e261768eSSathya Perla #define be_max_irqs(adapter) \ 740e261768eSSathya Perla (min_t(u16, be_max_nic_eqs(adapter), num_online_cpus())) 74192bf14abSSathya Perla 742e261768eSSathya Perla /* Max irqs *needed* for RX queues */ 743e261768eSSathya Perla static inline u16 be_max_rx_irqs(struct be_adapter *adapter) 74492bf14abSSathya Perla { 745e261768eSSathya Perla /* If no RSS, need atleast one irq for def-RXQ */ 74692bf14abSSathya Perla u16 num = max_t(u16, be_max_rss(adapter), 1); 74792bf14abSSathya Perla 748e261768eSSathya Perla return min_t(u16, num, be_max_irqs(adapter)); 749e261768eSSathya Perla } 750e261768eSSathya Perla 751e261768eSSathya Perla /* Max irqs *needed* for TX queues */ 752e261768eSSathya Perla static inline u16 be_max_tx_irqs(struct be_adapter *adapter) 753e261768eSSathya Perla { 754e261768eSSathya Perla return min_t(u16, be_max_txqs(adapter), be_max_irqs(adapter)); 755e261768eSSathya Perla } 756e261768eSSathya Perla 757e261768eSSathya Perla /* Max irqs *needed* for combined queues */ 758e261768eSSathya Perla static inline u16 be_max_qp_irqs(struct be_adapter *adapter) 759e261768eSSathya Perla { 760e261768eSSathya Perla return min(be_max_tx_irqs(adapter), be_max_rx_irqs(adapter)); 761e261768eSSathya Perla } 762e261768eSSathya Perla 763e261768eSSathya Perla /* Max irqs *needed* for RX and TX queues together */ 764e261768eSSathya Perla static inline u16 be_max_any_irqs(struct be_adapter *adapter) 765e261768eSSathya Perla { 766e261768eSSathya Perla return max(be_max_tx_irqs(adapter), be_max_rx_irqs(adapter)); 76792bf14abSSathya Perla } 76892bf14abSSathya Perla 769f93f160bSVasundhara Volam /* Is BE in pvid_tagging mode */ 770f93f160bSVasundhara Volam #define be_pvid_tagging_enabled(adapter) (adapter->pvid) 771f93f160bSVasundhara Volam 772f93f160bSVasundhara Volam /* Is BE in QNQ multi-channel mode */ 77366064dbcSSuresh Reddy #define be_is_qnq_mode(adapter) (adapter->function_mode & QNQ_MODE) 774f93f160bSVasundhara Volam 775ca34fe38SSathya Perla #define lancer_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID3 || \ 776ca34fe38SSathya Perla adapter->pdev->device == OC_DEVICE_ID4) 7779aebddd1SJeff Kirsher 77876b73530SPadmanabh Ratnakar #define skyhawk_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID5 || \ 77976b73530SPadmanabh Ratnakar adapter->pdev->device == OC_DEVICE_ID6) 780d3bd3a5eSPadmanabh Ratnakar 781ca34fe38SSathya Perla #define BE3_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID2 || \ 782ca34fe38SSathya Perla adapter->pdev->device == OC_DEVICE_ID2) 783ca34fe38SSathya Perla 784ca34fe38SSathya Perla #define BE2_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID1 || \ 785ca34fe38SSathya Perla adapter->pdev->device == OC_DEVICE_ID1) 786ca34fe38SSathya Perla 787ca34fe38SSathya Perla #define BEx_chip(adapter) (BE3_chip(adapter) || BE2_chip(adapter)) 788d3bd3a5eSPadmanabh Ratnakar 789dbf0f2a7SSathya Perla #define be_roce_supported(adapter) (skyhawk_chip(adapter) && \ 790045508a8SParav Pandit (adapter->function_mode & RDMA_ENABLED)) 791045508a8SParav Pandit 7929aebddd1SJeff Kirsher extern const struct ethtool_ops be_ethtool_ops; 7939aebddd1SJeff Kirsher 7949aebddd1SJeff Kirsher #define msix_enabled(adapter) (adapter->num_msix_vec > 0) 79510ef9ab4SSathya Perla #define num_irqs(adapter) (msix_enabled(adapter) ? \ 79610ef9ab4SSathya Perla adapter->num_msix_vec : 1) 79710ef9ab4SSathya Perla #define tx_stats(txo) (&(txo)->stats) 79810ef9ab4SSathya Perla #define rx_stats(rxo) (&(rxo)->stats) 7999aebddd1SJeff Kirsher 80010ef9ab4SSathya Perla /* The default RXQ is the last RXQ */ 80110ef9ab4SSathya Perla #define default_rxo(adpt) (&adpt->rx_obj[adpt->num_rx_qs - 1]) 8029aebddd1SJeff Kirsher 8039aebddd1SJeff Kirsher #define for_all_rx_queues(adapter, rxo, i) \ 8049aebddd1SJeff Kirsher for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \ 8059aebddd1SJeff Kirsher i++, rxo++) 8069aebddd1SJeff Kirsher 8079aebddd1SJeff Kirsher #define for_all_rss_queues(adapter, rxo, i) \ 80871bb8bd0SVasundhara Volam for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rss_qs; \ 8099aebddd1SJeff Kirsher i++, rxo++) 8109aebddd1SJeff Kirsher 8119aebddd1SJeff Kirsher #define for_all_tx_queues(adapter, txo, i) \ 8129aebddd1SJeff Kirsher for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs; \ 8139aebddd1SJeff Kirsher i++, txo++) 8149aebddd1SJeff Kirsher 81510ef9ab4SSathya Perla #define for_all_evt_queues(adapter, eqo, i) \ 81610ef9ab4SSathya Perla for (i = 0, eqo = &adapter->eq_obj[i]; i < adapter->num_evt_qs; \ 81710ef9ab4SSathya Perla i++, eqo++) 81810ef9ab4SSathya Perla 8196384a4d0SSathya Perla #define for_all_rx_queues_on_eq(adapter, eqo, rxo, i) \ 8206384a4d0SSathya Perla for (i = eqo->idx, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs;\ 8216384a4d0SSathya Perla i += adapter->num_evt_qs, rxo += adapter->num_evt_qs) 8226384a4d0SSathya Perla 823a4906ea0SSathya Perla #define for_all_tx_queues_on_eq(adapter, eqo, txo, i) \ 824a4906ea0SSathya Perla for (i = eqo->idx, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs;\ 825a4906ea0SSathya Perla i += adapter->num_evt_qs, txo += adapter->num_evt_qs) 826a4906ea0SSathya Perla 82710ef9ab4SSathya Perla #define is_mcc_eqo(eqo) (eqo->idx == 0) 82810ef9ab4SSathya Perla #define mcc_eqo(adapter) (&adapter->eq_obj[0]) 82910ef9ab4SSathya Perla 8309aebddd1SJeff Kirsher #define PAGE_SHIFT_4K 12 8319aebddd1SJeff Kirsher #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K) 8329aebddd1SJeff Kirsher 8339aebddd1SJeff Kirsher /* Returns number of pages spanned by the data starting at the given addr */ 8349aebddd1SJeff Kirsher #define PAGES_4K_SPANNED(_address, size) \ 8359aebddd1SJeff Kirsher ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \ 8369aebddd1SJeff Kirsher (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K)) 8379aebddd1SJeff Kirsher 8389aebddd1SJeff Kirsher /* Returns bit offset within a DWORD of a bitfield */ 8399aebddd1SJeff Kirsher #define AMAP_BIT_OFFSET(_struct, field) \ 8409aebddd1SJeff Kirsher (((size_t)&(((_struct *)0)->field))%32) 8419aebddd1SJeff Kirsher 8429aebddd1SJeff Kirsher /* Returns the bit mask of the field that is NOT shifted into location. */ 8439aebddd1SJeff Kirsher static inline u32 amap_mask(u32 bitsize) 8449aebddd1SJeff Kirsher { 8459aebddd1SJeff Kirsher return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1); 8469aebddd1SJeff Kirsher } 8479aebddd1SJeff Kirsher 8489aebddd1SJeff Kirsher static inline void 8499aebddd1SJeff Kirsher amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value) 8509aebddd1SJeff Kirsher { 8519aebddd1SJeff Kirsher u32 *dw = (u32 *) ptr + dw_offset; 8529aebddd1SJeff Kirsher *dw &= ~(mask << offset); 8539aebddd1SJeff Kirsher *dw |= (mask & value) << offset; 8549aebddd1SJeff Kirsher } 8559aebddd1SJeff Kirsher 8569aebddd1SJeff Kirsher #define AMAP_SET_BITS(_struct, field, ptr, val) \ 8579aebddd1SJeff Kirsher amap_set(ptr, \ 8589aebddd1SJeff Kirsher offsetof(_struct, field)/32, \ 8599aebddd1SJeff Kirsher amap_mask(sizeof(((_struct *)0)->field)), \ 8609aebddd1SJeff Kirsher AMAP_BIT_OFFSET(_struct, field), \ 8619aebddd1SJeff Kirsher val) 8629aebddd1SJeff Kirsher 8639aebddd1SJeff Kirsher static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset) 8649aebddd1SJeff Kirsher { 8659aebddd1SJeff Kirsher u32 *dw = (u32 *) ptr; 8669aebddd1SJeff Kirsher return mask & (*(dw + dw_offset) >> offset); 8679aebddd1SJeff Kirsher } 8689aebddd1SJeff Kirsher 8699aebddd1SJeff Kirsher #define AMAP_GET_BITS(_struct, field, ptr) \ 8709aebddd1SJeff Kirsher amap_get(ptr, \ 8719aebddd1SJeff Kirsher offsetof(_struct, field)/32, \ 8729aebddd1SJeff Kirsher amap_mask(sizeof(((_struct *)0)->field)), \ 8739aebddd1SJeff Kirsher AMAP_BIT_OFFSET(_struct, field)) 8749aebddd1SJeff Kirsher 875c3c18bc1SSathya Perla #define GET_RX_COMPL_V0_BITS(field, ptr) \ 876c3c18bc1SSathya Perla AMAP_GET_BITS(struct amap_eth_rx_compl_v0, field, ptr) 877c3c18bc1SSathya Perla 878c3c18bc1SSathya Perla #define GET_RX_COMPL_V1_BITS(field, ptr) \ 879c3c18bc1SSathya Perla AMAP_GET_BITS(struct amap_eth_rx_compl_v1, field, ptr) 880c3c18bc1SSathya Perla 881c3c18bc1SSathya Perla #define GET_TX_COMPL_BITS(field, ptr) \ 882c3c18bc1SSathya Perla AMAP_GET_BITS(struct amap_eth_tx_compl, field, ptr) 883c3c18bc1SSathya Perla 884c3c18bc1SSathya Perla #define SET_TX_WRB_HDR_BITS(field, ptr, val) \ 885c3c18bc1SSathya Perla AMAP_SET_BITS(struct amap_eth_hdr_wrb, field, ptr, val) 886c3c18bc1SSathya Perla 8879aebddd1SJeff Kirsher #define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len) 8889aebddd1SJeff Kirsher #define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len) 8899aebddd1SJeff Kirsher static inline void swap_dws(void *wrb, int len) 8909aebddd1SJeff Kirsher { 8919aebddd1SJeff Kirsher #ifdef __BIG_ENDIAN 8929aebddd1SJeff Kirsher u32 *dw = wrb; 8939aebddd1SJeff Kirsher BUG_ON(len % 4); 8949aebddd1SJeff Kirsher do { 8959aebddd1SJeff Kirsher *dw = cpu_to_le32(*dw); 8969aebddd1SJeff Kirsher dw++; 8979aebddd1SJeff Kirsher len -= 4; 8989aebddd1SJeff Kirsher } while (len); 8999aebddd1SJeff Kirsher #endif /* __BIG_ENDIAN */ 9009aebddd1SJeff Kirsher } 9019aebddd1SJeff Kirsher 9020532d4e3SKalesh AP #define be_cmd_status(status) (status > 0 ? -EIO : status) 9030532d4e3SKalesh AP 9049aebddd1SJeff Kirsher static inline u8 is_tcp_pkt(struct sk_buff *skb) 9059aebddd1SJeff Kirsher { 9069aebddd1SJeff Kirsher u8 val = 0; 9079aebddd1SJeff Kirsher 9089aebddd1SJeff Kirsher if (ip_hdr(skb)->version == 4) 9099aebddd1SJeff Kirsher val = (ip_hdr(skb)->protocol == IPPROTO_TCP); 9109aebddd1SJeff Kirsher else if (ip_hdr(skb)->version == 6) 9119aebddd1SJeff Kirsher val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP); 9129aebddd1SJeff Kirsher 9139aebddd1SJeff Kirsher return val; 9149aebddd1SJeff Kirsher } 9159aebddd1SJeff Kirsher 9169aebddd1SJeff Kirsher static inline u8 is_udp_pkt(struct sk_buff *skb) 9179aebddd1SJeff Kirsher { 9189aebddd1SJeff Kirsher u8 val = 0; 9199aebddd1SJeff Kirsher 9209aebddd1SJeff Kirsher if (ip_hdr(skb)->version == 4) 9219aebddd1SJeff Kirsher val = (ip_hdr(skb)->protocol == IPPROTO_UDP); 9229aebddd1SJeff Kirsher else if (ip_hdr(skb)->version == 6) 9239aebddd1SJeff Kirsher val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP); 9249aebddd1SJeff Kirsher 9259aebddd1SJeff Kirsher return val; 9269aebddd1SJeff Kirsher } 9279aebddd1SJeff Kirsher 92893040ae5SSomnath Kotur static inline bool is_ipv4_pkt(struct sk_buff *skb) 92993040ae5SSomnath Kotur { 930e8efcec5SLi RongQing return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 93193040ae5SSomnath Kotur } 93293040ae5SSomnath Kotur 933710f3e59SSriharsha Basavapatna #define be_error_recovering(adapter) \ 934710f3e59SSriharsha Basavapatna (adapter->flags & BE_FLAGS_TRY_RECOVERY) 935710f3e59SSriharsha Basavapatna 936954f6825SVenkata Duvvuru #define BE_ERROR_EEH 1 937954f6825SVenkata Duvvuru #define BE_ERROR_UE BIT(1) 938954f6825SVenkata Duvvuru #define BE_ERROR_FW BIT(2) 939954f6825SVenkata Duvvuru #define BE_ERROR_HW (BE_ERROR_EEH | BE_ERROR_UE) 940954f6825SVenkata Duvvuru #define BE_ERROR_ANY (BE_ERROR_EEH | BE_ERROR_UE | BE_ERROR_FW) 941954f6825SVenkata Duvvuru #define BE_CLEAR_ALL 0xFF 942954f6825SVenkata Duvvuru 943954f6825SVenkata Duvvuru static inline u8 be_check_error(struct be_adapter *adapter, u32 err_type) 944954f6825SVenkata Duvvuru { 945954f6825SVenkata Duvvuru return (adapter->err_flags & err_type); 946954f6825SVenkata Duvvuru } 947954f6825SVenkata Duvvuru 948954f6825SVenkata Duvvuru static inline void be_set_error(struct be_adapter *adapter, int err_type) 949954f6825SVenkata Duvvuru { 950954f6825SVenkata Duvvuru struct net_device *netdev = adapter->netdev; 951954f6825SVenkata Duvvuru 952954f6825SVenkata Duvvuru adapter->err_flags |= err_type; 953954f6825SVenkata Duvvuru netif_carrier_off(netdev); 954954f6825SVenkata Duvvuru 955954f6825SVenkata Duvvuru dev_info(&adapter->pdev->dev, "%s: Link down\n", netdev->name); 956954f6825SVenkata Duvvuru } 957954f6825SVenkata Duvvuru 958954f6825SVenkata Duvvuru static inline void be_clear_error(struct be_adapter *adapter, int err_type) 959954f6825SVenkata Duvvuru { 960954f6825SVenkata Duvvuru adapter->err_flags &= ~err_type; 961954f6825SVenkata Duvvuru } 962954f6825SVenkata Duvvuru 9639aebddd1SJeff Kirsher static inline bool be_multi_rxq(const struct be_adapter *adapter) 9649aebddd1SJeff Kirsher { 9659aebddd1SJeff Kirsher return adapter->num_rx_qs > 1; 9669aebddd1SJeff Kirsher } 9679aebddd1SJeff Kirsher 96831886e87SJoe Perches void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, 9699aebddd1SJeff Kirsher u16 num_popped); 97031886e87SJoe Perches void be_link_status_update(struct be_adapter *adapter, u8 link_status); 97131886e87SJoe Perches void be_parse_stats(struct be_adapter *adapter); 97231886e87SJoe Perches int be_load_fw(struct be_adapter *adapter, u8 *func); 97331886e87SJoe Perches bool be_is_wol_supported(struct be_adapter *adapter); 97431886e87SJoe Perches bool be_pause_supported(struct be_adapter *adapter); 97531886e87SJoe Perches u32 be_get_fw_log_level(struct be_adapter *adapter); 97668d7bdcbSSathya Perla int be_update_queues(struct be_adapter *adapter); 97768d7bdcbSSathya Perla int be_poll(struct napi_struct *napi, int budget); 97820947770SPadmanabh Ratnakar void be_eqd_update(struct be_adapter *adapter, bool force_update); 979941a77d5SSomnath Kotur 980045508a8SParav Pandit /* 981045508a8SParav Pandit * internal function to initialize-cleanup roce device. 982045508a8SParav Pandit */ 98331886e87SJoe Perches void be_roce_dev_add(struct be_adapter *); 98431886e87SJoe Perches void be_roce_dev_remove(struct be_adapter *); 985045508a8SParav Pandit 986045508a8SParav Pandit /* 987045508a8SParav Pandit * internal function to open-close roce device during ifup-ifdown. 988045508a8SParav Pandit */ 989d114f99aSDevesh Sharma void be_roce_dev_shutdown(struct be_adapter *); 990045508a8SParav Pandit 9919aebddd1SJeff Kirsher #endif /* BE_H */ 992