19aebddd1SJeff Kirsher /* 2d19261b8SVasundhara Volam * Copyright (C) 2005 - 2015 Emulex 39aebddd1SJeff Kirsher * All rights reserved. 49aebddd1SJeff Kirsher * 59aebddd1SJeff Kirsher * This program is free software; you can redistribute it and/or 69aebddd1SJeff Kirsher * modify it under the terms of the GNU General Public License version 2 79aebddd1SJeff Kirsher * as published by the Free Software Foundation. The full GNU General 89aebddd1SJeff Kirsher * Public License is included in this distribution in the file called COPYING. 99aebddd1SJeff Kirsher * 109aebddd1SJeff Kirsher * Contact Information: 119aebddd1SJeff Kirsher * linux-drivers@emulex.com 129aebddd1SJeff Kirsher * 139aebddd1SJeff Kirsher * Emulex 149aebddd1SJeff Kirsher * 3333 Susan Street 159aebddd1SJeff Kirsher * Costa Mesa, CA 92626 169aebddd1SJeff Kirsher */ 179aebddd1SJeff Kirsher 189aebddd1SJeff Kirsher #ifndef BE_H 199aebddd1SJeff Kirsher #define BE_H 209aebddd1SJeff Kirsher 219aebddd1SJeff Kirsher #include <linux/pci.h> 229aebddd1SJeff Kirsher #include <linux/etherdevice.h> 239aebddd1SJeff Kirsher #include <linux/delay.h> 249aebddd1SJeff Kirsher #include <net/tcp.h> 259aebddd1SJeff Kirsher #include <net/ip.h> 269aebddd1SJeff Kirsher #include <net/ipv6.h> 279aebddd1SJeff Kirsher #include <linux/if_vlan.h> 289aebddd1SJeff Kirsher #include <linux/workqueue.h> 299aebddd1SJeff Kirsher #include <linux/interrupt.h> 309aebddd1SJeff Kirsher #include <linux/firmware.h> 319aebddd1SJeff Kirsher #include <linux/slab.h> 329aebddd1SJeff Kirsher #include <linux/u64_stats_sync.h> 33d658d98aSPadmanabh Ratnakar #include <linux/cpumask.h> 3429e9122bSVenkata Duvvuru #include <linux/hwmon.h> 3529e9122bSVenkata Duvvuru #include <linux/hwmon-sysfs.h> 369aebddd1SJeff Kirsher 379aebddd1SJeff Kirsher #include "be_hw.h" 38045508a8SParav Pandit #include "be_roce.h" 399aebddd1SJeff Kirsher 40ab07ead5SSuresh Reddy #define DRV_VER "11.0.0.0" 419aebddd1SJeff Kirsher #define DRV_NAME "be2net" 4200d3d51eSSarveshwar Bandi #define BE_NAME "Emulex BladeEngine2" 4300d3d51eSSarveshwar Bandi #define BE3_NAME "Emulex BladeEngine3" 4400d3d51eSSarveshwar Bandi #define OC_NAME "Emulex OneConnect" 459aebddd1SJeff Kirsher #define OC_NAME_BE OC_NAME "(be3)" 469aebddd1SJeff Kirsher #define OC_NAME_LANCER OC_NAME "(Lancer)" 47ecedb6aeSAjit Khaparde #define OC_NAME_SH OC_NAME "(Skyhawk)" 48f3effb45SSuresh Reddy #define DRV_DESC "Emulex OneConnect NIC Driver" 499aebddd1SJeff Kirsher 509aebddd1SJeff Kirsher #define BE_VENDOR_ID 0x19a2 519aebddd1SJeff Kirsher #define EMULEX_VENDOR_ID 0x10df 529aebddd1SJeff Kirsher #define BE_DEVICE_ID1 0x211 539aebddd1SJeff Kirsher #define BE_DEVICE_ID2 0x221 549aebddd1SJeff Kirsher #define OC_DEVICE_ID1 0x700 /* Device Id for BE2 cards */ 559aebddd1SJeff Kirsher #define OC_DEVICE_ID2 0x710 /* Device Id for BE3 cards */ 569aebddd1SJeff Kirsher #define OC_DEVICE_ID3 0xe220 /* Device id for Lancer cards */ 579aebddd1SJeff Kirsher #define OC_DEVICE_ID4 0xe228 /* Device id for VF in Lancer */ 58ecedb6aeSAjit Khaparde #define OC_DEVICE_ID5 0x720 /* Device Id for Skyhawk cards */ 5976b73530SPadmanabh Ratnakar #define OC_DEVICE_ID6 0x728 /* Device id for VF in SkyHawk */ 604762f6ceSAjit Khaparde #define OC_SUBSYS_DEVICE_ID1 0xE602 614762f6ceSAjit Khaparde #define OC_SUBSYS_DEVICE_ID2 0xE642 624762f6ceSAjit Khaparde #define OC_SUBSYS_DEVICE_ID3 0xE612 634762f6ceSAjit Khaparde #define OC_SUBSYS_DEVICE_ID4 0xE652 649aebddd1SJeff Kirsher 659aebddd1SJeff Kirsher /* Number of bytes of an RX frame that are copied to skb->data */ 669aebddd1SJeff Kirsher #define BE_HDR_LEN ((u16) 64) 67bb349bb4SEric Dumazet /* allocate extra space to allow tunneling decapsulation without head reallocation */ 68bb349bb4SEric Dumazet #define BE_RX_SKB_ALLOC_SIZE (BE_HDR_LEN + 64) 69bb349bb4SEric Dumazet 709aebddd1SJeff Kirsher #define BE_MAX_JUMBO_FRAME_SIZE 9018 719aebddd1SJeff Kirsher #define BE_MIN_MTU 256 720d3f5cceSKalesh AP #define BE_MAX_MTU (BE_MAX_JUMBO_FRAME_SIZE - \ 730d3f5cceSKalesh AP (ETH_HLEN + ETH_FCS_LEN)) 749aebddd1SJeff Kirsher 759aebddd1SJeff Kirsher #define BE_NUM_VLANS_SUPPORTED 64 762632bafdSSathya Perla #define BE_MAX_EQD 128u 779aebddd1SJeff Kirsher #define BE_MAX_TX_FRAG_COUNT 30 789aebddd1SJeff Kirsher 799aebddd1SJeff Kirsher #define EVNT_Q_LEN 1024 809aebddd1SJeff Kirsher #define TX_Q_LEN 2048 819aebddd1SJeff Kirsher #define TX_CQ_LEN 1024 829aebddd1SJeff Kirsher #define RX_Q_LEN 1024 /* Does not support any other value */ 839aebddd1SJeff Kirsher #define RX_CQ_LEN 1024 849aebddd1SJeff Kirsher #define MCC_Q_LEN 128 /* total size not to exceed 8 pages */ 859aebddd1SJeff Kirsher #define MCC_CQ_LEN 256 869aebddd1SJeff Kirsher 8710ef9ab4SSathya Perla #define BE2_MAX_RSS_QS 4 8868d7bdcbSSathya Perla #define BE3_MAX_RSS_QS 16 8968d7bdcbSSathya Perla #define BE3_MAX_TX_QS 16 9068d7bdcbSSathya Perla #define BE3_MAX_EVT_QS 16 91e3dc867cSSuresh Reddy #define BE3_SRIOV_MAX_EVT_QS 8 9210ef9ab4SSathya Perla 93f2858738SVasundhara Volam #define MAX_RSS_IFACES 15 9468d7bdcbSSathya Perla #define MAX_RX_QS 32 9568d7bdcbSSathya Perla #define MAX_EVT_QS 32 9668d7bdcbSSathya Perla #define MAX_TX_QS 32 9768d7bdcbSSathya Perla 98045508a8SParav Pandit #define MAX_ROCE_EQS 5 9968d7bdcbSSathya Perla #define MAX_MSIX_VECTORS 32 10092bf14abSSathya Perla #define MIN_MSIX_VECTORS 1 1019aebddd1SJeff Kirsher #define BE_NAPI_WEIGHT 64 1029aebddd1SJeff Kirsher #define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */ 1039aebddd1SJeff Kirsher #define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST) 10469304cc9SAjit Khaparde #define MAX_NUM_POST_ERX_DB 255u 1059aebddd1SJeff Kirsher 1067c5a5242SVasundhara Volam #define MAX_VFS 30 /* Max VFs supported by BE3 FW */ 1079aebddd1SJeff Kirsher #define FW_VER_LEN 32 108a155a5dbSSriharsha Basavapatna #define CNTL_SERIAL_NUM_WORDS 8 /* Controller serial number words */ 109a155a5dbSSriharsha Basavapatna #define CNTL_SERIAL_NUM_WORD_SZ (sizeof(u16)) /* Byte-sz of serial num word */ 1109aebddd1SJeff Kirsher 111e2557877SVenkata Duvvuru #define RSS_INDIR_TABLE_LEN 128 112e2557877SVenkata Duvvuru #define RSS_HASH_KEY_LEN 40 113e2557877SVenkata Duvvuru 1149aebddd1SJeff Kirsher struct be_dma_mem { 1159aebddd1SJeff Kirsher void *va; 1169aebddd1SJeff Kirsher dma_addr_t dma; 1179aebddd1SJeff Kirsher u32 size; 1189aebddd1SJeff Kirsher }; 1199aebddd1SJeff Kirsher 1209aebddd1SJeff Kirsher struct be_queue_info { 1219aebddd1SJeff Kirsher struct be_dma_mem dma_mem; 1229aebddd1SJeff Kirsher u16 len; 1239aebddd1SJeff Kirsher u16 entry_size; /* Size of an element in the queue */ 1249aebddd1SJeff Kirsher u16 id; 1259aebddd1SJeff Kirsher u16 tail, head; 1269aebddd1SJeff Kirsher bool created; 1279aebddd1SJeff Kirsher atomic_t used; /* Number of valid elements in the queue */ 1289aebddd1SJeff Kirsher }; 1299aebddd1SJeff Kirsher 1309aebddd1SJeff Kirsher static inline u32 MODULO(u16 val, u16 limit) 1319aebddd1SJeff Kirsher { 1329aebddd1SJeff Kirsher BUG_ON(limit & (limit - 1)); 1339aebddd1SJeff Kirsher return val & (limit - 1); 1349aebddd1SJeff Kirsher } 1359aebddd1SJeff Kirsher 1369aebddd1SJeff Kirsher static inline void index_adv(u16 *index, u16 val, u16 limit) 1379aebddd1SJeff Kirsher { 1389aebddd1SJeff Kirsher *index = MODULO((*index + val), limit); 1399aebddd1SJeff Kirsher } 1409aebddd1SJeff Kirsher 1419aebddd1SJeff Kirsher static inline void index_inc(u16 *index, u16 limit) 1429aebddd1SJeff Kirsher { 1439aebddd1SJeff Kirsher *index = MODULO((*index + 1), limit); 1449aebddd1SJeff Kirsher } 1459aebddd1SJeff Kirsher 1469aebddd1SJeff Kirsher static inline void *queue_head_node(struct be_queue_info *q) 1479aebddd1SJeff Kirsher { 1489aebddd1SJeff Kirsher return q->dma_mem.va + q->head * q->entry_size; 1499aebddd1SJeff Kirsher } 1509aebddd1SJeff Kirsher 1519aebddd1SJeff Kirsher static inline void *queue_tail_node(struct be_queue_info *q) 1529aebddd1SJeff Kirsher { 1539aebddd1SJeff Kirsher return q->dma_mem.va + q->tail * q->entry_size; 1549aebddd1SJeff Kirsher } 1559aebddd1SJeff Kirsher 1563de09455SSomnath Kotur static inline void *queue_index_node(struct be_queue_info *q, u16 index) 1573de09455SSomnath Kotur { 1583de09455SSomnath Kotur return q->dma_mem.va + index * q->entry_size; 1593de09455SSomnath Kotur } 1603de09455SSomnath Kotur 1619aebddd1SJeff Kirsher static inline void queue_head_inc(struct be_queue_info *q) 1629aebddd1SJeff Kirsher { 1639aebddd1SJeff Kirsher index_inc(&q->head, q->len); 1649aebddd1SJeff Kirsher } 1659aebddd1SJeff Kirsher 166652bf646SPadmanabh Ratnakar static inline void index_dec(u16 *index, u16 limit) 167652bf646SPadmanabh Ratnakar { 168652bf646SPadmanabh Ratnakar *index = MODULO((*index - 1), limit); 169652bf646SPadmanabh Ratnakar } 170652bf646SPadmanabh Ratnakar 1719aebddd1SJeff Kirsher static inline void queue_tail_inc(struct be_queue_info *q) 1729aebddd1SJeff Kirsher { 1739aebddd1SJeff Kirsher index_inc(&q->tail, q->len); 1749aebddd1SJeff Kirsher } 1759aebddd1SJeff Kirsher 1769aebddd1SJeff Kirsher struct be_eq_obj { 1779aebddd1SJeff Kirsher struct be_queue_info q; 1789aebddd1SJeff Kirsher char desc[32]; 1799aebddd1SJeff Kirsher 1809aebddd1SJeff Kirsher /* Adaptive interrupt coalescing (AIC) info */ 1819aebddd1SJeff Kirsher bool enable_aic; 18210ef9ab4SSathya Perla u32 min_eqd; /* in usecs */ 18310ef9ab4SSathya Perla u32 max_eqd; /* in usecs */ 18410ef9ab4SSathya Perla u32 eqd; /* configured val when aic is off */ 18510ef9ab4SSathya Perla u32 cur_eqd; /* in usecs */ 1869aebddd1SJeff Kirsher 18710ef9ab4SSathya Perla u8 idx; /* array index */ 188f2f781a7SSathya Perla u8 msix_idx; 189d0b9cec3SSathya Perla u16 spurious_intr; 1909aebddd1SJeff Kirsher struct napi_struct napi; 19110ef9ab4SSathya Perla struct be_adapter *adapter; 192d658d98aSPadmanabh Ratnakar cpumask_var_t affinity_mask; 1936384a4d0SSathya Perla 1946384a4d0SSathya Perla #ifdef CONFIG_NET_RX_BUSY_POLL 1956384a4d0SSathya Perla #define BE_EQ_IDLE 0 1966384a4d0SSathya Perla #define BE_EQ_NAPI 1 /* napi owns this EQ */ 1976384a4d0SSathya Perla #define BE_EQ_POLL 2 /* poll owns this EQ */ 1986384a4d0SSathya Perla #define BE_EQ_LOCKED (BE_EQ_NAPI | BE_EQ_POLL) 1996384a4d0SSathya Perla #define BE_EQ_NAPI_YIELD 4 /* napi yielded this EQ */ 2006384a4d0SSathya Perla #define BE_EQ_POLL_YIELD 8 /* poll yielded this EQ */ 2016384a4d0SSathya Perla #define BE_EQ_YIELD (BE_EQ_NAPI_YIELD | BE_EQ_POLL_YIELD) 2026384a4d0SSathya Perla #define BE_EQ_USER_PEND (BE_EQ_POLL | BE_EQ_POLL_YIELD) 2036384a4d0SSathya Perla unsigned int state; 2046384a4d0SSathya Perla spinlock_t lock; /* lock to serialize napi and busy-poll */ 2056384a4d0SSathya Perla #endif /* CONFIG_NET_RX_BUSY_POLL */ 20610ef9ab4SSathya Perla } ____cacheline_aligned_in_smp; 2079aebddd1SJeff Kirsher 2082632bafdSSathya Perla struct be_aic_obj { /* Adaptive interrupt coalescing (AIC) info */ 2092632bafdSSathya Perla bool enable; 2102632bafdSSathya Perla u32 min_eqd; /* in usecs */ 2112632bafdSSathya Perla u32 max_eqd; /* in usecs */ 2122632bafdSSathya Perla u32 prev_eqd; /* in usecs */ 2132632bafdSSathya Perla u32 et_eqd; /* configured val when aic is off */ 2142632bafdSSathya Perla ulong jiffies; 2152632bafdSSathya Perla u64 rx_pkts_prev; /* Used to calculate RX pps */ 2162632bafdSSathya Perla u64 tx_reqs_prev; /* Used to calculate TX pps */ 2172632bafdSSathya Perla }; 2182632bafdSSathya Perla 2196384a4d0SSathya Perla enum { 2206384a4d0SSathya Perla NAPI_POLLING, 2216384a4d0SSathya Perla BUSY_POLLING 2226384a4d0SSathya Perla }; 2236384a4d0SSathya Perla 2249aebddd1SJeff Kirsher struct be_mcc_obj { 2259aebddd1SJeff Kirsher struct be_queue_info q; 2269aebddd1SJeff Kirsher struct be_queue_info cq; 2279aebddd1SJeff Kirsher bool rearm_cq; 2289aebddd1SJeff Kirsher }; 2299aebddd1SJeff Kirsher 2309aebddd1SJeff Kirsher struct be_tx_stats { 2319aebddd1SJeff Kirsher u64 tx_bytes; 2329aebddd1SJeff Kirsher u64 tx_pkts; 2338670f2a5SSriharsha Basavapatna u64 tx_vxlan_offload_pkts; 2349aebddd1SJeff Kirsher u64 tx_reqs; 2359aebddd1SJeff Kirsher u64 tx_compl; 2369aebddd1SJeff Kirsher ulong tx_jiffies; 2379aebddd1SJeff Kirsher u32 tx_stops; 238bc617526SSathya Perla u32 tx_drv_drops; /* pkts dropped by driver */ 239512bb8a2SKalesh AP /* the error counters are described in be_ethtool.c */ 240512bb8a2SKalesh AP u32 tx_hdr_parse_err; 241512bb8a2SKalesh AP u32 tx_dma_err; 242512bb8a2SKalesh AP u32 tx_tso_err; 243512bb8a2SKalesh AP u32 tx_spoof_check_err; 244512bb8a2SKalesh AP u32 tx_qinq_err; 245512bb8a2SKalesh AP u32 tx_internal_parity_err; 2469aebddd1SJeff Kirsher struct u64_stats_sync sync; 2479aebddd1SJeff Kirsher struct u64_stats_sync sync_compl; 2489aebddd1SJeff Kirsher }; 2499aebddd1SJeff Kirsher 250152ffe5bSSriharsha Basavapatna /* Structure to hold some data of interest obtained from a TX CQE */ 251152ffe5bSSriharsha Basavapatna struct be_tx_compl_info { 252152ffe5bSSriharsha Basavapatna u8 status; /* Completion status */ 253152ffe5bSSriharsha Basavapatna u16 end_index; /* Completed TXQ Index */ 254152ffe5bSSriharsha Basavapatna }; 255152ffe5bSSriharsha Basavapatna 2569aebddd1SJeff Kirsher struct be_tx_obj { 25794d73aaaSVasundhara Volam u32 db_offset; 2589aebddd1SJeff Kirsher struct be_queue_info q; 2599aebddd1SJeff Kirsher struct be_queue_info cq; 260152ffe5bSSriharsha Basavapatna struct be_tx_compl_info txcp; 2619aebddd1SJeff Kirsher /* Remember the skbs that were transmitted */ 2629aebddd1SJeff Kirsher struct sk_buff *sent_skb_list[TX_Q_LEN]; 2639aebddd1SJeff Kirsher struct be_tx_stats stats; 2645f07b3c5SSathya Perla u16 pend_wrb_cnt; /* Number of WRBs yet to be given to HW */ 2655f07b3c5SSathya Perla u16 last_req_wrb_cnt; /* wrb cnt of the last req in the Q */ 2665f07b3c5SSathya Perla u16 last_req_hdr; /* index of the last req's hdr-wrb */ 26710ef9ab4SSathya Perla } ____cacheline_aligned_in_smp; 2689aebddd1SJeff Kirsher 2699aebddd1SJeff Kirsher /* Struct to remember the pages posted for rx frags */ 2709aebddd1SJeff Kirsher struct be_rx_page_info { 2719aebddd1SJeff Kirsher struct page *page; 272e50287beSSathya Perla /* set to page-addr for last frag of the page & frag-addr otherwise */ 2739aebddd1SJeff Kirsher DEFINE_DMA_UNMAP_ADDR(bus); 2749aebddd1SJeff Kirsher u16 page_offset; 275e50287beSSathya Perla bool last_frag; /* last frag of the page */ 2769aebddd1SJeff Kirsher }; 2779aebddd1SJeff Kirsher 2789aebddd1SJeff Kirsher struct be_rx_stats { 2799aebddd1SJeff Kirsher u64 rx_bytes; 2809aebddd1SJeff Kirsher u64 rx_pkts; 2818670f2a5SSriharsha Basavapatna u64 rx_vxlan_offload_pkts; 2829aebddd1SJeff Kirsher u32 rx_drops_no_skbs; /* skb allocation errors */ 2839aebddd1SJeff Kirsher u32 rx_drops_no_frags; /* HW has no fetched frags */ 2849aebddd1SJeff Kirsher u32 rx_post_fail; /* page post alloc failures */ 2859aebddd1SJeff Kirsher u32 rx_compl; 2869aebddd1SJeff Kirsher u32 rx_mcast_pkts; 2879aebddd1SJeff Kirsher u32 rx_compl_err; /* completions with err set */ 2889aebddd1SJeff Kirsher struct u64_stats_sync sync; 2899aebddd1SJeff Kirsher }; 2909aebddd1SJeff Kirsher 2919aebddd1SJeff Kirsher struct be_rx_compl_info { 2929aebddd1SJeff Kirsher u32 rss_hash; 2939aebddd1SJeff Kirsher u16 vlan_tag; 2949aebddd1SJeff Kirsher u16 pkt_size; 2959aebddd1SJeff Kirsher u16 port; 2969aebddd1SJeff Kirsher u8 vlanf; 2979aebddd1SJeff Kirsher u8 num_rcvd; 2989aebddd1SJeff Kirsher u8 err; 2999aebddd1SJeff Kirsher u8 ipf; 3009aebddd1SJeff Kirsher u8 tcpf; 3019aebddd1SJeff Kirsher u8 udpf; 3029aebddd1SJeff Kirsher u8 ip_csum; 3039aebddd1SJeff Kirsher u8 l4_csum; 3049aebddd1SJeff Kirsher u8 ipv6; 305f93f160bSVasundhara Volam u8 qnq; 3069aebddd1SJeff Kirsher u8 pkt_type; 307e38b1706SSomnath Kotur u8 ip_frag; 308c9c47142SSathya Perla u8 tunneled; 3099aebddd1SJeff Kirsher }; 3109aebddd1SJeff Kirsher 3119aebddd1SJeff Kirsher struct be_rx_obj { 3129aebddd1SJeff Kirsher struct be_adapter *adapter; 3139aebddd1SJeff Kirsher struct be_queue_info q; 3149aebddd1SJeff Kirsher struct be_queue_info cq; 3159aebddd1SJeff Kirsher struct be_rx_compl_info rxcp; 3169aebddd1SJeff Kirsher struct be_rx_page_info page_info_tbl[RX_Q_LEN]; 3179aebddd1SJeff Kirsher struct be_rx_stats stats; 3189aebddd1SJeff Kirsher u8 rss_id; 3199aebddd1SJeff Kirsher bool rx_post_starved; /* Zero rx frags have been posted to BE */ 32010ef9ab4SSathya Perla } ____cacheline_aligned_in_smp; 3219aebddd1SJeff Kirsher 3229aebddd1SJeff Kirsher struct be_drv_stats { 3239aebddd1SJeff Kirsher u32 eth_red_drops; 324d3de1540SVasundhara Volam u32 dma_map_errors; 3259aebddd1SJeff Kirsher u32 rx_drops_no_pbuf; 3269aebddd1SJeff Kirsher u32 rx_drops_no_txpb; 3279aebddd1SJeff Kirsher u32 rx_drops_no_erx_descr; 3289aebddd1SJeff Kirsher u32 rx_drops_no_tpre_descr; 3299aebddd1SJeff Kirsher u32 rx_drops_too_many_frags; 3309aebddd1SJeff Kirsher u32 forwarded_packets; 3319aebddd1SJeff Kirsher u32 rx_drops_mtu; 3329aebddd1SJeff Kirsher u32 rx_crc_errors; 3339aebddd1SJeff Kirsher u32 rx_alignment_symbol_errors; 3349aebddd1SJeff Kirsher u32 rx_pause_frames; 3359aebddd1SJeff Kirsher u32 rx_priority_pause_frames; 3369aebddd1SJeff Kirsher u32 rx_control_frames; 3379aebddd1SJeff Kirsher u32 rx_in_range_errors; 3389aebddd1SJeff Kirsher u32 rx_out_range_errors; 3399aebddd1SJeff Kirsher u32 rx_frame_too_long; 34018fb06a1SSuresh Reddy u32 rx_address_filtered; 3419aebddd1SJeff Kirsher u32 rx_dropped_too_small; 3429aebddd1SJeff Kirsher u32 rx_dropped_too_short; 3439aebddd1SJeff Kirsher u32 rx_dropped_header_too_small; 3449aebddd1SJeff Kirsher u32 rx_dropped_tcp_length; 3459aebddd1SJeff Kirsher u32 rx_dropped_runt; 3469aebddd1SJeff Kirsher u32 rx_ip_checksum_errs; 3479aebddd1SJeff Kirsher u32 rx_tcp_checksum_errs; 3489aebddd1SJeff Kirsher u32 rx_udp_checksum_errs; 3499aebddd1SJeff Kirsher u32 tx_pauseframes; 3509aebddd1SJeff Kirsher u32 tx_priority_pauseframes; 3519aebddd1SJeff Kirsher u32 tx_controlframes; 3529aebddd1SJeff Kirsher u32 rxpp_fifo_overflow_drop; 3539aebddd1SJeff Kirsher u32 rx_input_fifo_overflow_drop; 3549aebddd1SJeff Kirsher u32 pmem_fifo_overflow_drop; 3559aebddd1SJeff Kirsher u32 jabber_events; 356461ae379SAjit Khaparde u32 rx_roce_bytes_lsd; 357461ae379SAjit Khaparde u32 rx_roce_bytes_msd; 358461ae379SAjit Khaparde u32 rx_roce_frames; 359461ae379SAjit Khaparde u32 roce_drops_payload_len; 360461ae379SAjit Khaparde u32 roce_drops_crc; 3619aebddd1SJeff Kirsher }; 3629aebddd1SJeff Kirsher 363c502224eSSomnath Kotur /* A vlan-id of 0xFFFF must be used to clear transparent vlan-tagging */ 364c502224eSSomnath Kotur #define BE_RESET_VLAN_TAG_ID 0xFFFF 365c502224eSSomnath Kotur 3669aebddd1SJeff Kirsher struct be_vf_cfg { 36711ac75edSSathya Perla unsigned char mac_addr[ETH_ALEN]; 36811ac75edSSathya Perla int if_handle; 36911ac75edSSathya Perla int pmac_id; 37011ac75edSSathya Perla u16 vlan_tag; 37111ac75edSSathya Perla u32 tx_rate; 372bdce2ad7SSuresh Reddy u32 plink_tracking; 373435452aaSVasundhara Volam u32 privileges; 374e7bcbd7bSKalesh AP bool spoofchk; 3759aebddd1SJeff Kirsher }; 3769aebddd1SJeff Kirsher 37739f1d94dSSathya Perla enum vf_state { 37839f1d94dSSathya Perla ENABLED = 0, 37939f1d94dSSathya Perla ASSIGNED = 1 38039f1d94dSSathya Perla }; 38139f1d94dSSathya Perla 38283b06116SVasundhara Volam #define BE_FLAGS_LINK_STATUS_INIT BIT(1) 38383b06116SVasundhara Volam #define BE_FLAGS_SRIOV_ENABLED BIT(2) 38483b06116SVasundhara Volam #define BE_FLAGS_WORKER_SCHEDULED BIT(3) 38583b06116SVasundhara Volam #define BE_FLAGS_NAPI_ENABLED BIT(6) 38683b06116SVasundhara Volam #define BE_FLAGS_QNQ_ASYNC_EVT_RCVD BIT(7) 38783b06116SVasundhara Volam #define BE_FLAGS_VXLAN_OFFLOADS BIT(8) 38883b06116SVasundhara Volam #define BE_FLAGS_SETUP_DONE BIT(9) 38921252377SVasundhara Volam #define BE_FLAGS_EVT_INCOMPATIBLE_SFP BIT(10) 390eb7dd46cSSathya Perla #define BE_FLAGS_ERR_DETECTION_SCHEDULED BIT(11) 391760c295eSVenkata Duvvuru #define BE_FLAGS_OS2BMC BIT(12) 392c9c47142SSathya Perla 393fbc13f01SAjit Khaparde #define BE_UC_PMAC_COUNT 30 394fbc13f01SAjit Khaparde #define BE_VF_UC_PMAC_COUNT 2 395f0613380SKalesh AP 3965c510811SSomnath Kotur /* Ethtool set_dump flags */ 3975c510811SSomnath Kotur #define LANCER_INITIATE_FW_DUMP 0x1 398f0613380SKalesh AP #define LANCER_DELETE_FW_DUMP 0x2 3995c510811SSomnath Kotur 40042f11cf2SAjit Khaparde struct phy_info { 40121252377SVasundhara Volam /* From SFF-8472 spec */ 40221252377SVasundhara Volam #define SFP_VENDOR_NAME_LEN 17 40342f11cf2SAjit Khaparde u8 transceiver; 40442f11cf2SAjit Khaparde u8 autoneg; 40542f11cf2SAjit Khaparde u8 fc_autoneg; 40642f11cf2SAjit Khaparde u8 port_type; 40742f11cf2SAjit Khaparde u16 phy_type; 40842f11cf2SAjit Khaparde u16 interface_type; 40942f11cf2SAjit Khaparde u32 misc_params; 41042f11cf2SAjit Khaparde u16 auto_speeds_supported; 41142f11cf2SAjit Khaparde u16 fixed_speeds_supported; 41242f11cf2SAjit Khaparde int link_speed; 41342f11cf2SAjit Khaparde u32 advertising; 41442f11cf2SAjit Khaparde u32 supported; 4156809cee0SRavikumar Nelavelli u8 cable_type; 41621252377SVasundhara Volam u8 vendor_name[SFP_VENDOR_NAME_LEN]; 41721252377SVasundhara Volam u8 vendor_pn[SFP_VENDOR_NAME_LEN]; 41842f11cf2SAjit Khaparde }; 41942f11cf2SAjit Khaparde 42092bf14abSSathya Perla struct be_resources { 42192bf14abSSathya Perla u16 max_vfs; /* Total VFs "really" supported by FW/HW */ 42292bf14abSSathya Perla u16 max_mcast_mac; 42392bf14abSSathya Perla u16 max_tx_qs; 42492bf14abSSathya Perla u16 max_rss_qs; 42592bf14abSSathya Perla u16 max_rx_qs; 426f2858738SVasundhara Volam u16 max_cq_count; 42792bf14abSSathya Perla u16 max_uc_mac; /* Max UC MACs programmable */ 42892bf14abSSathya Perla u16 max_vlans; /* Number of vlans supported */ 429f2858738SVasundhara Volam u16 max_iface_count; 430f2858738SVasundhara Volam u16 max_mcc_count; 43192bf14abSSathya Perla u16 max_evt_qs; 43292bf14abSSathya Perla u32 if_cap_flags; 43310cccf60SVasundhara Volam u32 vf_if_cap_flags; /* VF if capability flags */ 43492bf14abSSathya Perla }; 43592bf14abSSathya Perla 436760c295eSVenkata Duvvuru #define be_is_os2bmc_enabled(adapter) (adapter->flags & BE_FLAGS_OS2BMC) 437760c295eSVenkata Duvvuru 438e2557877SVenkata Duvvuru struct rss_info { 439e2557877SVenkata Duvvuru u64 rss_flags; 440e2557877SVenkata Duvvuru u8 rsstable[RSS_INDIR_TABLE_LEN]; 441e2557877SVenkata Duvvuru u8 rss_queue[RSS_INDIR_TABLE_LEN]; 442e2557877SVenkata Duvvuru u8 rss_hkey[RSS_HASH_KEY_LEN]; 443e2557877SVenkata Duvvuru }; 444e2557877SVenkata Duvvuru 44529e9122bSVenkata Duvvuru #define BE_INVALID_DIE_TEMP 0xFF 44629e9122bSVenkata Duvvuru struct be_hwmon { 44729e9122bSVenkata Duvvuru struct device *hwmon_dev; 44829e9122bSVenkata Duvvuru u8 be_on_die_temp; /* Unit: millidegree Celsius */ 44929e9122bSVenkata Duvvuru }; 45029e9122bSVenkata Duvvuru 451804abcdbSSriharsha Basavapatna /* Macros to read/write the 'features' word of be_wrb_params structure. 452804abcdbSSriharsha Basavapatna */ 453804abcdbSSriharsha Basavapatna #define BE_WRB_F_BIT(name) BE_WRB_F_##name##_BIT 454804abcdbSSriharsha Basavapatna #define BE_WRB_F_MASK(name) BIT_MASK(BE_WRB_F_##name##_BIT) 455804abcdbSSriharsha Basavapatna 456804abcdbSSriharsha Basavapatna #define BE_WRB_F_GET(word, name) \ 457804abcdbSSriharsha Basavapatna (((word) & (BE_WRB_F_MASK(name))) >> BE_WRB_F_BIT(name)) 458804abcdbSSriharsha Basavapatna 459804abcdbSSriharsha Basavapatna #define BE_WRB_F_SET(word, name, val) \ 460804abcdbSSriharsha Basavapatna ((word) |= (((val) << BE_WRB_F_BIT(name)) & BE_WRB_F_MASK(name))) 461804abcdbSSriharsha Basavapatna 462804abcdbSSriharsha Basavapatna /* Feature/offload bits */ 463804abcdbSSriharsha Basavapatna enum { 464804abcdbSSriharsha Basavapatna BE_WRB_F_CRC_BIT, /* Ethernet CRC */ 465804abcdbSSriharsha Basavapatna BE_WRB_F_IPCS_BIT, /* IP csum */ 466804abcdbSSriharsha Basavapatna BE_WRB_F_TCPCS_BIT, /* TCP csum */ 467804abcdbSSriharsha Basavapatna BE_WRB_F_UDPCS_BIT, /* UDP csum */ 468804abcdbSSriharsha Basavapatna BE_WRB_F_LSO_BIT, /* LSO */ 469804abcdbSSriharsha Basavapatna BE_WRB_F_LSO6_BIT, /* LSO6 */ 470804abcdbSSriharsha Basavapatna BE_WRB_F_VLAN_BIT, /* VLAN */ 471760c295eSVenkata Duvvuru BE_WRB_F_VLAN_SKIP_HW_BIT, /* Skip VLAN tag (workaround) */ 472760c295eSVenkata Duvvuru BE_WRB_F_OS2BMC_BIT /* Send packet to the management ring */ 473804abcdbSSriharsha Basavapatna }; 474804abcdbSSriharsha Basavapatna 475804abcdbSSriharsha Basavapatna /* The structure below provides a HW-agnostic abstraction of WRB params 476804abcdbSSriharsha Basavapatna * retrieved from a TX skb. This is in turn passed to chip specific routines 477804abcdbSSriharsha Basavapatna * during transmit, to set the corresponding params in the WRB. 478804abcdbSSriharsha Basavapatna */ 479804abcdbSSriharsha Basavapatna struct be_wrb_params { 480804abcdbSSriharsha Basavapatna u32 features; /* Feature bits */ 481804abcdbSSriharsha Basavapatna u16 vlan_tag; /* VLAN tag */ 482804abcdbSSriharsha Basavapatna u16 lso_mss; /* MSS for LSO */ 483804abcdbSSriharsha Basavapatna }; 484804abcdbSSriharsha Basavapatna 4859aebddd1SJeff Kirsher struct be_adapter { 4869aebddd1SJeff Kirsher struct pci_dev *pdev; 4879aebddd1SJeff Kirsher struct net_device *netdev; 4889aebddd1SJeff Kirsher 489c5b3ad4cSSathya Perla u8 __iomem *csr; /* CSR BAR used only for BE2/3 */ 4909aebddd1SJeff Kirsher u8 __iomem *db; /* Door Bell */ 49125848c90SSuresh Reddy u8 __iomem *pcicfg; /* On SH,BEx only. Shadow of PCI config space */ 4929aebddd1SJeff Kirsher 4939aebddd1SJeff Kirsher struct mutex mbox_lock; /* For serializing mbox cmds to BE card */ 4949aebddd1SJeff Kirsher struct be_dma_mem mbox_mem; 4959aebddd1SJeff Kirsher /* Mbox mem is adjusted to align to 16 bytes. The allocated addr 4969aebddd1SJeff Kirsher * is stored for freeing purpose */ 4979aebddd1SJeff Kirsher struct be_dma_mem mbox_mem_alloced; 4989aebddd1SJeff Kirsher 4999aebddd1SJeff Kirsher struct be_mcc_obj mcc_obj; 5009aebddd1SJeff Kirsher spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */ 5019aebddd1SJeff Kirsher spinlock_t mcc_cq_lock; 5029aebddd1SJeff Kirsher 50392bf14abSSathya Perla u16 cfg_num_qs; /* configured via set-channels */ 50492bf14abSSathya Perla u16 num_evt_qs; 50592bf14abSSathya Perla u16 num_msix_vec; 50692bf14abSSathya Perla struct be_eq_obj eq_obj[MAX_EVT_QS]; 50710ef9ab4SSathya Perla struct msix_entry msix_entries[MAX_MSIX_VECTORS]; 5089aebddd1SJeff Kirsher bool isr_registered; 5099aebddd1SJeff Kirsher 5109aebddd1SJeff Kirsher /* TX Rings */ 51192bf14abSSathya Perla u16 num_tx_qs; 5129aebddd1SJeff Kirsher struct be_tx_obj tx_obj[MAX_TX_QS]; 5139aebddd1SJeff Kirsher 5149aebddd1SJeff Kirsher /* Rx rings */ 51592bf14abSSathya Perla u16 num_rx_qs; 51671bb8bd0SVasundhara Volam u16 num_rss_qs; 51771bb8bd0SVasundhara Volam u16 need_def_rxq; 51810ef9ab4SSathya Perla struct be_rx_obj rx_obj[MAX_RX_QS]; 5199aebddd1SJeff Kirsher u32 big_page_size; /* Compounded page size shared by rx wrbs */ 5209aebddd1SJeff Kirsher 5219aebddd1SJeff Kirsher struct be_drv_stats drv_stats; 5222632bafdSSathya Perla struct be_aic_obj aic_obj[MAX_EVT_QS]; 5239aebddd1SJeff Kirsher u8 vlan_prio_bmap; /* Available Priority BitMap */ 524fdf81bfbSSathya Perla u16 recommended_prio_bits;/* Recommended Priority bits in vlan tag */ 5259aebddd1SJeff Kirsher struct be_dma_mem rx_filter; /* Cmd DMA mem for rx-filter */ 5269aebddd1SJeff Kirsher 5279aebddd1SJeff Kirsher struct be_dma_mem stats_cmd; 5289aebddd1SJeff Kirsher /* Work queue used to perform periodic tasks like getting statistics */ 5299aebddd1SJeff Kirsher struct delayed_work work; 5309aebddd1SJeff Kirsher u16 work_counter; 5319aebddd1SJeff Kirsher 532eb7dd46cSSathya Perla struct delayed_work be_err_detection_work; 533954f6825SVenkata Duvvuru u8 err_flags; 534a69bf3c5SDouglas Miller bool pcicfg_mapped; /* pcicfg obtained via pci_iomap() */ 535b236916aSAjit Khaparde u32 flags; 536f25b119cSPadmanabh Ratnakar u32 cmd_privileges; 5379aebddd1SJeff Kirsher /* Ethtool knobs and info */ 5389aebddd1SJeff Kirsher char fw_ver[FW_VER_LEN]; 539eeb65cedSSomnath Kotur char fw_on_flash[FW_VER_LEN]; 540f66b7cfdSSathya Perla 541f66b7cfdSSathya Perla /* IFACE filtering fields */ 54230128031SSathya Perla int if_handle; /* Used to configure filtering */ 543f66b7cfdSSathya Perla u32 if_flags; /* Interface filtering flags */ 544fbc13f01SAjit Khaparde u32 *pmac_id; /* MAC addr handle used by BE card */ 545f66b7cfdSSathya Perla u32 uc_macs; /* Count of secondary UC MAC programmed */ 546f66b7cfdSSathya Perla unsigned long vids[BITS_TO_LONGS(VLAN_N_VID)]; 547f66b7cfdSSathya Perla u16 vlans_added; 548f66b7cfdSSathya Perla 5499aebddd1SJeff Kirsher u32 beacon_state; /* for set_phys_id */ 5509aebddd1SJeff Kirsher 5519aebddd1SJeff Kirsher u32 port_num; 55221252377SVasundhara Volam char port_name; 553f93f160bSVasundhara Volam u8 mc_type; 5549aebddd1SJeff Kirsher u32 function_mode; 5559aebddd1SJeff Kirsher u32 function_caps; 5569aebddd1SJeff Kirsher u32 rx_fc; /* Rx flow control */ 5579aebddd1SJeff Kirsher u32 tx_fc; /* Tx flow control */ 5589aebddd1SJeff Kirsher bool stats_cmd_sent; 559045508a8SParav Pandit struct { 560045508a8SParav Pandit u32 size; 561045508a8SParav Pandit u32 total_size; 562045508a8SParav Pandit u64 io_addr; 563045508a8SParav Pandit } roce_db; 564045508a8SParav Pandit u32 num_msix_roce_vec; 565045508a8SParav Pandit struct ocrdma_dev *ocrdma_dev; 566045508a8SParav Pandit struct list_head entry; 567045508a8SParav Pandit 5689aebddd1SJeff Kirsher u32 flash_status; 5695eeff635SSuresh Reddy struct completion et_cmd_compl; 5709aebddd1SJeff Kirsher 571bec84e6bSVasundhara Volam struct be_resources pool_res; /* resources available for the port */ 57292bf14abSSathya Perla struct be_resources res; /* resources available for the func */ 57392bf14abSSathya Perla u16 num_vfs; /* Number of VFs provisioned by PF */ 574980df249SSuresh Reddy u8 pf_num; /* Numbering used by FW, starts at 0 */ 575980df249SSuresh Reddy u8 vf_num; /* Numbering used by FW, starts at 1 */ 57639f1d94dSSathya Perla u8 virtfn; 57711ac75edSSathya Perla struct be_vf_cfg *vf_cfg; 57811ac75edSSathya Perla bool be3_native; 5799aebddd1SJeff Kirsher u32 sli_family; 5809aebddd1SJeff Kirsher u8 hba_port_num; 5819aebddd1SJeff Kirsher u16 pvid; 582c9c47142SSathya Perla __be16 vxlan_port; 583630f4b70SSriharsha Basavapatna int vxlan_port_count; 5841e5b311aSJiri Benc int vxlan_port_aliases; 58542f11cf2SAjit Khaparde struct phy_info phy; 5864762f6ceSAjit Khaparde u8 wol_cap; 58776a9e08eSSuresh Reddy bool wol_en; 5880ad3157eSVasundhara Volam u16 asic_rev; 589bc0c3405SAjit Khaparde u16 qnq_vid; 590941a77d5SSomnath Kotur u32 msg_enable; 5917aeb2156SPadmanabh Ratnakar int be_get_temp_freq; 59229e9122bSVenkata Duvvuru struct be_hwmon hwmon_info; 593e2557877SVenkata Duvvuru struct rss_info rss_info; 594760c295eSVenkata Duvvuru /* Filters for packets that need to be sent to BMC */ 595760c295eSVenkata Duvvuru u32 bmc_filt_mask; 596fd7ff6f0SVenkat Duvvuru u32 fat_dump_len; 597a155a5dbSSriharsha Basavapatna u16 serial_num[CNTL_SERIAL_NUM_WORDS]; 5989aebddd1SJeff Kirsher }; 5999aebddd1SJeff Kirsher 60039f1d94dSSathya Perla #define be_physfn(adapter) (!adapter->virtfn) 6012c7a9dc1SAjit Khaparde #define be_virtfn(adapter) (adapter->virtfn) 602f174c7ecSVasundhara Volam #define sriov_enabled(adapter) (adapter->flags & \ 603f174c7ecSVasundhara Volam BE_FLAGS_SRIOV_ENABLED) 604bec84e6bSVasundhara Volam 60511ac75edSSathya Perla #define for_all_vfs(adapter, vf_cfg, i) \ 60611ac75edSSathya Perla for (i = 0, vf_cfg = &adapter->vf_cfg[i]; i < adapter->num_vfs; \ 60711ac75edSSathya Perla i++, vf_cfg++) 6089aebddd1SJeff Kirsher 6099aebddd1SJeff Kirsher #define ON 1 6109aebddd1SJeff Kirsher #define OFF 0 611ca34fe38SSathya Perla 61292bf14abSSathya Perla #define be_max_vlans(adapter) (adapter->res.max_vlans) 61392bf14abSSathya Perla #define be_max_uc(adapter) (adapter->res.max_uc_mac) 61492bf14abSSathya Perla #define be_max_mc(adapter) (adapter->res.max_mcast_mac) 615bec84e6bSVasundhara Volam #define be_max_vfs(adapter) (adapter->pool_res.max_vfs) 61692bf14abSSathya Perla #define be_max_rss(adapter) (adapter->res.max_rss_qs) 61792bf14abSSathya Perla #define be_max_txqs(adapter) (adapter->res.max_tx_qs) 61892bf14abSSathya Perla #define be_max_prio_txqs(adapter) (adapter->res.max_prio_tx_qs) 61992bf14abSSathya Perla #define be_max_rxqs(adapter) (adapter->res.max_rx_qs) 62092bf14abSSathya Perla #define be_max_eqs(adapter) (adapter->res.max_evt_qs) 62192bf14abSSathya Perla #define be_if_cap_flags(adapter) (adapter->res.if_cap_flags) 62292bf14abSSathya Perla 62392bf14abSSathya Perla static inline u16 be_max_qs(struct be_adapter *adapter) 62492bf14abSSathya Perla { 62592bf14abSSathya Perla /* If no RSS, need atleast the one def RXQ */ 62692bf14abSSathya Perla u16 num = max_t(u16, be_max_rss(adapter), 1); 62792bf14abSSathya Perla 62892bf14abSSathya Perla num = min(num, be_max_eqs(adapter)); 62992bf14abSSathya Perla return min_t(u16, num, num_online_cpus()); 63092bf14abSSathya Perla } 63192bf14abSSathya Perla 632f93f160bSVasundhara Volam /* Is BE in pvid_tagging mode */ 633f93f160bSVasundhara Volam #define be_pvid_tagging_enabled(adapter) (adapter->pvid) 634f93f160bSVasundhara Volam 635f93f160bSVasundhara Volam /* Is BE in QNQ multi-channel mode */ 63666064dbcSSuresh Reddy #define be_is_qnq_mode(adapter) (adapter->function_mode & QNQ_MODE) 637f93f160bSVasundhara Volam 638ca34fe38SSathya Perla #define lancer_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID3 || \ 639ca34fe38SSathya Perla adapter->pdev->device == OC_DEVICE_ID4) 6409aebddd1SJeff Kirsher 64176b73530SPadmanabh Ratnakar #define skyhawk_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID5 || \ 64276b73530SPadmanabh Ratnakar adapter->pdev->device == OC_DEVICE_ID6) 643d3bd3a5eSPadmanabh Ratnakar 644ca34fe38SSathya Perla #define BE3_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID2 || \ 645ca34fe38SSathya Perla adapter->pdev->device == OC_DEVICE_ID2) 646ca34fe38SSathya Perla 647ca34fe38SSathya Perla #define BE2_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID1 || \ 648ca34fe38SSathya Perla adapter->pdev->device == OC_DEVICE_ID1) 649ca34fe38SSathya Perla 650ca34fe38SSathya Perla #define BEx_chip(adapter) (BE3_chip(adapter) || BE2_chip(adapter)) 651d3bd3a5eSPadmanabh Ratnakar 652dbf0f2a7SSathya Perla #define be_roce_supported(adapter) (skyhawk_chip(adapter) && \ 653045508a8SParav Pandit (adapter->function_mode & RDMA_ENABLED)) 654045508a8SParav Pandit 6559aebddd1SJeff Kirsher extern const struct ethtool_ops be_ethtool_ops; 6569aebddd1SJeff Kirsher 6579aebddd1SJeff Kirsher #define msix_enabled(adapter) (adapter->num_msix_vec > 0) 65810ef9ab4SSathya Perla #define num_irqs(adapter) (msix_enabled(adapter) ? \ 65910ef9ab4SSathya Perla adapter->num_msix_vec : 1) 66010ef9ab4SSathya Perla #define tx_stats(txo) (&(txo)->stats) 66110ef9ab4SSathya Perla #define rx_stats(rxo) (&(rxo)->stats) 6629aebddd1SJeff Kirsher 66310ef9ab4SSathya Perla /* The default RXQ is the last RXQ */ 66410ef9ab4SSathya Perla #define default_rxo(adpt) (&adpt->rx_obj[adpt->num_rx_qs - 1]) 6659aebddd1SJeff Kirsher 6669aebddd1SJeff Kirsher #define for_all_rx_queues(adapter, rxo, i) \ 6679aebddd1SJeff Kirsher for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \ 6689aebddd1SJeff Kirsher i++, rxo++) 6699aebddd1SJeff Kirsher 6709aebddd1SJeff Kirsher #define for_all_rss_queues(adapter, rxo, i) \ 67171bb8bd0SVasundhara Volam for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rss_qs; \ 6729aebddd1SJeff Kirsher i++, rxo++) 6739aebddd1SJeff Kirsher 6749aebddd1SJeff Kirsher #define for_all_tx_queues(adapter, txo, i) \ 6759aebddd1SJeff Kirsher for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs; \ 6769aebddd1SJeff Kirsher i++, txo++) 6779aebddd1SJeff Kirsher 67810ef9ab4SSathya Perla #define for_all_evt_queues(adapter, eqo, i) \ 67910ef9ab4SSathya Perla for (i = 0, eqo = &adapter->eq_obj[i]; i < adapter->num_evt_qs; \ 68010ef9ab4SSathya Perla i++, eqo++) 68110ef9ab4SSathya Perla 6826384a4d0SSathya Perla #define for_all_rx_queues_on_eq(adapter, eqo, rxo, i) \ 6836384a4d0SSathya Perla for (i = eqo->idx, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs;\ 6846384a4d0SSathya Perla i += adapter->num_evt_qs, rxo += adapter->num_evt_qs) 6856384a4d0SSathya Perla 686a4906ea0SSathya Perla #define for_all_tx_queues_on_eq(adapter, eqo, txo, i) \ 687a4906ea0SSathya Perla for (i = eqo->idx, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs;\ 688a4906ea0SSathya Perla i += adapter->num_evt_qs, txo += adapter->num_evt_qs) 689a4906ea0SSathya Perla 69010ef9ab4SSathya Perla #define is_mcc_eqo(eqo) (eqo->idx == 0) 69110ef9ab4SSathya Perla #define mcc_eqo(adapter) (&adapter->eq_obj[0]) 69210ef9ab4SSathya Perla 6939aebddd1SJeff Kirsher #define PAGE_SHIFT_4K 12 6949aebddd1SJeff Kirsher #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K) 6959aebddd1SJeff Kirsher 6969aebddd1SJeff Kirsher /* Returns number of pages spanned by the data starting at the given addr */ 6979aebddd1SJeff Kirsher #define PAGES_4K_SPANNED(_address, size) \ 6989aebddd1SJeff Kirsher ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \ 6999aebddd1SJeff Kirsher (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K)) 7009aebddd1SJeff Kirsher 7019aebddd1SJeff Kirsher /* Returns bit offset within a DWORD of a bitfield */ 7029aebddd1SJeff Kirsher #define AMAP_BIT_OFFSET(_struct, field) \ 7039aebddd1SJeff Kirsher (((size_t)&(((_struct *)0)->field))%32) 7049aebddd1SJeff Kirsher 7059aebddd1SJeff Kirsher /* Returns the bit mask of the field that is NOT shifted into location. */ 7069aebddd1SJeff Kirsher static inline u32 amap_mask(u32 bitsize) 7079aebddd1SJeff Kirsher { 7089aebddd1SJeff Kirsher return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1); 7099aebddd1SJeff Kirsher } 7109aebddd1SJeff Kirsher 7119aebddd1SJeff Kirsher static inline void 7129aebddd1SJeff Kirsher amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value) 7139aebddd1SJeff Kirsher { 7149aebddd1SJeff Kirsher u32 *dw = (u32 *) ptr + dw_offset; 7159aebddd1SJeff Kirsher *dw &= ~(mask << offset); 7169aebddd1SJeff Kirsher *dw |= (mask & value) << offset; 7179aebddd1SJeff Kirsher } 7189aebddd1SJeff Kirsher 7199aebddd1SJeff Kirsher #define AMAP_SET_BITS(_struct, field, ptr, val) \ 7209aebddd1SJeff Kirsher amap_set(ptr, \ 7219aebddd1SJeff Kirsher offsetof(_struct, field)/32, \ 7229aebddd1SJeff Kirsher amap_mask(sizeof(((_struct *)0)->field)), \ 7239aebddd1SJeff Kirsher AMAP_BIT_OFFSET(_struct, field), \ 7249aebddd1SJeff Kirsher val) 7259aebddd1SJeff Kirsher 7269aebddd1SJeff Kirsher static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset) 7279aebddd1SJeff Kirsher { 7289aebddd1SJeff Kirsher u32 *dw = (u32 *) ptr; 7299aebddd1SJeff Kirsher return mask & (*(dw + dw_offset) >> offset); 7309aebddd1SJeff Kirsher } 7319aebddd1SJeff Kirsher 7329aebddd1SJeff Kirsher #define AMAP_GET_BITS(_struct, field, ptr) \ 7339aebddd1SJeff Kirsher amap_get(ptr, \ 7349aebddd1SJeff Kirsher offsetof(_struct, field)/32, \ 7359aebddd1SJeff Kirsher amap_mask(sizeof(((_struct *)0)->field)), \ 7369aebddd1SJeff Kirsher AMAP_BIT_OFFSET(_struct, field)) 7379aebddd1SJeff Kirsher 738c3c18bc1SSathya Perla #define GET_RX_COMPL_V0_BITS(field, ptr) \ 739c3c18bc1SSathya Perla AMAP_GET_BITS(struct amap_eth_rx_compl_v0, field, ptr) 740c3c18bc1SSathya Perla 741c3c18bc1SSathya Perla #define GET_RX_COMPL_V1_BITS(field, ptr) \ 742c3c18bc1SSathya Perla AMAP_GET_BITS(struct amap_eth_rx_compl_v1, field, ptr) 743c3c18bc1SSathya Perla 744c3c18bc1SSathya Perla #define GET_TX_COMPL_BITS(field, ptr) \ 745c3c18bc1SSathya Perla AMAP_GET_BITS(struct amap_eth_tx_compl, field, ptr) 746c3c18bc1SSathya Perla 747c3c18bc1SSathya Perla #define SET_TX_WRB_HDR_BITS(field, ptr, val) \ 748c3c18bc1SSathya Perla AMAP_SET_BITS(struct amap_eth_hdr_wrb, field, ptr, val) 749c3c18bc1SSathya Perla 7509aebddd1SJeff Kirsher #define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len) 7519aebddd1SJeff Kirsher #define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len) 7529aebddd1SJeff Kirsher static inline void swap_dws(void *wrb, int len) 7539aebddd1SJeff Kirsher { 7549aebddd1SJeff Kirsher #ifdef __BIG_ENDIAN 7559aebddd1SJeff Kirsher u32 *dw = wrb; 7569aebddd1SJeff Kirsher BUG_ON(len % 4); 7579aebddd1SJeff Kirsher do { 7589aebddd1SJeff Kirsher *dw = cpu_to_le32(*dw); 7599aebddd1SJeff Kirsher dw++; 7609aebddd1SJeff Kirsher len -= 4; 7619aebddd1SJeff Kirsher } while (len); 7629aebddd1SJeff Kirsher #endif /* __BIG_ENDIAN */ 7639aebddd1SJeff Kirsher } 7649aebddd1SJeff Kirsher 7650532d4e3SKalesh AP #define be_cmd_status(status) (status > 0 ? -EIO : status) 7660532d4e3SKalesh AP 7679aebddd1SJeff Kirsher static inline u8 is_tcp_pkt(struct sk_buff *skb) 7689aebddd1SJeff Kirsher { 7699aebddd1SJeff Kirsher u8 val = 0; 7709aebddd1SJeff Kirsher 7719aebddd1SJeff Kirsher if (ip_hdr(skb)->version == 4) 7729aebddd1SJeff Kirsher val = (ip_hdr(skb)->protocol == IPPROTO_TCP); 7739aebddd1SJeff Kirsher else if (ip_hdr(skb)->version == 6) 7749aebddd1SJeff Kirsher val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP); 7759aebddd1SJeff Kirsher 7769aebddd1SJeff Kirsher return val; 7779aebddd1SJeff Kirsher } 7789aebddd1SJeff Kirsher 7799aebddd1SJeff Kirsher static inline u8 is_udp_pkt(struct sk_buff *skb) 7809aebddd1SJeff Kirsher { 7819aebddd1SJeff Kirsher u8 val = 0; 7829aebddd1SJeff Kirsher 7839aebddd1SJeff Kirsher if (ip_hdr(skb)->version == 4) 7849aebddd1SJeff Kirsher val = (ip_hdr(skb)->protocol == IPPROTO_UDP); 7859aebddd1SJeff Kirsher else if (ip_hdr(skb)->version == 6) 7869aebddd1SJeff Kirsher val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP); 7879aebddd1SJeff Kirsher 7889aebddd1SJeff Kirsher return val; 7899aebddd1SJeff Kirsher } 7909aebddd1SJeff Kirsher 79193040ae5SSomnath Kotur static inline bool is_ipv4_pkt(struct sk_buff *skb) 79293040ae5SSomnath Kotur { 793e8efcec5SLi RongQing return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 79493040ae5SSomnath Kotur } 79593040ae5SSomnath Kotur 796954f6825SVenkata Duvvuru #define BE_ERROR_EEH 1 797954f6825SVenkata Duvvuru #define BE_ERROR_UE BIT(1) 798954f6825SVenkata Duvvuru #define BE_ERROR_FW BIT(2) 799954f6825SVenkata Duvvuru #define BE_ERROR_HW (BE_ERROR_EEH | BE_ERROR_UE) 800954f6825SVenkata Duvvuru #define BE_ERROR_ANY (BE_ERROR_EEH | BE_ERROR_UE | BE_ERROR_FW) 801954f6825SVenkata Duvvuru #define BE_CLEAR_ALL 0xFF 802954f6825SVenkata Duvvuru 803954f6825SVenkata Duvvuru static inline u8 be_check_error(struct be_adapter *adapter, u32 err_type) 804954f6825SVenkata Duvvuru { 805954f6825SVenkata Duvvuru return (adapter->err_flags & err_type); 806954f6825SVenkata Duvvuru } 807954f6825SVenkata Duvvuru 808954f6825SVenkata Duvvuru static inline void be_set_error(struct be_adapter *adapter, int err_type) 809954f6825SVenkata Duvvuru { 810954f6825SVenkata Duvvuru struct net_device *netdev = adapter->netdev; 811954f6825SVenkata Duvvuru 812954f6825SVenkata Duvvuru adapter->err_flags |= err_type; 813954f6825SVenkata Duvvuru netif_carrier_off(netdev); 814954f6825SVenkata Duvvuru 815954f6825SVenkata Duvvuru dev_info(&adapter->pdev->dev, "%s: Link down\n", netdev->name); 816954f6825SVenkata Duvvuru } 817954f6825SVenkata Duvvuru 818954f6825SVenkata Duvvuru static inline void be_clear_error(struct be_adapter *adapter, int err_type) 819954f6825SVenkata Duvvuru { 820954f6825SVenkata Duvvuru adapter->err_flags &= ~err_type; 821954f6825SVenkata Duvvuru } 822954f6825SVenkata Duvvuru 8239aebddd1SJeff Kirsher static inline bool be_multi_rxq(const struct be_adapter *adapter) 8249aebddd1SJeff Kirsher { 8259aebddd1SJeff Kirsher return adapter->num_rx_qs > 1; 8269aebddd1SJeff Kirsher } 8279aebddd1SJeff Kirsher 82831886e87SJoe Perches void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, 8299aebddd1SJeff Kirsher u16 num_popped); 83031886e87SJoe Perches void be_link_status_update(struct be_adapter *adapter, u8 link_status); 83131886e87SJoe Perches void be_parse_stats(struct be_adapter *adapter); 83231886e87SJoe Perches int be_load_fw(struct be_adapter *adapter, u8 *func); 83331886e87SJoe Perches bool be_is_wol_supported(struct be_adapter *adapter); 83431886e87SJoe Perches bool be_pause_supported(struct be_adapter *adapter); 83531886e87SJoe Perches u32 be_get_fw_log_level(struct be_adapter *adapter); 83668d7bdcbSSathya Perla int be_update_queues(struct be_adapter *adapter); 83768d7bdcbSSathya Perla int be_poll(struct napi_struct *napi, int budget); 83820947770SPadmanabh Ratnakar void be_eqd_update(struct be_adapter *adapter, bool force_update); 839941a77d5SSomnath Kotur 840045508a8SParav Pandit /* 841045508a8SParav Pandit * internal function to initialize-cleanup roce device. 842045508a8SParav Pandit */ 84331886e87SJoe Perches void be_roce_dev_add(struct be_adapter *); 84431886e87SJoe Perches void be_roce_dev_remove(struct be_adapter *); 845045508a8SParav Pandit 846045508a8SParav Pandit /* 847045508a8SParav Pandit * internal function to open-close roce device during ifup-ifdown. 848045508a8SParav Pandit */ 849d114f99aSDevesh Sharma void be_roce_dev_shutdown(struct be_adapter *); 850045508a8SParav Pandit 8519aebddd1SJeff Kirsher #endif /* BE_H */ 852