19aebddd1SJeff Kirsher /* 29aebddd1SJeff Kirsher * Copyright (C) 2005 - 2011 Emulex 39aebddd1SJeff Kirsher * All rights reserved. 49aebddd1SJeff Kirsher * 59aebddd1SJeff Kirsher * This program is free software; you can redistribute it and/or 69aebddd1SJeff Kirsher * modify it under the terms of the GNU General Public License version 2 79aebddd1SJeff Kirsher * as published by the Free Software Foundation. The full GNU General 89aebddd1SJeff Kirsher * Public License is included in this distribution in the file called COPYING. 99aebddd1SJeff Kirsher * 109aebddd1SJeff Kirsher * Contact Information: 119aebddd1SJeff Kirsher * linux-drivers@emulex.com 129aebddd1SJeff Kirsher * 139aebddd1SJeff Kirsher * Emulex 149aebddd1SJeff Kirsher * 3333 Susan Street 159aebddd1SJeff Kirsher * Costa Mesa, CA 92626 169aebddd1SJeff Kirsher */ 179aebddd1SJeff Kirsher 189aebddd1SJeff Kirsher #ifndef BE_H 199aebddd1SJeff Kirsher #define BE_H 209aebddd1SJeff Kirsher 219aebddd1SJeff Kirsher #include <linux/pci.h> 229aebddd1SJeff Kirsher #include <linux/etherdevice.h> 239aebddd1SJeff Kirsher #include <linux/delay.h> 249aebddd1SJeff Kirsher #include <net/tcp.h> 259aebddd1SJeff Kirsher #include <net/ip.h> 269aebddd1SJeff Kirsher #include <net/ipv6.h> 279aebddd1SJeff Kirsher #include <linux/if_vlan.h> 289aebddd1SJeff Kirsher #include <linux/workqueue.h> 299aebddd1SJeff Kirsher #include <linux/interrupt.h> 309aebddd1SJeff Kirsher #include <linux/firmware.h> 319aebddd1SJeff Kirsher #include <linux/slab.h> 329aebddd1SJeff Kirsher #include <linux/u64_stats_sync.h> 339aebddd1SJeff Kirsher 349aebddd1SJeff Kirsher #include "be_hw.h" 359aebddd1SJeff Kirsher 369aebddd1SJeff Kirsher #define DRV_VER "4.0.100u" 379aebddd1SJeff Kirsher #define DRV_NAME "be2net" 389aebddd1SJeff Kirsher #define BE_NAME "ServerEngines BladeEngine2 10Gbps NIC" 399aebddd1SJeff Kirsher #define BE3_NAME "ServerEngines BladeEngine3 10Gbps NIC" 409aebddd1SJeff Kirsher #define OC_NAME "Emulex OneConnect 10Gbps NIC" 419aebddd1SJeff Kirsher #define OC_NAME_BE OC_NAME "(be3)" 429aebddd1SJeff Kirsher #define OC_NAME_LANCER OC_NAME "(Lancer)" 439aebddd1SJeff Kirsher #define DRV_DESC "ServerEngines BladeEngine 10Gbps NIC Driver" 449aebddd1SJeff Kirsher 459aebddd1SJeff Kirsher #define BE_VENDOR_ID 0x19a2 469aebddd1SJeff Kirsher #define EMULEX_VENDOR_ID 0x10df 479aebddd1SJeff Kirsher #define BE_DEVICE_ID1 0x211 489aebddd1SJeff Kirsher #define BE_DEVICE_ID2 0x221 499aebddd1SJeff Kirsher #define OC_DEVICE_ID1 0x700 /* Device Id for BE2 cards */ 509aebddd1SJeff Kirsher #define OC_DEVICE_ID2 0x710 /* Device Id for BE3 cards */ 519aebddd1SJeff Kirsher #define OC_DEVICE_ID3 0xe220 /* Device id for Lancer cards */ 529aebddd1SJeff Kirsher #define OC_DEVICE_ID4 0xe228 /* Device id for VF in Lancer */ 539aebddd1SJeff Kirsher 549aebddd1SJeff Kirsher static inline char *nic_name(struct pci_dev *pdev) 559aebddd1SJeff Kirsher { 569aebddd1SJeff Kirsher switch (pdev->device) { 579aebddd1SJeff Kirsher case OC_DEVICE_ID1: 589aebddd1SJeff Kirsher return OC_NAME; 599aebddd1SJeff Kirsher case OC_DEVICE_ID2: 609aebddd1SJeff Kirsher return OC_NAME_BE; 619aebddd1SJeff Kirsher case OC_DEVICE_ID3: 629aebddd1SJeff Kirsher case OC_DEVICE_ID4: 639aebddd1SJeff Kirsher return OC_NAME_LANCER; 649aebddd1SJeff Kirsher case BE_DEVICE_ID2: 659aebddd1SJeff Kirsher return BE3_NAME; 669aebddd1SJeff Kirsher default: 679aebddd1SJeff Kirsher return BE_NAME; 689aebddd1SJeff Kirsher } 699aebddd1SJeff Kirsher } 709aebddd1SJeff Kirsher 719aebddd1SJeff Kirsher /* Number of bytes of an RX frame that are copied to skb->data */ 729aebddd1SJeff Kirsher #define BE_HDR_LEN ((u16) 64) 739aebddd1SJeff Kirsher #define BE_MAX_JUMBO_FRAME_SIZE 9018 749aebddd1SJeff Kirsher #define BE_MIN_MTU 256 759aebddd1SJeff Kirsher 769aebddd1SJeff Kirsher #define BE_NUM_VLANS_SUPPORTED 64 779aebddd1SJeff Kirsher #define BE_MAX_EQD 96 789aebddd1SJeff Kirsher #define BE_MAX_TX_FRAG_COUNT 30 799aebddd1SJeff Kirsher 809aebddd1SJeff Kirsher #define EVNT_Q_LEN 1024 819aebddd1SJeff Kirsher #define TX_Q_LEN 2048 829aebddd1SJeff Kirsher #define TX_CQ_LEN 1024 839aebddd1SJeff Kirsher #define RX_Q_LEN 1024 /* Does not support any other value */ 849aebddd1SJeff Kirsher #define RX_CQ_LEN 1024 859aebddd1SJeff Kirsher #define MCC_Q_LEN 128 /* total size not to exceed 8 pages */ 869aebddd1SJeff Kirsher #define MCC_CQ_LEN 256 879aebddd1SJeff Kirsher 889aebddd1SJeff Kirsher #define MAX_RSS_QS 4 /* BE limit is 4 queues/port */ 899aebddd1SJeff Kirsher #define MAX_RX_QS (MAX_RSS_QS + 1) /* RSS qs + 1 def Rx */ 909aebddd1SJeff Kirsher #define MAX_TX_QS 8 919aebddd1SJeff Kirsher #define BE_MAX_MSIX_VECTORS (MAX_RX_QS + 1)/* RX + TX */ 929aebddd1SJeff Kirsher #define BE_NAPI_WEIGHT 64 939aebddd1SJeff Kirsher #define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */ 949aebddd1SJeff Kirsher #define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST) 959aebddd1SJeff Kirsher 969aebddd1SJeff Kirsher #define FW_VER_LEN 32 979aebddd1SJeff Kirsher 989aebddd1SJeff Kirsher struct be_dma_mem { 999aebddd1SJeff Kirsher void *va; 1009aebddd1SJeff Kirsher dma_addr_t dma; 1019aebddd1SJeff Kirsher u32 size; 1029aebddd1SJeff Kirsher }; 1039aebddd1SJeff Kirsher 1049aebddd1SJeff Kirsher struct be_queue_info { 1059aebddd1SJeff Kirsher struct be_dma_mem dma_mem; 1069aebddd1SJeff Kirsher u16 len; 1079aebddd1SJeff Kirsher u16 entry_size; /* Size of an element in the queue */ 1089aebddd1SJeff Kirsher u16 id; 1099aebddd1SJeff Kirsher u16 tail, head; 1109aebddd1SJeff Kirsher bool created; 1119aebddd1SJeff Kirsher atomic_t used; /* Number of valid elements in the queue */ 1129aebddd1SJeff Kirsher }; 1139aebddd1SJeff Kirsher 1149aebddd1SJeff Kirsher static inline u32 MODULO(u16 val, u16 limit) 1159aebddd1SJeff Kirsher { 1169aebddd1SJeff Kirsher BUG_ON(limit & (limit - 1)); 1179aebddd1SJeff Kirsher return val & (limit - 1); 1189aebddd1SJeff Kirsher } 1199aebddd1SJeff Kirsher 1209aebddd1SJeff Kirsher static inline void index_adv(u16 *index, u16 val, u16 limit) 1219aebddd1SJeff Kirsher { 1229aebddd1SJeff Kirsher *index = MODULO((*index + val), limit); 1239aebddd1SJeff Kirsher } 1249aebddd1SJeff Kirsher 1259aebddd1SJeff Kirsher static inline void index_inc(u16 *index, u16 limit) 1269aebddd1SJeff Kirsher { 1279aebddd1SJeff Kirsher *index = MODULO((*index + 1), limit); 1289aebddd1SJeff Kirsher } 1299aebddd1SJeff Kirsher 1309aebddd1SJeff Kirsher static inline void *queue_head_node(struct be_queue_info *q) 1319aebddd1SJeff Kirsher { 1329aebddd1SJeff Kirsher return q->dma_mem.va + q->head * q->entry_size; 1339aebddd1SJeff Kirsher } 1349aebddd1SJeff Kirsher 1359aebddd1SJeff Kirsher static inline void *queue_tail_node(struct be_queue_info *q) 1369aebddd1SJeff Kirsher { 1379aebddd1SJeff Kirsher return q->dma_mem.va + q->tail * q->entry_size; 1389aebddd1SJeff Kirsher } 1399aebddd1SJeff Kirsher 1403de09455SSomnath Kotur static inline void *queue_index_node(struct be_queue_info *q, u16 index) 1413de09455SSomnath Kotur { 1423de09455SSomnath Kotur return q->dma_mem.va + index * q->entry_size; 1433de09455SSomnath Kotur } 1443de09455SSomnath Kotur 1459aebddd1SJeff Kirsher static inline void queue_head_inc(struct be_queue_info *q) 1469aebddd1SJeff Kirsher { 1479aebddd1SJeff Kirsher index_inc(&q->head, q->len); 1489aebddd1SJeff Kirsher } 1499aebddd1SJeff Kirsher 1509aebddd1SJeff Kirsher static inline void queue_tail_inc(struct be_queue_info *q) 1519aebddd1SJeff Kirsher { 1529aebddd1SJeff Kirsher index_inc(&q->tail, q->len); 1539aebddd1SJeff Kirsher } 1549aebddd1SJeff Kirsher 1559aebddd1SJeff Kirsher struct be_eq_obj { 1569aebddd1SJeff Kirsher struct be_queue_info q; 1579aebddd1SJeff Kirsher char desc[32]; 1589aebddd1SJeff Kirsher 1599aebddd1SJeff Kirsher /* Adaptive interrupt coalescing (AIC) info */ 1609aebddd1SJeff Kirsher bool enable_aic; 1619aebddd1SJeff Kirsher u16 min_eqd; /* in usecs */ 1629aebddd1SJeff Kirsher u16 max_eqd; /* in usecs */ 1639aebddd1SJeff Kirsher u16 cur_eqd; /* in usecs */ 1649aebddd1SJeff Kirsher u8 eq_idx; 1659aebddd1SJeff Kirsher 1669aebddd1SJeff Kirsher struct napi_struct napi; 1679aebddd1SJeff Kirsher }; 1689aebddd1SJeff Kirsher 1699aebddd1SJeff Kirsher struct be_mcc_obj { 1709aebddd1SJeff Kirsher struct be_queue_info q; 1719aebddd1SJeff Kirsher struct be_queue_info cq; 1729aebddd1SJeff Kirsher bool rearm_cq; 1739aebddd1SJeff Kirsher }; 1749aebddd1SJeff Kirsher 1759aebddd1SJeff Kirsher struct be_tx_stats { 1769aebddd1SJeff Kirsher u64 tx_bytes; 1779aebddd1SJeff Kirsher u64 tx_pkts; 1789aebddd1SJeff Kirsher u64 tx_reqs; 1799aebddd1SJeff Kirsher u64 tx_wrbs; 1809aebddd1SJeff Kirsher u64 tx_compl; 1819aebddd1SJeff Kirsher ulong tx_jiffies; 1829aebddd1SJeff Kirsher u32 tx_stops; 1839aebddd1SJeff Kirsher struct u64_stats_sync sync; 1849aebddd1SJeff Kirsher struct u64_stats_sync sync_compl; 1859aebddd1SJeff Kirsher }; 1869aebddd1SJeff Kirsher 1879aebddd1SJeff Kirsher struct be_tx_obj { 1889aebddd1SJeff Kirsher struct be_queue_info q; 1899aebddd1SJeff Kirsher struct be_queue_info cq; 1909aebddd1SJeff Kirsher /* Remember the skbs that were transmitted */ 1919aebddd1SJeff Kirsher struct sk_buff *sent_skb_list[TX_Q_LEN]; 1929aebddd1SJeff Kirsher struct be_tx_stats stats; 1939aebddd1SJeff Kirsher }; 1949aebddd1SJeff Kirsher 1959aebddd1SJeff Kirsher /* Struct to remember the pages posted for rx frags */ 1969aebddd1SJeff Kirsher struct be_rx_page_info { 1979aebddd1SJeff Kirsher struct page *page; 1989aebddd1SJeff Kirsher DEFINE_DMA_UNMAP_ADDR(bus); 1999aebddd1SJeff Kirsher u16 page_offset; 2009aebddd1SJeff Kirsher bool last_page_user; 2019aebddd1SJeff Kirsher }; 2029aebddd1SJeff Kirsher 2039aebddd1SJeff Kirsher struct be_rx_stats { 2049aebddd1SJeff Kirsher u64 rx_bytes; 2059aebddd1SJeff Kirsher u64 rx_pkts; 2069aebddd1SJeff Kirsher u64 rx_pkts_prev; 2079aebddd1SJeff Kirsher ulong rx_jiffies; 2089aebddd1SJeff Kirsher u32 rx_drops_no_skbs; /* skb allocation errors */ 2099aebddd1SJeff Kirsher u32 rx_drops_no_frags; /* HW has no fetched frags */ 2109aebddd1SJeff Kirsher u32 rx_post_fail; /* page post alloc failures */ 2119aebddd1SJeff Kirsher u32 rx_polls; /* NAPI calls */ 2129aebddd1SJeff Kirsher u32 rx_events; 2139aebddd1SJeff Kirsher u32 rx_compl; 2149aebddd1SJeff Kirsher u32 rx_mcast_pkts; 2159aebddd1SJeff Kirsher u32 rx_compl_err; /* completions with err set */ 2169aebddd1SJeff Kirsher u32 rx_pps; /* pkts per second */ 2179aebddd1SJeff Kirsher struct u64_stats_sync sync; 2189aebddd1SJeff Kirsher }; 2199aebddd1SJeff Kirsher 2209aebddd1SJeff Kirsher struct be_rx_compl_info { 2219aebddd1SJeff Kirsher u32 rss_hash; 2229aebddd1SJeff Kirsher u16 vlan_tag; 2239aebddd1SJeff Kirsher u16 pkt_size; 2249aebddd1SJeff Kirsher u16 rxq_idx; 2259aebddd1SJeff Kirsher u16 port; 2269aebddd1SJeff Kirsher u8 vlanf; 2279aebddd1SJeff Kirsher u8 num_rcvd; 2289aebddd1SJeff Kirsher u8 err; 2299aebddd1SJeff Kirsher u8 ipf; 2309aebddd1SJeff Kirsher u8 tcpf; 2319aebddd1SJeff Kirsher u8 udpf; 2329aebddd1SJeff Kirsher u8 ip_csum; 2339aebddd1SJeff Kirsher u8 l4_csum; 2349aebddd1SJeff Kirsher u8 ipv6; 2359aebddd1SJeff Kirsher u8 vtm; 2369aebddd1SJeff Kirsher u8 pkt_type; 2379aebddd1SJeff Kirsher }; 2389aebddd1SJeff Kirsher 2399aebddd1SJeff Kirsher struct be_rx_obj { 2409aebddd1SJeff Kirsher struct be_adapter *adapter; 2419aebddd1SJeff Kirsher struct be_queue_info q; 2429aebddd1SJeff Kirsher struct be_queue_info cq; 2439aebddd1SJeff Kirsher struct be_rx_compl_info rxcp; 2449aebddd1SJeff Kirsher struct be_rx_page_info page_info_tbl[RX_Q_LEN]; 2459aebddd1SJeff Kirsher struct be_eq_obj rx_eq; 2469aebddd1SJeff Kirsher struct be_rx_stats stats; 2479aebddd1SJeff Kirsher u8 rss_id; 2489aebddd1SJeff Kirsher bool rx_post_starved; /* Zero rx frags have been posted to BE */ 2499aebddd1SJeff Kirsher u32 cache_line_barrier[16]; 2509aebddd1SJeff Kirsher }; 2519aebddd1SJeff Kirsher 2529aebddd1SJeff Kirsher struct be_drv_stats { 2539ae081c6SSomnath Kotur u32 be_on_die_temperature; 2549aebddd1SJeff Kirsher u32 tx_events; 2559aebddd1SJeff Kirsher u32 eth_red_drops; 2569aebddd1SJeff Kirsher u32 rx_drops_no_pbuf; 2579aebddd1SJeff Kirsher u32 rx_drops_no_txpb; 2589aebddd1SJeff Kirsher u32 rx_drops_no_erx_descr; 2599aebddd1SJeff Kirsher u32 rx_drops_no_tpre_descr; 2609aebddd1SJeff Kirsher u32 rx_drops_too_many_frags; 2619aebddd1SJeff Kirsher u32 rx_drops_invalid_ring; 2629aebddd1SJeff Kirsher u32 forwarded_packets; 2639aebddd1SJeff Kirsher u32 rx_drops_mtu; 2649aebddd1SJeff Kirsher u32 rx_crc_errors; 2659aebddd1SJeff Kirsher u32 rx_alignment_symbol_errors; 2669aebddd1SJeff Kirsher u32 rx_pause_frames; 2679aebddd1SJeff Kirsher u32 rx_priority_pause_frames; 2689aebddd1SJeff Kirsher u32 rx_control_frames; 2699aebddd1SJeff Kirsher u32 rx_in_range_errors; 2709aebddd1SJeff Kirsher u32 rx_out_range_errors; 2719aebddd1SJeff Kirsher u32 rx_frame_too_long; 2729aebddd1SJeff Kirsher u32 rx_address_match_errors; 2739aebddd1SJeff Kirsher u32 rx_dropped_too_small; 2749aebddd1SJeff Kirsher u32 rx_dropped_too_short; 2759aebddd1SJeff Kirsher u32 rx_dropped_header_too_small; 2769aebddd1SJeff Kirsher u32 rx_dropped_tcp_length; 2779aebddd1SJeff Kirsher u32 rx_dropped_runt; 2789aebddd1SJeff Kirsher u32 rx_ip_checksum_errs; 2799aebddd1SJeff Kirsher u32 rx_tcp_checksum_errs; 2809aebddd1SJeff Kirsher u32 rx_udp_checksum_errs; 2819aebddd1SJeff Kirsher u32 tx_pauseframes; 2829aebddd1SJeff Kirsher u32 tx_priority_pauseframes; 2839aebddd1SJeff Kirsher u32 tx_controlframes; 2849aebddd1SJeff Kirsher u32 rxpp_fifo_overflow_drop; 2859aebddd1SJeff Kirsher u32 rx_input_fifo_overflow_drop; 2869aebddd1SJeff Kirsher u32 pmem_fifo_overflow_drop; 2879aebddd1SJeff Kirsher u32 jabber_events; 2889aebddd1SJeff Kirsher }; 2899aebddd1SJeff Kirsher 2909aebddd1SJeff Kirsher struct be_vf_cfg { 2919aebddd1SJeff Kirsher unsigned char vf_mac_addr[ETH_ALEN]; 29230128031SSathya Perla int vf_if_handle; 29330128031SSathya Perla int vf_pmac_id; 2949aebddd1SJeff Kirsher u16 vf_vlan_tag; 2959aebddd1SJeff Kirsher u32 vf_tx_rate; 2969aebddd1SJeff Kirsher }; 2979aebddd1SJeff Kirsher 2989aebddd1SJeff Kirsher struct be_adapter { 2999aebddd1SJeff Kirsher struct pci_dev *pdev; 3009aebddd1SJeff Kirsher struct net_device *netdev; 3019aebddd1SJeff Kirsher 3029aebddd1SJeff Kirsher u8 __iomem *csr; 3039aebddd1SJeff Kirsher u8 __iomem *db; /* Door Bell */ 3049aebddd1SJeff Kirsher 3059aebddd1SJeff Kirsher struct mutex mbox_lock; /* For serializing mbox cmds to BE card */ 3069aebddd1SJeff Kirsher struct be_dma_mem mbox_mem; 3079aebddd1SJeff Kirsher /* Mbox mem is adjusted to align to 16 bytes. The allocated addr 3089aebddd1SJeff Kirsher * is stored for freeing purpose */ 3099aebddd1SJeff Kirsher struct be_dma_mem mbox_mem_alloced; 3109aebddd1SJeff Kirsher 3119aebddd1SJeff Kirsher struct be_mcc_obj mcc_obj; 3129aebddd1SJeff Kirsher spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */ 3139aebddd1SJeff Kirsher spinlock_t mcc_cq_lock; 3149aebddd1SJeff Kirsher 3159aebddd1SJeff Kirsher struct msix_entry msix_entries[BE_MAX_MSIX_VECTORS]; 3169aebddd1SJeff Kirsher u32 num_msix_vec; 3179aebddd1SJeff Kirsher bool isr_registered; 3189aebddd1SJeff Kirsher 3199aebddd1SJeff Kirsher /* TX Rings */ 3209aebddd1SJeff Kirsher struct be_eq_obj tx_eq; 3219aebddd1SJeff Kirsher struct be_tx_obj tx_obj[MAX_TX_QS]; 3229aebddd1SJeff Kirsher u8 num_tx_qs; 3239aebddd1SJeff Kirsher 3249aebddd1SJeff Kirsher u32 cache_line_break[8]; 3259aebddd1SJeff Kirsher 3269aebddd1SJeff Kirsher /* Rx rings */ 3279aebddd1SJeff Kirsher struct be_rx_obj rx_obj[MAX_RX_QS]; 3289aebddd1SJeff Kirsher u32 num_rx_qs; 3299aebddd1SJeff Kirsher u32 big_page_size; /* Compounded page size shared by rx wrbs */ 3309aebddd1SJeff Kirsher 3319aebddd1SJeff Kirsher u8 eq_next_idx; 3329aebddd1SJeff Kirsher struct be_drv_stats drv_stats; 3339aebddd1SJeff Kirsher 3349aebddd1SJeff Kirsher u16 vlans_added; 3359aebddd1SJeff Kirsher u16 max_vlans; /* Number of vlans supported */ 3369aebddd1SJeff Kirsher u8 vlan_tag[VLAN_N_VID]; 3379aebddd1SJeff Kirsher u8 vlan_prio_bmap; /* Available Priority BitMap */ 3389aebddd1SJeff Kirsher u16 recommended_prio; /* Recommended Priority */ 3399aebddd1SJeff Kirsher struct be_dma_mem rx_filter; /* Cmd DMA mem for rx-filter */ 3409aebddd1SJeff Kirsher 3419aebddd1SJeff Kirsher struct be_dma_mem stats_cmd; 3429aebddd1SJeff Kirsher /* Work queue used to perform periodic tasks like getting statistics */ 3439aebddd1SJeff Kirsher struct delayed_work work; 3449aebddd1SJeff Kirsher u16 work_counter; 3459aebddd1SJeff Kirsher 3469aebddd1SJeff Kirsher /* Ethtool knobs and info */ 3479aebddd1SJeff Kirsher char fw_ver[FW_VER_LEN]; 34830128031SSathya Perla int if_handle; /* Used to configure filtering */ 3499aebddd1SJeff Kirsher u32 pmac_id; /* MAC addr handle used by BE card */ 3509aebddd1SJeff Kirsher u32 beacon_state; /* for set_phys_id */ 3519aebddd1SJeff Kirsher 3529aebddd1SJeff Kirsher bool eeh_err; 3536589ade0SSathya Perla bool ue_detected; 3546589ade0SSathya Perla bool fw_timeout; 3559aebddd1SJeff Kirsher u32 port_num; 3569aebddd1SJeff Kirsher bool promiscuous; 3579aebddd1SJeff Kirsher bool wol; 3589aebddd1SJeff Kirsher u32 function_mode; 3599aebddd1SJeff Kirsher u32 function_caps; 3609aebddd1SJeff Kirsher u32 rx_fc; /* Rx flow control */ 3619aebddd1SJeff Kirsher u32 tx_fc; /* Tx flow control */ 3629aebddd1SJeff Kirsher bool stats_cmd_sent; 3639aebddd1SJeff Kirsher int link_speed; 3649aebddd1SJeff Kirsher u8 port_type; 3659aebddd1SJeff Kirsher u8 transceiver; 3669aebddd1SJeff Kirsher u8 autoneg; 3679aebddd1SJeff Kirsher u8 generation; /* BladeEngine ASIC generation */ 3689aebddd1SJeff Kirsher u32 flash_status; 3699aebddd1SJeff Kirsher struct completion flash_compl; 3709aebddd1SJeff Kirsher 3719aebddd1SJeff Kirsher bool be3_native; 3729aebddd1SJeff Kirsher bool sriov_enabled; 3739aebddd1SJeff Kirsher struct be_vf_cfg *vf_cfg; 3749aebddd1SJeff Kirsher u8 is_virtfn; 3759aebddd1SJeff Kirsher u32 sli_family; 3769aebddd1SJeff Kirsher u8 hba_port_num; 3779aebddd1SJeff Kirsher u16 pvid; 3789aebddd1SJeff Kirsher }; 3799aebddd1SJeff Kirsher 3809aebddd1SJeff Kirsher #define be_physfn(adapter) (!adapter->is_virtfn) 3819aebddd1SJeff Kirsher 3829aebddd1SJeff Kirsher /* BladeEngine Generation numbers */ 3839aebddd1SJeff Kirsher #define BE_GEN2 2 3849aebddd1SJeff Kirsher #define BE_GEN3 3 3859aebddd1SJeff Kirsher 3869aebddd1SJeff Kirsher #define ON 1 3879aebddd1SJeff Kirsher #define OFF 0 3889aebddd1SJeff Kirsher #define lancer_chip(adapter) ((adapter->pdev->device == OC_DEVICE_ID3) || \ 3899aebddd1SJeff Kirsher (adapter->pdev->device == OC_DEVICE_ID4)) 3909aebddd1SJeff Kirsher 3919aebddd1SJeff Kirsher extern const struct ethtool_ops be_ethtool_ops; 3929aebddd1SJeff Kirsher 3939aebddd1SJeff Kirsher #define msix_enabled(adapter) (adapter->num_msix_vec > 0) 3949aebddd1SJeff Kirsher #define tx_stats(txo) (&txo->stats) 3959aebddd1SJeff Kirsher #define rx_stats(rxo) (&rxo->stats) 3969aebddd1SJeff Kirsher 3979aebddd1SJeff Kirsher #define BE_SET_NETDEV_OPS(netdev, ops) (netdev->netdev_ops = ops) 3989aebddd1SJeff Kirsher 3999aebddd1SJeff Kirsher #define for_all_rx_queues(adapter, rxo, i) \ 4009aebddd1SJeff Kirsher for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \ 4019aebddd1SJeff Kirsher i++, rxo++) 4029aebddd1SJeff Kirsher 4039aebddd1SJeff Kirsher /* Just skip the first default non-rss queue */ 4049aebddd1SJeff Kirsher #define for_all_rss_queues(adapter, rxo, i) \ 4059aebddd1SJeff Kirsher for (i = 0, rxo = &adapter->rx_obj[i+1]; i < (adapter->num_rx_qs - 1);\ 4069aebddd1SJeff Kirsher i++, rxo++) 4079aebddd1SJeff Kirsher 4089aebddd1SJeff Kirsher #define for_all_tx_queues(adapter, txo, i) \ 4099aebddd1SJeff Kirsher for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs; \ 4109aebddd1SJeff Kirsher i++, txo++) 4119aebddd1SJeff Kirsher 4129aebddd1SJeff Kirsher #define PAGE_SHIFT_4K 12 4139aebddd1SJeff Kirsher #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K) 4149aebddd1SJeff Kirsher 4159aebddd1SJeff Kirsher /* Returns number of pages spanned by the data starting at the given addr */ 4169aebddd1SJeff Kirsher #define PAGES_4K_SPANNED(_address, size) \ 4179aebddd1SJeff Kirsher ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \ 4189aebddd1SJeff Kirsher (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K)) 4199aebddd1SJeff Kirsher 4209aebddd1SJeff Kirsher /* Byte offset into the page corresponding to given address */ 4219aebddd1SJeff Kirsher #define OFFSET_IN_PAGE(addr) \ 4229aebddd1SJeff Kirsher ((size_t)(addr) & (PAGE_SIZE_4K-1)) 4239aebddd1SJeff Kirsher 4249aebddd1SJeff Kirsher /* Returns bit offset within a DWORD of a bitfield */ 4259aebddd1SJeff Kirsher #define AMAP_BIT_OFFSET(_struct, field) \ 4269aebddd1SJeff Kirsher (((size_t)&(((_struct *)0)->field))%32) 4279aebddd1SJeff Kirsher 4289aebddd1SJeff Kirsher /* Returns the bit mask of the field that is NOT shifted into location. */ 4299aebddd1SJeff Kirsher static inline u32 amap_mask(u32 bitsize) 4309aebddd1SJeff Kirsher { 4319aebddd1SJeff Kirsher return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1); 4329aebddd1SJeff Kirsher } 4339aebddd1SJeff Kirsher 4349aebddd1SJeff Kirsher static inline void 4359aebddd1SJeff Kirsher amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value) 4369aebddd1SJeff Kirsher { 4379aebddd1SJeff Kirsher u32 *dw = (u32 *) ptr + dw_offset; 4389aebddd1SJeff Kirsher *dw &= ~(mask << offset); 4399aebddd1SJeff Kirsher *dw |= (mask & value) << offset; 4409aebddd1SJeff Kirsher } 4419aebddd1SJeff Kirsher 4429aebddd1SJeff Kirsher #define AMAP_SET_BITS(_struct, field, ptr, val) \ 4439aebddd1SJeff Kirsher amap_set(ptr, \ 4449aebddd1SJeff Kirsher offsetof(_struct, field)/32, \ 4459aebddd1SJeff Kirsher amap_mask(sizeof(((_struct *)0)->field)), \ 4469aebddd1SJeff Kirsher AMAP_BIT_OFFSET(_struct, field), \ 4479aebddd1SJeff Kirsher val) 4489aebddd1SJeff Kirsher 4499aebddd1SJeff Kirsher static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset) 4509aebddd1SJeff Kirsher { 4519aebddd1SJeff Kirsher u32 *dw = (u32 *) ptr; 4529aebddd1SJeff Kirsher return mask & (*(dw + dw_offset) >> offset); 4539aebddd1SJeff Kirsher } 4549aebddd1SJeff Kirsher 4559aebddd1SJeff Kirsher #define AMAP_GET_BITS(_struct, field, ptr) \ 4569aebddd1SJeff Kirsher amap_get(ptr, \ 4579aebddd1SJeff Kirsher offsetof(_struct, field)/32, \ 4589aebddd1SJeff Kirsher amap_mask(sizeof(((_struct *)0)->field)), \ 4599aebddd1SJeff Kirsher AMAP_BIT_OFFSET(_struct, field)) 4609aebddd1SJeff Kirsher 4619aebddd1SJeff Kirsher #define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len) 4629aebddd1SJeff Kirsher #define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len) 4639aebddd1SJeff Kirsher static inline void swap_dws(void *wrb, int len) 4649aebddd1SJeff Kirsher { 4659aebddd1SJeff Kirsher #ifdef __BIG_ENDIAN 4669aebddd1SJeff Kirsher u32 *dw = wrb; 4679aebddd1SJeff Kirsher BUG_ON(len % 4); 4689aebddd1SJeff Kirsher do { 4699aebddd1SJeff Kirsher *dw = cpu_to_le32(*dw); 4709aebddd1SJeff Kirsher dw++; 4719aebddd1SJeff Kirsher len -= 4; 4729aebddd1SJeff Kirsher } while (len); 4739aebddd1SJeff Kirsher #endif /* __BIG_ENDIAN */ 4749aebddd1SJeff Kirsher } 4759aebddd1SJeff Kirsher 4769aebddd1SJeff Kirsher static inline u8 is_tcp_pkt(struct sk_buff *skb) 4779aebddd1SJeff Kirsher { 4789aebddd1SJeff Kirsher u8 val = 0; 4799aebddd1SJeff Kirsher 4809aebddd1SJeff Kirsher if (ip_hdr(skb)->version == 4) 4819aebddd1SJeff Kirsher val = (ip_hdr(skb)->protocol == IPPROTO_TCP); 4829aebddd1SJeff Kirsher else if (ip_hdr(skb)->version == 6) 4839aebddd1SJeff Kirsher val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP); 4849aebddd1SJeff Kirsher 4859aebddd1SJeff Kirsher return val; 4869aebddd1SJeff Kirsher } 4879aebddd1SJeff Kirsher 4889aebddd1SJeff Kirsher static inline u8 is_udp_pkt(struct sk_buff *skb) 4899aebddd1SJeff Kirsher { 4909aebddd1SJeff Kirsher u8 val = 0; 4919aebddd1SJeff Kirsher 4929aebddd1SJeff Kirsher if (ip_hdr(skb)->version == 4) 4939aebddd1SJeff Kirsher val = (ip_hdr(skb)->protocol == IPPROTO_UDP); 4949aebddd1SJeff Kirsher else if (ip_hdr(skb)->version == 6) 4959aebddd1SJeff Kirsher val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP); 4969aebddd1SJeff Kirsher 4979aebddd1SJeff Kirsher return val; 4989aebddd1SJeff Kirsher } 4999aebddd1SJeff Kirsher 5009aebddd1SJeff Kirsher static inline void be_check_sriov_fn_type(struct be_adapter *adapter) 5019aebddd1SJeff Kirsher { 5029aebddd1SJeff Kirsher u32 sli_intf; 5039aebddd1SJeff Kirsher 5049aebddd1SJeff Kirsher pci_read_config_dword(adapter->pdev, SLI_INTF_REG_OFFSET, &sli_intf); 5059aebddd1SJeff Kirsher adapter->is_virtfn = (sli_intf & SLI_INTF_FT_MASK) ? 1 : 0; 5069aebddd1SJeff Kirsher } 5079aebddd1SJeff Kirsher 5089aebddd1SJeff Kirsher static inline void be_vf_eth_addr_generate(struct be_adapter *adapter, u8 *mac) 5099aebddd1SJeff Kirsher { 5109aebddd1SJeff Kirsher u32 addr; 5119aebddd1SJeff Kirsher 5129aebddd1SJeff Kirsher addr = jhash(adapter->netdev->dev_addr, ETH_ALEN, 0); 5139aebddd1SJeff Kirsher 5149aebddd1SJeff Kirsher mac[5] = (u8)(addr & 0xFF); 5159aebddd1SJeff Kirsher mac[4] = (u8)((addr >> 8) & 0xFF); 5169aebddd1SJeff Kirsher mac[3] = (u8)((addr >> 16) & 0xFF); 5179aebddd1SJeff Kirsher /* Use the OUI from the current MAC address */ 5189aebddd1SJeff Kirsher memcpy(mac, adapter->netdev->dev_addr, 3); 5199aebddd1SJeff Kirsher } 5209aebddd1SJeff Kirsher 5219aebddd1SJeff Kirsher static inline bool be_multi_rxq(const struct be_adapter *adapter) 5229aebddd1SJeff Kirsher { 5239aebddd1SJeff Kirsher return adapter->num_rx_qs > 1; 5249aebddd1SJeff Kirsher } 5259aebddd1SJeff Kirsher 5266589ade0SSathya Perla static inline bool be_error(struct be_adapter *adapter) 5276589ade0SSathya Perla { 5286589ade0SSathya Perla return adapter->eeh_err || adapter->ue_detected || adapter->fw_timeout; 5296589ade0SSathya Perla } 5306589ade0SSathya Perla 5319aebddd1SJeff Kirsher extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, 5329aebddd1SJeff Kirsher u16 num_popped); 5339aebddd1SJeff Kirsher extern void be_link_status_update(struct be_adapter *adapter, u32 link_status); 5349aebddd1SJeff Kirsher extern void be_parse_stats(struct be_adapter *adapter); 5359aebddd1SJeff Kirsher extern int be_load_fw(struct be_adapter *adapter, u8 *func); 5369aebddd1SJeff Kirsher #endif /* BE_H */ 537