19aebddd1SJeff Kirsher /* 2c7bb15a6SVasundhara Volam * Copyright (C) 2005 - 2013 Emulex 39aebddd1SJeff Kirsher * All rights reserved. 49aebddd1SJeff Kirsher * 59aebddd1SJeff Kirsher * This program is free software; you can redistribute it and/or 69aebddd1SJeff Kirsher * modify it under the terms of the GNU General Public License version 2 79aebddd1SJeff Kirsher * as published by the Free Software Foundation. The full GNU General 89aebddd1SJeff Kirsher * Public License is included in this distribution in the file called COPYING. 99aebddd1SJeff Kirsher * 109aebddd1SJeff Kirsher * Contact Information: 119aebddd1SJeff Kirsher * linux-drivers@emulex.com 129aebddd1SJeff Kirsher * 139aebddd1SJeff Kirsher * Emulex 149aebddd1SJeff Kirsher * 3333 Susan Street 159aebddd1SJeff Kirsher * Costa Mesa, CA 92626 169aebddd1SJeff Kirsher */ 179aebddd1SJeff Kirsher 189aebddd1SJeff Kirsher #ifndef BE_H 199aebddd1SJeff Kirsher #define BE_H 209aebddd1SJeff Kirsher 219aebddd1SJeff Kirsher #include <linux/pci.h> 229aebddd1SJeff Kirsher #include <linux/etherdevice.h> 239aebddd1SJeff Kirsher #include <linux/delay.h> 249aebddd1SJeff Kirsher #include <net/tcp.h> 259aebddd1SJeff Kirsher #include <net/ip.h> 269aebddd1SJeff Kirsher #include <net/ipv6.h> 279aebddd1SJeff Kirsher #include <linux/if_vlan.h> 289aebddd1SJeff Kirsher #include <linux/workqueue.h> 299aebddd1SJeff Kirsher #include <linux/interrupt.h> 309aebddd1SJeff Kirsher #include <linux/firmware.h> 319aebddd1SJeff Kirsher #include <linux/slab.h> 329aebddd1SJeff Kirsher #include <linux/u64_stats_sync.h> 339aebddd1SJeff Kirsher 349aebddd1SJeff Kirsher #include "be_hw.h" 35045508a8SParav Pandit #include "be_roce.h" 369aebddd1SJeff Kirsher 375721f943SSathya Perla #define DRV_VER "4.9.134.0u" 389aebddd1SJeff Kirsher #define DRV_NAME "be2net" 3900d3d51eSSarveshwar Bandi #define BE_NAME "Emulex BladeEngine2" 4000d3d51eSSarveshwar Bandi #define BE3_NAME "Emulex BladeEngine3" 4100d3d51eSSarveshwar Bandi #define OC_NAME "Emulex OneConnect" 429aebddd1SJeff Kirsher #define OC_NAME_BE OC_NAME "(be3)" 439aebddd1SJeff Kirsher #define OC_NAME_LANCER OC_NAME "(Lancer)" 44ecedb6aeSAjit Khaparde #define OC_NAME_SH OC_NAME "(Skyhawk)" 4500d3d51eSSarveshwar Bandi #define DRV_DESC "Emulex OneConnect 10Gbps NIC Driver" 469aebddd1SJeff Kirsher 479aebddd1SJeff Kirsher #define BE_VENDOR_ID 0x19a2 489aebddd1SJeff Kirsher #define EMULEX_VENDOR_ID 0x10df 499aebddd1SJeff Kirsher #define BE_DEVICE_ID1 0x211 509aebddd1SJeff Kirsher #define BE_DEVICE_ID2 0x221 519aebddd1SJeff Kirsher #define OC_DEVICE_ID1 0x700 /* Device Id for BE2 cards */ 529aebddd1SJeff Kirsher #define OC_DEVICE_ID2 0x710 /* Device Id for BE3 cards */ 539aebddd1SJeff Kirsher #define OC_DEVICE_ID3 0xe220 /* Device id for Lancer cards */ 549aebddd1SJeff Kirsher #define OC_DEVICE_ID4 0xe228 /* Device id for VF in Lancer */ 55ecedb6aeSAjit Khaparde #define OC_DEVICE_ID5 0x720 /* Device Id for Skyhawk cards */ 5676b73530SPadmanabh Ratnakar #define OC_DEVICE_ID6 0x728 /* Device id for VF in SkyHawk */ 574762f6ceSAjit Khaparde #define OC_SUBSYS_DEVICE_ID1 0xE602 584762f6ceSAjit Khaparde #define OC_SUBSYS_DEVICE_ID2 0xE642 594762f6ceSAjit Khaparde #define OC_SUBSYS_DEVICE_ID3 0xE612 604762f6ceSAjit Khaparde #define OC_SUBSYS_DEVICE_ID4 0xE652 619aebddd1SJeff Kirsher 629aebddd1SJeff Kirsher static inline char *nic_name(struct pci_dev *pdev) 639aebddd1SJeff Kirsher { 649aebddd1SJeff Kirsher switch (pdev->device) { 659aebddd1SJeff Kirsher case OC_DEVICE_ID1: 669aebddd1SJeff Kirsher return OC_NAME; 679aebddd1SJeff Kirsher case OC_DEVICE_ID2: 689aebddd1SJeff Kirsher return OC_NAME_BE; 699aebddd1SJeff Kirsher case OC_DEVICE_ID3: 709aebddd1SJeff Kirsher case OC_DEVICE_ID4: 719aebddd1SJeff Kirsher return OC_NAME_LANCER; 729aebddd1SJeff Kirsher case BE_DEVICE_ID2: 739aebddd1SJeff Kirsher return BE3_NAME; 74ecedb6aeSAjit Khaparde case OC_DEVICE_ID5: 7576b73530SPadmanabh Ratnakar case OC_DEVICE_ID6: 76ecedb6aeSAjit Khaparde return OC_NAME_SH; 779aebddd1SJeff Kirsher default: 789aebddd1SJeff Kirsher return BE_NAME; 799aebddd1SJeff Kirsher } 809aebddd1SJeff Kirsher } 819aebddd1SJeff Kirsher 829aebddd1SJeff Kirsher /* Number of bytes of an RX frame that are copied to skb->data */ 839aebddd1SJeff Kirsher #define BE_HDR_LEN ((u16) 64) 84bb349bb4SEric Dumazet /* allocate extra space to allow tunneling decapsulation without head reallocation */ 85bb349bb4SEric Dumazet #define BE_RX_SKB_ALLOC_SIZE (BE_HDR_LEN + 64) 86bb349bb4SEric Dumazet 879aebddd1SJeff Kirsher #define BE_MAX_JUMBO_FRAME_SIZE 9018 889aebddd1SJeff Kirsher #define BE_MIN_MTU 256 899aebddd1SJeff Kirsher 909aebddd1SJeff Kirsher #define BE_NUM_VLANS_SUPPORTED 64 9110ef9ab4SSathya Perla #define BE_MAX_EQD 96u 929aebddd1SJeff Kirsher #define BE_MAX_TX_FRAG_COUNT 30 939aebddd1SJeff Kirsher 949aebddd1SJeff Kirsher #define EVNT_Q_LEN 1024 959aebddd1SJeff Kirsher #define TX_Q_LEN 2048 969aebddd1SJeff Kirsher #define TX_CQ_LEN 1024 979aebddd1SJeff Kirsher #define RX_Q_LEN 1024 /* Does not support any other value */ 989aebddd1SJeff Kirsher #define RX_CQ_LEN 1024 999aebddd1SJeff Kirsher #define MCC_Q_LEN 128 /* total size not to exceed 8 pages */ 1009aebddd1SJeff Kirsher #define MCC_CQ_LEN 256 1019aebddd1SJeff Kirsher 10210ef9ab4SSathya Perla #define BE3_MAX_RSS_QS 8 10310ef9ab4SSathya Perla #define BE2_MAX_RSS_QS 4 10410ef9ab4SSathya Perla #define MAX_RSS_QS BE3_MAX_RSS_QS 1059aebddd1SJeff Kirsher #define MAX_RX_QS (MAX_RSS_QS + 1) /* RSS qs + 1 def Rx */ 10610ef9ab4SSathya Perla 1079aebddd1SJeff Kirsher #define MAX_TX_QS 8 108045508a8SParav Pandit #define MAX_ROCE_EQS 5 109045508a8SParav Pandit #define MAX_MSIX_VECTORS (MAX_RSS_QS + MAX_ROCE_EQS) /* RSS qs + RoCE */ 11010ef9ab4SSathya Perla #define BE_TX_BUDGET 256 1119aebddd1SJeff Kirsher #define BE_NAPI_WEIGHT 64 1129aebddd1SJeff Kirsher #define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */ 1139aebddd1SJeff Kirsher #define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST) 1149aebddd1SJeff Kirsher 1157c5a5242SVasundhara Volam #define MAX_VFS 30 /* Max VFs supported by BE3 FW */ 1169aebddd1SJeff Kirsher #define FW_VER_LEN 32 1179aebddd1SJeff Kirsher 1189aebddd1SJeff Kirsher struct be_dma_mem { 1199aebddd1SJeff Kirsher void *va; 1209aebddd1SJeff Kirsher dma_addr_t dma; 1219aebddd1SJeff Kirsher u32 size; 1229aebddd1SJeff Kirsher }; 1239aebddd1SJeff Kirsher 1249aebddd1SJeff Kirsher struct be_queue_info { 1259aebddd1SJeff Kirsher struct be_dma_mem dma_mem; 1269aebddd1SJeff Kirsher u16 len; 1279aebddd1SJeff Kirsher u16 entry_size; /* Size of an element in the queue */ 1289aebddd1SJeff Kirsher u16 id; 1299aebddd1SJeff Kirsher u16 tail, head; 1309aebddd1SJeff Kirsher bool created; 1319aebddd1SJeff Kirsher atomic_t used; /* Number of valid elements in the queue */ 1329aebddd1SJeff Kirsher }; 1339aebddd1SJeff Kirsher 1349aebddd1SJeff Kirsher static inline u32 MODULO(u16 val, u16 limit) 1359aebddd1SJeff Kirsher { 1369aebddd1SJeff Kirsher BUG_ON(limit & (limit - 1)); 1379aebddd1SJeff Kirsher return val & (limit - 1); 1389aebddd1SJeff Kirsher } 1399aebddd1SJeff Kirsher 1409aebddd1SJeff Kirsher static inline void index_adv(u16 *index, u16 val, u16 limit) 1419aebddd1SJeff Kirsher { 1429aebddd1SJeff Kirsher *index = MODULO((*index + val), limit); 1439aebddd1SJeff Kirsher } 1449aebddd1SJeff Kirsher 1459aebddd1SJeff Kirsher static inline void index_inc(u16 *index, u16 limit) 1469aebddd1SJeff Kirsher { 1479aebddd1SJeff Kirsher *index = MODULO((*index + 1), limit); 1489aebddd1SJeff Kirsher } 1499aebddd1SJeff Kirsher 1509aebddd1SJeff Kirsher static inline void *queue_head_node(struct be_queue_info *q) 1519aebddd1SJeff Kirsher { 1529aebddd1SJeff Kirsher return q->dma_mem.va + q->head * q->entry_size; 1539aebddd1SJeff Kirsher } 1549aebddd1SJeff Kirsher 1559aebddd1SJeff Kirsher static inline void *queue_tail_node(struct be_queue_info *q) 1569aebddd1SJeff Kirsher { 1579aebddd1SJeff Kirsher return q->dma_mem.va + q->tail * q->entry_size; 1589aebddd1SJeff Kirsher } 1599aebddd1SJeff Kirsher 1603de09455SSomnath Kotur static inline void *queue_index_node(struct be_queue_info *q, u16 index) 1613de09455SSomnath Kotur { 1623de09455SSomnath Kotur return q->dma_mem.va + index * q->entry_size; 1633de09455SSomnath Kotur } 1643de09455SSomnath Kotur 1659aebddd1SJeff Kirsher static inline void queue_head_inc(struct be_queue_info *q) 1669aebddd1SJeff Kirsher { 1679aebddd1SJeff Kirsher index_inc(&q->head, q->len); 1689aebddd1SJeff Kirsher } 1699aebddd1SJeff Kirsher 170652bf646SPadmanabh Ratnakar static inline void index_dec(u16 *index, u16 limit) 171652bf646SPadmanabh Ratnakar { 172652bf646SPadmanabh Ratnakar *index = MODULO((*index - 1), limit); 173652bf646SPadmanabh Ratnakar } 174652bf646SPadmanabh Ratnakar 1759aebddd1SJeff Kirsher static inline void queue_tail_inc(struct be_queue_info *q) 1769aebddd1SJeff Kirsher { 1779aebddd1SJeff Kirsher index_inc(&q->tail, q->len); 1789aebddd1SJeff Kirsher } 1799aebddd1SJeff Kirsher 1809aebddd1SJeff Kirsher struct be_eq_obj { 1819aebddd1SJeff Kirsher struct be_queue_info q; 1829aebddd1SJeff Kirsher char desc[32]; 1839aebddd1SJeff Kirsher 1849aebddd1SJeff Kirsher /* Adaptive interrupt coalescing (AIC) info */ 1859aebddd1SJeff Kirsher bool enable_aic; 18610ef9ab4SSathya Perla u32 min_eqd; /* in usecs */ 18710ef9ab4SSathya Perla u32 max_eqd; /* in usecs */ 18810ef9ab4SSathya Perla u32 eqd; /* configured val when aic is off */ 18910ef9ab4SSathya Perla u32 cur_eqd; /* in usecs */ 1909aebddd1SJeff Kirsher 19110ef9ab4SSathya Perla u8 idx; /* array index */ 19210ef9ab4SSathya Perla u16 tx_budget; 193d0b9cec3SSathya Perla u16 spurious_intr; 1949aebddd1SJeff Kirsher struct napi_struct napi; 19510ef9ab4SSathya Perla struct be_adapter *adapter; 19610ef9ab4SSathya Perla } ____cacheline_aligned_in_smp; 1979aebddd1SJeff Kirsher 1989aebddd1SJeff Kirsher struct be_mcc_obj { 1999aebddd1SJeff Kirsher struct be_queue_info q; 2009aebddd1SJeff Kirsher struct be_queue_info cq; 2019aebddd1SJeff Kirsher bool rearm_cq; 2029aebddd1SJeff Kirsher }; 2039aebddd1SJeff Kirsher 2049aebddd1SJeff Kirsher struct be_tx_stats { 2059aebddd1SJeff Kirsher u64 tx_bytes; 2069aebddd1SJeff Kirsher u64 tx_pkts; 2079aebddd1SJeff Kirsher u64 tx_reqs; 2089aebddd1SJeff Kirsher u64 tx_wrbs; 2099aebddd1SJeff Kirsher u64 tx_compl; 2109aebddd1SJeff Kirsher ulong tx_jiffies; 2119aebddd1SJeff Kirsher u32 tx_stops; 2129aebddd1SJeff Kirsher struct u64_stats_sync sync; 2139aebddd1SJeff Kirsher struct u64_stats_sync sync_compl; 2149aebddd1SJeff Kirsher }; 2159aebddd1SJeff Kirsher 2169aebddd1SJeff Kirsher struct be_tx_obj { 21794d73aaaSVasundhara Volam u32 db_offset; 2189aebddd1SJeff Kirsher struct be_queue_info q; 2199aebddd1SJeff Kirsher struct be_queue_info cq; 2209aebddd1SJeff Kirsher /* Remember the skbs that were transmitted */ 2219aebddd1SJeff Kirsher struct sk_buff *sent_skb_list[TX_Q_LEN]; 2229aebddd1SJeff Kirsher struct be_tx_stats stats; 22310ef9ab4SSathya Perla } ____cacheline_aligned_in_smp; 2249aebddd1SJeff Kirsher 2259aebddd1SJeff Kirsher /* Struct to remember the pages posted for rx frags */ 2269aebddd1SJeff Kirsher struct be_rx_page_info { 2279aebddd1SJeff Kirsher struct page *page; 2289aebddd1SJeff Kirsher DEFINE_DMA_UNMAP_ADDR(bus); 2299aebddd1SJeff Kirsher u16 page_offset; 2309aebddd1SJeff Kirsher bool last_page_user; 2319aebddd1SJeff Kirsher }; 2329aebddd1SJeff Kirsher 2339aebddd1SJeff Kirsher struct be_rx_stats { 2349aebddd1SJeff Kirsher u64 rx_bytes; 2359aebddd1SJeff Kirsher u64 rx_pkts; 2369aebddd1SJeff Kirsher u64 rx_pkts_prev; 2379aebddd1SJeff Kirsher ulong rx_jiffies; 2389aebddd1SJeff Kirsher u32 rx_drops_no_skbs; /* skb allocation errors */ 2399aebddd1SJeff Kirsher u32 rx_drops_no_frags; /* HW has no fetched frags */ 2409aebddd1SJeff Kirsher u32 rx_post_fail; /* page post alloc failures */ 2419aebddd1SJeff Kirsher u32 rx_compl; 2429aebddd1SJeff Kirsher u32 rx_mcast_pkts; 2439aebddd1SJeff Kirsher u32 rx_compl_err; /* completions with err set */ 2449aebddd1SJeff Kirsher u32 rx_pps; /* pkts per second */ 2459aebddd1SJeff Kirsher struct u64_stats_sync sync; 2469aebddd1SJeff Kirsher }; 2479aebddd1SJeff Kirsher 2489aebddd1SJeff Kirsher struct be_rx_compl_info { 2499aebddd1SJeff Kirsher u32 rss_hash; 2509aebddd1SJeff Kirsher u16 vlan_tag; 2519aebddd1SJeff Kirsher u16 pkt_size; 2529aebddd1SJeff Kirsher u16 rxq_idx; 2539aebddd1SJeff Kirsher u16 port; 2549aebddd1SJeff Kirsher u8 vlanf; 2559aebddd1SJeff Kirsher u8 num_rcvd; 2569aebddd1SJeff Kirsher u8 err; 2579aebddd1SJeff Kirsher u8 ipf; 2589aebddd1SJeff Kirsher u8 tcpf; 2599aebddd1SJeff Kirsher u8 udpf; 2609aebddd1SJeff Kirsher u8 ip_csum; 2619aebddd1SJeff Kirsher u8 l4_csum; 2629aebddd1SJeff Kirsher u8 ipv6; 2639aebddd1SJeff Kirsher u8 vtm; 2649aebddd1SJeff Kirsher u8 pkt_type; 265e38b1706SSomnath Kotur u8 ip_frag; 2669aebddd1SJeff Kirsher }; 2679aebddd1SJeff Kirsher 2689aebddd1SJeff Kirsher struct be_rx_obj { 2699aebddd1SJeff Kirsher struct be_adapter *adapter; 2709aebddd1SJeff Kirsher struct be_queue_info q; 2719aebddd1SJeff Kirsher struct be_queue_info cq; 2729aebddd1SJeff Kirsher struct be_rx_compl_info rxcp; 2739aebddd1SJeff Kirsher struct be_rx_page_info page_info_tbl[RX_Q_LEN]; 2749aebddd1SJeff Kirsher struct be_rx_stats stats; 2759aebddd1SJeff Kirsher u8 rss_id; 2769aebddd1SJeff Kirsher bool rx_post_starved; /* Zero rx frags have been posted to BE */ 27710ef9ab4SSathya Perla } ____cacheline_aligned_in_smp; 2789aebddd1SJeff Kirsher 2799aebddd1SJeff Kirsher struct be_drv_stats { 2809ae081c6SSomnath Kotur u32 be_on_die_temperature; 2819aebddd1SJeff Kirsher u32 eth_red_drops; 2829aebddd1SJeff Kirsher u32 rx_drops_no_pbuf; 2839aebddd1SJeff Kirsher u32 rx_drops_no_txpb; 2849aebddd1SJeff Kirsher u32 rx_drops_no_erx_descr; 2859aebddd1SJeff Kirsher u32 rx_drops_no_tpre_descr; 2869aebddd1SJeff Kirsher u32 rx_drops_too_many_frags; 2879aebddd1SJeff Kirsher u32 forwarded_packets; 2889aebddd1SJeff Kirsher u32 rx_drops_mtu; 2899aebddd1SJeff Kirsher u32 rx_crc_errors; 2909aebddd1SJeff Kirsher u32 rx_alignment_symbol_errors; 2919aebddd1SJeff Kirsher u32 rx_pause_frames; 2929aebddd1SJeff Kirsher u32 rx_priority_pause_frames; 2939aebddd1SJeff Kirsher u32 rx_control_frames; 2949aebddd1SJeff Kirsher u32 rx_in_range_errors; 2959aebddd1SJeff Kirsher u32 rx_out_range_errors; 2969aebddd1SJeff Kirsher u32 rx_frame_too_long; 29718fb06a1SSuresh Reddy u32 rx_address_filtered; 2989aebddd1SJeff Kirsher u32 rx_dropped_too_small; 2999aebddd1SJeff Kirsher u32 rx_dropped_too_short; 3009aebddd1SJeff Kirsher u32 rx_dropped_header_too_small; 3019aebddd1SJeff Kirsher u32 rx_dropped_tcp_length; 3029aebddd1SJeff Kirsher u32 rx_dropped_runt; 3039aebddd1SJeff Kirsher u32 rx_ip_checksum_errs; 3049aebddd1SJeff Kirsher u32 rx_tcp_checksum_errs; 3059aebddd1SJeff Kirsher u32 rx_udp_checksum_errs; 3069aebddd1SJeff Kirsher u32 tx_pauseframes; 3079aebddd1SJeff Kirsher u32 tx_priority_pauseframes; 3089aebddd1SJeff Kirsher u32 tx_controlframes; 3099aebddd1SJeff Kirsher u32 rxpp_fifo_overflow_drop; 3109aebddd1SJeff Kirsher u32 rx_input_fifo_overflow_drop; 3119aebddd1SJeff Kirsher u32 pmem_fifo_overflow_drop; 3129aebddd1SJeff Kirsher u32 jabber_events; 3139aebddd1SJeff Kirsher }; 3149aebddd1SJeff Kirsher 3159aebddd1SJeff Kirsher struct be_vf_cfg { 31611ac75edSSathya Perla unsigned char mac_addr[ETH_ALEN]; 31711ac75edSSathya Perla int if_handle; 31811ac75edSSathya Perla int pmac_id; 319f1f3ee1bSAjit Khaparde u16 def_vid; 32011ac75edSSathya Perla u16 vlan_tag; 32111ac75edSSathya Perla u32 tx_rate; 3229aebddd1SJeff Kirsher }; 3239aebddd1SJeff Kirsher 32439f1d94dSSathya Perla enum vf_state { 32539f1d94dSSathya Perla ENABLED = 0, 32639f1d94dSSathya Perla ASSIGNED = 1 32739f1d94dSSathya Perla }; 32839f1d94dSSathya Perla 329b236916aSAjit Khaparde #define BE_FLAGS_LINK_STATUS_INIT 1 330191eb756SSathya Perla #define BE_FLAGS_WORKER_SCHEDULED (1 << 3) 33104d3d624SSomnath Kotur #define BE_FLAGS_NAPI_ENABLED (1 << 9) 332fbc13f01SAjit Khaparde #define BE_UC_PMAC_COUNT 30 333fbc13f01SAjit Khaparde #define BE_VF_UC_PMAC_COUNT 2 334bc0c3405SAjit Khaparde #define BE_FLAGS_QNQ_ASYNC_EVT_RCVD (1 << 11) 335b236916aSAjit Khaparde 3365c510811SSomnath Kotur /* Ethtool set_dump flags */ 3375c510811SSomnath Kotur #define LANCER_INITIATE_FW_DUMP 0x1 3385c510811SSomnath Kotur 33942f11cf2SAjit Khaparde struct phy_info { 34042f11cf2SAjit Khaparde u8 transceiver; 34142f11cf2SAjit Khaparde u8 autoneg; 34242f11cf2SAjit Khaparde u8 fc_autoneg; 34342f11cf2SAjit Khaparde u8 port_type; 34442f11cf2SAjit Khaparde u16 phy_type; 34542f11cf2SAjit Khaparde u16 interface_type; 34642f11cf2SAjit Khaparde u32 misc_params; 34742f11cf2SAjit Khaparde u16 auto_speeds_supported; 34842f11cf2SAjit Khaparde u16 fixed_speeds_supported; 34942f11cf2SAjit Khaparde int link_speed; 35042f11cf2SAjit Khaparde u32 dac_cable_len; 35142f11cf2SAjit Khaparde u32 advertising; 35242f11cf2SAjit Khaparde u32 supported; 35342f11cf2SAjit Khaparde }; 35442f11cf2SAjit Khaparde 3559aebddd1SJeff Kirsher struct be_adapter { 3569aebddd1SJeff Kirsher struct pci_dev *pdev; 3579aebddd1SJeff Kirsher struct net_device *netdev; 3589aebddd1SJeff Kirsher 359c5b3ad4cSSathya Perla u8 __iomem *csr; /* CSR BAR used only for BE2/3 */ 3609aebddd1SJeff Kirsher u8 __iomem *db; /* Door Bell */ 3619aebddd1SJeff Kirsher 3629aebddd1SJeff Kirsher struct mutex mbox_lock; /* For serializing mbox cmds to BE card */ 3639aebddd1SJeff Kirsher struct be_dma_mem mbox_mem; 3649aebddd1SJeff Kirsher /* Mbox mem is adjusted to align to 16 bytes. The allocated addr 3659aebddd1SJeff Kirsher * is stored for freeing purpose */ 3669aebddd1SJeff Kirsher struct be_dma_mem mbox_mem_alloced; 3679aebddd1SJeff Kirsher 3689aebddd1SJeff Kirsher struct be_mcc_obj mcc_obj; 3699aebddd1SJeff Kirsher spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */ 3709aebddd1SJeff Kirsher spinlock_t mcc_cq_lock; 3719aebddd1SJeff Kirsher 3729aebddd1SJeff Kirsher u32 num_msix_vec; 37310ef9ab4SSathya Perla u32 num_evt_qs; 37410ef9ab4SSathya Perla struct be_eq_obj eq_obj[MAX_MSIX_VECTORS]; 37510ef9ab4SSathya Perla struct msix_entry msix_entries[MAX_MSIX_VECTORS]; 3769aebddd1SJeff Kirsher bool isr_registered; 3779aebddd1SJeff Kirsher 3789aebddd1SJeff Kirsher /* TX Rings */ 37910ef9ab4SSathya Perla u32 num_tx_qs; 3809aebddd1SJeff Kirsher struct be_tx_obj tx_obj[MAX_TX_QS]; 3819aebddd1SJeff Kirsher 3829aebddd1SJeff Kirsher /* Rx rings */ 3839aebddd1SJeff Kirsher u32 num_rx_qs; 38410ef9ab4SSathya Perla struct be_rx_obj rx_obj[MAX_RX_QS]; 3859aebddd1SJeff Kirsher u32 big_page_size; /* Compounded page size shared by rx wrbs */ 3869aebddd1SJeff Kirsher 3879aebddd1SJeff Kirsher struct be_drv_stats drv_stats; 3889aebddd1SJeff Kirsher u16 vlans_added; 3899aebddd1SJeff Kirsher u8 vlan_tag[VLAN_N_VID]; 3909aebddd1SJeff Kirsher u8 vlan_prio_bmap; /* Available Priority BitMap */ 3919aebddd1SJeff Kirsher u16 recommended_prio; /* Recommended Priority */ 3929aebddd1SJeff Kirsher struct be_dma_mem rx_filter; /* Cmd DMA mem for rx-filter */ 3939aebddd1SJeff Kirsher 3949aebddd1SJeff Kirsher struct be_dma_mem stats_cmd; 3959aebddd1SJeff Kirsher /* Work queue used to perform periodic tasks like getting statistics */ 3969aebddd1SJeff Kirsher struct delayed_work work; 3979aebddd1SJeff Kirsher u16 work_counter; 3989aebddd1SJeff Kirsher 399f67ef7baSPadmanabh Ratnakar struct delayed_work func_recovery_work; 400b236916aSAjit Khaparde u32 flags; 401f25b119cSPadmanabh Ratnakar u32 cmd_privileges; 4029aebddd1SJeff Kirsher /* Ethtool knobs and info */ 4039aebddd1SJeff Kirsher char fw_ver[FW_VER_LEN]; 404eeb65cedSSomnath Kotur char fw_on_flash[FW_VER_LEN]; 40530128031SSathya Perla int if_handle; /* Used to configure filtering */ 406fbc13f01SAjit Khaparde u32 *pmac_id; /* MAC addr handle used by BE card */ 4079aebddd1SJeff Kirsher u32 beacon_state; /* for set_phys_id */ 4089aebddd1SJeff Kirsher 409f67ef7baSPadmanabh Ratnakar bool eeh_error; 4106589ade0SSathya Perla bool fw_timeout; 411f67ef7baSPadmanabh Ratnakar bool hw_error; 412f67ef7baSPadmanabh Ratnakar 4139aebddd1SJeff Kirsher u32 port_num; 4149aebddd1SJeff Kirsher bool promiscuous; 4159aebddd1SJeff Kirsher u32 function_mode; 4169aebddd1SJeff Kirsher u32 function_caps; 4179aebddd1SJeff Kirsher u32 rx_fc; /* Rx flow control */ 4189aebddd1SJeff Kirsher u32 tx_fc; /* Tx flow control */ 4199aebddd1SJeff Kirsher bool stats_cmd_sent; 420045508a8SParav Pandit u32 if_type; 421045508a8SParav Pandit struct { 422045508a8SParav Pandit u32 size; 423045508a8SParav Pandit u32 total_size; 424045508a8SParav Pandit u64 io_addr; 425045508a8SParav Pandit } roce_db; 426045508a8SParav Pandit u32 num_msix_roce_vec; 427045508a8SParav Pandit struct ocrdma_dev *ocrdma_dev; 428045508a8SParav Pandit struct list_head entry; 429045508a8SParav Pandit 4309aebddd1SJeff Kirsher u32 flash_status; 4319aebddd1SJeff Kirsher struct completion flash_compl; 4329aebddd1SJeff Kirsher 43339f1d94dSSathya Perla u32 num_vfs; /* Number of VFs provisioned by PF driver */ 43439f1d94dSSathya Perla u32 dev_num_vfs; /* Number of VFs supported by HW */ 43539f1d94dSSathya Perla u8 virtfn; 43611ac75edSSathya Perla struct be_vf_cfg *vf_cfg; 43711ac75edSSathya Perla bool be3_native; 4389aebddd1SJeff Kirsher u32 sli_family; 4399aebddd1SJeff Kirsher u8 hba_port_num; 4409aebddd1SJeff Kirsher u16 pvid; 44142f11cf2SAjit Khaparde struct phy_info phy; 4424762f6ceSAjit Khaparde u8 wol_cap; 4434762f6ceSAjit Khaparde bool wol; 444fbc13f01SAjit Khaparde u32 uc_macs; /* Count of secondary UC MAC programmed */ 4450ad3157eSVasundhara Volam u16 asic_rev; 446bc0c3405SAjit Khaparde u16 qnq_vid; 447941a77d5SSomnath Kotur u32 msg_enable; 4487aeb2156SPadmanabh Ratnakar int be_get_temp_freq; 449abb93951SPadmanabh Ratnakar u16 max_mcast_mac; 450abb93951SPadmanabh Ratnakar u16 max_tx_queues; 451abb93951SPadmanabh Ratnakar u16 max_rss_queues; 452abb93951SPadmanabh Ratnakar u16 max_rx_queues; 453abb93951SPadmanabh Ratnakar u16 max_pmac_cnt; 454abb93951SPadmanabh Ratnakar u16 max_vlans; 455abb93951SPadmanabh Ratnakar u16 max_event_queues; 456abb93951SPadmanabh Ratnakar u32 if_cap_flags; 457d5c18473SPadmanabh Ratnakar u8 pf_number; 458594ad54aSSuresh Reddy u64 rss_flags; 4599aebddd1SJeff Kirsher }; 4609aebddd1SJeff Kirsher 46139f1d94dSSathya Perla #define be_physfn(adapter) (!adapter->virtfn) 46211ac75edSSathya Perla #define sriov_enabled(adapter) (adapter->num_vfs > 0) 46339f1d94dSSathya Perla #define sriov_want(adapter) (adapter->dev_num_vfs && num_vfs && \ 46439f1d94dSSathya Perla be_physfn(adapter)) 46511ac75edSSathya Perla #define for_all_vfs(adapter, vf_cfg, i) \ 46611ac75edSSathya Perla for (i = 0, vf_cfg = &adapter->vf_cfg[i]; i < adapter->num_vfs; \ 46711ac75edSSathya Perla i++, vf_cfg++) 4689aebddd1SJeff Kirsher 4699aebddd1SJeff Kirsher #define ON 1 4709aebddd1SJeff Kirsher #define OFF 0 471ca34fe38SSathya Perla 472ca34fe38SSathya Perla #define lancer_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID3 || \ 473ca34fe38SSathya Perla adapter->pdev->device == OC_DEVICE_ID4) 4749aebddd1SJeff Kirsher 47576b73530SPadmanabh Ratnakar #define skyhawk_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID5 || \ 47676b73530SPadmanabh Ratnakar adapter->pdev->device == OC_DEVICE_ID6) 477d3bd3a5eSPadmanabh Ratnakar 478ca34fe38SSathya Perla #define BE3_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID2 || \ 479ca34fe38SSathya Perla adapter->pdev->device == OC_DEVICE_ID2) 480ca34fe38SSathya Perla 481ca34fe38SSathya Perla #define BE2_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID1 || \ 482ca34fe38SSathya Perla adapter->pdev->device == OC_DEVICE_ID1) 483ca34fe38SSathya Perla 484ca34fe38SSathya Perla #define BEx_chip(adapter) (BE3_chip(adapter) || BE2_chip(adapter)) 485d3bd3a5eSPadmanabh Ratnakar 486dbf0f2a7SSathya Perla #define be_roce_supported(adapter) (skyhawk_chip(adapter) && \ 487045508a8SParav Pandit (adapter->function_mode & RDMA_ENABLED)) 488045508a8SParav Pandit 4899aebddd1SJeff Kirsher extern const struct ethtool_ops be_ethtool_ops; 4909aebddd1SJeff Kirsher 4919aebddd1SJeff Kirsher #define msix_enabled(adapter) (adapter->num_msix_vec > 0) 49210ef9ab4SSathya Perla #define num_irqs(adapter) (msix_enabled(adapter) ? \ 49310ef9ab4SSathya Perla adapter->num_msix_vec : 1) 49410ef9ab4SSathya Perla #define tx_stats(txo) (&(txo)->stats) 49510ef9ab4SSathya Perla #define rx_stats(rxo) (&(rxo)->stats) 4969aebddd1SJeff Kirsher 49710ef9ab4SSathya Perla /* The default RXQ is the last RXQ */ 49810ef9ab4SSathya Perla #define default_rxo(adpt) (&adpt->rx_obj[adpt->num_rx_qs - 1]) 4999aebddd1SJeff Kirsher 5009aebddd1SJeff Kirsher #define for_all_rx_queues(adapter, rxo, i) \ 5019aebddd1SJeff Kirsher for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \ 5029aebddd1SJeff Kirsher i++, rxo++) 5039aebddd1SJeff Kirsher 50410ef9ab4SSathya Perla /* Skip the default non-rss queue (last one)*/ 5059aebddd1SJeff Kirsher #define for_all_rss_queues(adapter, rxo, i) \ 50610ef9ab4SSathya Perla for (i = 0, rxo = &adapter->rx_obj[i]; i < (adapter->num_rx_qs - 1);\ 5079aebddd1SJeff Kirsher i++, rxo++) 5089aebddd1SJeff Kirsher 5099aebddd1SJeff Kirsher #define for_all_tx_queues(adapter, txo, i) \ 5109aebddd1SJeff Kirsher for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs; \ 5119aebddd1SJeff Kirsher i++, txo++) 5129aebddd1SJeff Kirsher 51310ef9ab4SSathya Perla #define for_all_evt_queues(adapter, eqo, i) \ 51410ef9ab4SSathya Perla for (i = 0, eqo = &adapter->eq_obj[i]; i < adapter->num_evt_qs; \ 51510ef9ab4SSathya Perla i++, eqo++) 51610ef9ab4SSathya Perla 51710ef9ab4SSathya Perla #define is_mcc_eqo(eqo) (eqo->idx == 0) 51810ef9ab4SSathya Perla #define mcc_eqo(adapter) (&adapter->eq_obj[0]) 51910ef9ab4SSathya Perla 5209aebddd1SJeff Kirsher #define PAGE_SHIFT_4K 12 5219aebddd1SJeff Kirsher #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K) 5229aebddd1SJeff Kirsher 5239aebddd1SJeff Kirsher /* Returns number of pages spanned by the data starting at the given addr */ 5249aebddd1SJeff Kirsher #define PAGES_4K_SPANNED(_address, size) \ 5259aebddd1SJeff Kirsher ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \ 5269aebddd1SJeff Kirsher (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K)) 5279aebddd1SJeff Kirsher 5289aebddd1SJeff Kirsher /* Returns bit offset within a DWORD of a bitfield */ 5299aebddd1SJeff Kirsher #define AMAP_BIT_OFFSET(_struct, field) \ 5309aebddd1SJeff Kirsher (((size_t)&(((_struct *)0)->field))%32) 5319aebddd1SJeff Kirsher 5329aebddd1SJeff Kirsher /* Returns the bit mask of the field that is NOT shifted into location. */ 5339aebddd1SJeff Kirsher static inline u32 amap_mask(u32 bitsize) 5349aebddd1SJeff Kirsher { 5359aebddd1SJeff Kirsher return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1); 5369aebddd1SJeff Kirsher } 5379aebddd1SJeff Kirsher 5389aebddd1SJeff Kirsher static inline void 5399aebddd1SJeff Kirsher amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value) 5409aebddd1SJeff Kirsher { 5419aebddd1SJeff Kirsher u32 *dw = (u32 *) ptr + dw_offset; 5429aebddd1SJeff Kirsher *dw &= ~(mask << offset); 5439aebddd1SJeff Kirsher *dw |= (mask & value) << offset; 5449aebddd1SJeff Kirsher } 5459aebddd1SJeff Kirsher 5469aebddd1SJeff Kirsher #define AMAP_SET_BITS(_struct, field, ptr, val) \ 5479aebddd1SJeff Kirsher amap_set(ptr, \ 5489aebddd1SJeff Kirsher offsetof(_struct, field)/32, \ 5499aebddd1SJeff Kirsher amap_mask(sizeof(((_struct *)0)->field)), \ 5509aebddd1SJeff Kirsher AMAP_BIT_OFFSET(_struct, field), \ 5519aebddd1SJeff Kirsher val) 5529aebddd1SJeff Kirsher 5539aebddd1SJeff Kirsher static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset) 5549aebddd1SJeff Kirsher { 5559aebddd1SJeff Kirsher u32 *dw = (u32 *) ptr; 5569aebddd1SJeff Kirsher return mask & (*(dw + dw_offset) >> offset); 5579aebddd1SJeff Kirsher } 5589aebddd1SJeff Kirsher 5599aebddd1SJeff Kirsher #define AMAP_GET_BITS(_struct, field, ptr) \ 5609aebddd1SJeff Kirsher amap_get(ptr, \ 5619aebddd1SJeff Kirsher offsetof(_struct, field)/32, \ 5629aebddd1SJeff Kirsher amap_mask(sizeof(((_struct *)0)->field)), \ 5639aebddd1SJeff Kirsher AMAP_BIT_OFFSET(_struct, field)) 5649aebddd1SJeff Kirsher 5659aebddd1SJeff Kirsher #define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len) 5669aebddd1SJeff Kirsher #define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len) 5679aebddd1SJeff Kirsher static inline void swap_dws(void *wrb, int len) 5689aebddd1SJeff Kirsher { 5699aebddd1SJeff Kirsher #ifdef __BIG_ENDIAN 5709aebddd1SJeff Kirsher u32 *dw = wrb; 5719aebddd1SJeff Kirsher BUG_ON(len % 4); 5729aebddd1SJeff Kirsher do { 5739aebddd1SJeff Kirsher *dw = cpu_to_le32(*dw); 5749aebddd1SJeff Kirsher dw++; 5759aebddd1SJeff Kirsher len -= 4; 5769aebddd1SJeff Kirsher } while (len); 5779aebddd1SJeff Kirsher #endif /* __BIG_ENDIAN */ 5789aebddd1SJeff Kirsher } 5799aebddd1SJeff Kirsher 5809aebddd1SJeff Kirsher static inline u8 is_tcp_pkt(struct sk_buff *skb) 5819aebddd1SJeff Kirsher { 5829aebddd1SJeff Kirsher u8 val = 0; 5839aebddd1SJeff Kirsher 5849aebddd1SJeff Kirsher if (ip_hdr(skb)->version == 4) 5859aebddd1SJeff Kirsher val = (ip_hdr(skb)->protocol == IPPROTO_TCP); 5869aebddd1SJeff Kirsher else if (ip_hdr(skb)->version == 6) 5879aebddd1SJeff Kirsher val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP); 5889aebddd1SJeff Kirsher 5899aebddd1SJeff Kirsher return val; 5909aebddd1SJeff Kirsher } 5919aebddd1SJeff Kirsher 5929aebddd1SJeff Kirsher static inline u8 is_udp_pkt(struct sk_buff *skb) 5939aebddd1SJeff Kirsher { 5949aebddd1SJeff Kirsher u8 val = 0; 5959aebddd1SJeff Kirsher 5969aebddd1SJeff Kirsher if (ip_hdr(skb)->version == 4) 5979aebddd1SJeff Kirsher val = (ip_hdr(skb)->protocol == IPPROTO_UDP); 5989aebddd1SJeff Kirsher else if (ip_hdr(skb)->version == 6) 5999aebddd1SJeff Kirsher val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP); 6009aebddd1SJeff Kirsher 6019aebddd1SJeff Kirsher return val; 6029aebddd1SJeff Kirsher } 6039aebddd1SJeff Kirsher 60493040ae5SSomnath Kotur static inline bool is_ipv4_pkt(struct sk_buff *skb) 60593040ae5SSomnath Kotur { 606e8efcec5SLi RongQing return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 60793040ae5SSomnath Kotur } 60893040ae5SSomnath Kotur 6099aebddd1SJeff Kirsher static inline void be_vf_eth_addr_generate(struct be_adapter *adapter, u8 *mac) 6109aebddd1SJeff Kirsher { 6119aebddd1SJeff Kirsher u32 addr; 6129aebddd1SJeff Kirsher 6139aebddd1SJeff Kirsher addr = jhash(adapter->netdev->dev_addr, ETH_ALEN, 0); 6149aebddd1SJeff Kirsher 6159aebddd1SJeff Kirsher mac[5] = (u8)(addr & 0xFF); 6169aebddd1SJeff Kirsher mac[4] = (u8)((addr >> 8) & 0xFF); 6179aebddd1SJeff Kirsher mac[3] = (u8)((addr >> 16) & 0xFF); 6189aebddd1SJeff Kirsher /* Use the OUI from the current MAC address */ 6199aebddd1SJeff Kirsher memcpy(mac, adapter->netdev->dev_addr, 3); 6209aebddd1SJeff Kirsher } 6219aebddd1SJeff Kirsher 6229aebddd1SJeff Kirsher static inline bool be_multi_rxq(const struct be_adapter *adapter) 6239aebddd1SJeff Kirsher { 6249aebddd1SJeff Kirsher return adapter->num_rx_qs > 1; 6259aebddd1SJeff Kirsher } 6269aebddd1SJeff Kirsher 6276589ade0SSathya Perla static inline bool be_error(struct be_adapter *adapter) 6286589ade0SSathya Perla { 629f67ef7baSPadmanabh Ratnakar return adapter->eeh_error || adapter->hw_error || adapter->fw_timeout; 630f67ef7baSPadmanabh Ratnakar } 631f67ef7baSPadmanabh Ratnakar 632d23e946cSSathya Perla static inline bool be_hw_error(struct be_adapter *adapter) 633f67ef7baSPadmanabh Ratnakar { 634f67ef7baSPadmanabh Ratnakar return adapter->eeh_error || adapter->hw_error; 635f67ef7baSPadmanabh Ratnakar } 636f67ef7baSPadmanabh Ratnakar 637f67ef7baSPadmanabh Ratnakar static inline void be_clear_all_error(struct be_adapter *adapter) 638f67ef7baSPadmanabh Ratnakar { 639f67ef7baSPadmanabh Ratnakar adapter->eeh_error = false; 640f67ef7baSPadmanabh Ratnakar adapter->hw_error = false; 641f67ef7baSPadmanabh Ratnakar adapter->fw_timeout = false; 6426589ade0SSathya Perla } 6436589ade0SSathya Perla 6444762f6ceSAjit Khaparde static inline bool be_is_wol_excluded(struct be_adapter *adapter) 6454762f6ceSAjit Khaparde { 6464762f6ceSAjit Khaparde struct pci_dev *pdev = adapter->pdev; 6474762f6ceSAjit Khaparde 6484762f6ceSAjit Khaparde if (!be_physfn(adapter)) 6494762f6ceSAjit Khaparde return true; 6504762f6ceSAjit Khaparde 6514762f6ceSAjit Khaparde switch (pdev->subsystem_device) { 6524762f6ceSAjit Khaparde case OC_SUBSYS_DEVICE_ID1: 6534762f6ceSAjit Khaparde case OC_SUBSYS_DEVICE_ID2: 6544762f6ceSAjit Khaparde case OC_SUBSYS_DEVICE_ID3: 6554762f6ceSAjit Khaparde case OC_SUBSYS_DEVICE_ID4: 6564762f6ceSAjit Khaparde return true; 6574762f6ceSAjit Khaparde default: 6584762f6ceSAjit Khaparde return false; 6594762f6ceSAjit Khaparde } 6604762f6ceSAjit Khaparde } 6614762f6ceSAjit Khaparde 662bc0c3405SAjit Khaparde static inline int qnq_async_evt_rcvd(struct be_adapter *adapter) 663bc0c3405SAjit Khaparde { 664bc0c3405SAjit Khaparde return adapter->flags & BE_FLAGS_QNQ_ASYNC_EVT_RCVD; 665bc0c3405SAjit Khaparde } 666bc0c3405SAjit Khaparde 6679aebddd1SJeff Kirsher extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, 6689aebddd1SJeff Kirsher u16 num_popped); 669b236916aSAjit Khaparde extern void be_link_status_update(struct be_adapter *adapter, u8 link_status); 6709aebddd1SJeff Kirsher extern void be_parse_stats(struct be_adapter *adapter); 6719aebddd1SJeff Kirsher extern int be_load_fw(struct be_adapter *adapter, u8 *func); 6724762f6ceSAjit Khaparde extern bool be_is_wol_supported(struct be_adapter *adapter); 67342f11cf2SAjit Khaparde extern bool be_pause_supported(struct be_adapter *adapter); 674941a77d5SSomnath Kotur extern u32 be_get_fw_log_level(struct be_adapter *adapter); 675941a77d5SSomnath Kotur 676045508a8SParav Pandit /* 677045508a8SParav Pandit * internal function to initialize-cleanup roce device. 678045508a8SParav Pandit */ 679045508a8SParav Pandit extern void be_roce_dev_add(struct be_adapter *); 680045508a8SParav Pandit extern void be_roce_dev_remove(struct be_adapter *); 681045508a8SParav Pandit 682045508a8SParav Pandit /* 683045508a8SParav Pandit * internal function to open-close roce device during ifup-ifdown. 684045508a8SParav Pandit */ 685045508a8SParav Pandit extern void be_roce_dev_open(struct be_adapter *); 686045508a8SParav Pandit extern void be_roce_dev_close(struct be_adapter *); 687045508a8SParav Pandit 6889aebddd1SJeff Kirsher #endif /* BE_H */ 689