19aebddd1SJeff Kirsher /* 240263820SVasundhara Volam * Copyright (C) 2005 - 2014 Emulex 39aebddd1SJeff Kirsher * All rights reserved. 49aebddd1SJeff Kirsher * 59aebddd1SJeff Kirsher * This program is free software; you can redistribute it and/or 69aebddd1SJeff Kirsher * modify it under the terms of the GNU General Public License version 2 79aebddd1SJeff Kirsher * as published by the Free Software Foundation. The full GNU General 89aebddd1SJeff Kirsher * Public License is included in this distribution in the file called COPYING. 99aebddd1SJeff Kirsher * 109aebddd1SJeff Kirsher * Contact Information: 119aebddd1SJeff Kirsher * linux-drivers@emulex.com 129aebddd1SJeff Kirsher * 139aebddd1SJeff Kirsher * Emulex 149aebddd1SJeff Kirsher * 3333 Susan Street 159aebddd1SJeff Kirsher * Costa Mesa, CA 92626 169aebddd1SJeff Kirsher */ 179aebddd1SJeff Kirsher 189aebddd1SJeff Kirsher #ifndef BE_H 199aebddd1SJeff Kirsher #define BE_H 209aebddd1SJeff Kirsher 219aebddd1SJeff Kirsher #include <linux/pci.h> 229aebddd1SJeff Kirsher #include <linux/etherdevice.h> 239aebddd1SJeff Kirsher #include <linux/delay.h> 249aebddd1SJeff Kirsher #include <net/tcp.h> 259aebddd1SJeff Kirsher #include <net/ip.h> 269aebddd1SJeff Kirsher #include <net/ipv6.h> 279aebddd1SJeff Kirsher #include <linux/if_vlan.h> 289aebddd1SJeff Kirsher #include <linux/workqueue.h> 299aebddd1SJeff Kirsher #include <linux/interrupt.h> 309aebddd1SJeff Kirsher #include <linux/firmware.h> 319aebddd1SJeff Kirsher #include <linux/slab.h> 329aebddd1SJeff Kirsher #include <linux/u64_stats_sync.h> 339aebddd1SJeff Kirsher 349aebddd1SJeff Kirsher #include "be_hw.h" 35045508a8SParav Pandit #include "be_roce.h" 369aebddd1SJeff Kirsher 37c346e6e5SSathya Perla #define DRV_VER "10.4u" 389aebddd1SJeff Kirsher #define DRV_NAME "be2net" 3900d3d51eSSarveshwar Bandi #define BE_NAME "Emulex BladeEngine2" 4000d3d51eSSarveshwar Bandi #define BE3_NAME "Emulex BladeEngine3" 4100d3d51eSSarveshwar Bandi #define OC_NAME "Emulex OneConnect" 429aebddd1SJeff Kirsher #define OC_NAME_BE OC_NAME "(be3)" 439aebddd1SJeff Kirsher #define OC_NAME_LANCER OC_NAME "(Lancer)" 44ecedb6aeSAjit Khaparde #define OC_NAME_SH OC_NAME "(Skyhawk)" 45f3effb45SSuresh Reddy #define DRV_DESC "Emulex OneConnect NIC Driver" 469aebddd1SJeff Kirsher 479aebddd1SJeff Kirsher #define BE_VENDOR_ID 0x19a2 489aebddd1SJeff Kirsher #define EMULEX_VENDOR_ID 0x10df 499aebddd1SJeff Kirsher #define BE_DEVICE_ID1 0x211 509aebddd1SJeff Kirsher #define BE_DEVICE_ID2 0x221 519aebddd1SJeff Kirsher #define OC_DEVICE_ID1 0x700 /* Device Id for BE2 cards */ 529aebddd1SJeff Kirsher #define OC_DEVICE_ID2 0x710 /* Device Id for BE3 cards */ 539aebddd1SJeff Kirsher #define OC_DEVICE_ID3 0xe220 /* Device id for Lancer cards */ 549aebddd1SJeff Kirsher #define OC_DEVICE_ID4 0xe228 /* Device id for VF in Lancer */ 55ecedb6aeSAjit Khaparde #define OC_DEVICE_ID5 0x720 /* Device Id for Skyhawk cards */ 5676b73530SPadmanabh Ratnakar #define OC_DEVICE_ID6 0x728 /* Device id for VF in SkyHawk */ 574762f6ceSAjit Khaparde #define OC_SUBSYS_DEVICE_ID1 0xE602 584762f6ceSAjit Khaparde #define OC_SUBSYS_DEVICE_ID2 0xE642 594762f6ceSAjit Khaparde #define OC_SUBSYS_DEVICE_ID3 0xE612 604762f6ceSAjit Khaparde #define OC_SUBSYS_DEVICE_ID4 0xE652 619aebddd1SJeff Kirsher 629aebddd1SJeff Kirsher /* Number of bytes of an RX frame that are copied to skb->data */ 639aebddd1SJeff Kirsher #define BE_HDR_LEN ((u16) 64) 64bb349bb4SEric Dumazet /* allocate extra space to allow tunneling decapsulation without head reallocation */ 65bb349bb4SEric Dumazet #define BE_RX_SKB_ALLOC_SIZE (BE_HDR_LEN + 64) 66bb349bb4SEric Dumazet 679aebddd1SJeff Kirsher #define BE_MAX_JUMBO_FRAME_SIZE 9018 689aebddd1SJeff Kirsher #define BE_MIN_MTU 256 690d3f5cceSKalesh AP #define BE_MAX_MTU (BE_MAX_JUMBO_FRAME_SIZE - \ 700d3f5cceSKalesh AP (ETH_HLEN + ETH_FCS_LEN)) 719aebddd1SJeff Kirsher 729aebddd1SJeff Kirsher #define BE_NUM_VLANS_SUPPORTED 64 732632bafdSSathya Perla #define BE_MAX_EQD 128u 749aebddd1SJeff Kirsher #define BE_MAX_TX_FRAG_COUNT 30 759aebddd1SJeff Kirsher 769aebddd1SJeff Kirsher #define EVNT_Q_LEN 1024 779aebddd1SJeff Kirsher #define TX_Q_LEN 2048 789aebddd1SJeff Kirsher #define TX_CQ_LEN 1024 799aebddd1SJeff Kirsher #define RX_Q_LEN 1024 /* Does not support any other value */ 809aebddd1SJeff Kirsher #define RX_CQ_LEN 1024 819aebddd1SJeff Kirsher #define MCC_Q_LEN 128 /* total size not to exceed 8 pages */ 829aebddd1SJeff Kirsher #define MCC_CQ_LEN 256 839aebddd1SJeff Kirsher 8410ef9ab4SSathya Perla #define BE2_MAX_RSS_QS 4 8568d7bdcbSSathya Perla #define BE3_MAX_RSS_QS 16 8668d7bdcbSSathya Perla #define BE3_MAX_TX_QS 16 8768d7bdcbSSathya Perla #define BE3_MAX_EVT_QS 16 88e3dc867cSSuresh Reddy #define BE3_SRIOV_MAX_EVT_QS 8 8910ef9ab4SSathya Perla 9068d7bdcbSSathya Perla #define MAX_RX_QS 32 9168d7bdcbSSathya Perla #define MAX_EVT_QS 32 9268d7bdcbSSathya Perla #define MAX_TX_QS 32 9368d7bdcbSSathya Perla 94045508a8SParav Pandit #define MAX_ROCE_EQS 5 9568d7bdcbSSathya Perla #define MAX_MSIX_VECTORS 32 9692bf14abSSathya Perla #define MIN_MSIX_VECTORS 1 979aebddd1SJeff Kirsher #define BE_NAPI_WEIGHT 64 989aebddd1SJeff Kirsher #define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */ 999aebddd1SJeff Kirsher #define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST) 1009aebddd1SJeff Kirsher 1017c5a5242SVasundhara Volam #define MAX_VFS 30 /* Max VFs supported by BE3 FW */ 1029aebddd1SJeff Kirsher #define FW_VER_LEN 32 1039aebddd1SJeff Kirsher 104e2557877SVenkata Duvvuru #define RSS_INDIR_TABLE_LEN 128 105e2557877SVenkata Duvvuru #define RSS_HASH_KEY_LEN 40 106e2557877SVenkata Duvvuru 1079aebddd1SJeff Kirsher struct be_dma_mem { 1089aebddd1SJeff Kirsher void *va; 1099aebddd1SJeff Kirsher dma_addr_t dma; 1109aebddd1SJeff Kirsher u32 size; 1119aebddd1SJeff Kirsher }; 1129aebddd1SJeff Kirsher 1139aebddd1SJeff Kirsher struct be_queue_info { 1149aebddd1SJeff Kirsher struct be_dma_mem dma_mem; 1159aebddd1SJeff Kirsher u16 len; 1169aebddd1SJeff Kirsher u16 entry_size; /* Size of an element in the queue */ 1179aebddd1SJeff Kirsher u16 id; 1189aebddd1SJeff Kirsher u16 tail, head; 1199aebddd1SJeff Kirsher bool created; 1209aebddd1SJeff Kirsher atomic_t used; /* Number of valid elements in the queue */ 1219aebddd1SJeff Kirsher }; 1229aebddd1SJeff Kirsher 1239aebddd1SJeff Kirsher static inline u32 MODULO(u16 val, u16 limit) 1249aebddd1SJeff Kirsher { 1259aebddd1SJeff Kirsher BUG_ON(limit & (limit - 1)); 1269aebddd1SJeff Kirsher return val & (limit - 1); 1279aebddd1SJeff Kirsher } 1289aebddd1SJeff Kirsher 1299aebddd1SJeff Kirsher static inline void index_adv(u16 *index, u16 val, u16 limit) 1309aebddd1SJeff Kirsher { 1319aebddd1SJeff Kirsher *index = MODULO((*index + val), limit); 1329aebddd1SJeff Kirsher } 1339aebddd1SJeff Kirsher 1349aebddd1SJeff Kirsher static inline void index_inc(u16 *index, u16 limit) 1359aebddd1SJeff Kirsher { 1369aebddd1SJeff Kirsher *index = MODULO((*index + 1), limit); 1379aebddd1SJeff Kirsher } 1389aebddd1SJeff Kirsher 1399aebddd1SJeff Kirsher static inline void *queue_head_node(struct be_queue_info *q) 1409aebddd1SJeff Kirsher { 1419aebddd1SJeff Kirsher return q->dma_mem.va + q->head * q->entry_size; 1429aebddd1SJeff Kirsher } 1439aebddd1SJeff Kirsher 1449aebddd1SJeff Kirsher static inline void *queue_tail_node(struct be_queue_info *q) 1459aebddd1SJeff Kirsher { 1469aebddd1SJeff Kirsher return q->dma_mem.va + q->tail * q->entry_size; 1479aebddd1SJeff Kirsher } 1489aebddd1SJeff Kirsher 1493de09455SSomnath Kotur static inline void *queue_index_node(struct be_queue_info *q, u16 index) 1503de09455SSomnath Kotur { 1513de09455SSomnath Kotur return q->dma_mem.va + index * q->entry_size; 1523de09455SSomnath Kotur } 1533de09455SSomnath Kotur 1549aebddd1SJeff Kirsher static inline void queue_head_inc(struct be_queue_info *q) 1559aebddd1SJeff Kirsher { 1569aebddd1SJeff Kirsher index_inc(&q->head, q->len); 1579aebddd1SJeff Kirsher } 1589aebddd1SJeff Kirsher 159652bf646SPadmanabh Ratnakar static inline void index_dec(u16 *index, u16 limit) 160652bf646SPadmanabh Ratnakar { 161652bf646SPadmanabh Ratnakar *index = MODULO((*index - 1), limit); 162652bf646SPadmanabh Ratnakar } 163652bf646SPadmanabh Ratnakar 1649aebddd1SJeff Kirsher static inline void queue_tail_inc(struct be_queue_info *q) 1659aebddd1SJeff Kirsher { 1669aebddd1SJeff Kirsher index_inc(&q->tail, q->len); 1679aebddd1SJeff Kirsher } 1689aebddd1SJeff Kirsher 1699aebddd1SJeff Kirsher struct be_eq_obj { 1709aebddd1SJeff Kirsher struct be_queue_info q; 1719aebddd1SJeff Kirsher char desc[32]; 1729aebddd1SJeff Kirsher 1739aebddd1SJeff Kirsher /* Adaptive interrupt coalescing (AIC) info */ 1749aebddd1SJeff Kirsher bool enable_aic; 17510ef9ab4SSathya Perla u32 min_eqd; /* in usecs */ 17610ef9ab4SSathya Perla u32 max_eqd; /* in usecs */ 17710ef9ab4SSathya Perla u32 eqd; /* configured val when aic is off */ 17810ef9ab4SSathya Perla u32 cur_eqd; /* in usecs */ 1799aebddd1SJeff Kirsher 18010ef9ab4SSathya Perla u8 idx; /* array index */ 181f2f781a7SSathya Perla u8 msix_idx; 182d0b9cec3SSathya Perla u16 spurious_intr; 1839aebddd1SJeff Kirsher struct napi_struct napi; 18410ef9ab4SSathya Perla struct be_adapter *adapter; 1856384a4d0SSathya Perla 1866384a4d0SSathya Perla #ifdef CONFIG_NET_RX_BUSY_POLL 1876384a4d0SSathya Perla #define BE_EQ_IDLE 0 1886384a4d0SSathya Perla #define BE_EQ_NAPI 1 /* napi owns this EQ */ 1896384a4d0SSathya Perla #define BE_EQ_POLL 2 /* poll owns this EQ */ 1906384a4d0SSathya Perla #define BE_EQ_LOCKED (BE_EQ_NAPI | BE_EQ_POLL) 1916384a4d0SSathya Perla #define BE_EQ_NAPI_YIELD 4 /* napi yielded this EQ */ 1926384a4d0SSathya Perla #define BE_EQ_POLL_YIELD 8 /* poll yielded this EQ */ 1936384a4d0SSathya Perla #define BE_EQ_YIELD (BE_EQ_NAPI_YIELD | BE_EQ_POLL_YIELD) 1946384a4d0SSathya Perla #define BE_EQ_USER_PEND (BE_EQ_POLL | BE_EQ_POLL_YIELD) 1956384a4d0SSathya Perla unsigned int state; 1966384a4d0SSathya Perla spinlock_t lock; /* lock to serialize napi and busy-poll */ 1976384a4d0SSathya Perla #endif /* CONFIG_NET_RX_BUSY_POLL */ 19810ef9ab4SSathya Perla } ____cacheline_aligned_in_smp; 1999aebddd1SJeff Kirsher 2002632bafdSSathya Perla struct be_aic_obj { /* Adaptive interrupt coalescing (AIC) info */ 2012632bafdSSathya Perla bool enable; 2022632bafdSSathya Perla u32 min_eqd; /* in usecs */ 2032632bafdSSathya Perla u32 max_eqd; /* in usecs */ 2042632bafdSSathya Perla u32 prev_eqd; /* in usecs */ 2052632bafdSSathya Perla u32 et_eqd; /* configured val when aic is off */ 2062632bafdSSathya Perla ulong jiffies; 2072632bafdSSathya Perla u64 rx_pkts_prev; /* Used to calculate RX pps */ 2082632bafdSSathya Perla u64 tx_reqs_prev; /* Used to calculate TX pps */ 2092632bafdSSathya Perla }; 2102632bafdSSathya Perla 2116384a4d0SSathya Perla enum { 2126384a4d0SSathya Perla NAPI_POLLING, 2136384a4d0SSathya Perla BUSY_POLLING 2146384a4d0SSathya Perla }; 2156384a4d0SSathya Perla 2169aebddd1SJeff Kirsher struct be_mcc_obj { 2179aebddd1SJeff Kirsher struct be_queue_info q; 2189aebddd1SJeff Kirsher struct be_queue_info cq; 2199aebddd1SJeff Kirsher bool rearm_cq; 2209aebddd1SJeff Kirsher }; 2219aebddd1SJeff Kirsher 2229aebddd1SJeff Kirsher struct be_tx_stats { 2239aebddd1SJeff Kirsher u64 tx_bytes; 2249aebddd1SJeff Kirsher u64 tx_pkts; 2259aebddd1SJeff Kirsher u64 tx_reqs; 2269aebddd1SJeff Kirsher u64 tx_compl; 2279aebddd1SJeff Kirsher ulong tx_jiffies; 2289aebddd1SJeff Kirsher u32 tx_stops; 229bc617526SSathya Perla u32 tx_drv_drops; /* pkts dropped by driver */ 230512bb8a2SKalesh AP /* the error counters are described in be_ethtool.c */ 231512bb8a2SKalesh AP u32 tx_hdr_parse_err; 232512bb8a2SKalesh AP u32 tx_dma_err; 233512bb8a2SKalesh AP u32 tx_tso_err; 234512bb8a2SKalesh AP u32 tx_spoof_check_err; 235512bb8a2SKalesh AP u32 tx_qinq_err; 236512bb8a2SKalesh AP u32 tx_internal_parity_err; 2379aebddd1SJeff Kirsher struct u64_stats_sync sync; 2389aebddd1SJeff Kirsher struct u64_stats_sync sync_compl; 2399aebddd1SJeff Kirsher }; 2409aebddd1SJeff Kirsher 241152ffe5bSSriharsha Basavapatna /* Structure to hold some data of interest obtained from a TX CQE */ 242152ffe5bSSriharsha Basavapatna struct be_tx_compl_info { 243152ffe5bSSriharsha Basavapatna u8 status; /* Completion status */ 244152ffe5bSSriharsha Basavapatna u16 end_index; /* Completed TXQ Index */ 245152ffe5bSSriharsha Basavapatna }; 246152ffe5bSSriharsha Basavapatna 2479aebddd1SJeff Kirsher struct be_tx_obj { 24894d73aaaSVasundhara Volam u32 db_offset; 2499aebddd1SJeff Kirsher struct be_queue_info q; 2509aebddd1SJeff Kirsher struct be_queue_info cq; 251152ffe5bSSriharsha Basavapatna struct be_tx_compl_info txcp; 2529aebddd1SJeff Kirsher /* Remember the skbs that were transmitted */ 2539aebddd1SJeff Kirsher struct sk_buff *sent_skb_list[TX_Q_LEN]; 2549aebddd1SJeff Kirsher struct be_tx_stats stats; 2555f07b3c5SSathya Perla u16 pend_wrb_cnt; /* Number of WRBs yet to be given to HW */ 2565f07b3c5SSathya Perla u16 last_req_wrb_cnt; /* wrb cnt of the last req in the Q */ 2575f07b3c5SSathya Perla u16 last_req_hdr; /* index of the last req's hdr-wrb */ 25810ef9ab4SSathya Perla } ____cacheline_aligned_in_smp; 2599aebddd1SJeff Kirsher 2609aebddd1SJeff Kirsher /* Struct to remember the pages posted for rx frags */ 2619aebddd1SJeff Kirsher struct be_rx_page_info { 2629aebddd1SJeff Kirsher struct page *page; 263e50287beSSathya Perla /* set to page-addr for last frag of the page & frag-addr otherwise */ 2649aebddd1SJeff Kirsher DEFINE_DMA_UNMAP_ADDR(bus); 2659aebddd1SJeff Kirsher u16 page_offset; 266e50287beSSathya Perla bool last_frag; /* last frag of the page */ 2679aebddd1SJeff Kirsher }; 2689aebddd1SJeff Kirsher 2699aebddd1SJeff Kirsher struct be_rx_stats { 2709aebddd1SJeff Kirsher u64 rx_bytes; 2719aebddd1SJeff Kirsher u64 rx_pkts; 2729aebddd1SJeff Kirsher u32 rx_drops_no_skbs; /* skb allocation errors */ 2739aebddd1SJeff Kirsher u32 rx_drops_no_frags; /* HW has no fetched frags */ 2749aebddd1SJeff Kirsher u32 rx_post_fail; /* page post alloc failures */ 2759aebddd1SJeff Kirsher u32 rx_compl; 2769aebddd1SJeff Kirsher u32 rx_mcast_pkts; 2779aebddd1SJeff Kirsher u32 rx_compl_err; /* completions with err set */ 2789aebddd1SJeff Kirsher struct u64_stats_sync sync; 2799aebddd1SJeff Kirsher }; 2809aebddd1SJeff Kirsher 2819aebddd1SJeff Kirsher struct be_rx_compl_info { 2829aebddd1SJeff Kirsher u32 rss_hash; 2839aebddd1SJeff Kirsher u16 vlan_tag; 2849aebddd1SJeff Kirsher u16 pkt_size; 2859aebddd1SJeff Kirsher u16 port; 2869aebddd1SJeff Kirsher u8 vlanf; 2879aebddd1SJeff Kirsher u8 num_rcvd; 2889aebddd1SJeff Kirsher u8 err; 2899aebddd1SJeff Kirsher u8 ipf; 2909aebddd1SJeff Kirsher u8 tcpf; 2919aebddd1SJeff Kirsher u8 udpf; 2929aebddd1SJeff Kirsher u8 ip_csum; 2939aebddd1SJeff Kirsher u8 l4_csum; 2949aebddd1SJeff Kirsher u8 ipv6; 295f93f160bSVasundhara Volam u8 qnq; 2969aebddd1SJeff Kirsher u8 pkt_type; 297e38b1706SSomnath Kotur u8 ip_frag; 298c9c47142SSathya Perla u8 tunneled; 2999aebddd1SJeff Kirsher }; 3009aebddd1SJeff Kirsher 3019aebddd1SJeff Kirsher struct be_rx_obj { 3029aebddd1SJeff Kirsher struct be_adapter *adapter; 3039aebddd1SJeff Kirsher struct be_queue_info q; 3049aebddd1SJeff Kirsher struct be_queue_info cq; 3059aebddd1SJeff Kirsher struct be_rx_compl_info rxcp; 3069aebddd1SJeff Kirsher struct be_rx_page_info page_info_tbl[RX_Q_LEN]; 3079aebddd1SJeff Kirsher struct be_rx_stats stats; 3089aebddd1SJeff Kirsher u8 rss_id; 3099aebddd1SJeff Kirsher bool rx_post_starved; /* Zero rx frags have been posted to BE */ 31010ef9ab4SSathya Perla } ____cacheline_aligned_in_smp; 3119aebddd1SJeff Kirsher 3129aebddd1SJeff Kirsher struct be_drv_stats { 3139ae081c6SSomnath Kotur u32 be_on_die_temperature; 3149aebddd1SJeff Kirsher u32 eth_red_drops; 315d3de1540SVasundhara Volam u32 dma_map_errors; 3169aebddd1SJeff Kirsher u32 rx_drops_no_pbuf; 3179aebddd1SJeff Kirsher u32 rx_drops_no_txpb; 3189aebddd1SJeff Kirsher u32 rx_drops_no_erx_descr; 3199aebddd1SJeff Kirsher u32 rx_drops_no_tpre_descr; 3209aebddd1SJeff Kirsher u32 rx_drops_too_many_frags; 3219aebddd1SJeff Kirsher u32 forwarded_packets; 3229aebddd1SJeff Kirsher u32 rx_drops_mtu; 3239aebddd1SJeff Kirsher u32 rx_crc_errors; 3249aebddd1SJeff Kirsher u32 rx_alignment_symbol_errors; 3259aebddd1SJeff Kirsher u32 rx_pause_frames; 3269aebddd1SJeff Kirsher u32 rx_priority_pause_frames; 3279aebddd1SJeff Kirsher u32 rx_control_frames; 3289aebddd1SJeff Kirsher u32 rx_in_range_errors; 3299aebddd1SJeff Kirsher u32 rx_out_range_errors; 3309aebddd1SJeff Kirsher u32 rx_frame_too_long; 33118fb06a1SSuresh Reddy u32 rx_address_filtered; 3329aebddd1SJeff Kirsher u32 rx_dropped_too_small; 3339aebddd1SJeff Kirsher u32 rx_dropped_too_short; 3349aebddd1SJeff Kirsher u32 rx_dropped_header_too_small; 3359aebddd1SJeff Kirsher u32 rx_dropped_tcp_length; 3369aebddd1SJeff Kirsher u32 rx_dropped_runt; 3379aebddd1SJeff Kirsher u32 rx_ip_checksum_errs; 3389aebddd1SJeff Kirsher u32 rx_tcp_checksum_errs; 3399aebddd1SJeff Kirsher u32 rx_udp_checksum_errs; 3409aebddd1SJeff Kirsher u32 tx_pauseframes; 3419aebddd1SJeff Kirsher u32 tx_priority_pauseframes; 3429aebddd1SJeff Kirsher u32 tx_controlframes; 3439aebddd1SJeff Kirsher u32 rxpp_fifo_overflow_drop; 3449aebddd1SJeff Kirsher u32 rx_input_fifo_overflow_drop; 3459aebddd1SJeff Kirsher u32 pmem_fifo_overflow_drop; 3469aebddd1SJeff Kirsher u32 jabber_events; 347461ae379SAjit Khaparde u32 rx_roce_bytes_lsd; 348461ae379SAjit Khaparde u32 rx_roce_bytes_msd; 349461ae379SAjit Khaparde u32 rx_roce_frames; 350461ae379SAjit Khaparde u32 roce_drops_payload_len; 351461ae379SAjit Khaparde u32 roce_drops_crc; 3529aebddd1SJeff Kirsher }; 3539aebddd1SJeff Kirsher 354c502224eSSomnath Kotur /* A vlan-id of 0xFFFF must be used to clear transparent vlan-tagging */ 355c502224eSSomnath Kotur #define BE_RESET_VLAN_TAG_ID 0xFFFF 356c502224eSSomnath Kotur 3579aebddd1SJeff Kirsher struct be_vf_cfg { 35811ac75edSSathya Perla unsigned char mac_addr[ETH_ALEN]; 35911ac75edSSathya Perla int if_handle; 36011ac75edSSathya Perla int pmac_id; 36111ac75edSSathya Perla u16 vlan_tag; 36211ac75edSSathya Perla u32 tx_rate; 363bdce2ad7SSuresh Reddy u32 plink_tracking; 3649aebddd1SJeff Kirsher }; 3659aebddd1SJeff Kirsher 36639f1d94dSSathya Perla enum vf_state { 36739f1d94dSSathya Perla ENABLED = 0, 36839f1d94dSSathya Perla ASSIGNED = 1 36939f1d94dSSathya Perla }; 37039f1d94dSSathya Perla 37183b06116SVasundhara Volam #define BE_FLAGS_LINK_STATUS_INIT BIT(1) 37283b06116SVasundhara Volam #define BE_FLAGS_SRIOV_ENABLED BIT(2) 37383b06116SVasundhara Volam #define BE_FLAGS_WORKER_SCHEDULED BIT(3) 37483b06116SVasundhara Volam #define BE_FLAGS_NAPI_ENABLED BIT(6) 37583b06116SVasundhara Volam #define BE_FLAGS_QNQ_ASYNC_EVT_RCVD BIT(7) 37683b06116SVasundhara Volam #define BE_FLAGS_VXLAN_OFFLOADS BIT(8) 37783b06116SVasundhara Volam #define BE_FLAGS_SETUP_DONE BIT(9) 37821252377SVasundhara Volam #define BE_FLAGS_EVT_INCOMPATIBLE_SFP BIT(10) 379c9c47142SSathya Perla 380fbc13f01SAjit Khaparde #define BE_UC_PMAC_COUNT 30 381fbc13f01SAjit Khaparde #define BE_VF_UC_PMAC_COUNT 2 382f0613380SKalesh AP 3835c510811SSomnath Kotur /* Ethtool set_dump flags */ 3845c510811SSomnath Kotur #define LANCER_INITIATE_FW_DUMP 0x1 385f0613380SKalesh AP #define LANCER_DELETE_FW_DUMP 0x2 3865c510811SSomnath Kotur 38742f11cf2SAjit Khaparde struct phy_info { 38821252377SVasundhara Volam /* From SFF-8472 spec */ 38921252377SVasundhara Volam #define SFP_VENDOR_NAME_LEN 17 39042f11cf2SAjit Khaparde u8 transceiver; 39142f11cf2SAjit Khaparde u8 autoneg; 39242f11cf2SAjit Khaparde u8 fc_autoneg; 39342f11cf2SAjit Khaparde u8 port_type; 39442f11cf2SAjit Khaparde u16 phy_type; 39542f11cf2SAjit Khaparde u16 interface_type; 39642f11cf2SAjit Khaparde u32 misc_params; 39742f11cf2SAjit Khaparde u16 auto_speeds_supported; 39842f11cf2SAjit Khaparde u16 fixed_speeds_supported; 39942f11cf2SAjit Khaparde int link_speed; 40042f11cf2SAjit Khaparde u32 advertising; 40142f11cf2SAjit Khaparde u32 supported; 4026809cee0SRavikumar Nelavelli u8 cable_type; 40321252377SVasundhara Volam u8 vendor_name[SFP_VENDOR_NAME_LEN]; 40421252377SVasundhara Volam u8 vendor_pn[SFP_VENDOR_NAME_LEN]; 40542f11cf2SAjit Khaparde }; 40642f11cf2SAjit Khaparde 40792bf14abSSathya Perla struct be_resources { 40892bf14abSSathya Perla u16 max_vfs; /* Total VFs "really" supported by FW/HW */ 40992bf14abSSathya Perla u16 max_mcast_mac; 41092bf14abSSathya Perla u16 max_tx_qs; 41192bf14abSSathya Perla u16 max_rss_qs; 41292bf14abSSathya Perla u16 max_rx_qs; 41392bf14abSSathya Perla u16 max_uc_mac; /* Max UC MACs programmable */ 41492bf14abSSathya Perla u16 max_vlans; /* Number of vlans supported */ 41592bf14abSSathya Perla u16 max_evt_qs; 41692bf14abSSathya Perla u32 if_cap_flags; 41710cccf60SVasundhara Volam u32 vf_if_cap_flags; /* VF if capability flags */ 41892bf14abSSathya Perla }; 41992bf14abSSathya Perla 420e2557877SVenkata Duvvuru struct rss_info { 421e2557877SVenkata Duvvuru u64 rss_flags; 422e2557877SVenkata Duvvuru u8 rsstable[RSS_INDIR_TABLE_LEN]; 423e2557877SVenkata Duvvuru u8 rss_queue[RSS_INDIR_TABLE_LEN]; 424e2557877SVenkata Duvvuru u8 rss_hkey[RSS_HASH_KEY_LEN]; 425e2557877SVenkata Duvvuru }; 426e2557877SVenkata Duvvuru 427804abcdbSSriharsha Basavapatna /* Macros to read/write the 'features' word of be_wrb_params structure. 428804abcdbSSriharsha Basavapatna */ 429804abcdbSSriharsha Basavapatna #define BE_WRB_F_BIT(name) BE_WRB_F_##name##_BIT 430804abcdbSSriharsha Basavapatna #define BE_WRB_F_MASK(name) BIT_MASK(BE_WRB_F_##name##_BIT) 431804abcdbSSriharsha Basavapatna 432804abcdbSSriharsha Basavapatna #define BE_WRB_F_GET(word, name) \ 433804abcdbSSriharsha Basavapatna (((word) & (BE_WRB_F_MASK(name))) >> BE_WRB_F_BIT(name)) 434804abcdbSSriharsha Basavapatna 435804abcdbSSriharsha Basavapatna #define BE_WRB_F_SET(word, name, val) \ 436804abcdbSSriharsha Basavapatna ((word) |= (((val) << BE_WRB_F_BIT(name)) & BE_WRB_F_MASK(name))) 437804abcdbSSriharsha Basavapatna 438804abcdbSSriharsha Basavapatna /* Feature/offload bits */ 439804abcdbSSriharsha Basavapatna enum { 440804abcdbSSriharsha Basavapatna BE_WRB_F_CRC_BIT, /* Ethernet CRC */ 441804abcdbSSriharsha Basavapatna BE_WRB_F_IPCS_BIT, /* IP csum */ 442804abcdbSSriharsha Basavapatna BE_WRB_F_TCPCS_BIT, /* TCP csum */ 443804abcdbSSriharsha Basavapatna BE_WRB_F_UDPCS_BIT, /* UDP csum */ 444804abcdbSSriharsha Basavapatna BE_WRB_F_LSO_BIT, /* LSO */ 445804abcdbSSriharsha Basavapatna BE_WRB_F_LSO6_BIT, /* LSO6 */ 446804abcdbSSriharsha Basavapatna BE_WRB_F_VLAN_BIT, /* VLAN */ 447804abcdbSSriharsha Basavapatna BE_WRB_F_VLAN_SKIP_HW_BIT /* Skip VLAN tag (workaround) */ 448804abcdbSSriharsha Basavapatna }; 449804abcdbSSriharsha Basavapatna 450804abcdbSSriharsha Basavapatna /* The structure below provides a HW-agnostic abstraction of WRB params 451804abcdbSSriharsha Basavapatna * retrieved from a TX skb. This is in turn passed to chip specific routines 452804abcdbSSriharsha Basavapatna * during transmit, to set the corresponding params in the WRB. 453804abcdbSSriharsha Basavapatna */ 454804abcdbSSriharsha Basavapatna struct be_wrb_params { 455804abcdbSSriharsha Basavapatna u32 features; /* Feature bits */ 456804abcdbSSriharsha Basavapatna u16 vlan_tag; /* VLAN tag */ 457804abcdbSSriharsha Basavapatna u16 lso_mss; /* MSS for LSO */ 458804abcdbSSriharsha Basavapatna }; 459804abcdbSSriharsha Basavapatna 4609aebddd1SJeff Kirsher struct be_adapter { 4619aebddd1SJeff Kirsher struct pci_dev *pdev; 4629aebddd1SJeff Kirsher struct net_device *netdev; 4639aebddd1SJeff Kirsher 464c5b3ad4cSSathya Perla u8 __iomem *csr; /* CSR BAR used only for BE2/3 */ 4659aebddd1SJeff Kirsher u8 __iomem *db; /* Door Bell */ 4669aebddd1SJeff Kirsher 4679aebddd1SJeff Kirsher struct mutex mbox_lock; /* For serializing mbox cmds to BE card */ 4689aebddd1SJeff Kirsher struct be_dma_mem mbox_mem; 4699aebddd1SJeff Kirsher /* Mbox mem is adjusted to align to 16 bytes. The allocated addr 4709aebddd1SJeff Kirsher * is stored for freeing purpose */ 4719aebddd1SJeff Kirsher struct be_dma_mem mbox_mem_alloced; 4729aebddd1SJeff Kirsher 4739aebddd1SJeff Kirsher struct be_mcc_obj mcc_obj; 4749aebddd1SJeff Kirsher spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */ 4759aebddd1SJeff Kirsher spinlock_t mcc_cq_lock; 4769aebddd1SJeff Kirsher 47792bf14abSSathya Perla u16 cfg_num_qs; /* configured via set-channels */ 47892bf14abSSathya Perla u16 num_evt_qs; 47992bf14abSSathya Perla u16 num_msix_vec; 48092bf14abSSathya Perla struct be_eq_obj eq_obj[MAX_EVT_QS]; 48110ef9ab4SSathya Perla struct msix_entry msix_entries[MAX_MSIX_VECTORS]; 4829aebddd1SJeff Kirsher bool isr_registered; 4839aebddd1SJeff Kirsher 4849aebddd1SJeff Kirsher /* TX Rings */ 48592bf14abSSathya Perla u16 num_tx_qs; 4869aebddd1SJeff Kirsher struct be_tx_obj tx_obj[MAX_TX_QS]; 4879aebddd1SJeff Kirsher 4889aebddd1SJeff Kirsher /* Rx rings */ 48992bf14abSSathya Perla u16 num_rx_qs; 49010ef9ab4SSathya Perla struct be_rx_obj rx_obj[MAX_RX_QS]; 4919aebddd1SJeff Kirsher u32 big_page_size; /* Compounded page size shared by rx wrbs */ 4929aebddd1SJeff Kirsher 4939aebddd1SJeff Kirsher struct be_drv_stats drv_stats; 4942632bafdSSathya Perla struct be_aic_obj aic_obj[MAX_EVT_QS]; 4959aebddd1SJeff Kirsher u8 vlan_prio_bmap; /* Available Priority BitMap */ 4969aebddd1SJeff Kirsher u16 recommended_prio; /* Recommended Priority */ 4979aebddd1SJeff Kirsher struct be_dma_mem rx_filter; /* Cmd DMA mem for rx-filter */ 4989aebddd1SJeff Kirsher 4999aebddd1SJeff Kirsher struct be_dma_mem stats_cmd; 5009aebddd1SJeff Kirsher /* Work queue used to perform periodic tasks like getting statistics */ 5019aebddd1SJeff Kirsher struct delayed_work work; 5029aebddd1SJeff Kirsher u16 work_counter; 5039aebddd1SJeff Kirsher 504f67ef7baSPadmanabh Ratnakar struct delayed_work func_recovery_work; 505b236916aSAjit Khaparde u32 flags; 506f25b119cSPadmanabh Ratnakar u32 cmd_privileges; 5079aebddd1SJeff Kirsher /* Ethtool knobs and info */ 5089aebddd1SJeff Kirsher char fw_ver[FW_VER_LEN]; 509eeb65cedSSomnath Kotur char fw_on_flash[FW_VER_LEN]; 510f66b7cfdSSathya Perla 511f66b7cfdSSathya Perla /* IFACE filtering fields */ 51230128031SSathya Perla int if_handle; /* Used to configure filtering */ 513f66b7cfdSSathya Perla u32 if_flags; /* Interface filtering flags */ 514fbc13f01SAjit Khaparde u32 *pmac_id; /* MAC addr handle used by BE card */ 515f66b7cfdSSathya Perla u32 uc_macs; /* Count of secondary UC MAC programmed */ 516f66b7cfdSSathya Perla unsigned long vids[BITS_TO_LONGS(VLAN_N_VID)]; 517f66b7cfdSSathya Perla u16 vlans_added; 518f66b7cfdSSathya Perla 5199aebddd1SJeff Kirsher u32 beacon_state; /* for set_phys_id */ 5209aebddd1SJeff Kirsher 521f67ef7baSPadmanabh Ratnakar bool eeh_error; 5226589ade0SSathya Perla bool fw_timeout; 523f67ef7baSPadmanabh Ratnakar bool hw_error; 524f67ef7baSPadmanabh Ratnakar 5259aebddd1SJeff Kirsher u32 port_num; 52621252377SVasundhara Volam char port_name; 527f93f160bSVasundhara Volam u8 mc_type; 5289aebddd1SJeff Kirsher u32 function_mode; 5299aebddd1SJeff Kirsher u32 function_caps; 5309aebddd1SJeff Kirsher u32 rx_fc; /* Rx flow control */ 5319aebddd1SJeff Kirsher u32 tx_fc; /* Tx flow control */ 5329aebddd1SJeff Kirsher bool stats_cmd_sent; 533045508a8SParav Pandit struct { 534045508a8SParav Pandit u32 size; 535045508a8SParav Pandit u32 total_size; 536045508a8SParav Pandit u64 io_addr; 537045508a8SParav Pandit } roce_db; 538045508a8SParav Pandit u32 num_msix_roce_vec; 539045508a8SParav Pandit struct ocrdma_dev *ocrdma_dev; 540045508a8SParav Pandit struct list_head entry; 541045508a8SParav Pandit 5429aebddd1SJeff Kirsher u32 flash_status; 5435eeff635SSuresh Reddy struct completion et_cmd_compl; 5449aebddd1SJeff Kirsher 545bec84e6bSVasundhara Volam struct be_resources pool_res; /* resources available for the port */ 54692bf14abSSathya Perla struct be_resources res; /* resources available for the func */ 54792bf14abSSathya Perla u16 num_vfs; /* Number of VFs provisioned by PF */ 54839f1d94dSSathya Perla u8 virtfn; 54911ac75edSSathya Perla struct be_vf_cfg *vf_cfg; 55011ac75edSSathya Perla bool be3_native; 5519aebddd1SJeff Kirsher u32 sli_family; 5529aebddd1SJeff Kirsher u8 hba_port_num; 5539aebddd1SJeff Kirsher u16 pvid; 554c9c47142SSathya Perla __be16 vxlan_port; 555630f4b70SSriharsha Basavapatna int vxlan_port_count; 55642f11cf2SAjit Khaparde struct phy_info phy; 5574762f6ceSAjit Khaparde u8 wol_cap; 55876a9e08eSSuresh Reddy bool wol_en; 5590ad3157eSVasundhara Volam u16 asic_rev; 560bc0c3405SAjit Khaparde u16 qnq_vid; 561941a77d5SSomnath Kotur u32 msg_enable; 5627aeb2156SPadmanabh Ratnakar int be_get_temp_freq; 563d5c18473SPadmanabh Ratnakar u8 pf_number; 564e2557877SVenkata Duvvuru struct rss_info rss_info; 5659aebddd1SJeff Kirsher }; 5669aebddd1SJeff Kirsher 56739f1d94dSSathya Perla #define be_physfn(adapter) (!adapter->virtfn) 5682c7a9dc1SAjit Khaparde #define be_virtfn(adapter) (adapter->virtfn) 569f174c7ecSVasundhara Volam #define sriov_enabled(adapter) (adapter->flags & \ 570f174c7ecSVasundhara Volam BE_FLAGS_SRIOV_ENABLED) 571bec84e6bSVasundhara Volam 57211ac75edSSathya Perla #define for_all_vfs(adapter, vf_cfg, i) \ 57311ac75edSSathya Perla for (i = 0, vf_cfg = &adapter->vf_cfg[i]; i < adapter->num_vfs; \ 57411ac75edSSathya Perla i++, vf_cfg++) 5759aebddd1SJeff Kirsher 5769aebddd1SJeff Kirsher #define ON 1 5779aebddd1SJeff Kirsher #define OFF 0 578ca34fe38SSathya Perla 57992bf14abSSathya Perla #define be_max_vlans(adapter) (adapter->res.max_vlans) 58092bf14abSSathya Perla #define be_max_uc(adapter) (adapter->res.max_uc_mac) 58192bf14abSSathya Perla #define be_max_mc(adapter) (adapter->res.max_mcast_mac) 582bec84e6bSVasundhara Volam #define be_max_vfs(adapter) (adapter->pool_res.max_vfs) 58392bf14abSSathya Perla #define be_max_rss(adapter) (adapter->res.max_rss_qs) 58492bf14abSSathya Perla #define be_max_txqs(adapter) (adapter->res.max_tx_qs) 58592bf14abSSathya Perla #define be_max_prio_txqs(adapter) (adapter->res.max_prio_tx_qs) 58692bf14abSSathya Perla #define be_max_rxqs(adapter) (adapter->res.max_rx_qs) 58792bf14abSSathya Perla #define be_max_eqs(adapter) (adapter->res.max_evt_qs) 58892bf14abSSathya Perla #define be_if_cap_flags(adapter) (adapter->res.if_cap_flags) 58992bf14abSSathya Perla 59092bf14abSSathya Perla static inline u16 be_max_qs(struct be_adapter *adapter) 59192bf14abSSathya Perla { 59292bf14abSSathya Perla /* If no RSS, need atleast the one def RXQ */ 59392bf14abSSathya Perla u16 num = max_t(u16, be_max_rss(adapter), 1); 59492bf14abSSathya Perla 59592bf14abSSathya Perla num = min(num, be_max_eqs(adapter)); 59692bf14abSSathya Perla return min_t(u16, num, num_online_cpus()); 59792bf14abSSathya Perla } 59892bf14abSSathya Perla 599f93f160bSVasundhara Volam /* Is BE in pvid_tagging mode */ 600f93f160bSVasundhara Volam #define be_pvid_tagging_enabled(adapter) (adapter->pvid) 601f93f160bSVasundhara Volam 602f93f160bSVasundhara Volam /* Is BE in QNQ multi-channel mode */ 60366064dbcSSuresh Reddy #define be_is_qnq_mode(adapter) (adapter->function_mode & QNQ_MODE) 604f93f160bSVasundhara Volam 605ca34fe38SSathya Perla #define lancer_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID3 || \ 606ca34fe38SSathya Perla adapter->pdev->device == OC_DEVICE_ID4) 6079aebddd1SJeff Kirsher 60876b73530SPadmanabh Ratnakar #define skyhawk_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID5 || \ 60976b73530SPadmanabh Ratnakar adapter->pdev->device == OC_DEVICE_ID6) 610d3bd3a5eSPadmanabh Ratnakar 611ca34fe38SSathya Perla #define BE3_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID2 || \ 612ca34fe38SSathya Perla adapter->pdev->device == OC_DEVICE_ID2) 613ca34fe38SSathya Perla 614ca34fe38SSathya Perla #define BE2_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID1 || \ 615ca34fe38SSathya Perla adapter->pdev->device == OC_DEVICE_ID1) 616ca34fe38SSathya Perla 617ca34fe38SSathya Perla #define BEx_chip(adapter) (BE3_chip(adapter) || BE2_chip(adapter)) 618d3bd3a5eSPadmanabh Ratnakar 619dbf0f2a7SSathya Perla #define be_roce_supported(adapter) (skyhawk_chip(adapter) && \ 620045508a8SParav Pandit (adapter->function_mode & RDMA_ENABLED)) 621045508a8SParav Pandit 6229aebddd1SJeff Kirsher extern const struct ethtool_ops be_ethtool_ops; 6239aebddd1SJeff Kirsher 6249aebddd1SJeff Kirsher #define msix_enabled(adapter) (adapter->num_msix_vec > 0) 62510ef9ab4SSathya Perla #define num_irqs(adapter) (msix_enabled(adapter) ? \ 62610ef9ab4SSathya Perla adapter->num_msix_vec : 1) 62710ef9ab4SSathya Perla #define tx_stats(txo) (&(txo)->stats) 62810ef9ab4SSathya Perla #define rx_stats(rxo) (&(rxo)->stats) 6299aebddd1SJeff Kirsher 63010ef9ab4SSathya Perla /* The default RXQ is the last RXQ */ 63110ef9ab4SSathya Perla #define default_rxo(adpt) (&adpt->rx_obj[adpt->num_rx_qs - 1]) 6329aebddd1SJeff Kirsher 6339aebddd1SJeff Kirsher #define for_all_rx_queues(adapter, rxo, i) \ 6349aebddd1SJeff Kirsher for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \ 6359aebddd1SJeff Kirsher i++, rxo++) 6369aebddd1SJeff Kirsher 63710ef9ab4SSathya Perla /* Skip the default non-rss queue (last one)*/ 6389aebddd1SJeff Kirsher #define for_all_rss_queues(adapter, rxo, i) \ 63910ef9ab4SSathya Perla for (i = 0, rxo = &adapter->rx_obj[i]; i < (adapter->num_rx_qs - 1);\ 6409aebddd1SJeff Kirsher i++, rxo++) 6419aebddd1SJeff Kirsher 6429aebddd1SJeff Kirsher #define for_all_tx_queues(adapter, txo, i) \ 6439aebddd1SJeff Kirsher for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs; \ 6449aebddd1SJeff Kirsher i++, txo++) 6459aebddd1SJeff Kirsher 64610ef9ab4SSathya Perla #define for_all_evt_queues(adapter, eqo, i) \ 64710ef9ab4SSathya Perla for (i = 0, eqo = &adapter->eq_obj[i]; i < adapter->num_evt_qs; \ 64810ef9ab4SSathya Perla i++, eqo++) 64910ef9ab4SSathya Perla 6506384a4d0SSathya Perla #define for_all_rx_queues_on_eq(adapter, eqo, rxo, i) \ 6516384a4d0SSathya Perla for (i = eqo->idx, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs;\ 6526384a4d0SSathya Perla i += adapter->num_evt_qs, rxo += adapter->num_evt_qs) 6536384a4d0SSathya Perla 654a4906ea0SSathya Perla #define for_all_tx_queues_on_eq(adapter, eqo, txo, i) \ 655a4906ea0SSathya Perla for (i = eqo->idx, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs;\ 656a4906ea0SSathya Perla i += adapter->num_evt_qs, txo += adapter->num_evt_qs) 657a4906ea0SSathya Perla 65810ef9ab4SSathya Perla #define is_mcc_eqo(eqo) (eqo->idx == 0) 65910ef9ab4SSathya Perla #define mcc_eqo(adapter) (&adapter->eq_obj[0]) 66010ef9ab4SSathya Perla 6619aebddd1SJeff Kirsher #define PAGE_SHIFT_4K 12 6629aebddd1SJeff Kirsher #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K) 6639aebddd1SJeff Kirsher 6649aebddd1SJeff Kirsher /* Returns number of pages spanned by the data starting at the given addr */ 6659aebddd1SJeff Kirsher #define PAGES_4K_SPANNED(_address, size) \ 6669aebddd1SJeff Kirsher ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \ 6679aebddd1SJeff Kirsher (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K)) 6689aebddd1SJeff Kirsher 6699aebddd1SJeff Kirsher /* Returns bit offset within a DWORD of a bitfield */ 6709aebddd1SJeff Kirsher #define AMAP_BIT_OFFSET(_struct, field) \ 6719aebddd1SJeff Kirsher (((size_t)&(((_struct *)0)->field))%32) 6729aebddd1SJeff Kirsher 6739aebddd1SJeff Kirsher /* Returns the bit mask of the field that is NOT shifted into location. */ 6749aebddd1SJeff Kirsher static inline u32 amap_mask(u32 bitsize) 6759aebddd1SJeff Kirsher { 6769aebddd1SJeff Kirsher return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1); 6779aebddd1SJeff Kirsher } 6789aebddd1SJeff Kirsher 6799aebddd1SJeff Kirsher static inline void 6809aebddd1SJeff Kirsher amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value) 6819aebddd1SJeff Kirsher { 6829aebddd1SJeff Kirsher u32 *dw = (u32 *) ptr + dw_offset; 6839aebddd1SJeff Kirsher *dw &= ~(mask << offset); 6849aebddd1SJeff Kirsher *dw |= (mask & value) << offset; 6859aebddd1SJeff Kirsher } 6869aebddd1SJeff Kirsher 6879aebddd1SJeff Kirsher #define AMAP_SET_BITS(_struct, field, ptr, val) \ 6889aebddd1SJeff Kirsher amap_set(ptr, \ 6899aebddd1SJeff Kirsher offsetof(_struct, field)/32, \ 6909aebddd1SJeff Kirsher amap_mask(sizeof(((_struct *)0)->field)), \ 6919aebddd1SJeff Kirsher AMAP_BIT_OFFSET(_struct, field), \ 6929aebddd1SJeff Kirsher val) 6939aebddd1SJeff Kirsher 6949aebddd1SJeff Kirsher static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset) 6959aebddd1SJeff Kirsher { 6969aebddd1SJeff Kirsher u32 *dw = (u32 *) ptr; 6979aebddd1SJeff Kirsher return mask & (*(dw + dw_offset) >> offset); 6989aebddd1SJeff Kirsher } 6999aebddd1SJeff Kirsher 7009aebddd1SJeff Kirsher #define AMAP_GET_BITS(_struct, field, ptr) \ 7019aebddd1SJeff Kirsher amap_get(ptr, \ 7029aebddd1SJeff Kirsher offsetof(_struct, field)/32, \ 7039aebddd1SJeff Kirsher amap_mask(sizeof(((_struct *)0)->field)), \ 7049aebddd1SJeff Kirsher AMAP_BIT_OFFSET(_struct, field)) 7059aebddd1SJeff Kirsher 706c3c18bc1SSathya Perla #define GET_RX_COMPL_V0_BITS(field, ptr) \ 707c3c18bc1SSathya Perla AMAP_GET_BITS(struct amap_eth_rx_compl_v0, field, ptr) 708c3c18bc1SSathya Perla 709c3c18bc1SSathya Perla #define GET_RX_COMPL_V1_BITS(field, ptr) \ 710c3c18bc1SSathya Perla AMAP_GET_BITS(struct amap_eth_rx_compl_v1, field, ptr) 711c3c18bc1SSathya Perla 712c3c18bc1SSathya Perla #define GET_TX_COMPL_BITS(field, ptr) \ 713c3c18bc1SSathya Perla AMAP_GET_BITS(struct amap_eth_tx_compl, field, ptr) 714c3c18bc1SSathya Perla 715c3c18bc1SSathya Perla #define SET_TX_WRB_HDR_BITS(field, ptr, val) \ 716c3c18bc1SSathya Perla AMAP_SET_BITS(struct amap_eth_hdr_wrb, field, ptr, val) 717c3c18bc1SSathya Perla 7189aebddd1SJeff Kirsher #define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len) 7199aebddd1SJeff Kirsher #define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len) 7209aebddd1SJeff Kirsher static inline void swap_dws(void *wrb, int len) 7219aebddd1SJeff Kirsher { 7229aebddd1SJeff Kirsher #ifdef __BIG_ENDIAN 7239aebddd1SJeff Kirsher u32 *dw = wrb; 7249aebddd1SJeff Kirsher BUG_ON(len % 4); 7259aebddd1SJeff Kirsher do { 7269aebddd1SJeff Kirsher *dw = cpu_to_le32(*dw); 7279aebddd1SJeff Kirsher dw++; 7289aebddd1SJeff Kirsher len -= 4; 7299aebddd1SJeff Kirsher } while (len); 7309aebddd1SJeff Kirsher #endif /* __BIG_ENDIAN */ 7319aebddd1SJeff Kirsher } 7329aebddd1SJeff Kirsher 7330532d4e3SKalesh AP #define be_cmd_status(status) (status > 0 ? -EIO : status) 7340532d4e3SKalesh AP 7359aebddd1SJeff Kirsher static inline u8 is_tcp_pkt(struct sk_buff *skb) 7369aebddd1SJeff Kirsher { 7379aebddd1SJeff Kirsher u8 val = 0; 7389aebddd1SJeff Kirsher 7399aebddd1SJeff Kirsher if (ip_hdr(skb)->version == 4) 7409aebddd1SJeff Kirsher val = (ip_hdr(skb)->protocol == IPPROTO_TCP); 7419aebddd1SJeff Kirsher else if (ip_hdr(skb)->version == 6) 7429aebddd1SJeff Kirsher val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP); 7439aebddd1SJeff Kirsher 7449aebddd1SJeff Kirsher return val; 7459aebddd1SJeff Kirsher } 7469aebddd1SJeff Kirsher 7479aebddd1SJeff Kirsher static inline u8 is_udp_pkt(struct sk_buff *skb) 7489aebddd1SJeff Kirsher { 7499aebddd1SJeff Kirsher u8 val = 0; 7509aebddd1SJeff Kirsher 7519aebddd1SJeff Kirsher if (ip_hdr(skb)->version == 4) 7529aebddd1SJeff Kirsher val = (ip_hdr(skb)->protocol == IPPROTO_UDP); 7539aebddd1SJeff Kirsher else if (ip_hdr(skb)->version == 6) 7549aebddd1SJeff Kirsher val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP); 7559aebddd1SJeff Kirsher 7569aebddd1SJeff Kirsher return val; 7579aebddd1SJeff Kirsher } 7589aebddd1SJeff Kirsher 75993040ae5SSomnath Kotur static inline bool is_ipv4_pkt(struct sk_buff *skb) 76093040ae5SSomnath Kotur { 761e8efcec5SLi RongQing return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 76293040ae5SSomnath Kotur } 76393040ae5SSomnath Kotur 7649aebddd1SJeff Kirsher static inline bool be_multi_rxq(const struct be_adapter *adapter) 7659aebddd1SJeff Kirsher { 7669aebddd1SJeff Kirsher return adapter->num_rx_qs > 1; 7679aebddd1SJeff Kirsher } 7689aebddd1SJeff Kirsher 7696589ade0SSathya Perla static inline bool be_error(struct be_adapter *adapter) 7706589ade0SSathya Perla { 771f67ef7baSPadmanabh Ratnakar return adapter->eeh_error || adapter->hw_error || adapter->fw_timeout; 772f67ef7baSPadmanabh Ratnakar } 773f67ef7baSPadmanabh Ratnakar 774d23e946cSSathya Perla static inline bool be_hw_error(struct be_adapter *adapter) 775f67ef7baSPadmanabh Ratnakar { 776f67ef7baSPadmanabh Ratnakar return adapter->eeh_error || adapter->hw_error; 777f67ef7baSPadmanabh Ratnakar } 778f67ef7baSPadmanabh Ratnakar 779f67ef7baSPadmanabh Ratnakar static inline void be_clear_all_error(struct be_adapter *adapter) 780f67ef7baSPadmanabh Ratnakar { 781f67ef7baSPadmanabh Ratnakar adapter->eeh_error = false; 782f67ef7baSPadmanabh Ratnakar adapter->hw_error = false; 783f67ef7baSPadmanabh Ratnakar adapter->fw_timeout = false; 7846589ade0SSathya Perla } 7856589ade0SSathya Perla 78631886e87SJoe Perches void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, 7879aebddd1SJeff Kirsher u16 num_popped); 78831886e87SJoe Perches void be_link_status_update(struct be_adapter *adapter, u8 link_status); 78931886e87SJoe Perches void be_parse_stats(struct be_adapter *adapter); 79031886e87SJoe Perches int be_load_fw(struct be_adapter *adapter, u8 *func); 79131886e87SJoe Perches bool be_is_wol_supported(struct be_adapter *adapter); 79231886e87SJoe Perches bool be_pause_supported(struct be_adapter *adapter); 79331886e87SJoe Perches u32 be_get_fw_log_level(struct be_adapter *adapter); 79468d7bdcbSSathya Perla int be_update_queues(struct be_adapter *adapter); 79568d7bdcbSSathya Perla int be_poll(struct napi_struct *napi, int budget); 796941a77d5SSomnath Kotur 797045508a8SParav Pandit /* 798045508a8SParav Pandit * internal function to initialize-cleanup roce device. 799045508a8SParav Pandit */ 80031886e87SJoe Perches void be_roce_dev_add(struct be_adapter *); 80131886e87SJoe Perches void be_roce_dev_remove(struct be_adapter *); 802045508a8SParav Pandit 803045508a8SParav Pandit /* 804045508a8SParav Pandit * internal function to open-close roce device during ifup-ifdown. 805045508a8SParav Pandit */ 80631886e87SJoe Perches void be_roce_dev_open(struct be_adapter *); 80731886e87SJoe Perches void be_roce_dev_close(struct be_adapter *); 808d114f99aSDevesh Sharma void be_roce_dev_shutdown(struct be_adapter *); 809045508a8SParav Pandit 8109aebddd1SJeff Kirsher #endif /* BE_H */ 811