16e9ef509SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
29aebddd1SJeff Kirsher /*
37dfbe7d7SSomnath Kotur * Copyright (C) 2005 - 2016 Broadcom
49aebddd1SJeff Kirsher * All rights reserved.
59aebddd1SJeff Kirsher *
69aebddd1SJeff Kirsher * Contact Information:
79aebddd1SJeff Kirsher * linux-drivers@emulex.com
89aebddd1SJeff Kirsher *
99aebddd1SJeff Kirsher * Emulex
109aebddd1SJeff Kirsher * 3333 Susan Street
119aebddd1SJeff Kirsher * Costa Mesa, CA 92626
129aebddd1SJeff Kirsher */
139aebddd1SJeff Kirsher
149aebddd1SJeff Kirsher #ifndef BE_H
159aebddd1SJeff Kirsher #define BE_H
169aebddd1SJeff Kirsher
179aebddd1SJeff Kirsher #include <linux/pci.h>
189aebddd1SJeff Kirsher #include <linux/etherdevice.h>
199aebddd1SJeff Kirsher #include <linux/delay.h>
209aebddd1SJeff Kirsher #include <net/tcp.h>
219aebddd1SJeff Kirsher #include <net/ip.h>
229aebddd1SJeff Kirsher #include <net/ipv6.h>
239aebddd1SJeff Kirsher #include <linux/if_vlan.h>
249aebddd1SJeff Kirsher #include <linux/workqueue.h>
259aebddd1SJeff Kirsher #include <linux/interrupt.h>
269aebddd1SJeff Kirsher #include <linux/firmware.h>
279aebddd1SJeff Kirsher #include <linux/slab.h>
289aebddd1SJeff Kirsher #include <linux/u64_stats_sync.h>
29d658d98aSPadmanabh Ratnakar #include <linux/cpumask.h>
3029e9122bSVenkata Duvvuru #include <linux/hwmon.h>
3129e9122bSVenkata Duvvuru #include <linux/hwmon-sysfs.h>
329aebddd1SJeff Kirsher
339aebddd1SJeff Kirsher #include "be_hw.h"
34045508a8SParav Pandit #include "be_roce.h"
359aebddd1SJeff Kirsher
369aebddd1SJeff Kirsher #define DRV_NAME "be2net"
3700d3d51eSSarveshwar Bandi #define BE_NAME "Emulex BladeEngine2"
3800d3d51eSSarveshwar Bandi #define BE3_NAME "Emulex BladeEngine3"
3900d3d51eSSarveshwar Bandi #define OC_NAME "Emulex OneConnect"
409aebddd1SJeff Kirsher #define OC_NAME_BE OC_NAME "(be3)"
419aebddd1SJeff Kirsher #define OC_NAME_LANCER OC_NAME "(Lancer)"
42ecedb6aeSAjit Khaparde #define OC_NAME_SH OC_NAME "(Skyhawk)"
43f3effb45SSuresh Reddy #define DRV_DESC "Emulex OneConnect NIC Driver"
449aebddd1SJeff Kirsher
459aebddd1SJeff Kirsher #define BE_VENDOR_ID 0x19a2
469aebddd1SJeff Kirsher #define EMULEX_VENDOR_ID 0x10df
479aebddd1SJeff Kirsher #define BE_DEVICE_ID1 0x211
489aebddd1SJeff Kirsher #define BE_DEVICE_ID2 0x221
499aebddd1SJeff Kirsher #define OC_DEVICE_ID1 0x700 /* Device Id for BE2 cards */
509aebddd1SJeff Kirsher #define OC_DEVICE_ID2 0x710 /* Device Id for BE3 cards */
519aebddd1SJeff Kirsher #define OC_DEVICE_ID3 0xe220 /* Device id for Lancer cards */
529aebddd1SJeff Kirsher #define OC_DEVICE_ID4 0xe228 /* Device id for VF in Lancer */
53ecedb6aeSAjit Khaparde #define OC_DEVICE_ID5 0x720 /* Device Id for Skyhawk cards */
5476b73530SPadmanabh Ratnakar #define OC_DEVICE_ID6 0x728 /* Device id for VF in SkyHawk */
554762f6ceSAjit Khaparde #define OC_SUBSYS_DEVICE_ID1 0xE602
564762f6ceSAjit Khaparde #define OC_SUBSYS_DEVICE_ID2 0xE642
574762f6ceSAjit Khaparde #define OC_SUBSYS_DEVICE_ID3 0xE612
584762f6ceSAjit Khaparde #define OC_SUBSYS_DEVICE_ID4 0xE652
599aebddd1SJeff Kirsher
609aebddd1SJeff Kirsher /* Number of bytes of an RX frame that are copied to skb->data */
619aebddd1SJeff Kirsher #define BE_HDR_LEN ((u16) 64)
62bb349bb4SEric Dumazet /* allocate extra space to allow tunneling decapsulation without head reallocation */
6376b15923SKalesh A P #define BE_RX_SKB_ALLOC_SIZE 256
64bb349bb4SEric Dumazet
659aebddd1SJeff Kirsher #define BE_MAX_JUMBO_FRAME_SIZE 9018
669aebddd1SJeff Kirsher #define BE_MIN_MTU 256
670d3f5cceSKalesh AP #define BE_MAX_MTU (BE_MAX_JUMBO_FRAME_SIZE - \
680d3f5cceSKalesh AP (ETH_HLEN + ETH_FCS_LEN))
699aebddd1SJeff Kirsher
70127bfce5Sajit.khaparde@broadcom.com /* Accommodate for QnQ configurations where VLAN insertion is enabled in HW */
71127bfce5Sajit.khaparde@broadcom.com #define BE_MAX_GSO_SIZE (65535 - 2 * VLAN_HLEN)
72127bfce5Sajit.khaparde@broadcom.com
739aebddd1SJeff Kirsher #define BE_NUM_VLANS_SUPPORTED 64
742632bafdSSathya Perla #define BE_MAX_EQD 128u
759aebddd1SJeff Kirsher #define BE_MAX_TX_FRAG_COUNT 30
769aebddd1SJeff Kirsher
779aebddd1SJeff Kirsher #define EVNT_Q_LEN 1024
789aebddd1SJeff Kirsher #define TX_Q_LEN 2048
799aebddd1SJeff Kirsher #define TX_CQ_LEN 1024
809aebddd1SJeff Kirsher #define RX_Q_LEN 1024 /* Does not support any other value */
819aebddd1SJeff Kirsher #define RX_CQ_LEN 1024
829aebddd1SJeff Kirsher #define MCC_Q_LEN 128 /* total size not to exceed 8 pages */
839aebddd1SJeff Kirsher #define MCC_CQ_LEN 256
849aebddd1SJeff Kirsher
8510ef9ab4SSathya Perla #define BE2_MAX_RSS_QS 4
8668d7bdcbSSathya Perla #define BE3_MAX_RSS_QS 16
8768d7bdcbSSathya Perla #define BE3_MAX_TX_QS 16
8868d7bdcbSSathya Perla #define BE3_MAX_EVT_QS 16
89e3dc867cSSuresh Reddy #define BE3_SRIOV_MAX_EVT_QS 8
90ee9ad280SSriharsha Basavapatna #define SH_VF_MAX_NIC_EQS 3 /* Skyhawk VFs can have a max of 4 EQs
91ee9ad280SSriharsha Basavapatna * and at least 1 is granted to either
92ee9ad280SSriharsha Basavapatna * SURF/DPDK
93ee9ad280SSriharsha Basavapatna */
9410ef9ab4SSathya Perla
95de2b1e03SSomnath Kotur #define MAX_PORT_RSS_TABLES 15
96de2b1e03SSomnath Kotur #define MAX_NIC_FUNCS 16
9768d7bdcbSSathya Perla #define MAX_RX_QS 32
9868d7bdcbSSathya Perla #define MAX_EVT_QS 32
9968d7bdcbSSathya Perla #define MAX_TX_QS 32
10068d7bdcbSSathya Perla
101045508a8SParav Pandit #define MAX_ROCE_EQS 5
10268d7bdcbSSathya Perla #define MAX_MSIX_VECTORS 32
10392bf14abSSathya Perla #define MIN_MSIX_VECTORS 1
104*e702def5SJakub Kicinski #define MAX_RX_POST NAPI_POLL_WEIGHT /* Frags posted at a time */
1059aebddd1SJeff Kirsher #define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST)
10669304cc9SAjit Khaparde #define MAX_NUM_POST_ERX_DB 255u
1079aebddd1SJeff Kirsher
1087c5a5242SVasundhara Volam #define MAX_VFS 30 /* Max VFs supported by BE3 FW */
1099aebddd1SJeff Kirsher #define FW_VER_LEN 32
110a155a5dbSSriharsha Basavapatna #define CNTL_SERIAL_NUM_WORDS 8 /* Controller serial number words */
111a155a5dbSSriharsha Basavapatna #define CNTL_SERIAL_NUM_WORD_SZ (sizeof(u16)) /* Byte-sz of serial num word */
1129aebddd1SJeff Kirsher
113e2557877SVenkata Duvvuru #define RSS_INDIR_TABLE_LEN 128
114e2557877SVenkata Duvvuru #define RSS_HASH_KEY_LEN 40
115e2557877SVenkata Duvvuru
11651d1f98aSAjit Khaparde #define BE_UNKNOWN_PHY_STATE 0xFF
11751d1f98aSAjit Khaparde
1189aebddd1SJeff Kirsher struct be_dma_mem {
1199aebddd1SJeff Kirsher void *va;
1209aebddd1SJeff Kirsher dma_addr_t dma;
1219aebddd1SJeff Kirsher u32 size;
1229aebddd1SJeff Kirsher };
1239aebddd1SJeff Kirsher
1249aebddd1SJeff Kirsher struct be_queue_info {
125b0fd2eb2Sajit.khaparde@broadcom.com u32 len;
126b0fd2eb2Sajit.khaparde@broadcom.com u32 entry_size; /* Size of an element in the queue */
127b0fd2eb2Sajit.khaparde@broadcom.com u32 tail, head;
1289aebddd1SJeff Kirsher atomic_t used; /* Number of valid elements in the queue */
129b0fd2eb2Sajit.khaparde@broadcom.com u32 id;
130b0fd2eb2Sajit.khaparde@broadcom.com struct be_dma_mem dma_mem;
131b0fd2eb2Sajit.khaparde@broadcom.com bool created;
1329aebddd1SJeff Kirsher };
1339aebddd1SJeff Kirsher
MODULO(u32 val,u32 limit)134b0fd2eb2Sajit.khaparde@broadcom.com static inline u32 MODULO(u32 val, u32 limit)
1359aebddd1SJeff Kirsher {
1369aebddd1SJeff Kirsher BUG_ON(limit & (limit - 1));
1379aebddd1SJeff Kirsher return val & (limit - 1);
1389aebddd1SJeff Kirsher }
1399aebddd1SJeff Kirsher
index_adv(u32 * index,u32 val,u32 limit)140b0fd2eb2Sajit.khaparde@broadcom.com static inline void index_adv(u32 *index, u32 val, u32 limit)
1419aebddd1SJeff Kirsher {
1429aebddd1SJeff Kirsher *index = MODULO((*index + val), limit);
1439aebddd1SJeff Kirsher }
1449aebddd1SJeff Kirsher
index_inc(u32 * index,u32 limit)145b0fd2eb2Sajit.khaparde@broadcom.com static inline void index_inc(u32 *index, u32 limit)
1469aebddd1SJeff Kirsher {
1479aebddd1SJeff Kirsher *index = MODULO((*index + 1), limit);
1489aebddd1SJeff Kirsher }
1499aebddd1SJeff Kirsher
queue_head_node(struct be_queue_info * q)1509aebddd1SJeff Kirsher static inline void *queue_head_node(struct be_queue_info *q)
1519aebddd1SJeff Kirsher {
1529aebddd1SJeff Kirsher return q->dma_mem.va + q->head * q->entry_size;
1539aebddd1SJeff Kirsher }
1549aebddd1SJeff Kirsher
queue_tail_node(struct be_queue_info * q)1559aebddd1SJeff Kirsher static inline void *queue_tail_node(struct be_queue_info *q)
1569aebddd1SJeff Kirsher {
1579aebddd1SJeff Kirsher return q->dma_mem.va + q->tail * q->entry_size;
1589aebddd1SJeff Kirsher }
1599aebddd1SJeff Kirsher
queue_index_node(struct be_queue_info * q,u16 index)1603de09455SSomnath Kotur static inline void *queue_index_node(struct be_queue_info *q, u16 index)
1613de09455SSomnath Kotur {
1623de09455SSomnath Kotur return q->dma_mem.va + index * q->entry_size;
1633de09455SSomnath Kotur }
1643de09455SSomnath Kotur
queue_head_inc(struct be_queue_info * q)1659aebddd1SJeff Kirsher static inline void queue_head_inc(struct be_queue_info *q)
1669aebddd1SJeff Kirsher {
1679aebddd1SJeff Kirsher index_inc(&q->head, q->len);
1689aebddd1SJeff Kirsher }
1699aebddd1SJeff Kirsher
index_dec(u32 * index,u32 limit)170b0fd2eb2Sajit.khaparde@broadcom.com static inline void index_dec(u32 *index, u32 limit)
171652bf646SPadmanabh Ratnakar {
172652bf646SPadmanabh Ratnakar *index = MODULO((*index - 1), limit);
173652bf646SPadmanabh Ratnakar }
174652bf646SPadmanabh Ratnakar
queue_tail_inc(struct be_queue_info * q)1759aebddd1SJeff Kirsher static inline void queue_tail_inc(struct be_queue_info *q)
1769aebddd1SJeff Kirsher {
1779aebddd1SJeff Kirsher index_inc(&q->tail, q->len);
1789aebddd1SJeff Kirsher }
1799aebddd1SJeff Kirsher
1809aebddd1SJeff Kirsher struct be_eq_obj {
1819aebddd1SJeff Kirsher struct be_queue_info q;
1825ef79151SIvan Vecera char desc[32];
1839aebddd1SJeff Kirsher
184e9c74cd8SIvan Vecera struct be_adapter *adapter;
185e9c74cd8SIvan Vecera struct napi_struct napi;
18610ef9ab4SSathya Perla u8 idx; /* array index */
187f2f781a7SSathya Perla u8 msix_idx;
188d0b9cec3SSathya Perla u16 spurious_intr;
189d658d98aSPadmanabh Ratnakar cpumask_var_t affinity_mask;
19010ef9ab4SSathya Perla } ____cacheline_aligned_in_smp;
1919aebddd1SJeff Kirsher
1922632bafdSSathya Perla struct be_aic_obj { /* Adaptive interrupt coalescing (AIC) info */
1932632bafdSSathya Perla u32 min_eqd; /* in usecs */
1942632bafdSSathya Perla u32 max_eqd; /* in usecs */
1952632bafdSSathya Perla u32 prev_eqd; /* in usecs */
1962632bafdSSathya Perla u32 et_eqd; /* configured val when aic is off */
1972632bafdSSathya Perla ulong jiffies;
1982632bafdSSathya Perla u64 rx_pkts_prev; /* Used to calculate RX pps */
1992632bafdSSathya Perla u64 tx_reqs_prev; /* Used to calculate TX pps */
2002632bafdSSathya Perla };
2012632bafdSSathya Perla
2029aebddd1SJeff Kirsher struct be_mcc_obj {
2039aebddd1SJeff Kirsher struct be_queue_info q;
2049aebddd1SJeff Kirsher struct be_queue_info cq;
2059aebddd1SJeff Kirsher bool rearm_cq;
2069aebddd1SJeff Kirsher };
2079aebddd1SJeff Kirsher
2089aebddd1SJeff Kirsher struct be_tx_stats {
2099aebddd1SJeff Kirsher u64 tx_bytes;
2109aebddd1SJeff Kirsher u64 tx_pkts;
2118670f2a5SSriharsha Basavapatna u64 tx_vxlan_offload_pkts;
2129aebddd1SJeff Kirsher u64 tx_reqs;
2139aebddd1SJeff Kirsher u64 tx_compl;
2149aebddd1SJeff Kirsher u32 tx_stops;
215bc617526SSathya Perla u32 tx_drv_drops; /* pkts dropped by driver */
216512bb8a2SKalesh AP /* the error counters are described in be_ethtool.c */
217512bb8a2SKalesh AP u32 tx_hdr_parse_err;
218512bb8a2SKalesh AP u32 tx_dma_err;
219512bb8a2SKalesh AP u32 tx_tso_err;
220512bb8a2SKalesh AP u32 tx_spoof_check_err;
221512bb8a2SKalesh AP u32 tx_qinq_err;
222512bb8a2SKalesh AP u32 tx_internal_parity_err;
223ffc39620SSuresh Reddy u32 tx_sge_err;
2249aebddd1SJeff Kirsher struct u64_stats_sync sync;
2259aebddd1SJeff Kirsher struct u64_stats_sync sync_compl;
2269aebddd1SJeff Kirsher };
2279aebddd1SJeff Kirsher
228152ffe5bSSriharsha Basavapatna /* Structure to hold some data of interest obtained from a TX CQE */
229152ffe5bSSriharsha Basavapatna struct be_tx_compl_info {
230152ffe5bSSriharsha Basavapatna u8 status; /* Completion status */
231152ffe5bSSriharsha Basavapatna u16 end_index; /* Completed TXQ Index */
232152ffe5bSSriharsha Basavapatna };
233152ffe5bSSriharsha Basavapatna
2349aebddd1SJeff Kirsher struct be_tx_obj {
23594d73aaaSVasundhara Volam u32 db_offset;
236646d2c10SIvan Vecera struct be_tx_compl_info txcp;
2379aebddd1SJeff Kirsher struct be_queue_info q;
2389aebddd1SJeff Kirsher struct be_queue_info cq;
2399aebddd1SJeff Kirsher /* Remember the skbs that were transmitted */
2409aebddd1SJeff Kirsher struct sk_buff *sent_skb_list[TX_Q_LEN];
2419aebddd1SJeff Kirsher struct be_tx_stats stats;
2425f07b3c5SSathya Perla u16 pend_wrb_cnt; /* Number of WRBs yet to be given to HW */
2435f07b3c5SSathya Perla u16 last_req_wrb_cnt; /* wrb cnt of the last req in the Q */
2445f07b3c5SSathya Perla u16 last_req_hdr; /* index of the last req's hdr-wrb */
24510ef9ab4SSathya Perla } ____cacheline_aligned_in_smp;
2469aebddd1SJeff Kirsher
2479aebddd1SJeff Kirsher /* Struct to remember the pages posted for rx frags */
2489aebddd1SJeff Kirsher struct be_rx_page_info {
2499aebddd1SJeff Kirsher struct page *page;
250e50287beSSathya Perla /* set to page-addr for last frag of the page & frag-addr otherwise */
2519aebddd1SJeff Kirsher DEFINE_DMA_UNMAP_ADDR(bus);
2529aebddd1SJeff Kirsher u16 page_offset;
253e50287beSSathya Perla bool last_frag; /* last frag of the page */
2549aebddd1SJeff Kirsher };
2559aebddd1SJeff Kirsher
2569aebddd1SJeff Kirsher struct be_rx_stats {
2579aebddd1SJeff Kirsher u64 rx_bytes;
2589aebddd1SJeff Kirsher u64 rx_pkts;
2598670f2a5SSriharsha Basavapatna u64 rx_vxlan_offload_pkts;
2609aebddd1SJeff Kirsher u32 rx_drops_no_skbs; /* skb allocation errors */
2619aebddd1SJeff Kirsher u32 rx_drops_no_frags; /* HW has no fetched frags */
2629aebddd1SJeff Kirsher u32 rx_post_fail; /* page post alloc failures */
2639aebddd1SJeff Kirsher u32 rx_compl;
2649aebddd1SJeff Kirsher u32 rx_mcast_pkts;
2659aebddd1SJeff Kirsher u32 rx_compl_err; /* completions with err set */
2669aebddd1SJeff Kirsher struct u64_stats_sync sync;
2679aebddd1SJeff Kirsher };
2689aebddd1SJeff Kirsher
2699aebddd1SJeff Kirsher struct be_rx_compl_info {
2709aebddd1SJeff Kirsher u32 rss_hash;
2719aebddd1SJeff Kirsher u16 vlan_tag;
2729aebddd1SJeff Kirsher u16 pkt_size;
2739aebddd1SJeff Kirsher u16 port;
2749aebddd1SJeff Kirsher u8 vlanf;
2759aebddd1SJeff Kirsher u8 num_rcvd;
2769aebddd1SJeff Kirsher u8 err;
2779aebddd1SJeff Kirsher u8 ipf;
2789aebddd1SJeff Kirsher u8 tcpf;
2799aebddd1SJeff Kirsher u8 udpf;
2809aebddd1SJeff Kirsher u8 ip_csum;
2819aebddd1SJeff Kirsher u8 l4_csum;
2829aebddd1SJeff Kirsher u8 ipv6;
283f93f160bSVasundhara Volam u8 qnq;
2849aebddd1SJeff Kirsher u8 pkt_type;
285e38b1706SSomnath Kotur u8 ip_frag;
286c9c47142SSathya Perla u8 tunneled;
2879aebddd1SJeff Kirsher };
2889aebddd1SJeff Kirsher
2899aebddd1SJeff Kirsher struct be_rx_obj {
2909aebddd1SJeff Kirsher struct be_adapter *adapter;
2919aebddd1SJeff Kirsher struct be_queue_info q;
2929aebddd1SJeff Kirsher struct be_queue_info cq;
2939aebddd1SJeff Kirsher struct be_rx_compl_info rxcp;
2949aebddd1SJeff Kirsher struct be_rx_page_info page_info_tbl[RX_Q_LEN];
2959aebddd1SJeff Kirsher struct be_rx_stats stats;
2969aebddd1SJeff Kirsher u8 rss_id;
2979aebddd1SJeff Kirsher bool rx_post_starved; /* Zero rx frags have been posted to BE */
29810ef9ab4SSathya Perla } ____cacheline_aligned_in_smp;
2999aebddd1SJeff Kirsher
3009aebddd1SJeff Kirsher struct be_drv_stats {
3019aebddd1SJeff Kirsher u32 eth_red_drops;
302d3de1540SVasundhara Volam u32 dma_map_errors;
3039aebddd1SJeff Kirsher u32 rx_drops_no_pbuf;
3049aebddd1SJeff Kirsher u32 rx_drops_no_txpb;
3059aebddd1SJeff Kirsher u32 rx_drops_no_erx_descr;
3069aebddd1SJeff Kirsher u32 rx_drops_no_tpre_descr;
3079aebddd1SJeff Kirsher u32 rx_drops_too_many_frags;
3089aebddd1SJeff Kirsher u32 forwarded_packets;
3099aebddd1SJeff Kirsher u32 rx_drops_mtu;
3109aebddd1SJeff Kirsher u32 rx_crc_errors;
3119aebddd1SJeff Kirsher u32 rx_alignment_symbol_errors;
3129aebddd1SJeff Kirsher u32 rx_pause_frames;
3139aebddd1SJeff Kirsher u32 rx_priority_pause_frames;
3149aebddd1SJeff Kirsher u32 rx_control_frames;
3159aebddd1SJeff Kirsher u32 rx_in_range_errors;
3169aebddd1SJeff Kirsher u32 rx_out_range_errors;
3179aebddd1SJeff Kirsher u32 rx_frame_too_long;
31818fb06a1SSuresh Reddy u32 rx_address_filtered;
3199aebddd1SJeff Kirsher u32 rx_dropped_too_small;
3209aebddd1SJeff Kirsher u32 rx_dropped_too_short;
3219aebddd1SJeff Kirsher u32 rx_dropped_header_too_small;
3229aebddd1SJeff Kirsher u32 rx_dropped_tcp_length;
3239aebddd1SJeff Kirsher u32 rx_dropped_runt;
3249aebddd1SJeff Kirsher u32 rx_ip_checksum_errs;
3259aebddd1SJeff Kirsher u32 rx_tcp_checksum_errs;
3269aebddd1SJeff Kirsher u32 rx_udp_checksum_errs;
3279aebddd1SJeff Kirsher u32 tx_pauseframes;
3289aebddd1SJeff Kirsher u32 tx_priority_pauseframes;
3299aebddd1SJeff Kirsher u32 tx_controlframes;
3309aebddd1SJeff Kirsher u32 rxpp_fifo_overflow_drop;
3319aebddd1SJeff Kirsher u32 rx_input_fifo_overflow_drop;
3329aebddd1SJeff Kirsher u32 pmem_fifo_overflow_drop;
3339aebddd1SJeff Kirsher u32 jabber_events;
334461ae379SAjit Khaparde u32 rx_roce_bytes_lsd;
335461ae379SAjit Khaparde u32 rx_roce_bytes_msd;
336461ae379SAjit Khaparde u32 rx_roce_frames;
337461ae379SAjit Khaparde u32 roce_drops_payload_len;
338461ae379SAjit Khaparde u32 roce_drops_crc;
3399aebddd1SJeff Kirsher };
3409aebddd1SJeff Kirsher
341c502224eSSomnath Kotur /* A vlan-id of 0xFFFF must be used to clear transparent vlan-tagging */
342c502224eSSomnath Kotur #define BE_RESET_VLAN_TAG_ID 0xFFFF
343c502224eSSomnath Kotur
3449aebddd1SJeff Kirsher struct be_vf_cfg {
34511ac75edSSathya Perla unsigned char mac_addr[ETH_ALEN];
34611ac75edSSathya Perla int if_handle;
34711ac75edSSathya Perla int pmac_id;
34811ac75edSSathya Perla u16 vlan_tag;
34911ac75edSSathya Perla u32 tx_rate;
350bdce2ad7SSuresh Reddy u32 plink_tracking;
351435452aaSVasundhara Volam u32 privileges;
352e7bcbd7bSKalesh AP bool spoofchk;
3539aebddd1SJeff Kirsher };
3549aebddd1SJeff Kirsher
35539f1d94dSSathya Perla enum vf_state {
35639f1d94dSSathya Perla ENABLED = 0,
35739f1d94dSSathya Perla ASSIGNED = 1
35839f1d94dSSathya Perla };
35939f1d94dSSathya Perla
36083b06116SVasundhara Volam #define BE_FLAGS_LINK_STATUS_INIT BIT(1)
36183b06116SVasundhara Volam #define BE_FLAGS_SRIOV_ENABLED BIT(2)
36283b06116SVasundhara Volam #define BE_FLAGS_WORKER_SCHEDULED BIT(3)
36383b06116SVasundhara Volam #define BE_FLAGS_NAPI_ENABLED BIT(6)
36483b06116SVasundhara Volam #define BE_FLAGS_QNQ_ASYNC_EVT_RCVD BIT(7)
36583b06116SVasundhara Volam #define BE_FLAGS_VXLAN_OFFLOADS BIT(8)
36683b06116SVasundhara Volam #define BE_FLAGS_SETUP_DONE BIT(9)
36751d1f98aSAjit Khaparde #define BE_FLAGS_PHY_MISCONFIGURED BIT(10)
368eb7dd46cSSathya Perla #define BE_FLAGS_ERR_DETECTION_SCHEDULED BIT(11)
369760c295eSVenkata Duvvuru #define BE_FLAGS_OS2BMC BIT(12)
370710f3e59SSriharsha Basavapatna #define BE_FLAGS_TRY_RECOVERY BIT(13)
371c9c47142SSathya Perla
372fbc13f01SAjit Khaparde #define BE_UC_PMAC_COUNT 30
373fbc13f01SAjit Khaparde #define BE_VF_UC_PMAC_COUNT 2
374f0613380SKalesh AP
375972f37b4SPadmanabh Ratnakar #define MAX_ERR_RECOVERY_RETRY_COUNT 3
376972f37b4SPadmanabh Ratnakar #define ERR_DETECTION_DELAY 1000
377972f37b4SPadmanabh Ratnakar
3785c510811SSomnath Kotur /* Ethtool set_dump flags */
3795c510811SSomnath Kotur #define LANCER_INITIATE_FW_DUMP 0x1
380f0613380SKalesh AP #define LANCER_DELETE_FW_DUMP 0x2
3815c510811SSomnath Kotur
38242f11cf2SAjit Khaparde struct phy_info {
38321252377SVasundhara Volam /* From SFF-8472 spec */
38421252377SVasundhara Volam #define SFP_VENDOR_NAME_LEN 17
38542f11cf2SAjit Khaparde u8 transceiver;
38642f11cf2SAjit Khaparde u8 autoneg;
38742f11cf2SAjit Khaparde u8 fc_autoneg;
38842f11cf2SAjit Khaparde u8 port_type;
38942f11cf2SAjit Khaparde u16 phy_type;
39042f11cf2SAjit Khaparde u16 interface_type;
39142f11cf2SAjit Khaparde u32 misc_params;
39242f11cf2SAjit Khaparde u16 auto_speeds_supported;
39342f11cf2SAjit Khaparde u16 fixed_speeds_supported;
39442f11cf2SAjit Khaparde int link_speed;
39542f11cf2SAjit Khaparde u32 advertising;
39642f11cf2SAjit Khaparde u32 supported;
3976809cee0SRavikumar Nelavelli u8 cable_type;
39821252377SVasundhara Volam u8 vendor_name[SFP_VENDOR_NAME_LEN];
39921252377SVasundhara Volam u8 vendor_pn[SFP_VENDOR_NAME_LEN];
40042f11cf2SAjit Khaparde };
40142f11cf2SAjit Khaparde
40292bf14abSSathya Perla struct be_resources {
40392bf14abSSathya Perla u16 max_vfs; /* Total VFs "really" supported by FW/HW */
40492bf14abSSathya Perla u16 max_mcast_mac;
40592bf14abSSathya Perla u16 max_tx_qs;
40692bf14abSSathya Perla u16 max_rss_qs;
40792bf14abSSathya Perla u16 max_rx_qs;
408f2858738SVasundhara Volam u16 max_cq_count;
40992bf14abSSathya Perla u16 max_uc_mac; /* Max UC MACs programmable */
41092bf14abSSathya Perla u16 max_vlans; /* Number of vlans supported */
411f2858738SVasundhara Volam u16 max_iface_count;
412f2858738SVasundhara Volam u16 max_mcc_count;
41392bf14abSSathya Perla u16 max_evt_qs;
414ce7faf0aSSathya Perla u16 max_nic_evt_qs; /* NIC's share of evt qs */
41592bf14abSSathya Perla u32 if_cap_flags;
41610cccf60SVasundhara Volam u32 vf_if_cap_flags; /* VF if capability flags */
417b9263cbfSSuresh Reddy u32 flags;
418de2b1e03SSomnath Kotur /* Calculated PF Pool's share of RSS Tables. This is not enforced by
419de2b1e03SSomnath Kotur * the FW, but is a self-imposed driver limitation.
420de2b1e03SSomnath Kotur */
421de2b1e03SSomnath Kotur u16 max_rss_tables;
422de2b1e03SSomnath Kotur };
423de2b1e03SSomnath Kotur
424de2b1e03SSomnath Kotur /* These are port-wide values */
425de2b1e03SSomnath Kotur struct be_port_resources {
426de2b1e03SSomnath Kotur u16 max_vfs;
427de2b1e03SSomnath Kotur u16 nic_pfs;
42892bf14abSSathya Perla };
42992bf14abSSathya Perla
430760c295eSVenkata Duvvuru #define be_is_os2bmc_enabled(adapter) (adapter->flags & BE_FLAGS_OS2BMC)
431760c295eSVenkata Duvvuru
432e2557877SVenkata Duvvuru struct rss_info {
433e2557877SVenkata Duvvuru u8 rsstable[RSS_INDIR_TABLE_LEN];
434e2557877SVenkata Duvvuru u8 rss_queue[RSS_INDIR_TABLE_LEN];
435e2557877SVenkata Duvvuru u8 rss_hkey[RSS_HASH_KEY_LEN];
43628ace84bSIvan Vecera u64 rss_flags;
437e2557877SVenkata Duvvuru };
438e2557877SVenkata Duvvuru
43929e9122bSVenkata Duvvuru #define BE_INVALID_DIE_TEMP 0xFF
44029e9122bSVenkata Duvvuru struct be_hwmon {
44129e9122bSVenkata Duvvuru struct device *hwmon_dev;
44229e9122bSVenkata Duvvuru u8 be_on_die_temp; /* Unit: millidegree Celsius */
44329e9122bSVenkata Duvvuru };
44429e9122bSVenkata Duvvuru
445804abcdbSSriharsha Basavapatna /* Macros to read/write the 'features' word of be_wrb_params structure.
446804abcdbSSriharsha Basavapatna */
447804abcdbSSriharsha Basavapatna #define BE_WRB_F_BIT(name) BE_WRB_F_##name##_BIT
448804abcdbSSriharsha Basavapatna #define BE_WRB_F_MASK(name) BIT_MASK(BE_WRB_F_##name##_BIT)
449804abcdbSSriharsha Basavapatna
450804abcdbSSriharsha Basavapatna #define BE_WRB_F_GET(word, name) \
451804abcdbSSriharsha Basavapatna (((word) & (BE_WRB_F_MASK(name))) >> BE_WRB_F_BIT(name))
452804abcdbSSriharsha Basavapatna
453804abcdbSSriharsha Basavapatna #define BE_WRB_F_SET(word, name, val) \
454804abcdbSSriharsha Basavapatna ((word) |= (((val) << BE_WRB_F_BIT(name)) & BE_WRB_F_MASK(name)))
455804abcdbSSriharsha Basavapatna
456804abcdbSSriharsha Basavapatna /* Feature/offload bits */
457804abcdbSSriharsha Basavapatna enum {
458804abcdbSSriharsha Basavapatna BE_WRB_F_CRC_BIT, /* Ethernet CRC */
459804abcdbSSriharsha Basavapatna BE_WRB_F_IPCS_BIT, /* IP csum */
460804abcdbSSriharsha Basavapatna BE_WRB_F_TCPCS_BIT, /* TCP csum */
461804abcdbSSriharsha Basavapatna BE_WRB_F_UDPCS_BIT, /* UDP csum */
462804abcdbSSriharsha Basavapatna BE_WRB_F_LSO_BIT, /* LSO */
463804abcdbSSriharsha Basavapatna BE_WRB_F_LSO6_BIT, /* LSO6 */
464804abcdbSSriharsha Basavapatna BE_WRB_F_VLAN_BIT, /* VLAN */
465760c295eSVenkata Duvvuru BE_WRB_F_VLAN_SKIP_HW_BIT, /* Skip VLAN tag (workaround) */
466760c295eSVenkata Duvvuru BE_WRB_F_OS2BMC_BIT /* Send packet to the management ring */
467804abcdbSSriharsha Basavapatna };
468804abcdbSSriharsha Basavapatna
469804abcdbSSriharsha Basavapatna /* The structure below provides a HW-agnostic abstraction of WRB params
470804abcdbSSriharsha Basavapatna * retrieved from a TX skb. This is in turn passed to chip specific routines
471804abcdbSSriharsha Basavapatna * during transmit, to set the corresponding params in the WRB.
472804abcdbSSriharsha Basavapatna */
473804abcdbSSriharsha Basavapatna struct be_wrb_params {
474804abcdbSSriharsha Basavapatna u32 features; /* Feature bits */
475804abcdbSSriharsha Basavapatna u16 vlan_tag; /* VLAN tag */
476804abcdbSSriharsha Basavapatna u16 lso_mss; /* MSS for LSO */
477804abcdbSSriharsha Basavapatna };
478804abcdbSSriharsha Basavapatna
479b7172414SSathya Perla struct be_eth_addr {
480b7172414SSathya Perla unsigned char mac[ETH_ALEN];
481b7172414SSathya Perla };
482b7172414SSathya Perla
483710f3e59SSriharsha Basavapatna #define BE_SEC 1000 /* in msec */
484710f3e59SSriharsha Basavapatna #define BE_MIN (60 * BE_SEC) /* in msec */
485710f3e59SSriharsha Basavapatna #define BE_HOUR (60 * BE_MIN) /* in msec */
486710f3e59SSriharsha Basavapatna
487710f3e59SSriharsha Basavapatna #define ERR_RECOVERY_MAX_RETRY_COUNT 3
488710f3e59SSriharsha Basavapatna #define ERR_RECOVERY_DETECTION_DELAY BE_SEC
489710f3e59SSriharsha Basavapatna #define ERR_RECOVERY_RETRY_DELAY (30 * BE_SEC)
490710f3e59SSriharsha Basavapatna
491710f3e59SSriharsha Basavapatna /* UE-detection-duration in BEx/Skyhawk:
492710f3e59SSriharsha Basavapatna * All PFs must wait for this duration after they detect UE before reading
493710f3e59SSriharsha Basavapatna * SLIPORT_SEMAPHORE register. At the end of this duration, the Firmware
494710f3e59SSriharsha Basavapatna * guarantees that the SLIPORT_SEMAPHORE register is updated to indicate
495710f3e59SSriharsha Basavapatna * if the UE is recoverable.
496710f3e59SSriharsha Basavapatna */
497710f3e59SSriharsha Basavapatna #define ERR_RECOVERY_UE_DETECT_DURATION BE_SEC
498710f3e59SSriharsha Basavapatna
499710f3e59SSriharsha Basavapatna /* Initial idle time (in msec) to elapse after driver load,
500710f3e59SSriharsha Basavapatna * before UE recovery is allowed.
501710f3e59SSriharsha Basavapatna */
502710f3e59SSriharsha Basavapatna #define ERR_IDLE_HR 24
503710f3e59SSriharsha Basavapatna #define ERR_RECOVERY_IDLE_TIME (ERR_IDLE_HR * BE_HOUR)
504710f3e59SSriharsha Basavapatna
505710f3e59SSriharsha Basavapatna /* Time interval (in msec) after which UE recovery can be repeated */
506710f3e59SSriharsha Basavapatna #define ERR_INTERVAL_HR 72
507710f3e59SSriharsha Basavapatna #define ERR_RECOVERY_INTERVAL (ERR_INTERVAL_HR * BE_HOUR)
508710f3e59SSriharsha Basavapatna
509710f3e59SSriharsha Basavapatna /* BEx/SH UE recovery state machine */
510710f3e59SSriharsha Basavapatna enum {
511710f3e59SSriharsha Basavapatna ERR_RECOVERY_ST_NONE = 0, /* No Recovery */
512710f3e59SSriharsha Basavapatna ERR_RECOVERY_ST_DETECT = 1, /* UE detection duration */
513710f3e59SSriharsha Basavapatna ERR_RECOVERY_ST_RESET = 2, /* Reset Phase (PF0 only) */
514710f3e59SSriharsha Basavapatna ERR_RECOVERY_ST_PRE_POLL = 3, /* Pre-Poll Phase (all PFs) */
515710f3e59SSriharsha Basavapatna ERR_RECOVERY_ST_REINIT = 4 /* Re-initialize Phase */
516710f3e59SSriharsha Basavapatna };
517710f3e59SSriharsha Basavapatna
518710f3e59SSriharsha Basavapatna struct be_error_recovery {
51903d231a9SIvan Vecera union {
52003d231a9SIvan Vecera u8 recovery_retries; /* used for Lancer */
52103d231a9SIvan Vecera u8 recovery_state; /* used for BEx and Skyhawk */
52203d231a9SIvan Vecera };
523710f3e59SSriharsha Basavapatna
524710f3e59SSriharsha Basavapatna /* BEx/Skyhawk error recovery variables */
52503d231a9SIvan Vecera bool recovery_supported;
526710f3e59SSriharsha Basavapatna u16 ue_to_reset_time; /* Time after UE, to soft reset
527710f3e59SSriharsha Basavapatna * the chip - PF0 only
528710f3e59SSriharsha Basavapatna */
529710f3e59SSriharsha Basavapatna u16 ue_to_poll_time; /* Time after UE, to Restart Polling
530710f3e59SSriharsha Basavapatna * of SLIPORT_SEMAPHORE reg
531710f3e59SSriharsha Basavapatna */
532710f3e59SSriharsha Basavapatna u16 last_err_code;
533710f3e59SSriharsha Basavapatna unsigned long probe_time;
534710f3e59SSriharsha Basavapatna unsigned long last_recovery_time;
535710f3e59SSriharsha Basavapatna
536710f3e59SSriharsha Basavapatna /* Common to both Lancer & BEx/SH error recovery */
537710f3e59SSriharsha Basavapatna u32 resched_delay;
538710f3e59SSriharsha Basavapatna struct delayed_work err_detection_work;
539710f3e59SSriharsha Basavapatna };
540710f3e59SSriharsha Basavapatna
541710f3e59SSriharsha Basavapatna /* Ethtool priv_flags */
542710f3e59SSriharsha Basavapatna #define BE_DISABLE_TPE_RECOVERY 0x1
543710f3e59SSriharsha Basavapatna
544bf8d9dfbSSriharsha Basavapatna struct be_vxlan_port {
545bf8d9dfbSSriharsha Basavapatna struct list_head list;
546bf8d9dfbSSriharsha Basavapatna __be16 port; /* VxLAN UDP dst port */
547bf8d9dfbSSriharsha Basavapatna int port_aliases; /* alias count */
548bf8d9dfbSSriharsha Basavapatna };
549bf8d9dfbSSriharsha Basavapatna
5509aebddd1SJeff Kirsher struct be_adapter {
5519aebddd1SJeff Kirsher struct pci_dev *pdev;
5529aebddd1SJeff Kirsher struct net_device *netdev;
5539aebddd1SJeff Kirsher
554c5b3ad4cSSathya Perla u8 __iomem *csr; /* CSR BAR used only for BE2/3 */
5559aebddd1SJeff Kirsher u8 __iomem *db; /* Door Bell */
55625848c90SSuresh Reddy u8 __iomem *pcicfg; /* On SH,BEx only. Shadow of PCI config space */
5579aebddd1SJeff Kirsher
5589aebddd1SJeff Kirsher struct mutex mbox_lock; /* For serializing mbox cmds to BE card */
5599aebddd1SJeff Kirsher struct be_dma_mem mbox_mem;
5609aebddd1SJeff Kirsher /* Mbox mem is adjusted to align to 16 bytes. The allocated addr
5619aebddd1SJeff Kirsher * is stored for freeing purpose */
5629aebddd1SJeff Kirsher struct be_dma_mem mbox_mem_alloced;
5639aebddd1SJeff Kirsher
5649aebddd1SJeff Kirsher struct be_mcc_obj mcc_obj;
565b7172414SSathya Perla struct mutex mcc_lock; /* For serializing mcc cmds to BE card */
5669aebddd1SJeff Kirsher spinlock_t mcc_cq_lock;
5679aebddd1SJeff Kirsher
568e261768eSSathya Perla u16 cfg_num_rx_irqs; /* configured via set-channels */
569e261768eSSathya Perla u16 cfg_num_tx_irqs; /* configured via set-channels */
57092bf14abSSathya Perla u16 num_evt_qs;
57192bf14abSSathya Perla u16 num_msix_vec;
57292bf14abSSathya Perla struct be_eq_obj eq_obj[MAX_EVT_QS];
57310ef9ab4SSathya Perla struct msix_entry msix_entries[MAX_MSIX_VECTORS];
5749aebddd1SJeff Kirsher bool isr_registered;
5759aebddd1SJeff Kirsher
5769aebddd1SJeff Kirsher /* TX Rings */
57792bf14abSSathya Perla u16 num_tx_qs;
5789aebddd1SJeff Kirsher struct be_tx_obj tx_obj[MAX_TX_QS];
5799aebddd1SJeff Kirsher
5809aebddd1SJeff Kirsher /* Rx rings */
58192bf14abSSathya Perla u16 num_rx_qs;
58271bb8bd0SVasundhara Volam u16 num_rss_qs;
58371bb8bd0SVasundhara Volam u16 need_def_rxq;
58410ef9ab4SSathya Perla struct be_rx_obj rx_obj[MAX_RX_QS];
5859aebddd1SJeff Kirsher u32 big_page_size; /* Compounded page size shared by rx wrbs */
5869aebddd1SJeff Kirsher
5879aebddd1SJeff Kirsher struct be_drv_stats drv_stats;
5882632bafdSSathya Perla struct be_aic_obj aic_obj[MAX_EVT_QS];
5899041f047SIvan Vecera bool aic_enabled;
5909aebddd1SJeff Kirsher u8 vlan_prio_bmap; /* Available Priority BitMap */
591fdf81bfbSSathya Perla u16 recommended_prio_bits;/* Recommended Priority bits in vlan tag */
5929aebddd1SJeff Kirsher struct be_dma_mem rx_filter; /* Cmd DMA mem for rx-filter */
5939aebddd1SJeff Kirsher
5949aebddd1SJeff Kirsher struct be_dma_mem stats_cmd;
5959aebddd1SJeff Kirsher /* Work queue used to perform periodic tasks like getting statistics */
5969aebddd1SJeff Kirsher struct delayed_work work;
5979aebddd1SJeff Kirsher u16 work_counter;
5989aebddd1SJeff Kirsher
599972f37b4SPadmanabh Ratnakar u8 recovery_retries;
600954f6825SVenkata Duvvuru u8 err_flags;
601a69bf3c5SDouglas Miller bool pcicfg_mapped; /* pcicfg obtained via pci_iomap() */
602b236916aSAjit Khaparde u32 flags;
603f25b119cSPadmanabh Ratnakar u32 cmd_privileges;
6049aebddd1SJeff Kirsher /* Ethtool knobs and info */
6059aebddd1SJeff Kirsher char fw_ver[FW_VER_LEN];
606eeb65cedSSomnath Kotur char fw_on_flash[FW_VER_LEN];
607f66b7cfdSSathya Perla
608f66b7cfdSSathya Perla /* IFACE filtering fields */
60930128031SSathya Perla int if_handle; /* Used to configure filtering */
610f66b7cfdSSathya Perla u32 if_flags; /* Interface filtering flags */
611fbc13f01SAjit Khaparde u32 *pmac_id; /* MAC addr handle used by BE card */
612b7172414SSathya Perla struct be_eth_addr *uc_list;/* list of uc-addrs programmed (not perm) */
613f66b7cfdSSathya Perla u32 uc_macs; /* Count of secondary UC MAC programmed */
614b7172414SSathya Perla struct be_eth_addr *mc_list;/* list of mcast addrs programmed */
615b7172414SSathya Perla u32 mc_count;
616f66b7cfdSSathya Perla unsigned long vids[BITS_TO_LONGS(VLAN_N_VID)];
617f66b7cfdSSathya Perla u16 vlans_added;
61892fbb1dfSSriharsha Basavapatna bool update_uc_list;
61992fbb1dfSSriharsha Basavapatna bool update_mc_list;
620b7172414SSathya Perla struct mutex rx_filter_lock;/* For protecting vids[] & mc/uc_list[] */
621f66b7cfdSSathya Perla
6229aebddd1SJeff Kirsher u32 beacon_state; /* for set_phys_id */
6239aebddd1SJeff Kirsher
6249aebddd1SJeff Kirsher u32 port_num;
62521252377SVasundhara Volam char port_name;
626f93f160bSVasundhara Volam u8 mc_type;
6279aebddd1SJeff Kirsher u32 function_mode;
6289aebddd1SJeff Kirsher u32 function_caps;
6299aebddd1SJeff Kirsher u32 rx_fc; /* Rx flow control */
6309aebddd1SJeff Kirsher u32 tx_fc; /* Tx flow control */
6319aebddd1SJeff Kirsher bool stats_cmd_sent;
632045508a8SParav Pandit struct {
633045508a8SParav Pandit u32 size;
634045508a8SParav Pandit u32 total_size;
635045508a8SParav Pandit u64 io_addr;
636045508a8SParav Pandit } roce_db;
637045508a8SParav Pandit u32 num_msix_roce_vec;
638045508a8SParav Pandit struct ocrdma_dev *ocrdma_dev;
639045508a8SParav Pandit struct list_head entry;
640045508a8SParav Pandit
6419aebddd1SJeff Kirsher u32 flash_status;
6425eeff635SSuresh Reddy struct completion et_cmd_compl;
6439aebddd1SJeff Kirsher
644bec84e6bSVasundhara Volam struct be_resources pool_res; /* resources available for the port */
64592bf14abSSathya Perla struct be_resources res; /* resources available for the func */
64692bf14abSSathya Perla u16 num_vfs; /* Number of VFs provisioned by PF */
647980df249SSuresh Reddy u8 pf_num; /* Numbering used by FW, starts at 0 */
648980df249SSuresh Reddy u8 vf_num; /* Numbering used by FW, starts at 1 */
64939f1d94dSSathya Perla u8 virtfn;
65011ac75edSSathya Perla struct be_vf_cfg *vf_cfg;
65111ac75edSSathya Perla bool be3_native;
6529aebddd1SJeff Kirsher u32 sli_family;
6539aebddd1SJeff Kirsher u8 hba_port_num;
6549aebddd1SJeff Kirsher u16 pvid;
655bf8d9dfbSSriharsha Basavapatna __be16 vxlan_port; /* offloaded vxlan port num */
65642f11cf2SAjit Khaparde struct phy_info phy;
6574762f6ceSAjit Khaparde u8 wol_cap;
65876a9e08eSSuresh Reddy bool wol_en;
6590ad3157eSVasundhara Volam u16 asic_rev;
660bc0c3405SAjit Khaparde u16 qnq_vid;
661941a77d5SSomnath Kotur u32 msg_enable;
6627aeb2156SPadmanabh Ratnakar int be_get_temp_freq;
66329e9122bSVenkata Duvvuru struct be_hwmon hwmon_info;
664e2557877SVenkata Duvvuru struct rss_info rss_info;
665760c295eSVenkata Duvvuru /* Filters for packets that need to be sent to BMC */
666760c295eSVenkata Duvvuru u32 bmc_filt_mask;
667fd7ff6f0SVenkat Duvvuru u32 fat_dump_len;
668a155a5dbSSriharsha Basavapatna u16 serial_num[CNTL_SERIAL_NUM_WORDS];
66951d1f98aSAjit Khaparde u8 phy_state; /* state of sfp optics (functional, faulted, etc.,) */
670c27ebf58SSuresh Reddy u8 dev_mac[ETH_ALEN];
671710f3e59SSriharsha Basavapatna u32 priv_flags; /* ethtool get/set_priv_flags() */
672710f3e59SSriharsha Basavapatna struct be_error_recovery error_recovery;
6739aebddd1SJeff Kirsher };
6749aebddd1SJeff Kirsher
675b7172414SSathya Perla /* Used for defered FW config cmds. Add fields to this struct as reqd */
676b7172414SSathya Perla struct be_cmd_work {
677b7172414SSathya Perla struct work_struct work;
678b7172414SSathya Perla struct be_adapter *adapter;
679b7172414SSathya Perla };
680b7172414SSathya Perla
68139f1d94dSSathya Perla #define be_physfn(adapter) (!adapter->virtfn)
6822c7a9dc1SAjit Khaparde #define be_virtfn(adapter) (adapter->virtfn)
683f174c7ecSVasundhara Volam #define sriov_enabled(adapter) (adapter->flags & \
684f174c7ecSVasundhara Volam BE_FLAGS_SRIOV_ENABLED)
685bec84e6bSVasundhara Volam
68611ac75edSSathya Perla #define for_all_vfs(adapter, vf_cfg, i) \
68711ac75edSSathya Perla for (i = 0, vf_cfg = &adapter->vf_cfg[i]; i < adapter->num_vfs; \
68811ac75edSSathya Perla i++, vf_cfg++)
6899aebddd1SJeff Kirsher
6909aebddd1SJeff Kirsher #define ON 1
6919aebddd1SJeff Kirsher #define OFF 0
692ca34fe38SSathya Perla
69392bf14abSSathya Perla #define be_max_vlans(adapter) (adapter->res.max_vlans)
69492bf14abSSathya Perla #define be_max_uc(adapter) (adapter->res.max_uc_mac)
69592bf14abSSathya Perla #define be_max_mc(adapter) (adapter->res.max_mcast_mac)
696bec84e6bSVasundhara Volam #define be_max_vfs(adapter) (adapter->pool_res.max_vfs)
69792bf14abSSathya Perla #define be_max_rss(adapter) (adapter->res.max_rss_qs)
69892bf14abSSathya Perla #define be_max_txqs(adapter) (adapter->res.max_tx_qs)
69992bf14abSSathya Perla #define be_max_prio_txqs(adapter) (adapter->res.max_prio_tx_qs)
70092bf14abSSathya Perla #define be_max_rxqs(adapter) (adapter->res.max_rx_qs)
701ce7faf0aSSathya Perla /* Max number of EQs available for the function (NIC + RoCE (if enabled)) */
702ce7faf0aSSathya Perla #define be_max_func_eqs(adapter) (adapter->res.max_evt_qs)
703ce7faf0aSSathya Perla /* Max number of EQs available avaialble only for NIC */
704ce7faf0aSSathya Perla #define be_max_nic_eqs(adapter) (adapter->res.max_nic_evt_qs)
70592bf14abSSathya Perla #define be_if_cap_flags(adapter) (adapter->res.if_cap_flags)
706de2b1e03SSomnath Kotur #define be_max_pf_pool_rss_tables(adapter) \
707de2b1e03SSomnath Kotur (adapter->pool_res.max_rss_tables)
708e261768eSSathya Perla /* Max irqs avaialble for NIC */
709e261768eSSathya Perla #define be_max_irqs(adapter) \
710e261768eSSathya Perla (min_t(u16, be_max_nic_eqs(adapter), num_online_cpus()))
71192bf14abSSathya Perla
712e261768eSSathya Perla /* Max irqs *needed* for RX queues */
be_max_rx_irqs(struct be_adapter * adapter)713e261768eSSathya Perla static inline u16 be_max_rx_irqs(struct be_adapter *adapter)
71492bf14abSSathya Perla {
715e261768eSSathya Perla /* If no RSS, need atleast one irq for def-RXQ */
71692bf14abSSathya Perla u16 num = max_t(u16, be_max_rss(adapter), 1);
71792bf14abSSathya Perla
718e261768eSSathya Perla return min_t(u16, num, be_max_irqs(adapter));
719e261768eSSathya Perla }
720e261768eSSathya Perla
721e261768eSSathya Perla /* Max irqs *needed* for TX queues */
be_max_tx_irqs(struct be_adapter * adapter)722e261768eSSathya Perla static inline u16 be_max_tx_irqs(struct be_adapter *adapter)
723e261768eSSathya Perla {
724e261768eSSathya Perla return min_t(u16, be_max_txqs(adapter), be_max_irqs(adapter));
725e261768eSSathya Perla }
726e261768eSSathya Perla
727e261768eSSathya Perla /* Max irqs *needed* for combined queues */
be_max_qp_irqs(struct be_adapter * adapter)728e261768eSSathya Perla static inline u16 be_max_qp_irqs(struct be_adapter *adapter)
729e261768eSSathya Perla {
730e261768eSSathya Perla return min(be_max_tx_irqs(adapter), be_max_rx_irqs(adapter));
731e261768eSSathya Perla }
732e261768eSSathya Perla
733e261768eSSathya Perla /* Max irqs *needed* for RX and TX queues together */
be_max_any_irqs(struct be_adapter * adapter)734e261768eSSathya Perla static inline u16 be_max_any_irqs(struct be_adapter *adapter)
735e261768eSSathya Perla {
736e261768eSSathya Perla return max(be_max_tx_irqs(adapter), be_max_rx_irqs(adapter));
73792bf14abSSathya Perla }
73892bf14abSSathya Perla
739f93f160bSVasundhara Volam /* Is BE in pvid_tagging mode */
740f93f160bSVasundhara Volam #define be_pvid_tagging_enabled(adapter) (adapter->pvid)
741f93f160bSVasundhara Volam
742f93f160bSVasundhara Volam /* Is BE in QNQ multi-channel mode */
74366064dbcSSuresh Reddy #define be_is_qnq_mode(adapter) (adapter->function_mode & QNQ_MODE)
744f93f160bSVasundhara Volam
74598471b5bSPetr Oros #ifdef CONFIG_BE2NET_LANCER
746ca34fe38SSathya Perla #define lancer_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID3 || \
747ca34fe38SSathya Perla adapter->pdev->device == OC_DEVICE_ID4)
74898471b5bSPetr Oros #else
74998471b5bSPetr Oros #define lancer_chip(adapter) (0)
75098471b5bSPetr Oros #endif /* CONFIG_BE2NET_LANCER */
7519aebddd1SJeff Kirsher
75298471b5bSPetr Oros #ifdef CONFIG_BE2NET_SKYHAWK
75376b73530SPadmanabh Ratnakar #define skyhawk_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID5 || \
75476b73530SPadmanabh Ratnakar adapter->pdev->device == OC_DEVICE_ID6)
75598471b5bSPetr Oros #else
75698471b5bSPetr Oros #define skyhawk_chip(adapter) (0)
75798471b5bSPetr Oros #endif /* CONFIG_BE2NET_SKYHAWK */
758d3bd3a5eSPadmanabh Ratnakar
75998471b5bSPetr Oros #ifdef CONFIG_BE2NET_BE3
760ca34fe38SSathya Perla #define BE3_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID2 || \
761ca34fe38SSathya Perla adapter->pdev->device == OC_DEVICE_ID2)
76298471b5bSPetr Oros #else
76398471b5bSPetr Oros #define BE3_chip(adapter) (0)
76498471b5bSPetr Oros #endif /* CONFIG_BE2NET_BE3 */
765ca34fe38SSathya Perla
76698471b5bSPetr Oros #ifdef CONFIG_BE2NET_BE2
767ca34fe38SSathya Perla #define BE2_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID1 || \
768ca34fe38SSathya Perla adapter->pdev->device == OC_DEVICE_ID1)
76998471b5bSPetr Oros #else
77098471b5bSPetr Oros #define BE2_chip(adapter) (0)
77198471b5bSPetr Oros #endif /* CONFIG_BE2NET_BE2 */
772ca34fe38SSathya Perla
773ca34fe38SSathya Perla #define BEx_chip(adapter) (BE3_chip(adapter) || BE2_chip(adapter))
774d3bd3a5eSPadmanabh Ratnakar
775dbf0f2a7SSathya Perla #define be_roce_supported(adapter) (skyhawk_chip(adapter) && \
776045508a8SParav Pandit (adapter->function_mode & RDMA_ENABLED))
777045508a8SParav Pandit
7789aebddd1SJeff Kirsher extern const struct ethtool_ops be_ethtool_ops;
7799aebddd1SJeff Kirsher
7809aebddd1SJeff Kirsher #define msix_enabled(adapter) (adapter->num_msix_vec > 0)
78110ef9ab4SSathya Perla #define num_irqs(adapter) (msix_enabled(adapter) ? \
78210ef9ab4SSathya Perla adapter->num_msix_vec : 1)
78310ef9ab4SSathya Perla #define tx_stats(txo) (&(txo)->stats)
78410ef9ab4SSathya Perla #define rx_stats(rxo) (&(rxo)->stats)
7859aebddd1SJeff Kirsher
78610ef9ab4SSathya Perla /* The default RXQ is the last RXQ */
78710ef9ab4SSathya Perla #define default_rxo(adpt) (&adpt->rx_obj[adpt->num_rx_qs - 1])
7889aebddd1SJeff Kirsher
7899aebddd1SJeff Kirsher #define for_all_rx_queues(adapter, rxo, i) \
7909aebddd1SJeff Kirsher for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \
7919aebddd1SJeff Kirsher i++, rxo++)
7929aebddd1SJeff Kirsher
7939aebddd1SJeff Kirsher #define for_all_rss_queues(adapter, rxo, i) \
79471bb8bd0SVasundhara Volam for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rss_qs; \
7959aebddd1SJeff Kirsher i++, rxo++)
7969aebddd1SJeff Kirsher
7979aebddd1SJeff Kirsher #define for_all_tx_queues(adapter, txo, i) \
7989aebddd1SJeff Kirsher for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs; \
7999aebddd1SJeff Kirsher i++, txo++)
8009aebddd1SJeff Kirsher
80110ef9ab4SSathya Perla #define for_all_evt_queues(adapter, eqo, i) \
80210ef9ab4SSathya Perla for (i = 0, eqo = &adapter->eq_obj[i]; i < adapter->num_evt_qs; \
80310ef9ab4SSathya Perla i++, eqo++)
80410ef9ab4SSathya Perla
8056384a4d0SSathya Perla #define for_all_rx_queues_on_eq(adapter, eqo, rxo, i) \
8066384a4d0SSathya Perla for (i = eqo->idx, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs;\
8076384a4d0SSathya Perla i += adapter->num_evt_qs, rxo += adapter->num_evt_qs)
8086384a4d0SSathya Perla
809a4906ea0SSathya Perla #define for_all_tx_queues_on_eq(adapter, eqo, txo, i) \
810a4906ea0SSathya Perla for (i = eqo->idx, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs;\
811a4906ea0SSathya Perla i += adapter->num_evt_qs, txo += adapter->num_evt_qs)
812a4906ea0SSathya Perla
81310ef9ab4SSathya Perla #define is_mcc_eqo(eqo) (eqo->idx == 0)
81410ef9ab4SSathya Perla #define mcc_eqo(adapter) (&adapter->eq_obj[0])
81510ef9ab4SSathya Perla
8169aebddd1SJeff Kirsher #define PAGE_SHIFT_4K 12
8179aebddd1SJeff Kirsher #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
8189aebddd1SJeff Kirsher
8199aebddd1SJeff Kirsher /* Returns number of pages spanned by the data starting at the given addr */
8209aebddd1SJeff Kirsher #define PAGES_4K_SPANNED(_address, size) \
8219aebddd1SJeff Kirsher ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
8229aebddd1SJeff Kirsher (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
8239aebddd1SJeff Kirsher
8249aebddd1SJeff Kirsher /* Returns bit offset within a DWORD of a bitfield */
8259aebddd1SJeff Kirsher #define AMAP_BIT_OFFSET(_struct, field) \
8269aebddd1SJeff Kirsher (((size_t)&(((_struct *)0)->field))%32)
8279aebddd1SJeff Kirsher
8289aebddd1SJeff Kirsher /* Returns the bit mask of the field that is NOT shifted into location. */
amap_mask(u32 bitsize)8299aebddd1SJeff Kirsher static inline u32 amap_mask(u32 bitsize)
8309aebddd1SJeff Kirsher {
8319aebddd1SJeff Kirsher return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
8329aebddd1SJeff Kirsher }
8339aebddd1SJeff Kirsher
8349aebddd1SJeff Kirsher static inline void
amap_set(void * ptr,u32 dw_offset,u32 mask,u32 offset,u32 value)8359aebddd1SJeff Kirsher amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
8369aebddd1SJeff Kirsher {
8379aebddd1SJeff Kirsher u32 *dw = (u32 *) ptr + dw_offset;
8389aebddd1SJeff Kirsher *dw &= ~(mask << offset);
8399aebddd1SJeff Kirsher *dw |= (mask & value) << offset;
8409aebddd1SJeff Kirsher }
8419aebddd1SJeff Kirsher
8429aebddd1SJeff Kirsher #define AMAP_SET_BITS(_struct, field, ptr, val) \
8439aebddd1SJeff Kirsher amap_set(ptr, \
8449aebddd1SJeff Kirsher offsetof(_struct, field)/32, \
8459aebddd1SJeff Kirsher amap_mask(sizeof(((_struct *)0)->field)), \
8469aebddd1SJeff Kirsher AMAP_BIT_OFFSET(_struct, field), \
8479aebddd1SJeff Kirsher val)
8489aebddd1SJeff Kirsher
amap_get(void * ptr,u32 dw_offset,u32 mask,u32 offset)8499aebddd1SJeff Kirsher static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
8509aebddd1SJeff Kirsher {
8519aebddd1SJeff Kirsher u32 *dw = (u32 *) ptr;
8529aebddd1SJeff Kirsher return mask & (*(dw + dw_offset) >> offset);
8539aebddd1SJeff Kirsher }
8549aebddd1SJeff Kirsher
8559aebddd1SJeff Kirsher #define AMAP_GET_BITS(_struct, field, ptr) \
8569aebddd1SJeff Kirsher amap_get(ptr, \
8579aebddd1SJeff Kirsher offsetof(_struct, field)/32, \
8589aebddd1SJeff Kirsher amap_mask(sizeof(((_struct *)0)->field)), \
8599aebddd1SJeff Kirsher AMAP_BIT_OFFSET(_struct, field))
8609aebddd1SJeff Kirsher
861c3c18bc1SSathya Perla #define GET_RX_COMPL_V0_BITS(field, ptr) \
862c3c18bc1SSathya Perla AMAP_GET_BITS(struct amap_eth_rx_compl_v0, field, ptr)
863c3c18bc1SSathya Perla
864c3c18bc1SSathya Perla #define GET_RX_COMPL_V1_BITS(field, ptr) \
865c3c18bc1SSathya Perla AMAP_GET_BITS(struct amap_eth_rx_compl_v1, field, ptr)
866c3c18bc1SSathya Perla
867c3c18bc1SSathya Perla #define GET_TX_COMPL_BITS(field, ptr) \
868c3c18bc1SSathya Perla AMAP_GET_BITS(struct amap_eth_tx_compl, field, ptr)
869c3c18bc1SSathya Perla
870c3c18bc1SSathya Perla #define SET_TX_WRB_HDR_BITS(field, ptr, val) \
871c3c18bc1SSathya Perla AMAP_SET_BITS(struct amap_eth_hdr_wrb, field, ptr, val)
872c3c18bc1SSathya Perla
8739aebddd1SJeff Kirsher #define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len)
8749aebddd1SJeff Kirsher #define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len)
swap_dws(void * wrb,int len)8759aebddd1SJeff Kirsher static inline void swap_dws(void *wrb, int len)
8769aebddd1SJeff Kirsher {
8779aebddd1SJeff Kirsher #ifdef __BIG_ENDIAN
8789aebddd1SJeff Kirsher u32 *dw = wrb;
8799aebddd1SJeff Kirsher BUG_ON(len % 4);
8809aebddd1SJeff Kirsher do {
8819aebddd1SJeff Kirsher *dw = cpu_to_le32(*dw);
8829aebddd1SJeff Kirsher dw++;
8839aebddd1SJeff Kirsher len -= 4;
8849aebddd1SJeff Kirsher } while (len);
8859aebddd1SJeff Kirsher #endif /* __BIG_ENDIAN */
8869aebddd1SJeff Kirsher }
8879aebddd1SJeff Kirsher
8880532d4e3SKalesh AP #define be_cmd_status(status) (status > 0 ? -EIO : status)
8890532d4e3SKalesh AP
is_tcp_pkt(struct sk_buff * skb)8909aebddd1SJeff Kirsher static inline u8 is_tcp_pkt(struct sk_buff *skb)
8919aebddd1SJeff Kirsher {
8929aebddd1SJeff Kirsher u8 val = 0;
8939aebddd1SJeff Kirsher
8949aebddd1SJeff Kirsher if (ip_hdr(skb)->version == 4)
8959aebddd1SJeff Kirsher val = (ip_hdr(skb)->protocol == IPPROTO_TCP);
8969aebddd1SJeff Kirsher else if (ip_hdr(skb)->version == 6)
8979aebddd1SJeff Kirsher val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP);
8989aebddd1SJeff Kirsher
8999aebddd1SJeff Kirsher return val;
9009aebddd1SJeff Kirsher }
9019aebddd1SJeff Kirsher
is_udp_pkt(struct sk_buff * skb)9029aebddd1SJeff Kirsher static inline u8 is_udp_pkt(struct sk_buff *skb)
9039aebddd1SJeff Kirsher {
9049aebddd1SJeff Kirsher u8 val = 0;
9059aebddd1SJeff Kirsher
9069aebddd1SJeff Kirsher if (ip_hdr(skb)->version == 4)
9079aebddd1SJeff Kirsher val = (ip_hdr(skb)->protocol == IPPROTO_UDP);
9089aebddd1SJeff Kirsher else if (ip_hdr(skb)->version == 6)
9099aebddd1SJeff Kirsher val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP);
9109aebddd1SJeff Kirsher
9119aebddd1SJeff Kirsher return val;
9129aebddd1SJeff Kirsher }
9139aebddd1SJeff Kirsher
is_ipv4_pkt(struct sk_buff * skb)91493040ae5SSomnath Kotur static inline bool is_ipv4_pkt(struct sk_buff *skb)
91593040ae5SSomnath Kotur {
916e8efcec5SLi RongQing return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
91793040ae5SSomnath Kotur }
91893040ae5SSomnath Kotur
is_ipv6_ext_hdr(struct sk_buff * skb)919822f8565SSuresh Reddy static inline bool is_ipv6_ext_hdr(struct sk_buff *skb)
920822f8565SSuresh Reddy {
921822f8565SSuresh Reddy if (ip_hdr(skb)->version == 6)
922822f8565SSuresh Reddy return ipv6_ext_hdr(ipv6_hdr(skb)->nexthdr);
923822f8565SSuresh Reddy else
924822f8565SSuresh Reddy return false;
925822f8565SSuresh Reddy }
926822f8565SSuresh Reddy
927710f3e59SSriharsha Basavapatna #define be_error_recovering(adapter) \
928710f3e59SSriharsha Basavapatna (adapter->flags & BE_FLAGS_TRY_RECOVERY)
929710f3e59SSriharsha Basavapatna
930954f6825SVenkata Duvvuru #define BE_ERROR_EEH 1
931954f6825SVenkata Duvvuru #define BE_ERROR_UE BIT(1)
932954f6825SVenkata Duvvuru #define BE_ERROR_FW BIT(2)
933ffc39620SSuresh Reddy #define BE_ERROR_TX BIT(3)
934ffc39620SSuresh Reddy #define BE_ERROR_HW (BE_ERROR_EEH | BE_ERROR_UE | BE_ERROR_TX)
935ffc39620SSuresh Reddy #define BE_ERROR_ANY (BE_ERROR_EEH | BE_ERROR_UE | BE_ERROR_FW | \
936ffc39620SSuresh Reddy BE_ERROR_TX)
937954f6825SVenkata Duvvuru #define BE_CLEAR_ALL 0xFF
938954f6825SVenkata Duvvuru
be_check_error(struct be_adapter * adapter,u32 err_type)939954f6825SVenkata Duvvuru static inline u8 be_check_error(struct be_adapter *adapter, u32 err_type)
940954f6825SVenkata Duvvuru {
941954f6825SVenkata Duvvuru return (adapter->err_flags & err_type);
942954f6825SVenkata Duvvuru }
943954f6825SVenkata Duvvuru
be_set_error(struct be_adapter * adapter,int err_type)944954f6825SVenkata Duvvuru static inline void be_set_error(struct be_adapter *adapter, int err_type)
945954f6825SVenkata Duvvuru {
946954f6825SVenkata Duvvuru struct net_device *netdev = adapter->netdev;
947954f6825SVenkata Duvvuru
948954f6825SVenkata Duvvuru adapter->err_flags |= err_type;
949954f6825SVenkata Duvvuru netif_carrier_off(netdev);
950954f6825SVenkata Duvvuru
951954f6825SVenkata Duvvuru dev_info(&adapter->pdev->dev, "%s: Link down\n", netdev->name);
952954f6825SVenkata Duvvuru }
953954f6825SVenkata Duvvuru
be_clear_error(struct be_adapter * adapter,int err_type)954954f6825SVenkata Duvvuru static inline void be_clear_error(struct be_adapter *adapter, int err_type)
955954f6825SVenkata Duvvuru {
956954f6825SVenkata Duvvuru adapter->err_flags &= ~err_type;
957954f6825SVenkata Duvvuru }
958954f6825SVenkata Duvvuru
be_multi_rxq(const struct be_adapter * adapter)9599aebddd1SJeff Kirsher static inline bool be_multi_rxq(const struct be_adapter *adapter)
9609aebddd1SJeff Kirsher {
9619aebddd1SJeff Kirsher return adapter->num_rx_qs > 1;
9629aebddd1SJeff Kirsher }
9639aebddd1SJeff Kirsher
96431886e87SJoe Perches void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm,
9659aebddd1SJeff Kirsher u16 num_popped);
96631886e87SJoe Perches void be_link_status_update(struct be_adapter *adapter, u8 link_status);
96731886e87SJoe Perches void be_parse_stats(struct be_adapter *adapter);
96831886e87SJoe Perches int be_load_fw(struct be_adapter *adapter, u8 *func);
96931886e87SJoe Perches bool be_is_wol_supported(struct be_adapter *adapter);
97031886e87SJoe Perches bool be_pause_supported(struct be_adapter *adapter);
97131886e87SJoe Perches u32 be_get_fw_log_level(struct be_adapter *adapter);
97268d7bdcbSSathya Perla int be_update_queues(struct be_adapter *adapter);
97368d7bdcbSSathya Perla int be_poll(struct napi_struct *napi, int budget);
97420947770SPadmanabh Ratnakar void be_eqd_update(struct be_adapter *adapter, bool force_update);
975941a77d5SSomnath Kotur
976045508a8SParav Pandit /*
977045508a8SParav Pandit * internal function to initialize-cleanup roce device.
978045508a8SParav Pandit */
97931886e87SJoe Perches void be_roce_dev_add(struct be_adapter *);
98031886e87SJoe Perches void be_roce_dev_remove(struct be_adapter *);
981045508a8SParav Pandit
982045508a8SParav Pandit /*
983045508a8SParav Pandit * internal function to open-close roce device during ifup-ifdown.
984045508a8SParav Pandit */
985d114f99aSDevesh Sharma void be_roce_dev_shutdown(struct be_adapter *);
986045508a8SParav Pandit
9879aebddd1SJeff Kirsher #endif /* BE_H */
988