1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Dave DNET Ethernet Controller driver 4 * 5 * Copyright (C) 2008 Dave S.r.l. <www.dave.eu> 6 */ 7 #ifndef _DNET_H 8 #define _DNET_H 9 10 #define DRV_NAME "dnet" 11 #define PFX DRV_NAME ": " 12 13 /* Register access macros */ 14 #define dnet_writel(port, value, reg) \ 15 writel((value), (port)->regs + DNET_##reg) 16 #define dnet_readl(port, reg) readl((port)->regs + DNET_##reg) 17 18 /* ALL DNET FIFO REGISTERS */ 19 #define DNET_RX_LEN_FIFO 0x000 /* RX_LEN_FIFO */ 20 #define DNET_RX_DATA_FIFO 0x004 /* RX_DATA_FIFO */ 21 #define DNET_TX_LEN_FIFO 0x008 /* TX_LEN_FIFO */ 22 #define DNET_TX_DATA_FIFO 0x00C /* TX_DATA_FIFO */ 23 24 /* ALL DNET CONTROL/STATUS REGISTERS OFFSETS */ 25 #define DNET_VERCAPS 0x100 /* VERCAPS */ 26 #define DNET_INTR_SRC 0x104 /* INTR_SRC */ 27 #define DNET_INTR_ENB 0x108 /* INTR_ENB */ 28 #define DNET_RX_STATUS 0x10C /* RX_STATUS */ 29 #define DNET_TX_STATUS 0x110 /* TX_STATUS */ 30 #define DNET_RX_FRAMES_CNT 0x114 /* RX_FRAMES_CNT */ 31 #define DNET_TX_FRAMES_CNT 0x118 /* TX_FRAMES_CNT */ 32 #define DNET_RX_FIFO_TH 0x11C /* RX_FIFO_TH */ 33 #define DNET_TX_FIFO_TH 0x120 /* TX_FIFO_TH */ 34 #define DNET_SYS_CTL 0x124 /* SYS_CTL */ 35 #define DNET_PAUSE_TMR 0x128 /* PAUSE_TMR */ 36 #define DNET_RX_FIFO_WCNT 0x12C /* RX_FIFO_WCNT */ 37 #define DNET_TX_FIFO_WCNT 0x130 /* TX_FIFO_WCNT */ 38 39 /* ALL DNET MAC REGISTERS */ 40 #define DNET_MACREG_DATA 0x200 /* Mac-Reg Data */ 41 #define DNET_MACREG_ADDR 0x204 /* Mac-Reg Addr */ 42 43 /* ALL DNET RX STATISTICS COUNTERS */ 44 #define DNET_RX_PKT_IGNR_CNT 0x300 45 #define DNET_RX_LEN_CHK_ERR_CNT 0x304 46 #define DNET_RX_LNG_FRM_CNT 0x308 47 #define DNET_RX_SHRT_FRM_CNT 0x30C 48 #define DNET_RX_IPG_VIOL_CNT 0x310 49 #define DNET_RX_CRC_ERR_CNT 0x314 50 #define DNET_RX_OK_PKT_CNT 0x318 51 #define DNET_RX_CTL_FRM_CNT 0x31C 52 #define DNET_RX_PAUSE_FRM_CNT 0x320 53 #define DNET_RX_MULTICAST_CNT 0x324 54 #define DNET_RX_BROADCAST_CNT 0x328 55 #define DNET_RX_VLAN_TAG_CNT 0x32C 56 #define DNET_RX_PRE_SHRINK_CNT 0x330 57 #define DNET_RX_DRIB_NIB_CNT 0x334 58 #define DNET_RX_UNSUP_OPCD_CNT 0x338 59 #define DNET_RX_BYTE_CNT 0x33C 60 61 /* DNET TX STATISTICS COUNTERS */ 62 #define DNET_TX_UNICAST_CNT 0x400 63 #define DNET_TX_PAUSE_FRM_CNT 0x404 64 #define DNET_TX_MULTICAST_CNT 0x408 65 #define DNET_TX_BRDCAST_CNT 0x40C 66 #define DNET_TX_VLAN_TAG_CNT 0x410 67 #define DNET_TX_BAD_FCS_CNT 0x414 68 #define DNET_TX_JUMBO_CNT 0x418 69 #define DNET_TX_BYTE_CNT 0x41C 70 71 /* SOME INTERNAL MAC-CORE REGISTER */ 72 #define DNET_INTERNAL_MODE_REG 0x0 73 #define DNET_INTERNAL_RXTX_CONTROL_REG 0x2 74 #define DNET_INTERNAL_MAX_PKT_SIZE_REG 0x4 75 #define DNET_INTERNAL_IGP_REG 0x8 76 #define DNET_INTERNAL_MAC_ADDR_0_REG 0xa 77 #define DNET_INTERNAL_MAC_ADDR_1_REG 0xc 78 #define DNET_INTERNAL_MAC_ADDR_2_REG 0xe 79 #define DNET_INTERNAL_TX_RX_STS_REG 0x12 80 #define DNET_INTERNAL_GMII_MNG_CTL_REG 0x14 81 #define DNET_INTERNAL_GMII_MNG_DAT_REG 0x16 82 83 #define DNET_INTERNAL_GMII_MNG_CMD_FIN (1 << 14) 84 85 #define DNET_INTERNAL_WRITE (1 << 31) 86 87 /* MAC-CORE REGISTER FIELDS */ 88 89 /* MAC-CORE MODE REGISTER FIELDS */ 90 #define DNET_INTERNAL_MODE_GBITEN (1 << 0) 91 #define DNET_INTERNAL_MODE_FCEN (1 << 1) 92 #define DNET_INTERNAL_MODE_RXEN (1 << 2) 93 #define DNET_INTERNAL_MODE_TXEN (1 << 3) 94 95 /* MAC-CORE RXTX CONTROL REGISTER FIELDS */ 96 #define DNET_INTERNAL_RXTX_CONTROL_RXSHORTFRAME (1 << 8) 97 #define DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST (1 << 7) 98 #define DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST (1 << 4) 99 #define DNET_INTERNAL_RXTX_CONTROL_RXPAUSE (1 << 3) 100 #define DNET_INTERNAL_RXTX_CONTROL_DISTXFCS (1 << 2) 101 #define DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS (1 << 1) 102 #define DNET_INTERNAL_RXTX_CONTROL_ENPROMISC (1 << 0) 103 #define DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL (1 << 6) 104 #define DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP (1 << 5) 105 106 /* SYSTEM CONTROL REGISTER FIELDS */ 107 #define DNET_SYS_CTL_IGNORENEXTPKT (1 << 0) 108 #define DNET_SYS_CTL_SENDPAUSE (1 << 2) 109 #define DNET_SYS_CTL_RXFIFOFLUSH (1 << 3) 110 #define DNET_SYS_CTL_TXFIFOFLUSH (1 << 4) 111 112 /* TX STATUS REGISTER FIELDS */ 113 #define DNET_TX_STATUS_FIFO_ALMOST_EMPTY (1 << 2) 114 #define DNET_TX_STATUS_FIFO_ALMOST_FULL (1 << 1) 115 116 /* INTERRUPT SOURCE REGISTER FIELDS */ 117 #define DNET_INTR_SRC_TX_PKTSENT (1 << 0) 118 #define DNET_INTR_SRC_TX_FIFOAF (1 << 1) 119 #define DNET_INTR_SRC_TX_FIFOAE (1 << 2) 120 #define DNET_INTR_SRC_TX_DISCFRM (1 << 3) 121 #define DNET_INTR_SRC_TX_FIFOFULL (1 << 4) 122 #define DNET_INTR_SRC_RX_CMDFIFOAF (1 << 8) 123 #define DNET_INTR_SRC_RX_CMDFIFOFF (1 << 9) 124 #define DNET_INTR_SRC_RX_DATAFIFOFF (1 << 10) 125 #define DNET_INTR_SRC_TX_SUMMARY (1 << 16) 126 #define DNET_INTR_SRC_RX_SUMMARY (1 << 17) 127 #define DNET_INTR_SRC_PHY (1 << 19) 128 129 /* INTERRUPT ENABLE REGISTER FIELDS */ 130 #define DNET_INTR_ENB_TX_PKTSENT (1 << 0) 131 #define DNET_INTR_ENB_TX_FIFOAF (1 << 1) 132 #define DNET_INTR_ENB_TX_FIFOAE (1 << 2) 133 #define DNET_INTR_ENB_TX_DISCFRM (1 << 3) 134 #define DNET_INTR_ENB_TX_FIFOFULL (1 << 4) 135 #define DNET_INTR_ENB_RX_PKTRDY (1 << 8) 136 #define DNET_INTR_ENB_RX_FIFOAF (1 << 9) 137 #define DNET_INTR_ENB_RX_FIFOERR (1 << 10) 138 #define DNET_INTR_ENB_RX_ERROR (1 << 11) 139 #define DNET_INTR_ENB_RX_FIFOFULL (1 << 12) 140 #define DNET_INTR_ENB_RX_FIFOAE (1 << 13) 141 #define DNET_INTR_ENB_TX_SUMMARY (1 << 16) 142 #define DNET_INTR_ENB_RX_SUMMARY (1 << 17) 143 #define DNET_INTR_ENB_GLOBAL_ENABLE (1 << 18) 144 145 /* default values: 146 * almost empty = less than one full sized ethernet frame (no jumbo) inside 147 * the fifo almost full = can write less than one full sized ethernet frame 148 * (no jumbo) inside the fifo 149 */ 150 #define DNET_CFG_TX_FIFO_FULL_THRES 25 151 #define DNET_CFG_RX_FIFO_FULL_THRES 20 152 153 /* 154 * Capabilities. Used by the driver to know the capabilities that the ethernet 155 * controller inside the FPGA have. 156 */ 157 158 #define DNET_HAS_MDIO (1 << 0) 159 #define DNET_HAS_IRQ (1 << 1) 160 #define DNET_HAS_GIGABIT (1 << 2) 161 #define DNET_HAS_DMA (1 << 3) 162 163 #define DNET_HAS_MII (1 << 4) /* or GMII */ 164 #define DNET_HAS_RMII (1 << 5) /* or RGMII */ 165 166 #define DNET_CAPS_MASK 0xFFFF 167 168 #define DNET_FIFO_SIZE 1024 /* 1K x 32 bit */ 169 #define DNET_FIFO_TX_DATA_AF_TH (DNET_FIFO_SIZE - 384) /* 384 = 1536 / 4 */ 170 #define DNET_FIFO_TX_DATA_AE_TH 384 171 172 #define DNET_FIFO_RX_CMD_AF_TH (1 << 16) /* just one frame inside the FIFO */ 173 174 /* 175 * Hardware-collected statistics. 176 */ 177 struct dnet_stats { 178 u32 rx_pkt_ignr; 179 u32 rx_len_chk_err; 180 u32 rx_lng_frm; 181 u32 rx_shrt_frm; 182 u32 rx_ipg_viol; 183 u32 rx_crc_err; 184 u32 rx_ok_pkt; 185 u32 rx_ctl_frm; 186 u32 rx_pause_frm; 187 u32 rx_multicast; 188 u32 rx_broadcast; 189 u32 rx_vlan_tag; 190 u32 rx_pre_shrink; 191 u32 rx_drib_nib; 192 u32 rx_unsup_opcd; 193 u32 rx_byte; 194 u32 tx_unicast; 195 u32 tx_pause_frm; 196 u32 tx_multicast; 197 u32 tx_brdcast; 198 u32 tx_vlan_tag; 199 u32 tx_bad_fcs; 200 u32 tx_jumbo; 201 u32 tx_byte; 202 }; 203 204 struct dnet { 205 void __iomem *regs; 206 spinlock_t lock; 207 struct platform_device *pdev; 208 struct net_device *dev; 209 struct dnet_stats hw_stats; 210 unsigned int capabilities; /* read from FPGA */ 211 struct napi_struct napi; 212 213 /* PHY stuff */ 214 struct mii_bus *mii_bus; 215 unsigned int link; 216 unsigned int speed; 217 unsigned int duplex; 218 }; 219 220 #endif /* _DNET_H */ 221