1 /* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */ 2 /* 3 Copyright (c) 2001, 2002 by D-Link Corporation 4 Written by Edward Peng.<edward_peng@dlink.com.tw> 5 Created 03-May-2001, base on Linux' sundance.c. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2 of the License, or 10 (at your option) any later version. 11 */ 12 13 #ifndef __DL2K_H__ 14 #define __DL2K_H__ 15 16 #include <linux/module.h> 17 #include <linux/kernel.h> 18 #include <linux/string.h> 19 #include <linux/timer.h> 20 #include <linux/errno.h> 21 #include <linux/ioport.h> 22 #include <linux/slab.h> 23 #include <linux/interrupt.h> 24 #include <linux/pci.h> 25 #include <linux/netdevice.h> 26 #include <linux/etherdevice.h> 27 #include <linux/skbuff.h> 28 #include <linux/init.h> 29 #include <linux/crc32.h> 30 #include <linux/ethtool.h> 31 #include <linux/mii.h> 32 #include <linux/bitops.h> 33 #include <asm/processor.h> /* Processor type for cache alignment. */ 34 #include <asm/io.h> 35 #include <asm/uaccess.h> 36 #include <linux/delay.h> 37 #include <linux/spinlock.h> 38 #include <linux/time.h> 39 #define TX_RING_SIZE 256 40 #define TX_QUEUE_LEN (TX_RING_SIZE - 1) /* Limit ring entries actually used.*/ 41 #define RX_RING_SIZE 256 42 #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct netdev_desc) 43 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct netdev_desc) 44 45 /* This driver was written to use PCI memory space, however x86-oriented 46 hardware often uses I/O space accesses. */ 47 #ifndef MEM_MAPPING 48 #undef readb 49 #undef readw 50 #undef readl 51 #undef writeb 52 #undef writew 53 #undef writel 54 #define readb inb 55 #define readw inw 56 #define readl inl 57 #define writeb outb 58 #define writew outw 59 #define writel outl 60 #endif 61 62 /* Offsets to the device registers. 63 Unlike software-only systems, device drivers interact with complex hardware. 64 It's not useful to define symbolic names for every register bit in the 65 device. The name can only partially document the semantics and make 66 the driver longer and more difficult to read. 67 In general, only the important configuration values or bits changed 68 multiple times should be defined symbolically. 69 */ 70 enum dl2x_offsets { 71 /* I/O register offsets */ 72 DMACtrl = 0x00, 73 RxDMAStatus = 0x08, 74 TFDListPtr0 = 0x10, 75 TFDListPtr1 = 0x14, 76 TxDMABurstThresh = 0x18, 77 TxDMAUrgentThresh = 0x19, 78 TxDMAPollPeriod = 0x1a, 79 RFDListPtr0 = 0x1c, 80 RFDListPtr1 = 0x20, 81 RxDMABurstThresh = 0x24, 82 RxDMAUrgentThresh = 0x25, 83 RxDMAPollPeriod = 0x26, 84 RxDMAIntCtrl = 0x28, 85 DebugCtrl = 0x2c, 86 ASICCtrl = 0x30, 87 FifoCtrl = 0x38, 88 RxEarlyThresh = 0x3a, 89 FlowOffThresh = 0x3c, 90 FlowOnThresh = 0x3e, 91 TxStartThresh = 0x44, 92 EepromData = 0x48, 93 EepromCtrl = 0x4a, 94 ExpromAddr = 0x4c, 95 Exprodata = 0x50, 96 WakeEvent = 0x51, 97 CountDown = 0x54, 98 IntStatusAck = 0x5a, 99 IntEnable = 0x5c, 100 IntStatus = 0x5e, 101 TxStatus = 0x60, 102 MACCtrl = 0x6c, 103 VLANTag = 0x70, 104 PhyCtrl = 0x76, 105 StationAddr0 = 0x78, 106 StationAddr1 = 0x7a, 107 StationAddr2 = 0x7c, 108 VLANId = 0x80, 109 MaxFrameSize = 0x86, 110 ReceiveMode = 0x88, 111 HashTable0 = 0x8c, 112 HashTable1 = 0x90, 113 RmonStatMask = 0x98, 114 StatMask = 0x9c, 115 RxJumboFrames = 0xbc, 116 TCPCheckSumErrors = 0xc0, 117 IPCheckSumErrors = 0xc2, 118 UDPCheckSumErrors = 0xc4, 119 TxJumboFrames = 0xf4, 120 /* Ethernet MIB statistic register offsets */ 121 OctetRcvOk = 0xa8, 122 McstOctetRcvOk = 0xac, 123 BcstOctetRcvOk = 0xb0, 124 FramesRcvOk = 0xb4, 125 McstFramesRcvdOk = 0xb8, 126 BcstFramesRcvdOk = 0xbe, 127 MacControlFramesRcvd = 0xc6, 128 FrameTooLongErrors = 0xc8, 129 InRangeLengthErrors = 0xca, 130 FramesCheckSeqErrors = 0xcc, 131 FramesLostRxErrors = 0xce, 132 OctetXmtOk = 0xd0, 133 McstOctetXmtOk = 0xd4, 134 BcstOctetXmtOk = 0xd8, 135 FramesXmtOk = 0xdc, 136 McstFramesXmtdOk = 0xe0, 137 FramesWDeferredXmt = 0xe4, 138 LateCollisions = 0xe8, 139 MultiColFrames = 0xec, 140 SingleColFrames = 0xf0, 141 BcstFramesXmtdOk = 0xf6, 142 CarrierSenseErrors = 0xf8, 143 MacControlFramesXmtd = 0xfa, 144 FramesAbortXSColls = 0xfc, 145 FramesWEXDeferal = 0xfe, 146 /* RMON statistic register offsets */ 147 EtherStatsCollisions = 0x100, 148 EtherStatsOctetsTransmit = 0x104, 149 EtherStatsPktsTransmit = 0x108, 150 EtherStatsPkts64OctetTransmit = 0x10c, 151 EtherStats65to127OctetsTransmit = 0x110, 152 EtherStatsPkts128to255OctetsTransmit = 0x114, 153 EtherStatsPkts256to511OctetsTransmit = 0x118, 154 EtherStatsPkts512to1023OctetsTransmit = 0x11c, 155 EtherStatsPkts1024to1518OctetsTransmit = 0x120, 156 EtherStatsCRCAlignErrors = 0x124, 157 EtherStatsUndersizePkts = 0x128, 158 EtherStatsFragments = 0x12c, 159 EtherStatsJabbers = 0x130, 160 EtherStatsOctets = 0x134, 161 EtherStatsPkts = 0x138, 162 EtherStats64Octets = 0x13c, 163 EtherStatsPkts65to127Octets = 0x140, 164 EtherStatsPkts128to255Octets = 0x144, 165 EtherStatsPkts256to511Octets = 0x148, 166 EtherStatsPkts512to1023Octets = 0x14c, 167 EtherStatsPkts1024to1518Octets = 0x150, 168 }; 169 170 /* Bits in the interrupt status/mask registers. */ 171 enum IntStatus_bits { 172 InterruptStatus = 0x0001, 173 HostError = 0x0002, 174 MACCtrlFrame = 0x0008, 175 TxComplete = 0x0004, 176 RxComplete = 0x0010, 177 RxEarly = 0x0020, 178 IntRequested = 0x0040, 179 UpdateStats = 0x0080, 180 LinkEvent = 0x0100, 181 TxDMAComplete = 0x0200, 182 RxDMAComplete = 0x0400, 183 RFDListEnd = 0x0800, 184 RxDMAPriority = 0x1000, 185 }; 186 187 /* Bits in the ReceiveMode register. */ 188 enum ReceiveMode_bits { 189 ReceiveUnicast = 0x0001, 190 ReceiveMulticast = 0x0002, 191 ReceiveBroadcast = 0x0004, 192 ReceiveAllFrames = 0x0008, 193 ReceiveMulticastHash = 0x0010, 194 ReceiveIPMulticast = 0x0020, 195 ReceiveVLANMatch = 0x0100, 196 ReceiveVLANHash = 0x0200, 197 }; 198 /* Bits in MACCtrl. */ 199 enum MACCtrl_bits { 200 DuplexSelect = 0x20, 201 TxFlowControlEnable = 0x80, 202 RxFlowControlEnable = 0x0100, 203 RcvFCS = 0x200, 204 AutoVLANtagging = 0x1000, 205 AutoVLANuntagging = 0x2000, 206 StatsEnable = 0x00200000, 207 StatsDisable = 0x00400000, 208 StatsEnabled = 0x00800000, 209 TxEnable = 0x01000000, 210 TxDisable = 0x02000000, 211 TxEnabled = 0x04000000, 212 RxEnable = 0x08000000, 213 RxDisable = 0x10000000, 214 RxEnabled = 0x20000000, 215 }; 216 217 enum ASICCtrl_LoWord_bits { 218 PhyMedia = 0x0080, 219 }; 220 221 enum ASICCtrl_HiWord_bits { 222 GlobalReset = 0x0001, 223 RxReset = 0x0002, 224 TxReset = 0x0004, 225 DMAReset = 0x0008, 226 FIFOReset = 0x0010, 227 NetworkReset = 0x0020, 228 HostReset = 0x0040, 229 ResetBusy = 0x0400, 230 }; 231 232 /* Transmit Frame Control bits */ 233 enum TFC_bits { 234 DwordAlign = 0x00000000, 235 WordAlignDisable = 0x00030000, 236 WordAlign = 0x00020000, 237 TCPChecksumEnable = 0x00040000, 238 UDPChecksumEnable = 0x00080000, 239 IPChecksumEnable = 0x00100000, 240 FCSAppendDisable = 0x00200000, 241 TxIndicate = 0x00400000, 242 TxDMAIndicate = 0x00800000, 243 FragCountShift = 24, 244 VLANTagInsert = 0x0000000010000000, 245 TFDDone = 0x80000000, 246 VIDShift = 32, 247 UsePriorityShift = 48, 248 }; 249 250 /* Receive Frames Status bits */ 251 enum RFS_bits { 252 RxFIFOOverrun = 0x00010000, 253 RxRuntFrame = 0x00020000, 254 RxAlignmentError = 0x00040000, 255 RxFCSError = 0x00080000, 256 RxOverSizedFrame = 0x00100000, 257 RxLengthError = 0x00200000, 258 VLANDetected = 0x00400000, 259 TCPDetected = 0x00800000, 260 TCPError = 0x01000000, 261 UDPDetected = 0x02000000, 262 UDPError = 0x04000000, 263 IPDetected = 0x08000000, 264 IPError = 0x10000000, 265 FrameStart = 0x20000000, 266 FrameEnd = 0x40000000, 267 RFDDone = 0x80000000, 268 TCIShift = 32, 269 RFS_Errors = 0x003f0000, 270 }; 271 272 #define MII_RESET_TIME_OUT 10000 273 /* MII register */ 274 enum _mii_reg { 275 MII_PHY_SCR = 16, 276 }; 277 278 /* PCS register */ 279 enum _pcs_reg { 280 PCS_BMCR = 0, 281 PCS_BMSR = 1, 282 PCS_ANAR = 4, 283 PCS_ANLPAR = 5, 284 PCS_ANER = 6, 285 PCS_ANNPT = 7, 286 PCS_ANLPRNP = 8, 287 PCS_ESR = 15, 288 }; 289 290 /* IEEE Extened Status Register */ 291 enum _mii_esr { 292 MII_ESR_1000BX_FD = 0x8000, 293 MII_ESR_1000BX_HD = 0x4000, 294 MII_ESR_1000BT_FD = 0x2000, 295 MII_ESR_1000BT_HD = 0x1000, 296 }; 297 /* PHY Specific Control Register */ 298 #if 0 299 typedef union t_MII_PHY_SCR { 300 u16 image; 301 struct { 302 u16 disable_jabber:1; // bit 0 303 u16 polarity_reversal:1; // bit 1 304 u16 SEQ_test:1; // bit 2 305 u16 _bit_3:1; // bit 3 306 u16 disable_CLK125:1; // bit 4 307 u16 mdi_crossover_mode:2; // bit 6:5 308 u16 enable_ext_dist:1; // bit 7 309 u16 _bit_8_9:2; // bit 9:8 310 u16 force_link:1; // bit 10 311 u16 assert_CRS:1; // bit 11 312 u16 rcv_fifo_depth:2; // bit 13:12 313 u16 xmit_fifo_depth:2; // bit 15:14 314 } bits; 315 } PHY_SCR_t, *PPHY_SCR_t; 316 #endif 317 318 typedef enum t_MII_ADMIN_STATUS { 319 adm_reset, 320 adm_operational, 321 adm_loopback, 322 adm_power_down, 323 adm_isolate 324 } MII_ADMIN_t, *PMII_ADMIN_t; 325 326 /* Physical Coding Sublayer Management (PCS) */ 327 /* PCS control and status registers bitmap as the same as MII */ 328 /* PCS Extended Status register bitmap as the same as MII */ 329 /* PCS ANAR */ 330 enum _pcs_anar { 331 PCS_ANAR_NEXT_PAGE = 0x8000, 332 PCS_ANAR_REMOTE_FAULT = 0x3000, 333 PCS_ANAR_ASYMMETRIC = 0x0100, 334 PCS_ANAR_PAUSE = 0x0080, 335 PCS_ANAR_HALF_DUPLEX = 0x0040, 336 PCS_ANAR_FULL_DUPLEX = 0x0020, 337 }; 338 /* PCS ANLPAR */ 339 enum _pcs_anlpar { 340 PCS_ANLPAR_NEXT_PAGE = PCS_ANAR_NEXT_PAGE, 341 PCS_ANLPAR_REMOTE_FAULT = PCS_ANAR_REMOTE_FAULT, 342 PCS_ANLPAR_ASYMMETRIC = PCS_ANAR_ASYMMETRIC, 343 PCS_ANLPAR_PAUSE = PCS_ANAR_PAUSE, 344 PCS_ANLPAR_HALF_DUPLEX = PCS_ANAR_HALF_DUPLEX, 345 PCS_ANLPAR_FULL_DUPLEX = PCS_ANAR_FULL_DUPLEX, 346 }; 347 348 typedef struct t_SROM { 349 u16 config_param; /* 0x00 */ 350 u16 asic_ctrl; /* 0x02 */ 351 u16 sub_vendor_id; /* 0x04 */ 352 u16 sub_system_id; /* 0x06 */ 353 u16 reserved1[12]; /* 0x08-0x1f */ 354 u8 mac_addr[6]; /* 0x20-0x25 */ 355 u8 reserved2[10]; /* 0x26-0x2f */ 356 u8 sib[204]; /* 0x30-0xfb */ 357 u32 crc; /* 0xfc-0xff */ 358 } SROM_t, *PSROM_t; 359 360 /* Ioctl custom data */ 361 struct ioctl_data { 362 char signature[10]; 363 int cmd; 364 int len; 365 char *data; 366 }; 367 368 /* The Rx and Tx buffer descriptors. */ 369 struct netdev_desc { 370 __le64 next_desc; 371 __le64 status; 372 __le64 fraginfo; 373 }; 374 375 #define PRIV_ALIGN 15 /* Required alignment mask */ 376 /* Use __attribute__((aligned (L1_CACHE_BYTES))) to maintain alignment 377 within the structure. */ 378 struct netdev_private { 379 /* Descriptor rings first for alignment. */ 380 struct netdev_desc *rx_ring; 381 struct netdev_desc *tx_ring; 382 struct sk_buff *rx_skbuff[RX_RING_SIZE]; 383 struct sk_buff *tx_skbuff[TX_RING_SIZE]; 384 dma_addr_t tx_ring_dma; 385 dma_addr_t rx_ring_dma; 386 struct pci_dev *pdev; 387 spinlock_t tx_lock; 388 spinlock_t rx_lock; 389 struct net_device_stats stats; 390 unsigned int rx_buf_sz; /* Based on MTU+slack. */ 391 unsigned int speed; /* Operating speed */ 392 unsigned int vlan; /* VLAN Id */ 393 unsigned int chip_id; /* PCI table chip id */ 394 unsigned int rx_coalesce; /* Maximum frames each RxDMAComplete intr */ 395 unsigned int rx_timeout; /* Wait time between RxDMAComplete intr */ 396 unsigned int tx_coalesce; /* Maximum frames each tx interrupt */ 397 unsigned int full_duplex:1; /* Full-duplex operation requested. */ 398 unsigned int an_enable:2; /* Auto-Negotiated Enable */ 399 unsigned int jumbo:1; /* Jumbo frame enable */ 400 unsigned int coalesce:1; /* Rx coalescing enable */ 401 unsigned int tx_flow:1; /* Tx flow control enable */ 402 unsigned int rx_flow:1; /* Rx flow control enable */ 403 unsigned int phy_media:1; /* 1: fiber, 0: copper */ 404 unsigned int link_status:1; /* Current link status */ 405 struct netdev_desc *last_tx; /* Last Tx descriptor used. */ 406 unsigned long cur_rx, old_rx; /* Producer/consumer ring indices */ 407 unsigned long cur_tx, old_tx; 408 struct timer_list timer; 409 int wake_polarity; 410 char name[256]; /* net device description */ 411 u8 duplex_polarity; 412 u16 mcast_filter[4]; 413 u16 advertising; /* NWay media advertisement */ 414 u16 negotiate; /* Negotiated media */ 415 int phy_addr; /* PHY addresses. */ 416 }; 417 418 /* The station address location in the EEPROM. */ 419 /* The struct pci_device_id consist of: 420 vendor, device Vendor and device ID to match (or PCI_ANY_ID) 421 subvendor, subdevice Subsystem vendor and device ID to match (or PCI_ANY_ID) 422 class Device class to match. The class_mask tells which bits 423 class_mask of the class are honored during the comparison. 424 driver_data Data private to the driver. 425 */ 426 427 static DEFINE_PCI_DEVICE_TABLE(rio_pci_tbl) = { 428 {0x1186, 0x4000, PCI_ANY_ID, PCI_ANY_ID, }, 429 {0x13f0, 0x1021, PCI_ANY_ID, PCI_ANY_ID, }, 430 { } 431 }; 432 MODULE_DEVICE_TABLE (pci, rio_pci_tbl); 433 #define TX_TIMEOUT (4*HZ) 434 #define PACKET_SIZE 1536 435 #define MAX_JUMBO 8000 436 #define RIO_IO_SIZE 340 437 #define DEFAULT_RXC 5 438 #define DEFAULT_RXT 750 439 #define DEFAULT_TXC 1 440 #define MAX_TXC 8 441 #endif /* __DL2K_H__ */ 442