1 /* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */ 2 /* 3 Copyright (c) 2001, 2002 by D-Link Corporation 4 Written by Edward Peng.<edward_peng@dlink.com.tw> 5 Created 03-May-2001, base on Linux' sundance.c. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2 of the License, or 10 (at your option) any later version. 11 */ 12 13 #define DRV_NAME "DL2000/TC902x-based linux driver" 14 #define DRV_VERSION "v1.19" 15 #define DRV_RELDATE "2007/08/12" 16 #include "dl2k.h" 17 #include <linux/dma-mapping.h> 18 19 #define dw32(reg, val) iowrite32(val, ioaddr + (reg)) 20 #define dw16(reg, val) iowrite16(val, ioaddr + (reg)) 21 #define dw8(reg, val) iowrite8(val, ioaddr + (reg)) 22 #define dr32(reg) ioread32(ioaddr + (reg)) 23 #define dr16(reg) ioread16(ioaddr + (reg)) 24 #define dr8(reg) ioread8(ioaddr + (reg)) 25 26 static char version[] = 27 KERN_INFO DRV_NAME " " DRV_VERSION " " DRV_RELDATE "\n"; 28 #define MAX_UNITS 8 29 static int mtu[MAX_UNITS]; 30 static int vlan[MAX_UNITS]; 31 static int jumbo[MAX_UNITS]; 32 static char *media[MAX_UNITS]; 33 static int tx_flow=-1; 34 static int rx_flow=-1; 35 static int copy_thresh; 36 static int rx_coalesce=10; /* Rx frame count each interrupt */ 37 static int rx_timeout=200; /* Rx DMA wait time in 640ns increments */ 38 static int tx_coalesce=16; /* HW xmit count each TxDMAComplete */ 39 40 41 MODULE_AUTHOR ("Edward Peng"); 42 MODULE_DESCRIPTION ("D-Link DL2000-based Gigabit Ethernet Adapter"); 43 MODULE_LICENSE("GPL"); 44 module_param_array(mtu, int, NULL, 0); 45 module_param_array(media, charp, NULL, 0); 46 module_param_array(vlan, int, NULL, 0); 47 module_param_array(jumbo, int, NULL, 0); 48 module_param(tx_flow, int, 0); 49 module_param(rx_flow, int, 0); 50 module_param(copy_thresh, int, 0); 51 module_param(rx_coalesce, int, 0); /* Rx frame count each interrupt */ 52 module_param(rx_timeout, int, 0); /* Rx DMA wait time in 64ns increments */ 53 module_param(tx_coalesce, int, 0); /* HW xmit count each TxDMAComplete */ 54 55 56 /* Enable the default interrupts */ 57 #define DEFAULT_INTR (RxDMAComplete | HostError | IntRequested | TxDMAComplete| \ 58 UpdateStats | LinkEvent) 59 60 static void dl2k_enable_int(struct netdev_private *np) 61 { 62 void __iomem *ioaddr = np->ioaddr; 63 64 dw16(IntEnable, DEFAULT_INTR); 65 } 66 67 static const int max_intrloop = 50; 68 static const int multicast_filter_limit = 0x40; 69 70 static int rio_open (struct net_device *dev); 71 static void rio_timer (unsigned long data); 72 static void rio_tx_timeout (struct net_device *dev); 73 static void alloc_list (struct net_device *dev); 74 static netdev_tx_t start_xmit (struct sk_buff *skb, struct net_device *dev); 75 static irqreturn_t rio_interrupt (int irq, void *dev_instance); 76 static void rio_free_tx (struct net_device *dev, int irq); 77 static void tx_error (struct net_device *dev, int tx_status); 78 static int receive_packet (struct net_device *dev); 79 static void rio_error (struct net_device *dev, int int_status); 80 static int change_mtu (struct net_device *dev, int new_mtu); 81 static void set_multicast (struct net_device *dev); 82 static struct net_device_stats *get_stats (struct net_device *dev); 83 static int clear_stats (struct net_device *dev); 84 static int rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd); 85 static int rio_close (struct net_device *dev); 86 static int find_miiphy (struct net_device *dev); 87 static int parse_eeprom (struct net_device *dev); 88 static int read_eeprom (struct netdev_private *, int eep_addr); 89 static int mii_wait_link (struct net_device *dev, int wait); 90 static int mii_set_media (struct net_device *dev); 91 static int mii_get_media (struct net_device *dev); 92 static int mii_set_media_pcs (struct net_device *dev); 93 static int mii_get_media_pcs (struct net_device *dev); 94 static int mii_read (struct net_device *dev, int phy_addr, int reg_num); 95 static int mii_write (struct net_device *dev, int phy_addr, int reg_num, 96 u16 data); 97 98 static const struct ethtool_ops ethtool_ops; 99 100 static const struct net_device_ops netdev_ops = { 101 .ndo_open = rio_open, 102 .ndo_start_xmit = start_xmit, 103 .ndo_stop = rio_close, 104 .ndo_get_stats = get_stats, 105 .ndo_validate_addr = eth_validate_addr, 106 .ndo_set_mac_address = eth_mac_addr, 107 .ndo_set_rx_mode = set_multicast, 108 .ndo_do_ioctl = rio_ioctl, 109 .ndo_tx_timeout = rio_tx_timeout, 110 .ndo_change_mtu = change_mtu, 111 }; 112 113 static int 114 rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent) 115 { 116 struct net_device *dev; 117 struct netdev_private *np; 118 static int card_idx; 119 int chip_idx = ent->driver_data; 120 int err, irq; 121 void __iomem *ioaddr; 122 static int version_printed; 123 void *ring_space; 124 dma_addr_t ring_dma; 125 126 if (!version_printed++) 127 printk ("%s", version); 128 129 err = pci_enable_device (pdev); 130 if (err) 131 return err; 132 133 irq = pdev->irq; 134 err = pci_request_regions (pdev, "dl2k"); 135 if (err) 136 goto err_out_disable; 137 138 pci_set_master (pdev); 139 140 err = -ENOMEM; 141 142 dev = alloc_etherdev (sizeof (*np)); 143 if (!dev) 144 goto err_out_res; 145 SET_NETDEV_DEV(dev, &pdev->dev); 146 147 np = netdev_priv(dev); 148 149 /* IO registers range. */ 150 ioaddr = pci_iomap(pdev, 0, 0); 151 if (!ioaddr) 152 goto err_out_dev; 153 np->eeprom_addr = ioaddr; 154 155 #ifdef MEM_MAPPING 156 /* MM registers range. */ 157 ioaddr = pci_iomap(pdev, 1, 0); 158 if (!ioaddr) 159 goto err_out_iounmap; 160 #endif 161 np->ioaddr = ioaddr; 162 np->chip_id = chip_idx; 163 np->pdev = pdev; 164 spin_lock_init (&np->tx_lock); 165 spin_lock_init (&np->rx_lock); 166 167 /* Parse manual configuration */ 168 np->an_enable = 1; 169 np->tx_coalesce = 1; 170 if (card_idx < MAX_UNITS) { 171 if (media[card_idx] != NULL) { 172 np->an_enable = 0; 173 if (strcmp (media[card_idx], "auto") == 0 || 174 strcmp (media[card_idx], "autosense") == 0 || 175 strcmp (media[card_idx], "0") == 0 ) { 176 np->an_enable = 2; 177 } else if (strcmp (media[card_idx], "100mbps_fd") == 0 || 178 strcmp (media[card_idx], "4") == 0) { 179 np->speed = 100; 180 np->full_duplex = 1; 181 } else if (strcmp (media[card_idx], "100mbps_hd") == 0 || 182 strcmp (media[card_idx], "3") == 0) { 183 np->speed = 100; 184 np->full_duplex = 0; 185 } else if (strcmp (media[card_idx], "10mbps_fd") == 0 || 186 strcmp (media[card_idx], "2") == 0) { 187 np->speed = 10; 188 np->full_duplex = 1; 189 } else if (strcmp (media[card_idx], "10mbps_hd") == 0 || 190 strcmp (media[card_idx], "1") == 0) { 191 np->speed = 10; 192 np->full_duplex = 0; 193 } else if (strcmp (media[card_idx], "1000mbps_fd") == 0 || 194 strcmp (media[card_idx], "6") == 0) { 195 np->speed=1000; 196 np->full_duplex=1; 197 } else if (strcmp (media[card_idx], "1000mbps_hd") == 0 || 198 strcmp (media[card_idx], "5") == 0) { 199 np->speed = 1000; 200 np->full_duplex = 0; 201 } else { 202 np->an_enable = 1; 203 } 204 } 205 if (jumbo[card_idx] != 0) { 206 np->jumbo = 1; 207 dev->mtu = MAX_JUMBO; 208 } else { 209 np->jumbo = 0; 210 if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE) 211 dev->mtu = mtu[card_idx]; 212 } 213 np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ? 214 vlan[card_idx] : 0; 215 if (rx_coalesce > 0 && rx_timeout > 0) { 216 np->rx_coalesce = rx_coalesce; 217 np->rx_timeout = rx_timeout; 218 np->coalesce = 1; 219 } 220 np->tx_flow = (tx_flow == 0) ? 0 : 1; 221 np->rx_flow = (rx_flow == 0) ? 0 : 1; 222 223 if (tx_coalesce < 1) 224 tx_coalesce = 1; 225 else if (tx_coalesce > TX_RING_SIZE-1) 226 tx_coalesce = TX_RING_SIZE - 1; 227 } 228 dev->netdev_ops = &netdev_ops; 229 dev->watchdog_timeo = TX_TIMEOUT; 230 dev->ethtool_ops = ðtool_ops; 231 #if 0 232 dev->features = NETIF_F_IP_CSUM; 233 #endif 234 pci_set_drvdata (pdev, dev); 235 236 ring_space = pci_alloc_consistent (pdev, TX_TOTAL_SIZE, &ring_dma); 237 if (!ring_space) 238 goto err_out_iounmap; 239 np->tx_ring = ring_space; 240 np->tx_ring_dma = ring_dma; 241 242 ring_space = pci_alloc_consistent (pdev, RX_TOTAL_SIZE, &ring_dma); 243 if (!ring_space) 244 goto err_out_unmap_tx; 245 np->rx_ring = ring_space; 246 np->rx_ring_dma = ring_dma; 247 248 /* Parse eeprom data */ 249 parse_eeprom (dev); 250 251 /* Find PHY address */ 252 err = find_miiphy (dev); 253 if (err) 254 goto err_out_unmap_rx; 255 256 /* Fiber device? */ 257 np->phy_media = (dr16(ASICCtrl) & PhyMedia) ? 1 : 0; 258 np->link_status = 0; 259 /* Set media and reset PHY */ 260 if (np->phy_media) { 261 /* default Auto-Negotiation for fiber deivices */ 262 if (np->an_enable == 2) { 263 np->an_enable = 1; 264 } 265 mii_set_media_pcs (dev); 266 } else { 267 /* Auto-Negotiation is mandatory for 1000BASE-T, 268 IEEE 802.3ab Annex 28D page 14 */ 269 if (np->speed == 1000) 270 np->an_enable = 1; 271 mii_set_media (dev); 272 } 273 274 err = register_netdev (dev); 275 if (err) 276 goto err_out_unmap_rx; 277 278 card_idx++; 279 280 printk (KERN_INFO "%s: %s, %pM, IRQ %d\n", 281 dev->name, np->name, dev->dev_addr, irq); 282 if (tx_coalesce > 1) 283 printk(KERN_INFO "tx_coalesce:\t%d packets\n", 284 tx_coalesce); 285 if (np->coalesce) 286 printk(KERN_INFO 287 "rx_coalesce:\t%d packets\n" 288 "rx_timeout: \t%d ns\n", 289 np->rx_coalesce, np->rx_timeout*640); 290 if (np->vlan) 291 printk(KERN_INFO "vlan(id):\t%d\n", np->vlan); 292 return 0; 293 294 err_out_unmap_rx: 295 pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma); 296 err_out_unmap_tx: 297 pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma); 298 err_out_iounmap: 299 #ifdef MEM_MAPPING 300 pci_iounmap(pdev, np->ioaddr); 301 #endif 302 pci_iounmap(pdev, np->eeprom_addr); 303 err_out_dev: 304 free_netdev (dev); 305 err_out_res: 306 pci_release_regions (pdev); 307 err_out_disable: 308 pci_disable_device (pdev); 309 return err; 310 } 311 312 static int 313 find_miiphy (struct net_device *dev) 314 { 315 struct netdev_private *np = netdev_priv(dev); 316 int i, phy_found = 0; 317 np = netdev_priv(dev); 318 np->phy_addr = 1; 319 320 for (i = 31; i >= 0; i--) { 321 int mii_status = mii_read (dev, i, 1); 322 if (mii_status != 0xffff && mii_status != 0x0000) { 323 np->phy_addr = i; 324 phy_found++; 325 } 326 } 327 if (!phy_found) { 328 printk (KERN_ERR "%s: No MII PHY found!\n", dev->name); 329 return -ENODEV; 330 } 331 return 0; 332 } 333 334 static int 335 parse_eeprom (struct net_device *dev) 336 { 337 struct netdev_private *np = netdev_priv(dev); 338 void __iomem *ioaddr = np->ioaddr; 339 int i, j; 340 u8 sromdata[256]; 341 u8 *psib; 342 u32 crc; 343 PSROM_t psrom = (PSROM_t) sromdata; 344 345 int cid, next; 346 347 for (i = 0; i < 128; i++) 348 ((__le16 *) sromdata)[i] = cpu_to_le16(read_eeprom(np, i)); 349 350 if (np->pdev->vendor == PCI_VENDOR_ID_DLINK) { /* D-Link Only */ 351 /* Check CRC */ 352 crc = ~ether_crc_le (256 - 4, sromdata); 353 if (psrom->crc != cpu_to_le32(crc)) { 354 printk (KERN_ERR "%s: EEPROM data CRC error.\n", 355 dev->name); 356 return -1; 357 } 358 } 359 360 /* Set MAC address */ 361 for (i = 0; i < 6; i++) 362 dev->dev_addr[i] = psrom->mac_addr[i]; 363 364 if (np->pdev->vendor != PCI_VENDOR_ID_DLINK) { 365 return 0; 366 } 367 368 /* Parse Software Information Block */ 369 i = 0x30; 370 psib = (u8 *) sromdata; 371 do { 372 cid = psib[i++]; 373 next = psib[i++]; 374 if ((cid == 0 && next == 0) || (cid == 0xff && next == 0xff)) { 375 printk (KERN_ERR "Cell data error\n"); 376 return -1; 377 } 378 switch (cid) { 379 case 0: /* Format version */ 380 break; 381 case 1: /* End of cell */ 382 return 0; 383 case 2: /* Duplex Polarity */ 384 np->duplex_polarity = psib[i]; 385 dw8(PhyCtrl, dr8(PhyCtrl) | psib[i]); 386 break; 387 case 3: /* Wake Polarity */ 388 np->wake_polarity = psib[i]; 389 break; 390 case 9: /* Adapter description */ 391 j = (next - i > 255) ? 255 : next - i; 392 memcpy (np->name, &(psib[i]), j); 393 break; 394 case 4: 395 case 5: 396 case 6: 397 case 7: 398 case 8: /* Reversed */ 399 break; 400 default: /* Unknown cell */ 401 return -1; 402 } 403 i = next; 404 } while (1); 405 406 return 0; 407 } 408 409 static int 410 rio_open (struct net_device *dev) 411 { 412 struct netdev_private *np = netdev_priv(dev); 413 void __iomem *ioaddr = np->ioaddr; 414 const int irq = np->pdev->irq; 415 int i; 416 u16 macctrl; 417 418 i = request_irq(irq, rio_interrupt, IRQF_SHARED, dev->name, dev); 419 if (i) 420 return i; 421 422 /* Reset all logic functions */ 423 dw16(ASICCtrl + 2, 424 GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset); 425 mdelay(10); 426 427 /* DebugCtrl bit 4, 5, 9 must set */ 428 dw32(DebugCtrl, dr32(DebugCtrl) | 0x0230); 429 430 /* Jumbo frame */ 431 if (np->jumbo != 0) 432 dw16(MaxFrameSize, MAX_JUMBO+14); 433 434 alloc_list (dev); 435 436 /* Get station address */ 437 for (i = 0; i < 6; i++) 438 dw8(StationAddr0 + i, dev->dev_addr[i]); 439 440 set_multicast (dev); 441 if (np->coalesce) { 442 dw32(RxDMAIntCtrl, np->rx_coalesce | np->rx_timeout << 16); 443 } 444 /* Set RIO to poll every N*320nsec. */ 445 dw8(RxDMAPollPeriod, 0x20); 446 dw8(TxDMAPollPeriod, 0xff); 447 dw8(RxDMABurstThresh, 0x30); 448 dw8(RxDMAUrgentThresh, 0x30); 449 dw32(RmonStatMask, 0x0007ffff); 450 /* clear statistics */ 451 clear_stats (dev); 452 453 /* VLAN supported */ 454 if (np->vlan) { 455 /* priority field in RxDMAIntCtrl */ 456 dw32(RxDMAIntCtrl, dr32(RxDMAIntCtrl) | 0x7 << 10); 457 /* VLANId */ 458 dw16(VLANId, np->vlan); 459 /* Length/Type should be 0x8100 */ 460 dw32(VLANTag, 0x8100 << 16 | np->vlan); 461 /* Enable AutoVLANuntagging, but disable AutoVLANtagging. 462 VLAN information tagged by TFC' VID, CFI fields. */ 463 dw32(MACCtrl, dr32(MACCtrl) | AutoVLANuntagging); 464 } 465 466 setup_timer(&np->timer, rio_timer, (unsigned long)dev); 467 np->timer.expires = jiffies + 1*HZ; 468 add_timer (&np->timer); 469 470 /* Start Tx/Rx */ 471 dw32(MACCtrl, dr32(MACCtrl) | StatsEnable | RxEnable | TxEnable); 472 473 macctrl = 0; 474 macctrl |= (np->vlan) ? AutoVLANuntagging : 0; 475 macctrl |= (np->full_duplex) ? DuplexSelect : 0; 476 macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0; 477 macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0; 478 dw16(MACCtrl, macctrl); 479 480 netif_start_queue (dev); 481 482 dl2k_enable_int(np); 483 return 0; 484 } 485 486 static void 487 rio_timer (unsigned long data) 488 { 489 struct net_device *dev = (struct net_device *)data; 490 struct netdev_private *np = netdev_priv(dev); 491 unsigned int entry; 492 int next_tick = 1*HZ; 493 unsigned long flags; 494 495 spin_lock_irqsave(&np->rx_lock, flags); 496 /* Recover rx ring exhausted error */ 497 if (np->cur_rx - np->old_rx >= RX_RING_SIZE) { 498 printk(KERN_INFO "Try to recover rx ring exhausted...\n"); 499 /* Re-allocate skbuffs to fill the descriptor ring */ 500 for (; np->cur_rx - np->old_rx > 0; np->old_rx++) { 501 struct sk_buff *skb; 502 entry = np->old_rx % RX_RING_SIZE; 503 /* Dropped packets don't need to re-allocate */ 504 if (np->rx_skbuff[entry] == NULL) { 505 skb = netdev_alloc_skb_ip_align(dev, 506 np->rx_buf_sz); 507 if (skb == NULL) { 508 np->rx_ring[entry].fraginfo = 0; 509 printk (KERN_INFO 510 "%s: Still unable to re-allocate Rx skbuff.#%d\n", 511 dev->name, entry); 512 break; 513 } 514 np->rx_skbuff[entry] = skb; 515 np->rx_ring[entry].fraginfo = 516 cpu_to_le64 (pci_map_single 517 (np->pdev, skb->data, np->rx_buf_sz, 518 PCI_DMA_FROMDEVICE)); 519 } 520 np->rx_ring[entry].fraginfo |= 521 cpu_to_le64((u64)np->rx_buf_sz << 48); 522 np->rx_ring[entry].status = 0; 523 } /* end for */ 524 } /* end if */ 525 spin_unlock_irqrestore (&np->rx_lock, flags); 526 np->timer.expires = jiffies + next_tick; 527 add_timer(&np->timer); 528 } 529 530 static void 531 rio_tx_timeout (struct net_device *dev) 532 { 533 struct netdev_private *np = netdev_priv(dev); 534 void __iomem *ioaddr = np->ioaddr; 535 536 printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n", 537 dev->name, dr32(TxStatus)); 538 rio_free_tx(dev, 0); 539 dev->if_port = 0; 540 dev->trans_start = jiffies; /* prevent tx timeout */ 541 } 542 543 /* allocate and initialize Tx and Rx descriptors */ 544 static void 545 alloc_list (struct net_device *dev) 546 { 547 struct netdev_private *np = netdev_priv(dev); 548 void __iomem *ioaddr = np->ioaddr; 549 int i; 550 551 np->cur_rx = np->cur_tx = 0; 552 np->old_rx = np->old_tx = 0; 553 np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32); 554 555 /* Initialize Tx descriptors, TFDListPtr leaves in start_xmit(). */ 556 for (i = 0; i < TX_RING_SIZE; i++) { 557 np->tx_skbuff[i] = NULL; 558 np->tx_ring[i].status = cpu_to_le64 (TFDDone); 559 np->tx_ring[i].next_desc = cpu_to_le64 (np->tx_ring_dma + 560 ((i+1)%TX_RING_SIZE) * 561 sizeof (struct netdev_desc)); 562 } 563 564 /* Initialize Rx descriptors */ 565 for (i = 0; i < RX_RING_SIZE; i++) { 566 np->rx_ring[i].next_desc = cpu_to_le64 (np->rx_ring_dma + 567 ((i + 1) % RX_RING_SIZE) * 568 sizeof (struct netdev_desc)); 569 np->rx_ring[i].status = 0; 570 np->rx_ring[i].fraginfo = 0; 571 np->rx_skbuff[i] = NULL; 572 } 573 574 /* Allocate the rx buffers */ 575 for (i = 0; i < RX_RING_SIZE; i++) { 576 /* Allocated fixed size of skbuff */ 577 struct sk_buff *skb; 578 579 skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz); 580 np->rx_skbuff[i] = skb; 581 if (skb == NULL) 582 break; 583 584 /* Rubicon now supports 40 bits of addressing space. */ 585 np->rx_ring[i].fraginfo = 586 cpu_to_le64 ( pci_map_single ( 587 np->pdev, skb->data, np->rx_buf_sz, 588 PCI_DMA_FROMDEVICE)); 589 np->rx_ring[i].fraginfo |= cpu_to_le64((u64)np->rx_buf_sz << 48); 590 } 591 592 /* Set RFDListPtr */ 593 dw32(RFDListPtr0, np->rx_ring_dma); 594 dw32(RFDListPtr1, 0); 595 } 596 597 static netdev_tx_t 598 start_xmit (struct sk_buff *skb, struct net_device *dev) 599 { 600 struct netdev_private *np = netdev_priv(dev); 601 void __iomem *ioaddr = np->ioaddr; 602 struct netdev_desc *txdesc; 603 unsigned entry; 604 u64 tfc_vlan_tag = 0; 605 606 if (np->link_status == 0) { /* Link Down */ 607 dev_kfree_skb(skb); 608 return NETDEV_TX_OK; 609 } 610 entry = np->cur_tx % TX_RING_SIZE; 611 np->tx_skbuff[entry] = skb; 612 txdesc = &np->tx_ring[entry]; 613 614 #if 0 615 if (skb->ip_summed == CHECKSUM_PARTIAL) { 616 txdesc->status |= 617 cpu_to_le64 (TCPChecksumEnable | UDPChecksumEnable | 618 IPChecksumEnable); 619 } 620 #endif 621 if (np->vlan) { 622 tfc_vlan_tag = VLANTagInsert | 623 ((u64)np->vlan << 32) | 624 ((u64)skb->priority << 45); 625 } 626 txdesc->fraginfo = cpu_to_le64 (pci_map_single (np->pdev, skb->data, 627 skb->len, 628 PCI_DMA_TODEVICE)); 629 txdesc->fraginfo |= cpu_to_le64((u64)skb->len << 48); 630 631 /* DL2K bug: DMA fails to get next descriptor ptr in 10Mbps mode 632 * Work around: Always use 1 descriptor in 10Mbps mode */ 633 if (entry % np->tx_coalesce == 0 || np->speed == 10) 634 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag | 635 WordAlignDisable | 636 TxDMAIndicate | 637 (1 << FragCountShift)); 638 else 639 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag | 640 WordAlignDisable | 641 (1 << FragCountShift)); 642 643 /* TxDMAPollNow */ 644 dw32(DMACtrl, dr32(DMACtrl) | 0x00001000); 645 /* Schedule ISR */ 646 dw32(CountDown, 10000); 647 np->cur_tx = (np->cur_tx + 1) % TX_RING_SIZE; 648 if ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE 649 < TX_QUEUE_LEN - 1 && np->speed != 10) { 650 /* do nothing */ 651 } else if (!netif_queue_stopped(dev)) { 652 netif_stop_queue (dev); 653 } 654 655 /* The first TFDListPtr */ 656 if (!dr32(TFDListPtr0)) { 657 dw32(TFDListPtr0, np->tx_ring_dma + 658 entry * sizeof (struct netdev_desc)); 659 dw32(TFDListPtr1, 0); 660 } 661 662 return NETDEV_TX_OK; 663 } 664 665 static irqreturn_t 666 rio_interrupt (int irq, void *dev_instance) 667 { 668 struct net_device *dev = dev_instance; 669 struct netdev_private *np = netdev_priv(dev); 670 void __iomem *ioaddr = np->ioaddr; 671 unsigned int_status; 672 int cnt = max_intrloop; 673 int handled = 0; 674 675 while (1) { 676 int_status = dr16(IntStatus); 677 dw16(IntStatus, int_status); 678 int_status &= DEFAULT_INTR; 679 if (int_status == 0 || --cnt < 0) 680 break; 681 handled = 1; 682 /* Processing received packets */ 683 if (int_status & RxDMAComplete) 684 receive_packet (dev); 685 /* TxDMAComplete interrupt */ 686 if ((int_status & (TxDMAComplete|IntRequested))) { 687 int tx_status; 688 tx_status = dr32(TxStatus); 689 if (tx_status & 0x01) 690 tx_error (dev, tx_status); 691 /* Free used tx skbuffs */ 692 rio_free_tx (dev, 1); 693 } 694 695 /* Handle uncommon events */ 696 if (int_status & 697 (HostError | LinkEvent | UpdateStats)) 698 rio_error (dev, int_status); 699 } 700 if (np->cur_tx != np->old_tx) 701 dw32(CountDown, 100); 702 return IRQ_RETVAL(handled); 703 } 704 705 static inline dma_addr_t desc_to_dma(struct netdev_desc *desc) 706 { 707 return le64_to_cpu(desc->fraginfo) & DMA_BIT_MASK(48); 708 } 709 710 static void 711 rio_free_tx (struct net_device *dev, int irq) 712 { 713 struct netdev_private *np = netdev_priv(dev); 714 int entry = np->old_tx % TX_RING_SIZE; 715 int tx_use = 0; 716 unsigned long flag = 0; 717 718 if (irq) 719 spin_lock(&np->tx_lock); 720 else 721 spin_lock_irqsave(&np->tx_lock, flag); 722 723 /* Free used tx skbuffs */ 724 while (entry != np->cur_tx) { 725 struct sk_buff *skb; 726 727 if (!(np->tx_ring[entry].status & cpu_to_le64(TFDDone))) 728 break; 729 skb = np->tx_skbuff[entry]; 730 pci_unmap_single (np->pdev, 731 desc_to_dma(&np->tx_ring[entry]), 732 skb->len, PCI_DMA_TODEVICE); 733 if (irq) 734 dev_kfree_skb_irq (skb); 735 else 736 dev_kfree_skb (skb); 737 738 np->tx_skbuff[entry] = NULL; 739 entry = (entry + 1) % TX_RING_SIZE; 740 tx_use++; 741 } 742 if (irq) 743 spin_unlock(&np->tx_lock); 744 else 745 spin_unlock_irqrestore(&np->tx_lock, flag); 746 np->old_tx = entry; 747 748 /* If the ring is no longer full, clear tx_full and 749 call netif_wake_queue() */ 750 751 if (netif_queue_stopped(dev) && 752 ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE 753 < TX_QUEUE_LEN - 1 || np->speed == 10)) { 754 netif_wake_queue (dev); 755 } 756 } 757 758 static void 759 tx_error (struct net_device *dev, int tx_status) 760 { 761 struct netdev_private *np = netdev_priv(dev); 762 void __iomem *ioaddr = np->ioaddr; 763 int frame_id; 764 int i; 765 766 frame_id = (tx_status & 0xffff0000); 767 printk (KERN_ERR "%s: Transmit error, TxStatus %4.4x, FrameId %d.\n", 768 dev->name, tx_status, frame_id); 769 np->stats.tx_errors++; 770 /* Ttransmit Underrun */ 771 if (tx_status & 0x10) { 772 np->stats.tx_fifo_errors++; 773 dw16(TxStartThresh, dr16(TxStartThresh) + 0x10); 774 /* Transmit Underrun need to set TxReset, DMARest, FIFOReset */ 775 dw16(ASICCtrl + 2, 776 TxReset | DMAReset | FIFOReset | NetworkReset); 777 /* Wait for ResetBusy bit clear */ 778 for (i = 50; i > 0; i--) { 779 if (!(dr16(ASICCtrl + 2) & ResetBusy)) 780 break; 781 mdelay (1); 782 } 783 rio_free_tx (dev, 1); 784 /* Reset TFDListPtr */ 785 dw32(TFDListPtr0, np->tx_ring_dma + 786 np->old_tx * sizeof (struct netdev_desc)); 787 dw32(TFDListPtr1, 0); 788 789 /* Let TxStartThresh stay default value */ 790 } 791 /* Late Collision */ 792 if (tx_status & 0x04) { 793 np->stats.tx_fifo_errors++; 794 /* TxReset and clear FIFO */ 795 dw16(ASICCtrl + 2, TxReset | FIFOReset); 796 /* Wait reset done */ 797 for (i = 50; i > 0; i--) { 798 if (!(dr16(ASICCtrl + 2) & ResetBusy)) 799 break; 800 mdelay (1); 801 } 802 /* Let TxStartThresh stay default value */ 803 } 804 /* Maximum Collisions */ 805 #ifdef ETHER_STATS 806 if (tx_status & 0x08) 807 np->stats.collisions16++; 808 #else 809 if (tx_status & 0x08) 810 np->stats.collisions++; 811 #endif 812 /* Restart the Tx */ 813 dw32(MACCtrl, dr16(MACCtrl) | TxEnable); 814 } 815 816 static int 817 receive_packet (struct net_device *dev) 818 { 819 struct netdev_private *np = netdev_priv(dev); 820 int entry = np->cur_rx % RX_RING_SIZE; 821 int cnt = 30; 822 823 /* If RFDDone, FrameStart and FrameEnd set, there is a new packet in. */ 824 while (1) { 825 struct netdev_desc *desc = &np->rx_ring[entry]; 826 int pkt_len; 827 u64 frame_status; 828 829 if (!(desc->status & cpu_to_le64(RFDDone)) || 830 !(desc->status & cpu_to_le64(FrameStart)) || 831 !(desc->status & cpu_to_le64(FrameEnd))) 832 break; 833 834 /* Chip omits the CRC. */ 835 frame_status = le64_to_cpu(desc->status); 836 pkt_len = frame_status & 0xffff; 837 if (--cnt < 0) 838 break; 839 /* Update rx error statistics, drop packet. */ 840 if (frame_status & RFS_Errors) { 841 np->stats.rx_errors++; 842 if (frame_status & (RxRuntFrame | RxLengthError)) 843 np->stats.rx_length_errors++; 844 if (frame_status & RxFCSError) 845 np->stats.rx_crc_errors++; 846 if (frame_status & RxAlignmentError && np->speed != 1000) 847 np->stats.rx_frame_errors++; 848 if (frame_status & RxFIFOOverrun) 849 np->stats.rx_fifo_errors++; 850 } else { 851 struct sk_buff *skb; 852 853 /* Small skbuffs for short packets */ 854 if (pkt_len > copy_thresh) { 855 pci_unmap_single (np->pdev, 856 desc_to_dma(desc), 857 np->rx_buf_sz, 858 PCI_DMA_FROMDEVICE); 859 skb_put (skb = np->rx_skbuff[entry], pkt_len); 860 np->rx_skbuff[entry] = NULL; 861 } else if ((skb = netdev_alloc_skb_ip_align(dev, pkt_len))) { 862 pci_dma_sync_single_for_cpu(np->pdev, 863 desc_to_dma(desc), 864 np->rx_buf_sz, 865 PCI_DMA_FROMDEVICE); 866 skb_copy_to_linear_data (skb, 867 np->rx_skbuff[entry]->data, 868 pkt_len); 869 skb_put (skb, pkt_len); 870 pci_dma_sync_single_for_device(np->pdev, 871 desc_to_dma(desc), 872 np->rx_buf_sz, 873 PCI_DMA_FROMDEVICE); 874 } 875 skb->protocol = eth_type_trans (skb, dev); 876 #if 0 877 /* Checksum done by hw, but csum value unavailable. */ 878 if (np->pdev->pci_rev_id >= 0x0c && 879 !(frame_status & (TCPError | UDPError | IPError))) { 880 skb->ip_summed = CHECKSUM_UNNECESSARY; 881 } 882 #endif 883 netif_rx (skb); 884 } 885 entry = (entry + 1) % RX_RING_SIZE; 886 } 887 spin_lock(&np->rx_lock); 888 np->cur_rx = entry; 889 /* Re-allocate skbuffs to fill the descriptor ring */ 890 entry = np->old_rx; 891 while (entry != np->cur_rx) { 892 struct sk_buff *skb; 893 /* Dropped packets don't need to re-allocate */ 894 if (np->rx_skbuff[entry] == NULL) { 895 skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz); 896 if (skb == NULL) { 897 np->rx_ring[entry].fraginfo = 0; 898 printk (KERN_INFO 899 "%s: receive_packet: " 900 "Unable to re-allocate Rx skbuff.#%d\n", 901 dev->name, entry); 902 break; 903 } 904 np->rx_skbuff[entry] = skb; 905 np->rx_ring[entry].fraginfo = 906 cpu_to_le64 (pci_map_single 907 (np->pdev, skb->data, np->rx_buf_sz, 908 PCI_DMA_FROMDEVICE)); 909 } 910 np->rx_ring[entry].fraginfo |= 911 cpu_to_le64((u64)np->rx_buf_sz << 48); 912 np->rx_ring[entry].status = 0; 913 entry = (entry + 1) % RX_RING_SIZE; 914 } 915 np->old_rx = entry; 916 spin_unlock(&np->rx_lock); 917 return 0; 918 } 919 920 static void 921 rio_error (struct net_device *dev, int int_status) 922 { 923 struct netdev_private *np = netdev_priv(dev); 924 void __iomem *ioaddr = np->ioaddr; 925 u16 macctrl; 926 927 /* Link change event */ 928 if (int_status & LinkEvent) { 929 if (mii_wait_link (dev, 10) == 0) { 930 printk (KERN_INFO "%s: Link up\n", dev->name); 931 if (np->phy_media) 932 mii_get_media_pcs (dev); 933 else 934 mii_get_media (dev); 935 if (np->speed == 1000) 936 np->tx_coalesce = tx_coalesce; 937 else 938 np->tx_coalesce = 1; 939 macctrl = 0; 940 macctrl |= (np->vlan) ? AutoVLANuntagging : 0; 941 macctrl |= (np->full_duplex) ? DuplexSelect : 0; 942 macctrl |= (np->tx_flow) ? 943 TxFlowControlEnable : 0; 944 macctrl |= (np->rx_flow) ? 945 RxFlowControlEnable : 0; 946 dw16(MACCtrl, macctrl); 947 np->link_status = 1; 948 netif_carrier_on(dev); 949 } else { 950 printk (KERN_INFO "%s: Link off\n", dev->name); 951 np->link_status = 0; 952 netif_carrier_off(dev); 953 } 954 } 955 956 /* UpdateStats statistics registers */ 957 if (int_status & UpdateStats) { 958 get_stats (dev); 959 } 960 961 /* PCI Error, a catastronphic error related to the bus interface 962 occurs, set GlobalReset and HostReset to reset. */ 963 if (int_status & HostError) { 964 printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n", 965 dev->name, int_status); 966 dw16(ASICCtrl + 2, GlobalReset | HostReset); 967 mdelay (500); 968 } 969 } 970 971 static struct net_device_stats * 972 get_stats (struct net_device *dev) 973 { 974 struct netdev_private *np = netdev_priv(dev); 975 void __iomem *ioaddr = np->ioaddr; 976 #ifdef MEM_MAPPING 977 int i; 978 #endif 979 unsigned int stat_reg; 980 981 /* All statistics registers need to be acknowledged, 982 else statistic overflow could cause problems */ 983 984 np->stats.rx_packets += dr32(FramesRcvOk); 985 np->stats.tx_packets += dr32(FramesXmtOk); 986 np->stats.rx_bytes += dr32(OctetRcvOk); 987 np->stats.tx_bytes += dr32(OctetXmtOk); 988 989 np->stats.multicast = dr32(McstFramesRcvdOk); 990 np->stats.collisions += dr32(SingleColFrames) 991 + dr32(MultiColFrames); 992 993 /* detailed tx errors */ 994 stat_reg = dr16(FramesAbortXSColls); 995 np->stats.tx_aborted_errors += stat_reg; 996 np->stats.tx_errors += stat_reg; 997 998 stat_reg = dr16(CarrierSenseErrors); 999 np->stats.tx_carrier_errors += stat_reg; 1000 np->stats.tx_errors += stat_reg; 1001 1002 /* Clear all other statistic register. */ 1003 dr32(McstOctetXmtOk); 1004 dr16(BcstFramesXmtdOk); 1005 dr32(McstFramesXmtdOk); 1006 dr16(BcstFramesRcvdOk); 1007 dr16(MacControlFramesRcvd); 1008 dr16(FrameTooLongErrors); 1009 dr16(InRangeLengthErrors); 1010 dr16(FramesCheckSeqErrors); 1011 dr16(FramesLostRxErrors); 1012 dr32(McstOctetXmtOk); 1013 dr32(BcstOctetXmtOk); 1014 dr32(McstFramesXmtdOk); 1015 dr32(FramesWDeferredXmt); 1016 dr32(LateCollisions); 1017 dr16(BcstFramesXmtdOk); 1018 dr16(MacControlFramesXmtd); 1019 dr16(FramesWEXDeferal); 1020 1021 #ifdef MEM_MAPPING 1022 for (i = 0x100; i <= 0x150; i += 4) 1023 dr32(i); 1024 #endif 1025 dr16(TxJumboFrames); 1026 dr16(RxJumboFrames); 1027 dr16(TCPCheckSumErrors); 1028 dr16(UDPCheckSumErrors); 1029 dr16(IPCheckSumErrors); 1030 return &np->stats; 1031 } 1032 1033 static int 1034 clear_stats (struct net_device *dev) 1035 { 1036 struct netdev_private *np = netdev_priv(dev); 1037 void __iomem *ioaddr = np->ioaddr; 1038 #ifdef MEM_MAPPING 1039 int i; 1040 #endif 1041 1042 /* All statistics registers need to be acknowledged, 1043 else statistic overflow could cause problems */ 1044 dr32(FramesRcvOk); 1045 dr32(FramesXmtOk); 1046 dr32(OctetRcvOk); 1047 dr32(OctetXmtOk); 1048 1049 dr32(McstFramesRcvdOk); 1050 dr32(SingleColFrames); 1051 dr32(MultiColFrames); 1052 dr32(LateCollisions); 1053 /* detailed rx errors */ 1054 dr16(FrameTooLongErrors); 1055 dr16(InRangeLengthErrors); 1056 dr16(FramesCheckSeqErrors); 1057 dr16(FramesLostRxErrors); 1058 1059 /* detailed tx errors */ 1060 dr16(FramesAbortXSColls); 1061 dr16(CarrierSenseErrors); 1062 1063 /* Clear all other statistic register. */ 1064 dr32(McstOctetXmtOk); 1065 dr16(BcstFramesXmtdOk); 1066 dr32(McstFramesXmtdOk); 1067 dr16(BcstFramesRcvdOk); 1068 dr16(MacControlFramesRcvd); 1069 dr32(McstOctetXmtOk); 1070 dr32(BcstOctetXmtOk); 1071 dr32(McstFramesXmtdOk); 1072 dr32(FramesWDeferredXmt); 1073 dr16(BcstFramesXmtdOk); 1074 dr16(MacControlFramesXmtd); 1075 dr16(FramesWEXDeferal); 1076 #ifdef MEM_MAPPING 1077 for (i = 0x100; i <= 0x150; i += 4) 1078 dr32(i); 1079 #endif 1080 dr16(TxJumboFrames); 1081 dr16(RxJumboFrames); 1082 dr16(TCPCheckSumErrors); 1083 dr16(UDPCheckSumErrors); 1084 dr16(IPCheckSumErrors); 1085 return 0; 1086 } 1087 1088 1089 static int 1090 change_mtu (struct net_device *dev, int new_mtu) 1091 { 1092 struct netdev_private *np = netdev_priv(dev); 1093 int max = (np->jumbo) ? MAX_JUMBO : 1536; 1094 1095 if ((new_mtu < 68) || (new_mtu > max)) { 1096 return -EINVAL; 1097 } 1098 1099 dev->mtu = new_mtu; 1100 1101 return 0; 1102 } 1103 1104 static void 1105 set_multicast (struct net_device *dev) 1106 { 1107 struct netdev_private *np = netdev_priv(dev); 1108 void __iomem *ioaddr = np->ioaddr; 1109 u32 hash_table[2]; 1110 u16 rx_mode = 0; 1111 1112 hash_table[0] = hash_table[1] = 0; 1113 /* RxFlowcontrol DA: 01-80-C2-00-00-01. Hash index=0x39 */ 1114 hash_table[1] |= 0x02000000; 1115 if (dev->flags & IFF_PROMISC) { 1116 /* Receive all frames promiscuously. */ 1117 rx_mode = ReceiveAllFrames; 1118 } else if ((dev->flags & IFF_ALLMULTI) || 1119 (netdev_mc_count(dev) > multicast_filter_limit)) { 1120 /* Receive broadcast and multicast frames */ 1121 rx_mode = ReceiveBroadcast | ReceiveMulticast | ReceiveUnicast; 1122 } else if (!netdev_mc_empty(dev)) { 1123 struct netdev_hw_addr *ha; 1124 /* Receive broadcast frames and multicast frames filtering 1125 by Hashtable */ 1126 rx_mode = 1127 ReceiveBroadcast | ReceiveMulticastHash | ReceiveUnicast; 1128 netdev_for_each_mc_addr(ha, dev) { 1129 int bit, index = 0; 1130 int crc = ether_crc_le(ETH_ALEN, ha->addr); 1131 /* The inverted high significant 6 bits of CRC are 1132 used as an index to hashtable */ 1133 for (bit = 0; bit < 6; bit++) 1134 if (crc & (1 << (31 - bit))) 1135 index |= (1 << bit); 1136 hash_table[index / 32] |= (1 << (index % 32)); 1137 } 1138 } else { 1139 rx_mode = ReceiveBroadcast | ReceiveUnicast; 1140 } 1141 if (np->vlan) { 1142 /* ReceiveVLANMatch field in ReceiveMode */ 1143 rx_mode |= ReceiveVLANMatch; 1144 } 1145 1146 dw32(HashTable0, hash_table[0]); 1147 dw32(HashTable1, hash_table[1]); 1148 dw16(ReceiveMode, rx_mode); 1149 } 1150 1151 static void rio_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 1152 { 1153 struct netdev_private *np = netdev_priv(dev); 1154 1155 strlcpy(info->driver, "dl2k", sizeof(info->driver)); 1156 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 1157 strlcpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info)); 1158 } 1159 1160 static int rio_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1161 { 1162 struct netdev_private *np = netdev_priv(dev); 1163 if (np->phy_media) { 1164 /* fiber device */ 1165 cmd->supported = SUPPORTED_Autoneg | SUPPORTED_FIBRE; 1166 cmd->advertising= ADVERTISED_Autoneg | ADVERTISED_FIBRE; 1167 cmd->port = PORT_FIBRE; 1168 cmd->transceiver = XCVR_INTERNAL; 1169 } else { 1170 /* copper device */ 1171 cmd->supported = SUPPORTED_10baseT_Half | 1172 SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half 1173 | SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full | 1174 SUPPORTED_Autoneg | SUPPORTED_MII; 1175 cmd->advertising = ADVERTISED_10baseT_Half | 1176 ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Half | 1177 ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full| 1178 ADVERTISED_Autoneg | ADVERTISED_MII; 1179 cmd->port = PORT_MII; 1180 cmd->transceiver = XCVR_INTERNAL; 1181 } 1182 if ( np->link_status ) { 1183 ethtool_cmd_speed_set(cmd, np->speed); 1184 cmd->duplex = np->full_duplex ? DUPLEX_FULL : DUPLEX_HALF; 1185 } else { 1186 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN); 1187 cmd->duplex = DUPLEX_UNKNOWN; 1188 } 1189 if ( np->an_enable) 1190 cmd->autoneg = AUTONEG_ENABLE; 1191 else 1192 cmd->autoneg = AUTONEG_DISABLE; 1193 1194 cmd->phy_address = np->phy_addr; 1195 return 0; 1196 } 1197 1198 static int rio_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1199 { 1200 struct netdev_private *np = netdev_priv(dev); 1201 netif_carrier_off(dev); 1202 if (cmd->autoneg == AUTONEG_ENABLE) { 1203 if (np->an_enable) 1204 return 0; 1205 else { 1206 np->an_enable = 1; 1207 mii_set_media(dev); 1208 return 0; 1209 } 1210 } else { 1211 np->an_enable = 0; 1212 if (np->speed == 1000) { 1213 ethtool_cmd_speed_set(cmd, SPEED_100); 1214 cmd->duplex = DUPLEX_FULL; 1215 printk("Warning!! Can't disable Auto negotiation in 1000Mbps, change to Manual 100Mbps, Full duplex.\n"); 1216 } 1217 switch (ethtool_cmd_speed(cmd)) { 1218 case SPEED_10: 1219 np->speed = 10; 1220 np->full_duplex = (cmd->duplex == DUPLEX_FULL); 1221 break; 1222 case SPEED_100: 1223 np->speed = 100; 1224 np->full_duplex = (cmd->duplex == DUPLEX_FULL); 1225 break; 1226 case SPEED_1000: /* not supported */ 1227 default: 1228 return -EINVAL; 1229 } 1230 mii_set_media(dev); 1231 } 1232 return 0; 1233 } 1234 1235 static u32 rio_get_link(struct net_device *dev) 1236 { 1237 struct netdev_private *np = netdev_priv(dev); 1238 return np->link_status; 1239 } 1240 1241 static const struct ethtool_ops ethtool_ops = { 1242 .get_drvinfo = rio_get_drvinfo, 1243 .get_settings = rio_get_settings, 1244 .set_settings = rio_set_settings, 1245 .get_link = rio_get_link, 1246 }; 1247 1248 static int 1249 rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd) 1250 { 1251 int phy_addr; 1252 struct netdev_private *np = netdev_priv(dev); 1253 struct mii_ioctl_data *miidata = if_mii(rq); 1254 1255 phy_addr = np->phy_addr; 1256 switch (cmd) { 1257 case SIOCGMIIPHY: 1258 miidata->phy_id = phy_addr; 1259 break; 1260 case SIOCGMIIREG: 1261 miidata->val_out = mii_read (dev, phy_addr, miidata->reg_num); 1262 break; 1263 case SIOCSMIIREG: 1264 if (!capable(CAP_NET_ADMIN)) 1265 return -EPERM; 1266 mii_write (dev, phy_addr, miidata->reg_num, miidata->val_in); 1267 break; 1268 default: 1269 return -EOPNOTSUPP; 1270 } 1271 return 0; 1272 } 1273 1274 #define EEP_READ 0x0200 1275 #define EEP_BUSY 0x8000 1276 /* Read the EEPROM word */ 1277 /* We use I/O instruction to read/write eeprom to avoid fail on some machines */ 1278 static int read_eeprom(struct netdev_private *np, int eep_addr) 1279 { 1280 void __iomem *ioaddr = np->eeprom_addr; 1281 int i = 1000; 1282 1283 dw16(EepromCtrl, EEP_READ | (eep_addr & 0xff)); 1284 while (i-- > 0) { 1285 if (!(dr16(EepromCtrl) & EEP_BUSY)) 1286 return dr16(EepromData); 1287 } 1288 return 0; 1289 } 1290 1291 enum phy_ctrl_bits { 1292 MII_READ = 0x00, MII_CLK = 0x01, MII_DATA1 = 0x02, MII_WRITE = 0x04, 1293 MII_DUPLEX = 0x08, 1294 }; 1295 1296 #define mii_delay() dr8(PhyCtrl) 1297 static void 1298 mii_sendbit (struct net_device *dev, u32 data) 1299 { 1300 struct netdev_private *np = netdev_priv(dev); 1301 void __iomem *ioaddr = np->ioaddr; 1302 1303 data = ((data) ? MII_DATA1 : 0) | (dr8(PhyCtrl) & 0xf8) | MII_WRITE; 1304 dw8(PhyCtrl, data); 1305 mii_delay (); 1306 dw8(PhyCtrl, data | MII_CLK); 1307 mii_delay (); 1308 } 1309 1310 static int 1311 mii_getbit (struct net_device *dev) 1312 { 1313 struct netdev_private *np = netdev_priv(dev); 1314 void __iomem *ioaddr = np->ioaddr; 1315 u8 data; 1316 1317 data = (dr8(PhyCtrl) & 0xf8) | MII_READ; 1318 dw8(PhyCtrl, data); 1319 mii_delay (); 1320 dw8(PhyCtrl, data | MII_CLK); 1321 mii_delay (); 1322 return (dr8(PhyCtrl) >> 1) & 1; 1323 } 1324 1325 static void 1326 mii_send_bits (struct net_device *dev, u32 data, int len) 1327 { 1328 int i; 1329 1330 for (i = len - 1; i >= 0; i--) { 1331 mii_sendbit (dev, data & (1 << i)); 1332 } 1333 } 1334 1335 static int 1336 mii_read (struct net_device *dev, int phy_addr, int reg_num) 1337 { 1338 u32 cmd; 1339 int i; 1340 u32 retval = 0; 1341 1342 /* Preamble */ 1343 mii_send_bits (dev, 0xffffffff, 32); 1344 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */ 1345 /* ST,OP = 0110'b for read operation */ 1346 cmd = (0x06 << 10 | phy_addr << 5 | reg_num); 1347 mii_send_bits (dev, cmd, 14); 1348 /* Turnaround */ 1349 if (mii_getbit (dev)) 1350 goto err_out; 1351 /* Read data */ 1352 for (i = 0; i < 16; i++) { 1353 retval |= mii_getbit (dev); 1354 retval <<= 1; 1355 } 1356 /* End cycle */ 1357 mii_getbit (dev); 1358 return (retval >> 1) & 0xffff; 1359 1360 err_out: 1361 return 0; 1362 } 1363 static int 1364 mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data) 1365 { 1366 u32 cmd; 1367 1368 /* Preamble */ 1369 mii_send_bits (dev, 0xffffffff, 32); 1370 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */ 1371 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */ 1372 cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data; 1373 mii_send_bits (dev, cmd, 32); 1374 /* End cycle */ 1375 mii_getbit (dev); 1376 return 0; 1377 } 1378 static int 1379 mii_wait_link (struct net_device *dev, int wait) 1380 { 1381 __u16 bmsr; 1382 int phy_addr; 1383 struct netdev_private *np; 1384 1385 np = netdev_priv(dev); 1386 phy_addr = np->phy_addr; 1387 1388 do { 1389 bmsr = mii_read (dev, phy_addr, MII_BMSR); 1390 if (bmsr & BMSR_LSTATUS) 1391 return 0; 1392 mdelay (1); 1393 } while (--wait > 0); 1394 return -1; 1395 } 1396 static int 1397 mii_get_media (struct net_device *dev) 1398 { 1399 __u16 negotiate; 1400 __u16 bmsr; 1401 __u16 mscr; 1402 __u16 mssr; 1403 int phy_addr; 1404 struct netdev_private *np; 1405 1406 np = netdev_priv(dev); 1407 phy_addr = np->phy_addr; 1408 1409 bmsr = mii_read (dev, phy_addr, MII_BMSR); 1410 if (np->an_enable) { 1411 if (!(bmsr & BMSR_ANEGCOMPLETE)) { 1412 /* Auto-Negotiation not completed */ 1413 return -1; 1414 } 1415 negotiate = mii_read (dev, phy_addr, MII_ADVERTISE) & 1416 mii_read (dev, phy_addr, MII_LPA); 1417 mscr = mii_read (dev, phy_addr, MII_CTRL1000); 1418 mssr = mii_read (dev, phy_addr, MII_STAT1000); 1419 if (mscr & ADVERTISE_1000FULL && mssr & LPA_1000FULL) { 1420 np->speed = 1000; 1421 np->full_duplex = 1; 1422 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n"); 1423 } else if (mscr & ADVERTISE_1000HALF && mssr & LPA_1000HALF) { 1424 np->speed = 1000; 1425 np->full_duplex = 0; 1426 printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n"); 1427 } else if (negotiate & ADVERTISE_100FULL) { 1428 np->speed = 100; 1429 np->full_duplex = 1; 1430 printk (KERN_INFO "Auto 100 Mbps, Full duplex\n"); 1431 } else if (negotiate & ADVERTISE_100HALF) { 1432 np->speed = 100; 1433 np->full_duplex = 0; 1434 printk (KERN_INFO "Auto 100 Mbps, Half duplex\n"); 1435 } else if (negotiate & ADVERTISE_10FULL) { 1436 np->speed = 10; 1437 np->full_duplex = 1; 1438 printk (KERN_INFO "Auto 10 Mbps, Full duplex\n"); 1439 } else if (negotiate & ADVERTISE_10HALF) { 1440 np->speed = 10; 1441 np->full_duplex = 0; 1442 printk (KERN_INFO "Auto 10 Mbps, Half duplex\n"); 1443 } 1444 if (negotiate & ADVERTISE_PAUSE_CAP) { 1445 np->tx_flow &= 1; 1446 np->rx_flow &= 1; 1447 } else if (negotiate & ADVERTISE_PAUSE_ASYM) { 1448 np->tx_flow = 0; 1449 np->rx_flow &= 1; 1450 } 1451 /* else tx_flow, rx_flow = user select */ 1452 } else { 1453 __u16 bmcr = mii_read (dev, phy_addr, MII_BMCR); 1454 switch (bmcr & (BMCR_SPEED100 | BMCR_SPEED1000)) { 1455 case BMCR_SPEED1000: 1456 printk (KERN_INFO "Operating at 1000 Mbps, "); 1457 break; 1458 case BMCR_SPEED100: 1459 printk (KERN_INFO "Operating at 100 Mbps, "); 1460 break; 1461 case 0: 1462 printk (KERN_INFO "Operating at 10 Mbps, "); 1463 } 1464 if (bmcr & BMCR_FULLDPLX) { 1465 printk (KERN_CONT "Full duplex\n"); 1466 } else { 1467 printk (KERN_CONT "Half duplex\n"); 1468 } 1469 } 1470 if (np->tx_flow) 1471 printk(KERN_INFO "Enable Tx Flow Control\n"); 1472 else 1473 printk(KERN_INFO "Disable Tx Flow Control\n"); 1474 if (np->rx_flow) 1475 printk(KERN_INFO "Enable Rx Flow Control\n"); 1476 else 1477 printk(KERN_INFO "Disable Rx Flow Control\n"); 1478 1479 return 0; 1480 } 1481 1482 static int 1483 mii_set_media (struct net_device *dev) 1484 { 1485 __u16 pscr; 1486 __u16 bmcr; 1487 __u16 bmsr; 1488 __u16 anar; 1489 int phy_addr; 1490 struct netdev_private *np; 1491 np = netdev_priv(dev); 1492 phy_addr = np->phy_addr; 1493 1494 /* Does user set speed? */ 1495 if (np->an_enable) { 1496 /* Advertise capabilities */ 1497 bmsr = mii_read (dev, phy_addr, MII_BMSR); 1498 anar = mii_read (dev, phy_addr, MII_ADVERTISE) & 1499 ~(ADVERTISE_100FULL | ADVERTISE_10FULL | 1500 ADVERTISE_100HALF | ADVERTISE_10HALF | 1501 ADVERTISE_100BASE4); 1502 if (bmsr & BMSR_100FULL) 1503 anar |= ADVERTISE_100FULL; 1504 if (bmsr & BMSR_100HALF) 1505 anar |= ADVERTISE_100HALF; 1506 if (bmsr & BMSR_100BASE4) 1507 anar |= ADVERTISE_100BASE4; 1508 if (bmsr & BMSR_10FULL) 1509 anar |= ADVERTISE_10FULL; 1510 if (bmsr & BMSR_10HALF) 1511 anar |= ADVERTISE_10HALF; 1512 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 1513 mii_write (dev, phy_addr, MII_ADVERTISE, anar); 1514 1515 /* Enable Auto crossover */ 1516 pscr = mii_read (dev, phy_addr, MII_PHY_SCR); 1517 pscr |= 3 << 5; /* 11'b */ 1518 mii_write (dev, phy_addr, MII_PHY_SCR, pscr); 1519 1520 /* Soft reset PHY */ 1521 mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET); 1522 bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET; 1523 mii_write (dev, phy_addr, MII_BMCR, bmcr); 1524 mdelay(1); 1525 } else { 1526 /* Force speed setting */ 1527 /* 1) Disable Auto crossover */ 1528 pscr = mii_read (dev, phy_addr, MII_PHY_SCR); 1529 pscr &= ~(3 << 5); 1530 mii_write (dev, phy_addr, MII_PHY_SCR, pscr); 1531 1532 /* 2) PHY Reset */ 1533 bmcr = mii_read (dev, phy_addr, MII_BMCR); 1534 bmcr |= BMCR_RESET; 1535 mii_write (dev, phy_addr, MII_BMCR, bmcr); 1536 1537 /* 3) Power Down */ 1538 bmcr = 0x1940; /* must be 0x1940 */ 1539 mii_write (dev, phy_addr, MII_BMCR, bmcr); 1540 mdelay (100); /* wait a certain time */ 1541 1542 /* 4) Advertise nothing */ 1543 mii_write (dev, phy_addr, MII_ADVERTISE, 0); 1544 1545 /* 5) Set media and Power Up */ 1546 bmcr = BMCR_PDOWN; 1547 if (np->speed == 100) { 1548 bmcr |= BMCR_SPEED100; 1549 printk (KERN_INFO "Manual 100 Mbps, "); 1550 } else if (np->speed == 10) { 1551 printk (KERN_INFO "Manual 10 Mbps, "); 1552 } 1553 if (np->full_duplex) { 1554 bmcr |= BMCR_FULLDPLX; 1555 printk (KERN_CONT "Full duplex\n"); 1556 } else { 1557 printk (KERN_CONT "Half duplex\n"); 1558 } 1559 #if 0 1560 /* Set 1000BaseT Master/Slave setting */ 1561 mscr = mii_read (dev, phy_addr, MII_CTRL1000); 1562 mscr |= MII_MSCR_CFG_ENABLE; 1563 mscr &= ~MII_MSCR_CFG_VALUE = 0; 1564 #endif 1565 mii_write (dev, phy_addr, MII_BMCR, bmcr); 1566 mdelay(10); 1567 } 1568 return 0; 1569 } 1570 1571 static int 1572 mii_get_media_pcs (struct net_device *dev) 1573 { 1574 __u16 negotiate; 1575 __u16 bmsr; 1576 int phy_addr; 1577 struct netdev_private *np; 1578 1579 np = netdev_priv(dev); 1580 phy_addr = np->phy_addr; 1581 1582 bmsr = mii_read (dev, phy_addr, PCS_BMSR); 1583 if (np->an_enable) { 1584 if (!(bmsr & BMSR_ANEGCOMPLETE)) { 1585 /* Auto-Negotiation not completed */ 1586 return -1; 1587 } 1588 negotiate = mii_read (dev, phy_addr, PCS_ANAR) & 1589 mii_read (dev, phy_addr, PCS_ANLPAR); 1590 np->speed = 1000; 1591 if (negotiate & PCS_ANAR_FULL_DUPLEX) { 1592 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n"); 1593 np->full_duplex = 1; 1594 } else { 1595 printk (KERN_INFO "Auto 1000 Mbps, half duplex\n"); 1596 np->full_duplex = 0; 1597 } 1598 if (negotiate & PCS_ANAR_PAUSE) { 1599 np->tx_flow &= 1; 1600 np->rx_flow &= 1; 1601 } else if (negotiate & PCS_ANAR_ASYMMETRIC) { 1602 np->tx_flow = 0; 1603 np->rx_flow &= 1; 1604 } 1605 /* else tx_flow, rx_flow = user select */ 1606 } else { 1607 __u16 bmcr = mii_read (dev, phy_addr, PCS_BMCR); 1608 printk (KERN_INFO "Operating at 1000 Mbps, "); 1609 if (bmcr & BMCR_FULLDPLX) { 1610 printk (KERN_CONT "Full duplex\n"); 1611 } else { 1612 printk (KERN_CONT "Half duplex\n"); 1613 } 1614 } 1615 if (np->tx_flow) 1616 printk(KERN_INFO "Enable Tx Flow Control\n"); 1617 else 1618 printk(KERN_INFO "Disable Tx Flow Control\n"); 1619 if (np->rx_flow) 1620 printk(KERN_INFO "Enable Rx Flow Control\n"); 1621 else 1622 printk(KERN_INFO "Disable Rx Flow Control\n"); 1623 1624 return 0; 1625 } 1626 1627 static int 1628 mii_set_media_pcs (struct net_device *dev) 1629 { 1630 __u16 bmcr; 1631 __u16 esr; 1632 __u16 anar; 1633 int phy_addr; 1634 struct netdev_private *np; 1635 np = netdev_priv(dev); 1636 phy_addr = np->phy_addr; 1637 1638 /* Auto-Negotiation? */ 1639 if (np->an_enable) { 1640 /* Advertise capabilities */ 1641 esr = mii_read (dev, phy_addr, PCS_ESR); 1642 anar = mii_read (dev, phy_addr, MII_ADVERTISE) & 1643 ~PCS_ANAR_HALF_DUPLEX & 1644 ~PCS_ANAR_FULL_DUPLEX; 1645 if (esr & (MII_ESR_1000BT_HD | MII_ESR_1000BX_HD)) 1646 anar |= PCS_ANAR_HALF_DUPLEX; 1647 if (esr & (MII_ESR_1000BT_FD | MII_ESR_1000BX_FD)) 1648 anar |= PCS_ANAR_FULL_DUPLEX; 1649 anar |= PCS_ANAR_PAUSE | PCS_ANAR_ASYMMETRIC; 1650 mii_write (dev, phy_addr, MII_ADVERTISE, anar); 1651 1652 /* Soft reset PHY */ 1653 mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET); 1654 bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET; 1655 mii_write (dev, phy_addr, MII_BMCR, bmcr); 1656 mdelay(1); 1657 } else { 1658 /* Force speed setting */ 1659 /* PHY Reset */ 1660 bmcr = BMCR_RESET; 1661 mii_write (dev, phy_addr, MII_BMCR, bmcr); 1662 mdelay(10); 1663 if (np->full_duplex) { 1664 bmcr = BMCR_FULLDPLX; 1665 printk (KERN_INFO "Manual full duplex\n"); 1666 } else { 1667 bmcr = 0; 1668 printk (KERN_INFO "Manual half duplex\n"); 1669 } 1670 mii_write (dev, phy_addr, MII_BMCR, bmcr); 1671 mdelay(10); 1672 1673 /* Advertise nothing */ 1674 mii_write (dev, phy_addr, MII_ADVERTISE, 0); 1675 } 1676 return 0; 1677 } 1678 1679 1680 static int 1681 rio_close (struct net_device *dev) 1682 { 1683 struct netdev_private *np = netdev_priv(dev); 1684 void __iomem *ioaddr = np->ioaddr; 1685 1686 struct pci_dev *pdev = np->pdev; 1687 struct sk_buff *skb; 1688 int i; 1689 1690 netif_stop_queue (dev); 1691 1692 /* Disable interrupts */ 1693 dw16(IntEnable, 0); 1694 1695 /* Stop Tx and Rx logics */ 1696 dw32(MACCtrl, TxDisable | RxDisable | StatsDisable); 1697 1698 free_irq(pdev->irq, dev); 1699 del_timer_sync (&np->timer); 1700 1701 /* Free all the skbuffs in the queue. */ 1702 for (i = 0; i < RX_RING_SIZE; i++) { 1703 skb = np->rx_skbuff[i]; 1704 if (skb) { 1705 pci_unmap_single(pdev, desc_to_dma(&np->rx_ring[i]), 1706 skb->len, PCI_DMA_FROMDEVICE); 1707 dev_kfree_skb (skb); 1708 np->rx_skbuff[i] = NULL; 1709 } 1710 np->rx_ring[i].status = 0; 1711 np->rx_ring[i].fraginfo = 0; 1712 } 1713 for (i = 0; i < TX_RING_SIZE; i++) { 1714 skb = np->tx_skbuff[i]; 1715 if (skb) { 1716 pci_unmap_single(pdev, desc_to_dma(&np->tx_ring[i]), 1717 skb->len, PCI_DMA_TODEVICE); 1718 dev_kfree_skb (skb); 1719 np->tx_skbuff[i] = NULL; 1720 } 1721 } 1722 1723 return 0; 1724 } 1725 1726 static void 1727 rio_remove1 (struct pci_dev *pdev) 1728 { 1729 struct net_device *dev = pci_get_drvdata (pdev); 1730 1731 if (dev) { 1732 struct netdev_private *np = netdev_priv(dev); 1733 1734 unregister_netdev (dev); 1735 pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring, 1736 np->rx_ring_dma); 1737 pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring, 1738 np->tx_ring_dma); 1739 #ifdef MEM_MAPPING 1740 pci_iounmap(pdev, np->ioaddr); 1741 #endif 1742 pci_iounmap(pdev, np->eeprom_addr); 1743 free_netdev (dev); 1744 pci_release_regions (pdev); 1745 pci_disable_device (pdev); 1746 } 1747 } 1748 1749 static struct pci_driver rio_driver = { 1750 .name = "dl2k", 1751 .id_table = rio_pci_tbl, 1752 .probe = rio_probe1, 1753 .remove = rio_remove1, 1754 }; 1755 1756 module_pci_driver(rio_driver); 1757 /* 1758 1759 Compile command: 1760 1761 gcc -D__KERNEL__ -DMODULE -I/usr/src/linux/include -Wall -Wstrict-prototypes -O2 -c dl2k.c 1762 1763 Read Documentation/networking/dl2k.txt for details. 1764 1765 */ 1766 1767