1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 
4 
5 */
6 
7 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8 
9 #define DRV_NAME	"uli526x"
10 
11 #include <linux/module.h>
12 
13 #include <linux/kernel.h>
14 #include <linux/string.h>
15 #include <linux/timer.h>
16 #include <linux/errno.h>
17 #include <linux/ioport.h>
18 #include <linux/interrupt.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/ethtool.h>
24 #include <linux/skbuff.h>
25 #include <linux/delay.h>
26 #include <linux/spinlock.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/bitops.h>
29 
30 #include <asm/processor.h>
31 #include <asm/io.h>
32 #include <asm/dma.h>
33 #include <linux/uaccess.h>
34 
35 #define uw32(reg, val)	iowrite32(val, ioaddr + (reg))
36 #define ur32(reg)	ioread32(ioaddr + (reg))
37 
38 /* Board/System/Debug information/definition ---------------- */
39 #define PCI_ULI5261_ID  0x526110B9	/* ULi M5261 ID*/
40 #define PCI_ULI5263_ID  0x526310B9	/* ULi M5263 ID*/
41 
42 #define ULI526X_IO_SIZE 0x100
43 #define TX_DESC_CNT     0x20            /* Allocated Tx descriptors */
44 #define RX_DESC_CNT     0x30            /* Allocated Rx descriptors */
45 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2)	/* Max TX packet count */
46 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3)	/* TX wakeup count */
47 #define DESC_ALL_CNT    (TX_DESC_CNT + RX_DESC_CNT)
48 #define TX_BUF_ALLOC    0x600
49 #define RX_ALLOC_SIZE   0x620
50 #define ULI526X_RESET    1
51 #define CR0_DEFAULT     0
52 #define CR6_DEFAULT     0x22200000
53 #define CR7_DEFAULT     0x180c1
54 #define CR15_DEFAULT    0x06            /* TxJabber RxWatchdog */
55 #define TDES0_ERR_MASK  0x4302          /* TXJT, LC, EC, FUE */
56 #define MAX_PACKET_SIZE 1514
57 #define ULI5261_MAX_MULTICAST 14
58 #define RX_COPY_SIZE	100
59 #define MAX_CHECK_PACKET 0x8000
60 
61 #define ULI526X_10MHF      0
62 #define ULI526X_100MHF     1
63 #define ULI526X_10MFD      4
64 #define ULI526X_100MFD     5
65 #define ULI526X_AUTO       8
66 
67 #define ULI526X_TXTH_72	0x400000	/* TX TH 72 byte */
68 #define ULI526X_TXTH_96	0x404000	/* TX TH 96 byte */
69 #define ULI526X_TXTH_128	0x0000		/* TX TH 128 byte */
70 #define ULI526X_TXTH_256	0x4000		/* TX TH 256 byte */
71 #define ULI526X_TXTH_512	0x8000		/* TX TH 512 byte */
72 #define ULI526X_TXTH_1K	0xC000		/* TX TH 1K  byte */
73 
74 #define ULI526X_TIMER_WUT  (jiffies + HZ * 1)/* timer wakeup time : 1 second */
75 #define ULI526X_TX_TIMEOUT ((16*HZ)/2)	/* tx packet time-out time 8 s" */
76 #define ULI526X_TX_KICK 	(4*HZ/2)	/* tx packet Kick-out time 2 s" */
77 
78 #define ULI526X_DBUG(dbug_now, msg, value)			\
79 do {								\
80 	if (uli526x_debug || (dbug_now))			\
81 		pr_err("%s %lx\n", (msg), (long) (value));	\
82 } while (0)
83 
84 #define SHOW_MEDIA_TYPE(mode)					\
85 	pr_err("Change Speed to %sMhz %s duplex\n",		\
86 	       mode & 1 ? "100" : "10",				\
87 	       mode & 4 ? "full" : "half");
88 
89 
90 /* CR9 definition: SROM/MII */
91 #define CR9_SROM_READ   0x4800
92 #define CR9_SRCS        0x1
93 #define CR9_SRCLK       0x2
94 #define CR9_CRDOUT      0x8
95 #define SROM_DATA_0     0x0
96 #define SROM_DATA_1     0x4
97 #define PHY_DATA_1      0x20000
98 #define PHY_DATA_0      0x00000
99 #define MDCLKH          0x10000
100 
101 #define PHY_POWER_DOWN	0x800
102 
103 #define SROM_V41_CODE   0x14
104 
105 /* Structure/enum declaration ------------------------------- */
106 struct tx_desc {
107         __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
108         char *tx_buf_ptr;               /* Data for us */
109         struct tx_desc *next_tx_desc;
110 } __attribute__(( aligned(32) ));
111 
112 struct rx_desc {
113 	__le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
114 	struct sk_buff *rx_skb_ptr;	/* Data for us */
115 	struct rx_desc *next_rx_desc;
116 } __attribute__(( aligned(32) ));
117 
118 struct uli526x_board_info {
119 	struct uli_phy_ops {
120 		void (*write)(struct uli526x_board_info *, u8, u8, u16);
121 		u16 (*read)(struct uli526x_board_info *, u8, u8);
122 	} phy;
123 	struct net_device *next_dev;	/* next device */
124 	struct pci_dev *pdev;		/* PCI device */
125 	spinlock_t lock;
126 
127 	void __iomem *ioaddr;		/* I/O base address */
128 	u32 cr0_data;
129 	u32 cr5_data;
130 	u32 cr6_data;
131 	u32 cr7_data;
132 	u32 cr15_data;
133 
134 	/* pointer for memory physical address */
135 	dma_addr_t buf_pool_dma_ptr;	/* Tx buffer pool memory */
136 	dma_addr_t buf_pool_dma_start;	/* Tx buffer pool align dword */
137 	dma_addr_t desc_pool_dma_ptr;	/* descriptor pool memory */
138 	dma_addr_t first_tx_desc_dma;
139 	dma_addr_t first_rx_desc_dma;
140 
141 	/* descriptor pointer */
142 	unsigned char *buf_pool_ptr;	/* Tx buffer pool memory */
143 	unsigned char *buf_pool_start;	/* Tx buffer pool align dword */
144 	unsigned char *desc_pool_ptr;	/* descriptor pool memory */
145 	struct tx_desc *first_tx_desc;
146 	struct tx_desc *tx_insert_ptr;
147 	struct tx_desc *tx_remove_ptr;
148 	struct rx_desc *first_rx_desc;
149 	struct rx_desc *rx_insert_ptr;
150 	struct rx_desc *rx_ready_ptr;	/* packet come pointer */
151 	unsigned long tx_packet_cnt;	/* transmitted packet count */
152 	unsigned long rx_avail_cnt;	/* available rx descriptor count */
153 	unsigned long interval_rx_cnt;	/* rx packet count a callback time */
154 
155 	u16 dbug_cnt;
156 	u16 NIC_capability;		/* NIC media capability */
157 	u16 PHY_reg4;			/* Saved Phyxcer register 4 value */
158 
159 	u8 media_mode;			/* user specify media mode */
160 	u8 op_mode;			/* real work media mode */
161 	u8 phy_addr;
162 	u8 link_failed;			/* Ever link failed */
163 	u8 wait_reset;			/* Hardware failed, need to reset */
164 	struct timer_list timer;
165 
166 	/* Driver defined statistic counter */
167 	unsigned long tx_fifo_underrun;
168 	unsigned long tx_loss_carrier;
169 	unsigned long tx_no_carrier;
170 	unsigned long tx_late_collision;
171 	unsigned long tx_excessive_collision;
172 	unsigned long tx_jabber_timeout;
173 	unsigned long reset_count;
174 	unsigned long reset_cr8;
175 	unsigned long reset_fatal;
176 	unsigned long reset_TXtimeout;
177 
178 	/* NIC SROM data */
179 	unsigned char srom[128];
180 	u8 init;
181 };
182 
183 enum uli526x_offsets {
184 	DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
185 	DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
186 	DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
187 	DCR15 = 0x78
188 };
189 
190 enum uli526x_CR6_bits {
191 	CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
192 	CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
193 	CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
194 };
195 
196 /* Global variable declaration ----------------------------- */
197 static int uli526x_debug;
198 static unsigned char uli526x_media_mode = ULI526X_AUTO;
199 static u32 uli526x_cr6_user_set;
200 
201 /* For module input parameter */
202 static int debug;
203 static u32 cr6set;
204 static int mode = 8;
205 
206 /* function declaration ------------------------------------- */
207 static int uli526x_open(struct net_device *);
208 static netdev_tx_t uli526x_start_xmit(struct sk_buff *,
209 					    struct net_device *);
210 static int uli526x_stop(struct net_device *);
211 static void uli526x_set_filter_mode(struct net_device *);
212 static const struct ethtool_ops netdev_ethtool_ops;
213 static u16 read_srom_word(struct uli526x_board_info *, int);
214 static irqreturn_t uli526x_interrupt(int, void *);
215 #ifdef CONFIG_NET_POLL_CONTROLLER
216 static void uli526x_poll(struct net_device *dev);
217 #endif
218 static void uli526x_descriptor_init(struct net_device *, void __iomem *);
219 static void allocate_rx_buffer(struct net_device *);
220 static void update_cr6(u32, void __iomem *);
221 static void send_filter_frame(struct net_device *, int);
222 static u16 phy_readby_cr9(struct uli526x_board_info *, u8, u8);
223 static u16 phy_readby_cr10(struct uli526x_board_info *, u8, u8);
224 static void phy_writeby_cr9(struct uli526x_board_info *, u8, u8, u16);
225 static void phy_writeby_cr10(struct uli526x_board_info *, u8, u8, u16);
226 static void phy_write_1bit(struct uli526x_board_info *db, u32);
227 static u16 phy_read_1bit(struct uli526x_board_info *db);
228 static u8 uli526x_sense_speed(struct uli526x_board_info *);
229 static void uli526x_process_mode(struct uli526x_board_info *);
230 static void uli526x_timer(struct timer_list *t);
231 static void uli526x_rx_packet(struct net_device *, struct uli526x_board_info *);
232 static void uli526x_free_tx_pkt(struct net_device *, struct uli526x_board_info *);
233 static void uli526x_reuse_skb(struct uli526x_board_info *, struct sk_buff *);
234 static void uli526x_dynamic_reset(struct net_device *);
235 static void uli526x_free_rxbuffer(struct uli526x_board_info *);
236 static void uli526x_init(struct net_device *);
237 static void uli526x_set_phyxcer(struct uli526x_board_info *);
238 
239 static void srom_clk_write(struct uli526x_board_info *db, u32 data)
240 {
241 	void __iomem *ioaddr = db->ioaddr;
242 
243 	uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS);
244 	udelay(5);
245 	uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);
246 	udelay(5);
247 	uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS);
248 	udelay(5);
249 }
250 
251 /* ULI526X network board routine ---------------------------- */
252 
253 static const struct net_device_ops netdev_ops = {
254 	.ndo_open		= uli526x_open,
255 	.ndo_stop		= uli526x_stop,
256 	.ndo_start_xmit		= uli526x_start_xmit,
257 	.ndo_set_rx_mode	= uli526x_set_filter_mode,
258 	.ndo_set_mac_address	= eth_mac_addr,
259 	.ndo_validate_addr	= eth_validate_addr,
260 #ifdef CONFIG_NET_POLL_CONTROLLER
261 	.ndo_poll_controller 	= uli526x_poll,
262 #endif
263 };
264 
265 /*
266  *	Search ULI526X board, allocate space and register it
267  */
268 
269 static int uli526x_init_one(struct pci_dev *pdev,
270 			    const struct pci_device_id *ent)
271 {
272 	struct uli526x_board_info *db;	/* board information structure */
273 	struct net_device *dev;
274 	void __iomem *ioaddr;
275 	int i, err;
276 
277 	ULI526X_DBUG(0, "uli526x_init_one()", 0);
278 
279 	/* Init network device */
280 	dev = alloc_etherdev(sizeof(*db));
281 	if (dev == NULL)
282 		return -ENOMEM;
283 	SET_NETDEV_DEV(dev, &pdev->dev);
284 
285 	if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
286 		pr_warn("32-bit PCI DMA not available\n");
287 		err = -ENODEV;
288 		goto err_out_free;
289 	}
290 
291 	/* Enable Master/IO access, Disable memory access */
292 	err = pci_enable_device(pdev);
293 	if (err)
294 		goto err_out_free;
295 
296 	if (!pci_resource_start(pdev, 0)) {
297 		pr_err("I/O base is zero\n");
298 		err = -ENODEV;
299 		goto err_out_disable;
300 	}
301 
302 	if (pci_resource_len(pdev, 0) < (ULI526X_IO_SIZE) ) {
303 		pr_err("Allocated I/O size too small\n");
304 		err = -ENODEV;
305 		goto err_out_disable;
306 	}
307 
308 	err = pci_request_regions(pdev, DRV_NAME);
309 	if (err < 0) {
310 		pr_err("Failed to request PCI regions\n");
311 		goto err_out_disable;
312 	}
313 
314 	/* Init system & device */
315 	db = netdev_priv(dev);
316 
317 	/* Allocate Tx/Rx descriptor memory */
318 	err = -ENOMEM;
319 
320 	db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
321 	if (!db->desc_pool_ptr)
322 		goto err_out_release;
323 
324 	db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
325 	if (!db->buf_pool_ptr)
326 		goto err_out_free_tx_desc;
327 
328 	db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
329 	db->first_tx_desc_dma = db->desc_pool_dma_ptr;
330 	db->buf_pool_start = db->buf_pool_ptr;
331 	db->buf_pool_dma_start = db->buf_pool_dma_ptr;
332 
333 	switch (ent->driver_data) {
334 	case PCI_ULI5263_ID:
335 		db->phy.write	= phy_writeby_cr10;
336 		db->phy.read	= phy_readby_cr10;
337 		break;
338 	default:
339 		db->phy.write	= phy_writeby_cr9;
340 		db->phy.read	= phy_readby_cr9;
341 		break;
342 	}
343 
344 	/* IO region. */
345 	ioaddr = pci_iomap(pdev, 0, 0);
346 	if (!ioaddr)
347 		goto err_out_free_tx_buf;
348 
349 	db->ioaddr = ioaddr;
350 	db->pdev = pdev;
351 	db->init = 1;
352 
353 	pci_set_drvdata(pdev, dev);
354 
355 	/* Register some necessary functions */
356 	dev->netdev_ops = &netdev_ops;
357 	dev->ethtool_ops = &netdev_ethtool_ops;
358 
359 	spin_lock_init(&db->lock);
360 
361 
362 	/* read 64 word srom data */
363 	for (i = 0; i < 64; i++)
364 		((__le16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db, i));
365 
366 	/* Set Node address */
367 	if(((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0)		/* SROM absent, so read MAC address from ID Table */
368 	{
369 		uw32(DCR0, 0x10000);	//Diagnosis mode
370 		uw32(DCR13, 0x1c0);	//Reset dianostic pointer port
371 		uw32(DCR14, 0);		//Clear reset port
372 		uw32(DCR14, 0x10);	//Reset ID Table pointer
373 		uw32(DCR14, 0);		//Clear reset port
374 		uw32(DCR13, 0);		//Clear CR13
375 		uw32(DCR13, 0x1b0);	//Select ID Table access port
376 		//Read MAC address from CR14
377 		for (i = 0; i < 6; i++)
378 			dev->dev_addr[i] = ur32(DCR14);
379 		//Read end
380 		uw32(DCR13, 0);		//Clear CR13
381 		uw32(DCR0, 0);		//Clear CR0
382 		udelay(10);
383 	}
384 	else		/*Exist SROM*/
385 	{
386 		for (i = 0; i < 6; i++)
387 			dev->dev_addr[i] = db->srom[20 + i];
388 	}
389 	err = register_netdev (dev);
390 	if (err)
391 		goto err_out_unmap;
392 
393 	netdev_info(dev, "ULi M%04lx at pci%s, %pM, irq %d\n",
394 		    ent->driver_data >> 16, pci_name(pdev),
395 		    dev->dev_addr, pdev->irq);
396 
397 	pci_set_master(pdev);
398 
399 	return 0;
400 
401 err_out_unmap:
402 	pci_iounmap(pdev, db->ioaddr);
403 err_out_free_tx_buf:
404 	pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
405 			    db->buf_pool_ptr, db->buf_pool_dma_ptr);
406 err_out_free_tx_desc:
407 	pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
408 			    db->desc_pool_ptr, db->desc_pool_dma_ptr);
409 err_out_release:
410 	pci_release_regions(pdev);
411 err_out_disable:
412 	pci_disable_device(pdev);
413 err_out_free:
414 	free_netdev(dev);
415 
416 	return err;
417 }
418 
419 
420 static void uli526x_remove_one(struct pci_dev *pdev)
421 {
422 	struct net_device *dev = pci_get_drvdata(pdev);
423 	struct uli526x_board_info *db = netdev_priv(dev);
424 
425 	unregister_netdev(dev);
426 	pci_iounmap(pdev, db->ioaddr);
427 	pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
428 				DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
429  				db->desc_pool_dma_ptr);
430 	pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
431 				db->buf_pool_ptr, db->buf_pool_dma_ptr);
432 	pci_release_regions(pdev);
433 	pci_disable_device(pdev);
434 	free_netdev(dev);
435 }
436 
437 
438 /*
439  *	Open the interface.
440  *	The interface is opened whenever "ifconfig" activates it.
441  */
442 
443 static int uli526x_open(struct net_device *dev)
444 {
445 	int ret;
446 	struct uli526x_board_info *db = netdev_priv(dev);
447 
448 	ULI526X_DBUG(0, "uli526x_open", 0);
449 
450 	/* system variable init */
451 	db->cr6_data = CR6_DEFAULT | uli526x_cr6_user_set;
452 	db->tx_packet_cnt = 0;
453 	db->rx_avail_cnt = 0;
454 	db->link_failed = 1;
455 	netif_carrier_off(dev);
456 	db->wait_reset = 0;
457 
458 	db->NIC_capability = 0xf;	/* All capability*/
459 	db->PHY_reg4 = 0x1e0;
460 
461 	/* CR6 operation mode decision */
462 	db->cr6_data |= ULI526X_TXTH_256;
463 	db->cr0_data = CR0_DEFAULT;
464 
465 	/* Initialize ULI526X board */
466 	uli526x_init(dev);
467 
468 	ret = request_irq(db->pdev->irq, uli526x_interrupt, IRQF_SHARED,
469 			  dev->name, dev);
470 	if (ret)
471 		return ret;
472 
473 	/* Active System Interface */
474 	netif_wake_queue(dev);
475 
476 	/* set and active a timer process */
477 	timer_setup(&db->timer, uli526x_timer, 0);
478 	db->timer.expires = ULI526X_TIMER_WUT + HZ * 2;
479 	add_timer(&db->timer);
480 
481 	return 0;
482 }
483 
484 
485 /*	Initialize ULI526X board
486  *	Reset ULI526X board
487  *	Initialize TX/Rx descriptor chain structure
488  *	Send the set-up frame
489  *	Enable Tx/Rx machine
490  */
491 
492 static void uli526x_init(struct net_device *dev)
493 {
494 	struct uli526x_board_info *db = netdev_priv(dev);
495 	struct uli_phy_ops *phy = &db->phy;
496 	void __iomem *ioaddr = db->ioaddr;
497 	u8	phy_tmp;
498 	u8	timeout;
499 	u16 phy_reg_reset;
500 
501 
502 	ULI526X_DBUG(0, "uli526x_init()", 0);
503 
504 	/* Reset M526x MAC controller */
505 	uw32(DCR0, ULI526X_RESET);	/* RESET MAC */
506 	udelay(100);
507 	uw32(DCR0, db->cr0_data);
508 	udelay(5);
509 
510 	/* Phy addr : In some boards,M5261/M5263 phy address != 1 */
511 	db->phy_addr = 1;
512 	for (phy_tmp = 0; phy_tmp < 32; phy_tmp++) {
513 		u16 phy_value;
514 
515 		phy_value = phy->read(db, phy_tmp, 3);	//peer add
516 		if (phy_value != 0xffff && phy_value != 0) {
517 			db->phy_addr = phy_tmp;
518 			break;
519 		}
520 	}
521 
522 	if (phy_tmp == 32)
523 		pr_warn("Can not find the phy address!!!\n");
524 	/* Parser SROM and media mode */
525 	db->media_mode = uli526x_media_mode;
526 
527 	/* phyxcer capability setting */
528 	phy_reg_reset = phy->read(db, db->phy_addr, 0);
529 	phy_reg_reset = (phy_reg_reset | 0x8000);
530 	phy->write(db, db->phy_addr, 0, phy_reg_reset);
531 
532 	/* See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management
533 	 * functions") or phy data sheet for details on phy reset
534 	 */
535 	udelay(500);
536 	timeout = 10;
537 	while (timeout-- && phy->read(db, db->phy_addr, 0) & 0x8000)
538 		udelay(100);
539 
540 	/* Process Phyxcer Media Mode */
541 	uli526x_set_phyxcer(db);
542 
543 	/* Media Mode Process */
544 	if ( !(db->media_mode & ULI526X_AUTO) )
545 		db->op_mode = db->media_mode;		/* Force Mode */
546 
547 	/* Initialize Transmit/Receive descriptor and CR3/4 */
548 	uli526x_descriptor_init(dev, ioaddr);
549 
550 	/* Init CR6 to program M526X operation */
551 	update_cr6(db->cr6_data, ioaddr);
552 
553 	/* Send setup frame */
554 	send_filter_frame(dev, netdev_mc_count(dev));	/* M5261/M5263 */
555 
556 	/* Init CR7, interrupt active bit */
557 	db->cr7_data = CR7_DEFAULT;
558 	uw32(DCR7, db->cr7_data);
559 
560 	/* Init CR15, Tx jabber and Rx watchdog timer */
561 	uw32(DCR15, db->cr15_data);
562 
563 	/* Enable ULI526X Tx/Rx function */
564 	db->cr6_data |= CR6_RXSC | CR6_TXSC;
565 	update_cr6(db->cr6_data, ioaddr);
566 }
567 
568 
569 /*
570  *	Hardware start transmission.
571  *	Send a packet to media from the upper layer.
572  */
573 
574 static netdev_tx_t uli526x_start_xmit(struct sk_buff *skb,
575 					    struct net_device *dev)
576 {
577 	struct uli526x_board_info *db = netdev_priv(dev);
578 	void __iomem *ioaddr = db->ioaddr;
579 	struct tx_desc *txptr;
580 	unsigned long flags;
581 
582 	ULI526X_DBUG(0, "uli526x_start_xmit", 0);
583 
584 	/* Resource flag check */
585 	netif_stop_queue(dev);
586 
587 	/* Too large packet check */
588 	if (skb->len > MAX_PACKET_SIZE) {
589 		netdev_err(dev, "big packet = %d\n", (u16)skb->len);
590 		dev_kfree_skb_any(skb);
591 		return NETDEV_TX_OK;
592 	}
593 
594 	spin_lock_irqsave(&db->lock, flags);
595 
596 	/* No Tx resource check, it never happen nromally */
597 	if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
598 		spin_unlock_irqrestore(&db->lock, flags);
599 		netdev_err(dev, "No Tx resource %ld\n", db->tx_packet_cnt);
600 		return NETDEV_TX_BUSY;
601 	}
602 
603 	/* Disable NIC interrupt */
604 	uw32(DCR7, 0);
605 
606 	/* transmit this packet */
607 	txptr = db->tx_insert_ptr;
608 	skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
609 	txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
610 
611 	/* Point to next transmit free descriptor */
612 	db->tx_insert_ptr = txptr->next_tx_desc;
613 
614 	/* Transmit Packet Process */
615 	if (db->tx_packet_cnt < TX_DESC_CNT) {
616 		txptr->tdes0 = cpu_to_le32(0x80000000);	/* Set owner bit */
617 		db->tx_packet_cnt++;			/* Ready to send */
618 		uw32(DCR1, 0x1);			/* Issue Tx polling */
619 		netif_trans_update(dev);		/* saved time stamp */
620 	}
621 
622 	/* Tx resource check */
623 	if ( db->tx_packet_cnt < TX_FREE_DESC_CNT )
624 		netif_wake_queue(dev);
625 
626 	/* Restore CR7 to enable interrupt */
627 	spin_unlock_irqrestore(&db->lock, flags);
628 	uw32(DCR7, db->cr7_data);
629 
630 	/* free this SKB */
631 	dev_consume_skb_any(skb);
632 
633 	return NETDEV_TX_OK;
634 }
635 
636 
637 /*
638  *	Stop the interface.
639  *	The interface is stopped when it is brought.
640  */
641 
642 static int uli526x_stop(struct net_device *dev)
643 {
644 	struct uli526x_board_info *db = netdev_priv(dev);
645 	void __iomem *ioaddr = db->ioaddr;
646 
647 	/* disable system */
648 	netif_stop_queue(dev);
649 
650 	/* deleted timer */
651 	del_timer_sync(&db->timer);
652 
653 	/* Reset & stop ULI526X board */
654 	uw32(DCR0, ULI526X_RESET);
655 	udelay(5);
656 	db->phy.write(db, db->phy_addr, 0, 0x8000);
657 
658 	/* free interrupt */
659 	free_irq(db->pdev->irq, dev);
660 
661 	/* free allocated rx buffer */
662 	uli526x_free_rxbuffer(db);
663 
664 	return 0;
665 }
666 
667 
668 /*
669  *	M5261/M5263 insterrupt handler
670  *	receive the packet to upper layer, free the transmitted packet
671  */
672 
673 static irqreturn_t uli526x_interrupt(int irq, void *dev_id)
674 {
675 	struct net_device *dev = dev_id;
676 	struct uli526x_board_info *db = netdev_priv(dev);
677 	void __iomem *ioaddr = db->ioaddr;
678 	unsigned long flags;
679 
680 	spin_lock_irqsave(&db->lock, flags);
681 	uw32(DCR7, 0);
682 
683 	/* Got ULI526X status */
684 	db->cr5_data = ur32(DCR5);
685 	uw32(DCR5, db->cr5_data);
686 	if ( !(db->cr5_data & 0x180c1) ) {
687 		/* Restore CR7 to enable interrupt mask */
688 		uw32(DCR7, db->cr7_data);
689 		spin_unlock_irqrestore(&db->lock, flags);
690 		return IRQ_HANDLED;
691 	}
692 
693 	/* Check system status */
694 	if (db->cr5_data & 0x2000) {
695 		/* system bus error happen */
696 		ULI526X_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
697 		db->reset_fatal++;
698 		db->wait_reset = 1;	/* Need to RESET */
699 		spin_unlock_irqrestore(&db->lock, flags);
700 		return IRQ_HANDLED;
701 	}
702 
703 	 /* Received the coming packet */
704 	if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
705 		uli526x_rx_packet(dev, db);
706 
707 	/* reallocate rx descriptor buffer */
708 	if (db->rx_avail_cnt<RX_DESC_CNT)
709 		allocate_rx_buffer(dev);
710 
711 	/* Free the transmitted descriptor */
712 	if ( db->cr5_data & 0x01)
713 		uli526x_free_tx_pkt(dev, db);
714 
715 	/* Restore CR7 to enable interrupt mask */
716 	uw32(DCR7, db->cr7_data);
717 
718 	spin_unlock_irqrestore(&db->lock, flags);
719 	return IRQ_HANDLED;
720 }
721 
722 #ifdef CONFIG_NET_POLL_CONTROLLER
723 static void uli526x_poll(struct net_device *dev)
724 {
725 	struct uli526x_board_info *db = netdev_priv(dev);
726 
727 	/* ISR grabs the irqsave lock, so this should be safe */
728 	uli526x_interrupt(db->pdev->irq, dev);
729 }
730 #endif
731 
732 /*
733  *	Free TX resource after TX complete
734  */
735 
736 static void uli526x_free_tx_pkt(struct net_device *dev,
737 				struct uli526x_board_info * db)
738 {
739 	struct tx_desc *txptr;
740 	u32 tdes0;
741 
742 	txptr = db->tx_remove_ptr;
743 	while(db->tx_packet_cnt) {
744 		tdes0 = le32_to_cpu(txptr->tdes0);
745 		if (tdes0 & 0x80000000)
746 			break;
747 
748 		/* A packet sent completed */
749 		db->tx_packet_cnt--;
750 		dev->stats.tx_packets++;
751 
752 		/* Transmit statistic counter */
753 		if ( tdes0 != 0x7fffffff ) {
754 			dev->stats.collisions += (tdes0 >> 3) & 0xf;
755 			dev->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
756 			if (tdes0 & TDES0_ERR_MASK) {
757 				dev->stats.tx_errors++;
758 				if (tdes0 & 0x0002) {	/* UnderRun */
759 					db->tx_fifo_underrun++;
760 					if ( !(db->cr6_data & CR6_SFT) ) {
761 						db->cr6_data = db->cr6_data | CR6_SFT;
762 						update_cr6(db->cr6_data, db->ioaddr);
763 					}
764 				}
765 				if (tdes0 & 0x0100)
766 					db->tx_excessive_collision++;
767 				if (tdes0 & 0x0200)
768 					db->tx_late_collision++;
769 				if (tdes0 & 0x0400)
770 					db->tx_no_carrier++;
771 				if (tdes0 & 0x0800)
772 					db->tx_loss_carrier++;
773 				if (tdes0 & 0x4000)
774 					db->tx_jabber_timeout++;
775 			}
776 		}
777 
778     		txptr = txptr->next_tx_desc;
779 	}/* End of while */
780 
781 	/* Update TX remove pointer to next */
782 	db->tx_remove_ptr = txptr;
783 
784 	/* Resource available check */
785 	if ( db->tx_packet_cnt < TX_WAKE_DESC_CNT )
786 		netif_wake_queue(dev);	/* Active upper layer, send again */
787 }
788 
789 
790 /*
791  *	Receive the come packet and pass to upper layer
792  */
793 
794 static void uli526x_rx_packet(struct net_device *dev, struct uli526x_board_info * db)
795 {
796 	struct rx_desc *rxptr;
797 	struct sk_buff *skb;
798 	int rxlen;
799 	u32 rdes0;
800 
801 	rxptr = db->rx_ready_ptr;
802 
803 	while(db->rx_avail_cnt) {
804 		rdes0 = le32_to_cpu(rxptr->rdes0);
805 		if (rdes0 & 0x80000000)	/* packet owner check */
806 		{
807 			break;
808 		}
809 
810 		db->rx_avail_cnt--;
811 		db->interval_rx_cnt++;
812 
813 		pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2), RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
814 		if ( (rdes0 & 0x300) != 0x300) {
815 			/* A packet without First/Last flag */
816 			/* reuse this SKB */
817 			ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
818 			uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
819 		} else {
820 			/* A packet with First/Last flag */
821 			rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
822 
823 			/* error summary bit check */
824 			if (rdes0 & 0x8000) {
825 				/* This is a error packet */
826 				dev->stats.rx_errors++;
827 				if (rdes0 & 1)
828 					dev->stats.rx_fifo_errors++;
829 				if (rdes0 & 2)
830 					dev->stats.rx_crc_errors++;
831 				if (rdes0 & 0x80)
832 					dev->stats.rx_length_errors++;
833 			}
834 
835 			if ( !(rdes0 & 0x8000) ||
836 				((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
837 				struct sk_buff *new_skb = NULL;
838 
839 				skb = rxptr->rx_skb_ptr;
840 
841 				/* Good packet, send to upper layer */
842 				/* Shorst packet used new SKB */
843 				if ((rxlen < RX_COPY_SIZE) &&
844 				    (((new_skb = netdev_alloc_skb(dev, rxlen + 2)) != NULL))) {
845 					skb = new_skb;
846 					/* size less than COPY_SIZE, allocate a rxlen SKB */
847 					skb_reserve(skb, 2); /* 16byte align */
848 					skb_put_data(skb,
849 						     skb_tail_pointer(rxptr->rx_skb_ptr),
850 						     rxlen);
851 					uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
852 				} else
853 					skb_put(skb, rxlen);
854 
855 				skb->protocol = eth_type_trans(skb, dev);
856 				netif_rx(skb);
857 				dev->stats.rx_packets++;
858 				dev->stats.rx_bytes += rxlen;
859 
860 			} else {
861 				/* Reuse SKB buffer when the packet is error */
862 				ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
863 				uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
864 			}
865 		}
866 
867 		rxptr = rxptr->next_rx_desc;
868 	}
869 
870 	db->rx_ready_ptr = rxptr;
871 }
872 
873 
874 /*
875  * Set ULI526X multicast address
876  */
877 
878 static void uli526x_set_filter_mode(struct net_device * dev)
879 {
880 	struct uli526x_board_info *db = netdev_priv(dev);
881 	unsigned long flags;
882 
883 	ULI526X_DBUG(0, "uli526x_set_filter_mode()", 0);
884 	spin_lock_irqsave(&db->lock, flags);
885 
886 	if (dev->flags & IFF_PROMISC) {
887 		ULI526X_DBUG(0, "Enable PROM Mode", 0);
888 		db->cr6_data |= CR6_PM | CR6_PBF;
889 		update_cr6(db->cr6_data, db->ioaddr);
890 		spin_unlock_irqrestore(&db->lock, flags);
891 		return;
892 	}
893 
894 	if (dev->flags & IFF_ALLMULTI ||
895 	    netdev_mc_count(dev) > ULI5261_MAX_MULTICAST) {
896 		ULI526X_DBUG(0, "Pass all multicast address",
897 			     netdev_mc_count(dev));
898 		db->cr6_data &= ~(CR6_PM | CR6_PBF);
899 		db->cr6_data |= CR6_PAM;
900 		spin_unlock_irqrestore(&db->lock, flags);
901 		return;
902 	}
903 
904 	ULI526X_DBUG(0, "Set multicast address", netdev_mc_count(dev));
905 	send_filter_frame(dev, netdev_mc_count(dev)); 	/* M5261/M5263 */
906 	spin_unlock_irqrestore(&db->lock, flags);
907 }
908 
909 static void
910 ULi_ethtool_get_link_ksettings(struct uli526x_board_info *db,
911 			       struct ethtool_link_ksettings *cmd)
912 {
913 	u32 supported, advertising;
914 
915 	supported = (SUPPORTED_10baseT_Half |
916 	                   SUPPORTED_10baseT_Full |
917 	                   SUPPORTED_100baseT_Half |
918 	                   SUPPORTED_100baseT_Full |
919 	                   SUPPORTED_Autoneg |
920 	                   SUPPORTED_MII);
921 
922 	advertising = (ADVERTISED_10baseT_Half |
923 	                   ADVERTISED_10baseT_Full |
924 	                   ADVERTISED_100baseT_Half |
925 	                   ADVERTISED_100baseT_Full |
926 	                   ADVERTISED_Autoneg |
927 	                   ADVERTISED_MII);
928 
929 	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
930 						supported);
931 	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
932 						advertising);
933 
934 	cmd->base.port = PORT_MII;
935 	cmd->base.phy_address = db->phy_addr;
936 
937 	cmd->base.speed = SPEED_10;
938 	cmd->base.duplex = DUPLEX_HALF;
939 
940 	if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
941 	{
942 		cmd->base.speed = SPEED_100;
943 	}
944 	if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
945 	{
946 		cmd->base.duplex = DUPLEX_FULL;
947 	}
948 	if(db->link_failed)
949 	{
950 		cmd->base.speed = SPEED_UNKNOWN;
951 		cmd->base.duplex = DUPLEX_UNKNOWN;
952 	}
953 
954 	if (db->media_mode & ULI526X_AUTO)
955 	{
956 		cmd->base.autoneg = AUTONEG_ENABLE;
957 	}
958 }
959 
960 static void netdev_get_drvinfo(struct net_device *dev,
961 			       struct ethtool_drvinfo *info)
962 {
963 	struct uli526x_board_info *np = netdev_priv(dev);
964 
965 	strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
966 	strlcpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info));
967 }
968 
969 static int netdev_get_link_ksettings(struct net_device *dev,
970 				     struct ethtool_link_ksettings *cmd)
971 {
972 	struct uli526x_board_info *np = netdev_priv(dev);
973 
974 	ULi_ethtool_get_link_ksettings(np, cmd);
975 
976 	return 0;
977 }
978 
979 static u32 netdev_get_link(struct net_device *dev) {
980 	struct uli526x_board_info *np = netdev_priv(dev);
981 
982 	if(np->link_failed)
983 		return 0;
984 	else
985 		return 1;
986 }
987 
988 static void uli526x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
989 {
990 	wol->supported = WAKE_PHY | WAKE_MAGIC;
991 	wol->wolopts = 0;
992 }
993 
994 static const struct ethtool_ops netdev_ethtool_ops = {
995 	.get_drvinfo		= netdev_get_drvinfo,
996 	.get_link		= netdev_get_link,
997 	.get_wol		= uli526x_get_wol,
998 	.get_link_ksettings	= netdev_get_link_ksettings,
999 };
1000 
1001 /*
1002  *	A periodic timer routine
1003  *	Dynamic media sense, allocate Rx buffer...
1004  */
1005 
1006 static void uli526x_timer(struct timer_list *t)
1007 {
1008 	struct uli526x_board_info *db = from_timer(db, t, timer);
1009 	struct net_device *dev = pci_get_drvdata(db->pdev);
1010 	struct uli_phy_ops *phy = &db->phy;
1011 	void __iomem *ioaddr = db->ioaddr;
1012  	unsigned long flags;
1013 	u8 tmp_cr12 = 0;
1014 	u32 tmp_cr8;
1015 
1016 	//ULI526X_DBUG(0, "uli526x_timer()", 0);
1017 	spin_lock_irqsave(&db->lock, flags);
1018 
1019 
1020 	/* Dynamic reset ULI526X : system error or transmit time-out */
1021 	tmp_cr8 = ur32(DCR8);
1022 	if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1023 		db->reset_cr8++;
1024 		db->wait_reset = 1;
1025 	}
1026 	db->interval_rx_cnt = 0;
1027 
1028 	/* TX polling kick monitor */
1029 	if ( db->tx_packet_cnt &&
1030 	     time_after(jiffies, dev_trans_start(dev) + ULI526X_TX_KICK) ) {
1031 		uw32(DCR1, 0x1);   // Tx polling again
1032 
1033 		// TX Timeout
1034 		if ( time_after(jiffies, dev_trans_start(dev) + ULI526X_TX_TIMEOUT) ) {
1035 			db->reset_TXtimeout++;
1036 			db->wait_reset = 1;
1037 			netdev_err(dev, " Tx timeout - resetting\n");
1038 		}
1039 	}
1040 
1041 	if (db->wait_reset) {
1042 		ULI526X_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1043 		db->reset_count++;
1044 		uli526x_dynamic_reset(dev);
1045 		db->timer.expires = ULI526X_TIMER_WUT;
1046 		add_timer(&db->timer);
1047 		spin_unlock_irqrestore(&db->lock, flags);
1048 		return;
1049 	}
1050 
1051 	/* Link status check, Dynamic media type change */
1052 	if ((phy->read(db, db->phy_addr, 5) & 0x01e0)!=0)
1053 		tmp_cr12 = 3;
1054 
1055 	if ( !(tmp_cr12 & 0x3) && !db->link_failed ) {
1056 		/* Link Failed */
1057 		ULI526X_DBUG(0, "Link Failed", tmp_cr12);
1058 		netif_carrier_off(dev);
1059 		netdev_info(dev, "NIC Link is Down\n");
1060 		db->link_failed = 1;
1061 
1062 		/* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1063 		/* AUTO don't need */
1064 		if ( !(db->media_mode & 0x8) )
1065 			phy->write(db, db->phy_addr, 0, 0x1000);
1066 
1067 		/* AUTO mode, if INT phyxcer link failed, select EXT device */
1068 		if (db->media_mode & ULI526X_AUTO) {
1069 			db->cr6_data&=~0x00000200;	/* bit9=0, HD mode */
1070 			update_cr6(db->cr6_data, db->ioaddr);
1071 		}
1072 	} else
1073 		if ((tmp_cr12 & 0x3) && db->link_failed) {
1074 			ULI526X_DBUG(0, "Link link OK", tmp_cr12);
1075 			db->link_failed = 0;
1076 
1077 			/* Auto Sense Speed */
1078 			if ( (db->media_mode & ULI526X_AUTO) &&
1079 				uli526x_sense_speed(db) )
1080 				db->link_failed = 1;
1081 			uli526x_process_mode(db);
1082 
1083 			if(db->link_failed==0)
1084 			{
1085 				netdev_info(dev, "NIC Link is Up %d Mbps %s duplex\n",
1086 					    (db->op_mode == ULI526X_100MHF ||
1087 					     db->op_mode == ULI526X_100MFD)
1088 					    ? 100 : 10,
1089 					    (db->op_mode == ULI526X_10MFD ||
1090 					     db->op_mode == ULI526X_100MFD)
1091 					    ? "Full" : "Half");
1092 				netif_carrier_on(dev);
1093 			}
1094 			/* SHOW_MEDIA_TYPE(db->op_mode); */
1095 		}
1096 		else if(!(tmp_cr12 & 0x3) && db->link_failed)
1097 		{
1098 			if(db->init==1)
1099 			{
1100 				netdev_info(dev, "NIC Link is Down\n");
1101 				netif_carrier_off(dev);
1102 			}
1103 		}
1104 	db->init = 0;
1105 
1106 	/* Timer active again */
1107 	db->timer.expires = ULI526X_TIMER_WUT;
1108 	add_timer(&db->timer);
1109 	spin_unlock_irqrestore(&db->lock, flags);
1110 }
1111 
1112 
1113 /*
1114  *	Stop ULI526X board
1115  *	Free Tx/Rx allocated memory
1116  *	Init system variable
1117  */
1118 
1119 static void uli526x_reset_prepare(struct net_device *dev)
1120 {
1121 	struct uli526x_board_info *db = netdev_priv(dev);
1122 	void __iomem *ioaddr = db->ioaddr;
1123 
1124 	/* Sopt MAC controller */
1125 	db->cr6_data &= ~(CR6_RXSC | CR6_TXSC);	/* Disable Tx/Rx */
1126 	update_cr6(db->cr6_data, ioaddr);
1127 	uw32(DCR7, 0);				/* Disable Interrupt */
1128 	uw32(DCR5, ur32(DCR5));
1129 
1130 	/* Disable upper layer interface */
1131 	netif_stop_queue(dev);
1132 
1133 	/* Free Rx Allocate buffer */
1134 	uli526x_free_rxbuffer(db);
1135 
1136 	/* system variable init */
1137 	db->tx_packet_cnt = 0;
1138 	db->rx_avail_cnt = 0;
1139 	db->link_failed = 1;
1140 	db->init=1;
1141 	db->wait_reset = 0;
1142 }
1143 
1144 
1145 /*
1146  *	Dynamic reset the ULI526X board
1147  *	Stop ULI526X board
1148  *	Free Tx/Rx allocated memory
1149  *	Reset ULI526X board
1150  *	Re-initialize ULI526X board
1151  */
1152 
1153 static void uli526x_dynamic_reset(struct net_device *dev)
1154 {
1155 	ULI526X_DBUG(0, "uli526x_dynamic_reset()", 0);
1156 
1157 	uli526x_reset_prepare(dev);
1158 
1159 	/* Re-initialize ULI526X board */
1160 	uli526x_init(dev);
1161 
1162 	/* Restart upper layer interface */
1163 	netif_wake_queue(dev);
1164 }
1165 
1166 
1167 #ifdef CONFIG_PM
1168 
1169 /*
1170  *	Suspend the interface.
1171  */
1172 
1173 static int uli526x_suspend(struct pci_dev *pdev, pm_message_t state)
1174 {
1175 	struct net_device *dev = pci_get_drvdata(pdev);
1176 	pci_power_t power_state;
1177 	int err;
1178 
1179 	ULI526X_DBUG(0, "uli526x_suspend", 0);
1180 
1181 	pci_save_state(pdev);
1182 
1183 	if (!netif_running(dev))
1184 		return 0;
1185 
1186 	netif_device_detach(dev);
1187 	uli526x_reset_prepare(dev);
1188 
1189 	power_state = pci_choose_state(pdev, state);
1190 	pci_enable_wake(pdev, power_state, 0);
1191 	err = pci_set_power_state(pdev, power_state);
1192 	if (err) {
1193 		netif_device_attach(dev);
1194 		/* Re-initialize ULI526X board */
1195 		uli526x_init(dev);
1196 		/* Restart upper layer interface */
1197 		netif_wake_queue(dev);
1198 	}
1199 
1200 	return err;
1201 }
1202 
1203 /*
1204  *	Resume the interface.
1205  */
1206 
1207 static int uli526x_resume(struct pci_dev *pdev)
1208 {
1209 	struct net_device *dev = pci_get_drvdata(pdev);
1210 	int err;
1211 
1212 	ULI526X_DBUG(0, "uli526x_resume", 0);
1213 
1214 	pci_restore_state(pdev);
1215 
1216 	if (!netif_running(dev))
1217 		return 0;
1218 
1219 	err = pci_set_power_state(pdev, PCI_D0);
1220 	if (err) {
1221 		netdev_warn(dev, "Could not put device into D0\n");
1222 		return err;
1223 	}
1224 
1225 	netif_device_attach(dev);
1226 	/* Re-initialize ULI526X board */
1227 	uli526x_init(dev);
1228 	/* Restart upper layer interface */
1229 	netif_wake_queue(dev);
1230 
1231 	return 0;
1232 }
1233 
1234 #else /* !CONFIG_PM */
1235 
1236 #define uli526x_suspend	NULL
1237 #define uli526x_resume	NULL
1238 
1239 #endif /* !CONFIG_PM */
1240 
1241 
1242 /*
1243  *	free all allocated rx buffer
1244  */
1245 
1246 static void uli526x_free_rxbuffer(struct uli526x_board_info * db)
1247 {
1248 	ULI526X_DBUG(0, "uli526x_free_rxbuffer()", 0);
1249 
1250 	/* free allocated rx buffer */
1251 	while (db->rx_avail_cnt) {
1252 		dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1253 		db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1254 		db->rx_avail_cnt--;
1255 	}
1256 }
1257 
1258 
1259 /*
1260  *	Reuse the SK buffer
1261  */
1262 
1263 static void uli526x_reuse_skb(struct uli526x_board_info *db, struct sk_buff * skb)
1264 {
1265 	struct rx_desc *rxptr = db->rx_insert_ptr;
1266 
1267 	if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1268 		rxptr->rx_skb_ptr = skb;
1269 		rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1270 							  skb_tail_pointer(skb),
1271 							  RX_ALLOC_SIZE,
1272 							  PCI_DMA_FROMDEVICE));
1273 		wmb();
1274 		rxptr->rdes0 = cpu_to_le32(0x80000000);
1275 		db->rx_avail_cnt++;
1276 		db->rx_insert_ptr = rxptr->next_rx_desc;
1277 	} else
1278 		ULI526X_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1279 }
1280 
1281 
1282 /*
1283  *	Initialize transmit/Receive descriptor
1284  *	Using Chain structure, and allocate Tx/Rx buffer
1285  */
1286 
1287 static void uli526x_descriptor_init(struct net_device *dev, void __iomem *ioaddr)
1288 {
1289 	struct uli526x_board_info *db = netdev_priv(dev);
1290 	struct tx_desc *tmp_tx;
1291 	struct rx_desc *tmp_rx;
1292 	unsigned char *tmp_buf;
1293 	dma_addr_t tmp_tx_dma, tmp_rx_dma;
1294 	dma_addr_t tmp_buf_dma;
1295 	int i;
1296 
1297 	ULI526X_DBUG(0, "uli526x_descriptor_init()", 0);
1298 
1299 	/* tx descriptor start pointer */
1300 	db->tx_insert_ptr = db->first_tx_desc;
1301 	db->tx_remove_ptr = db->first_tx_desc;
1302 	uw32(DCR4, db->first_tx_desc_dma);	/* TX DESC address */
1303 
1304 	/* rx descriptor start pointer */
1305 	db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT;
1306 	db->first_rx_desc_dma =  db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT;
1307 	db->rx_insert_ptr = db->first_rx_desc;
1308 	db->rx_ready_ptr = db->first_rx_desc;
1309 	uw32(DCR3, db->first_rx_desc_dma);	/* RX DESC address */
1310 
1311 	/* Init Transmit chain */
1312 	tmp_buf = db->buf_pool_start;
1313 	tmp_buf_dma = db->buf_pool_dma_start;
1314 	tmp_tx_dma = db->first_tx_desc_dma;
1315 	for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1316 		tmp_tx->tx_buf_ptr = tmp_buf;
1317 		tmp_tx->tdes0 = cpu_to_le32(0);
1318 		tmp_tx->tdes1 = cpu_to_le32(0x81000000);	/* IC, chain */
1319 		tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1320 		tmp_tx_dma += sizeof(struct tx_desc);
1321 		tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1322 		tmp_tx->next_tx_desc = tmp_tx + 1;
1323 		tmp_buf = tmp_buf + TX_BUF_ALLOC;
1324 		tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1325 	}
1326 	(--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1327 	tmp_tx->next_tx_desc = db->first_tx_desc;
1328 
1329 	 /* Init Receive descriptor chain */
1330 	tmp_rx_dma=db->first_rx_desc_dma;
1331 	for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1332 		tmp_rx->rdes0 = cpu_to_le32(0);
1333 		tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1334 		tmp_rx_dma += sizeof(struct rx_desc);
1335 		tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1336 		tmp_rx->next_rx_desc = tmp_rx + 1;
1337 	}
1338 	(--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1339 	tmp_rx->next_rx_desc = db->first_rx_desc;
1340 
1341 	/* pre-allocate Rx buffer */
1342 	allocate_rx_buffer(dev);
1343 }
1344 
1345 
1346 /*
1347  *	Update CR6 value
1348  *	Firstly stop ULI526X, then written value and start
1349  */
1350 static void update_cr6(u32 cr6_data, void __iomem *ioaddr)
1351 {
1352 	uw32(DCR6, cr6_data);
1353 	udelay(5);
1354 }
1355 
1356 
1357 /*
1358  *	Send a setup frame for M5261/M5263
1359  *	This setup frame initialize ULI526X address filter mode
1360  */
1361 
1362 #ifdef __BIG_ENDIAN
1363 #define FLT_SHIFT 16
1364 #else
1365 #define FLT_SHIFT 0
1366 #endif
1367 
1368 static void send_filter_frame(struct net_device *dev, int mc_cnt)
1369 {
1370 	struct uli526x_board_info *db = netdev_priv(dev);
1371 	void __iomem *ioaddr = db->ioaddr;
1372 	struct netdev_hw_addr *ha;
1373 	struct tx_desc *txptr;
1374 	u16 * addrptr;
1375 	u32 * suptr;
1376 	int i;
1377 
1378 	ULI526X_DBUG(0, "send_filter_frame()", 0);
1379 
1380 	txptr = db->tx_insert_ptr;
1381 	suptr = (u32 *) txptr->tx_buf_ptr;
1382 
1383 	/* Node address */
1384 	addrptr = (u16 *) dev->dev_addr;
1385 	*suptr++ = addrptr[0] << FLT_SHIFT;
1386 	*suptr++ = addrptr[1] << FLT_SHIFT;
1387 	*suptr++ = addrptr[2] << FLT_SHIFT;
1388 
1389 	/* broadcast address */
1390 	*suptr++ = 0xffff << FLT_SHIFT;
1391 	*suptr++ = 0xffff << FLT_SHIFT;
1392 	*suptr++ = 0xffff << FLT_SHIFT;
1393 
1394 	/* fit the multicast address */
1395 	netdev_for_each_mc_addr(ha, dev) {
1396 		addrptr = (u16 *) ha->addr;
1397 		*suptr++ = addrptr[0] << FLT_SHIFT;
1398 		*suptr++ = addrptr[1] << FLT_SHIFT;
1399 		*suptr++ = addrptr[2] << FLT_SHIFT;
1400 	}
1401 
1402 	for (i = netdev_mc_count(dev); i < 14; i++) {
1403 		*suptr++ = 0xffff << FLT_SHIFT;
1404 		*suptr++ = 0xffff << FLT_SHIFT;
1405 		*suptr++ = 0xffff << FLT_SHIFT;
1406 	}
1407 
1408 	/* prepare the setup frame */
1409 	db->tx_insert_ptr = txptr->next_tx_desc;
1410 	txptr->tdes1 = cpu_to_le32(0x890000c0);
1411 
1412 	/* Resource Check and Send the setup packet */
1413 	if (db->tx_packet_cnt < TX_DESC_CNT) {
1414 		/* Resource Empty */
1415 		db->tx_packet_cnt++;
1416 		txptr->tdes0 = cpu_to_le32(0x80000000);
1417 		update_cr6(db->cr6_data | 0x2000, ioaddr);
1418 		uw32(DCR1, 0x1);	/* Issue Tx polling */
1419 		update_cr6(db->cr6_data, ioaddr);
1420 		netif_trans_update(dev);
1421 	} else
1422 		netdev_err(dev, "No Tx resource - Send_filter_frame!\n");
1423 }
1424 
1425 
1426 /*
1427  *	Allocate rx buffer,
1428  *	As possible as allocate maxiumn Rx buffer
1429  */
1430 
1431 static void allocate_rx_buffer(struct net_device *dev)
1432 {
1433 	struct uli526x_board_info *db = netdev_priv(dev);
1434 	struct rx_desc *rxptr;
1435 	struct sk_buff *skb;
1436 
1437 	rxptr = db->rx_insert_ptr;
1438 
1439 	while(db->rx_avail_cnt < RX_DESC_CNT) {
1440 		skb = netdev_alloc_skb(dev, RX_ALLOC_SIZE);
1441 		if (skb == NULL)
1442 			break;
1443 		rxptr->rx_skb_ptr = skb; /* FIXME (?) */
1444 		rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1445 							  skb_tail_pointer(skb),
1446 							  RX_ALLOC_SIZE,
1447 							  PCI_DMA_FROMDEVICE));
1448 		wmb();
1449 		rxptr->rdes0 = cpu_to_le32(0x80000000);
1450 		rxptr = rxptr->next_rx_desc;
1451 		db->rx_avail_cnt++;
1452 	}
1453 
1454 	db->rx_insert_ptr = rxptr;
1455 }
1456 
1457 
1458 /*
1459  *	Read one word data from the serial ROM
1460  */
1461 
1462 static u16 read_srom_word(struct uli526x_board_info *db, int offset)
1463 {
1464 	void __iomem *ioaddr = db->ioaddr;
1465 	u16 srom_data = 0;
1466 	int i;
1467 
1468 	uw32(DCR9, CR9_SROM_READ);
1469 	uw32(DCR9, CR9_SROM_READ | CR9_SRCS);
1470 
1471 	/* Send the Read Command 110b */
1472 	srom_clk_write(db, SROM_DATA_1);
1473 	srom_clk_write(db, SROM_DATA_1);
1474 	srom_clk_write(db, SROM_DATA_0);
1475 
1476 	/* Send the offset */
1477 	for (i = 5; i >= 0; i--) {
1478 		srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1479 		srom_clk_write(db, srom_data);
1480 	}
1481 
1482 	uw32(DCR9, CR9_SROM_READ | CR9_SRCS);
1483 
1484 	for (i = 16; i > 0; i--) {
1485 		uw32(DCR9, CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);
1486 		udelay(5);
1487 		srom_data = (srom_data << 1) |
1488 			    ((ur32(DCR9) & CR9_CRDOUT) ? 1 : 0);
1489 		uw32(DCR9, CR9_SROM_READ | CR9_SRCS);
1490 		udelay(5);
1491 	}
1492 
1493 	uw32(DCR9, CR9_SROM_READ);
1494 	return srom_data;
1495 }
1496 
1497 
1498 /*
1499  *	Auto sense the media mode
1500  */
1501 
1502 static u8 uli526x_sense_speed(struct uli526x_board_info * db)
1503 {
1504 	struct uli_phy_ops *phy = &db->phy;
1505 	u8 ErrFlag = 0;
1506 	u16 phy_mode;
1507 
1508 	phy_mode = phy->read(db, db->phy_addr, 1);
1509 	phy_mode = phy->read(db, db->phy_addr, 1);
1510 
1511 	if ( (phy_mode & 0x24) == 0x24 ) {
1512 
1513 		phy_mode = ((phy->read(db, db->phy_addr, 5) & 0x01e0)<<7);
1514 		if(phy_mode&0x8000)
1515 			phy_mode = 0x8000;
1516 		else if(phy_mode&0x4000)
1517 			phy_mode = 0x4000;
1518 		else if(phy_mode&0x2000)
1519 			phy_mode = 0x2000;
1520 		else
1521 			phy_mode = 0x1000;
1522 
1523 		switch (phy_mode) {
1524 		case 0x1000: db->op_mode = ULI526X_10MHF; break;
1525 		case 0x2000: db->op_mode = ULI526X_10MFD; break;
1526 		case 0x4000: db->op_mode = ULI526X_100MHF; break;
1527 		case 0x8000: db->op_mode = ULI526X_100MFD; break;
1528 		default: db->op_mode = ULI526X_10MHF; ErrFlag = 1; break;
1529 		}
1530 	} else {
1531 		db->op_mode = ULI526X_10MHF;
1532 		ULI526X_DBUG(0, "Link Failed :", phy_mode);
1533 		ErrFlag = 1;
1534 	}
1535 
1536 	return ErrFlag;
1537 }
1538 
1539 
1540 /*
1541  *	Set 10/100 phyxcer capability
1542  *	AUTO mode : phyxcer register4 is NIC capability
1543  *	Force mode: phyxcer register4 is the force media
1544  */
1545 
1546 static void uli526x_set_phyxcer(struct uli526x_board_info *db)
1547 {
1548 	struct uli_phy_ops *phy = &db->phy;
1549 	u16 phy_reg;
1550 
1551 	/* Phyxcer capability setting */
1552 	phy_reg = phy->read(db, db->phy_addr, 4) & ~0x01e0;
1553 
1554 	if (db->media_mode & ULI526X_AUTO) {
1555 		/* AUTO Mode */
1556 		phy_reg |= db->PHY_reg4;
1557 	} else {
1558 		/* Force Mode */
1559 		switch(db->media_mode) {
1560 		case ULI526X_10MHF: phy_reg |= 0x20; break;
1561 		case ULI526X_10MFD: phy_reg |= 0x40; break;
1562 		case ULI526X_100MHF: phy_reg |= 0x80; break;
1563 		case ULI526X_100MFD: phy_reg |= 0x100; break;
1564 		}
1565 
1566 	}
1567 
1568   	/* Write new capability to Phyxcer Reg4 */
1569 	if ( !(phy_reg & 0x01e0)) {
1570 		phy_reg|=db->PHY_reg4;
1571 		db->media_mode|=ULI526X_AUTO;
1572 	}
1573 	phy->write(db, db->phy_addr, 4, phy_reg);
1574 
1575  	/* Restart Auto-Negotiation */
1576 	phy->write(db, db->phy_addr, 0, 0x1200);
1577 	udelay(50);
1578 }
1579 
1580 
1581 /*
1582  *	Process op-mode
1583  	AUTO mode : PHY controller in Auto-negotiation Mode
1584  *	Force mode: PHY controller in force mode with HUB
1585  *			N-way force capability with SWITCH
1586  */
1587 
1588 static void uli526x_process_mode(struct uli526x_board_info *db)
1589 {
1590 	struct uli_phy_ops *phy = &db->phy;
1591 	u16 phy_reg;
1592 
1593 	/* Full Duplex Mode Check */
1594 	if (db->op_mode & 0x4)
1595 		db->cr6_data |= CR6_FDM;	/* Set Full Duplex Bit */
1596 	else
1597 		db->cr6_data &= ~CR6_FDM;	/* Clear Full Duplex Bit */
1598 
1599 	update_cr6(db->cr6_data, db->ioaddr);
1600 
1601 	/* 10/100M phyxcer force mode need */
1602 	if (!(db->media_mode & 0x8)) {
1603 		/* Forece Mode */
1604 		phy_reg = phy->read(db, db->phy_addr, 6);
1605 		if (!(phy_reg & 0x1)) {
1606 			/* parter without N-Way capability */
1607 			phy_reg = 0x0;
1608 			switch(db->op_mode) {
1609 			case ULI526X_10MHF: phy_reg = 0x0; break;
1610 			case ULI526X_10MFD: phy_reg = 0x100; break;
1611 			case ULI526X_100MHF: phy_reg = 0x2000; break;
1612 			case ULI526X_100MFD: phy_reg = 0x2100; break;
1613 			}
1614 			phy->write(db, db->phy_addr, 0, phy_reg);
1615 		}
1616 	}
1617 }
1618 
1619 
1620 /* M5261/M5263 Chip */
1621 static void phy_writeby_cr9(struct uli526x_board_info *db, u8 phy_addr,
1622 			    u8 offset, u16 phy_data)
1623 {
1624 	u16 i;
1625 
1626 	/* Send 33 synchronization clock to Phy controller */
1627 	for (i = 0; i < 35; i++)
1628 		phy_write_1bit(db, PHY_DATA_1);
1629 
1630 	/* Send start command(01) to Phy */
1631 	phy_write_1bit(db, PHY_DATA_0);
1632 	phy_write_1bit(db, PHY_DATA_1);
1633 
1634 	/* Send write command(01) to Phy */
1635 	phy_write_1bit(db, PHY_DATA_0);
1636 	phy_write_1bit(db, PHY_DATA_1);
1637 
1638 	/* Send Phy address */
1639 	for (i = 0x10; i > 0; i = i >> 1)
1640 		phy_write_1bit(db, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1641 
1642 	/* Send register address */
1643 	for (i = 0x10; i > 0; i = i >> 1)
1644 		phy_write_1bit(db, offset & i ? PHY_DATA_1 : PHY_DATA_0);
1645 
1646 	/* written trasnition */
1647 	phy_write_1bit(db, PHY_DATA_1);
1648 	phy_write_1bit(db, PHY_DATA_0);
1649 
1650 	/* Write a word data to PHY controller */
1651 	for (i = 0x8000; i > 0; i >>= 1)
1652 		phy_write_1bit(db, phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
1653 }
1654 
1655 static u16 phy_readby_cr9(struct uli526x_board_info *db, u8 phy_addr, u8 offset)
1656 {
1657 	u16 phy_data;
1658 	int i;
1659 
1660 	/* Send 33 synchronization clock to Phy controller */
1661 	for (i = 0; i < 35; i++)
1662 		phy_write_1bit(db, PHY_DATA_1);
1663 
1664 	/* Send start command(01) to Phy */
1665 	phy_write_1bit(db, PHY_DATA_0);
1666 	phy_write_1bit(db, PHY_DATA_1);
1667 
1668 	/* Send read command(10) to Phy */
1669 	phy_write_1bit(db, PHY_DATA_1);
1670 	phy_write_1bit(db, PHY_DATA_0);
1671 
1672 	/* Send Phy address */
1673 	for (i = 0x10; i > 0; i = i >> 1)
1674 		phy_write_1bit(db, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1675 
1676 	/* Send register address */
1677 	for (i = 0x10; i > 0; i = i >> 1)
1678 		phy_write_1bit(db, offset & i ? PHY_DATA_1 : PHY_DATA_0);
1679 
1680 	/* Skip transition state */
1681 	phy_read_1bit(db);
1682 
1683 	/* read 16bit data */
1684 	for (phy_data = 0, i = 0; i < 16; i++) {
1685 		phy_data <<= 1;
1686 		phy_data |= phy_read_1bit(db);
1687 	}
1688 
1689 	return phy_data;
1690 }
1691 
1692 static u16 phy_readby_cr10(struct uli526x_board_info *db, u8 phy_addr,
1693 			   u8 offset)
1694 {
1695 	void __iomem *ioaddr = db->ioaddr;
1696 	u32 cr10_value = phy_addr;
1697 
1698 	cr10_value = (cr10_value <<  5) + offset;
1699 	cr10_value = (cr10_value << 16) + 0x08000000;
1700 	uw32(DCR10, cr10_value);
1701 	udelay(1);
1702 	while (1) {
1703 		cr10_value = ur32(DCR10);
1704 		if (cr10_value & 0x10000000)
1705 			break;
1706 	}
1707 	return cr10_value & 0x0ffff;
1708 }
1709 
1710 static void phy_writeby_cr10(struct uli526x_board_info *db, u8 phy_addr,
1711 			     u8 offset, u16 phy_data)
1712 {
1713 	void __iomem *ioaddr = db->ioaddr;
1714 	u32 cr10_value = phy_addr;
1715 
1716 	cr10_value = (cr10_value <<  5) + offset;
1717 	cr10_value = (cr10_value << 16) + 0x04000000 + phy_data;
1718 	uw32(DCR10, cr10_value);
1719 	udelay(1);
1720 }
1721 /*
1722  *	Write one bit data to Phy Controller
1723  */
1724 
1725 static void phy_write_1bit(struct uli526x_board_info *db, u32 data)
1726 {
1727 	void __iomem *ioaddr = db->ioaddr;
1728 
1729 	uw32(DCR9, data);		/* MII Clock Low */
1730 	udelay(1);
1731 	uw32(DCR9, data | MDCLKH);	/* MII Clock High */
1732 	udelay(1);
1733 	uw32(DCR9, data);		/* MII Clock Low */
1734 	udelay(1);
1735 }
1736 
1737 
1738 /*
1739  *	Read one bit phy data from PHY controller
1740  */
1741 
1742 static u16 phy_read_1bit(struct uli526x_board_info *db)
1743 {
1744 	void __iomem *ioaddr = db->ioaddr;
1745 	u16 phy_data;
1746 
1747 	uw32(DCR9, 0x50000);
1748 	udelay(1);
1749 	phy_data = (ur32(DCR9) >> 19) & 0x1;
1750 	uw32(DCR9, 0x40000);
1751 	udelay(1);
1752 
1753 	return phy_data;
1754 }
1755 
1756 
1757 static const struct pci_device_id uli526x_pci_tbl[] = {
1758 	{ 0x10B9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5261_ID },
1759 	{ 0x10B9, 0x5263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5263_ID },
1760 	{ 0, }
1761 };
1762 MODULE_DEVICE_TABLE(pci, uli526x_pci_tbl);
1763 
1764 
1765 static struct pci_driver uli526x_driver = {
1766 	.name		= "uli526x",
1767 	.id_table	= uli526x_pci_tbl,
1768 	.probe		= uli526x_init_one,
1769 	.remove		= uli526x_remove_one,
1770 	.suspend	= uli526x_suspend,
1771 	.resume		= uli526x_resume,
1772 };
1773 
1774 MODULE_AUTHOR("Peer Chen, peer.chen@uli.com.tw");
1775 MODULE_DESCRIPTION("ULi M5261/M5263 fast ethernet driver");
1776 MODULE_LICENSE("GPL");
1777 
1778 module_param(debug, int, 0644);
1779 module_param(mode, int, 0);
1780 module_param(cr6set, int, 0);
1781 MODULE_PARM_DESC(debug, "ULi M5261/M5263 enable debugging (0-1)");
1782 MODULE_PARM_DESC(mode, "ULi M5261/M5263: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
1783 
1784 /*	Description:
1785  *	when user used insmod to add module, system invoked init_module()
1786  *	to register the services.
1787  */
1788 
1789 static int __init uli526x_init_module(void)
1790 {
1791 
1792 	ULI526X_DBUG(0, "init_module() ", debug);
1793 
1794 	if (debug)
1795 		uli526x_debug = debug;	/* set debug flag */
1796 	if (cr6set)
1797 		uli526x_cr6_user_set = cr6set;
1798 
1799 	switch (mode) {
1800 	case ULI526X_10MHF:
1801 	case ULI526X_100MHF:
1802 	case ULI526X_10MFD:
1803 	case ULI526X_100MFD:
1804 		uli526x_media_mode = mode;
1805 		break;
1806 	default:
1807 		uli526x_media_mode = ULI526X_AUTO;
1808 		break;
1809 	}
1810 
1811 	return pci_register_driver(&uli526x_driver);
1812 }
1813 
1814 
1815 /*
1816  *	Description:
1817  *	when user used rmmod to delete module, system invoked clean_module()
1818  *	to un-register all registered services.
1819  */
1820 
1821 static void __exit uli526x_cleanup_module(void)
1822 {
1823 	ULI526X_DBUG(0, "uli526x_cleanup_module() ", debug);
1824 	pci_unregister_driver(&uli526x_driver);
1825 }
1826 
1827 module_init(uli526x_init_module);
1828 module_exit(uli526x_cleanup_module);
1829