1 /*
2     This program is free software; you can redistribute it and/or
3     modify it under the terms of the GNU General Public License
4     as published by the Free Software Foundation; either version 2
5     of the License, or (at your option) any later version.
6 
7     This program is distributed in the hope that it will be useful,
8     but WITHOUT ANY WARRANTY; without even the implied warranty of
9     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
10     GNU General Public License for more details.
11 
12 
13 */
14 
15 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16 
17 #define DRV_NAME	"uli526x"
18 #define DRV_VERSION	"0.9.3"
19 #define DRV_RELDATE	"2005-7-29"
20 
21 #include <linux/module.h>
22 
23 #include <linux/kernel.h>
24 #include <linux/string.h>
25 #include <linux/timer.h>
26 #include <linux/errno.h>
27 #include <linux/ioport.h>
28 #include <linux/interrupt.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/skbuff.h>
35 #include <linux/delay.h>
36 #include <linux/spinlock.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/bitops.h>
39 
40 #include <asm/processor.h>
41 #include <asm/io.h>
42 #include <asm/dma.h>
43 #include <asm/uaccess.h>
44 
45 #define uw32(reg, val)	iowrite32(val, ioaddr + (reg))
46 #define ur32(reg)	ioread32(ioaddr + (reg))
47 
48 /* Board/System/Debug information/definition ---------------- */
49 #define PCI_ULI5261_ID  0x526110B9	/* ULi M5261 ID*/
50 #define PCI_ULI5263_ID  0x526310B9	/* ULi M5263 ID*/
51 
52 #define ULI526X_IO_SIZE 0x100
53 #define TX_DESC_CNT     0x20            /* Allocated Tx descriptors */
54 #define RX_DESC_CNT     0x30            /* Allocated Rx descriptors */
55 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2)	/* Max TX packet count */
56 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3)	/* TX wakeup count */
57 #define DESC_ALL_CNT    (TX_DESC_CNT + RX_DESC_CNT)
58 #define TX_BUF_ALLOC    0x600
59 #define RX_ALLOC_SIZE   0x620
60 #define ULI526X_RESET    1
61 #define CR0_DEFAULT     0
62 #define CR6_DEFAULT     0x22200000
63 #define CR7_DEFAULT     0x180c1
64 #define CR15_DEFAULT    0x06            /* TxJabber RxWatchdog */
65 #define TDES0_ERR_MASK  0x4302          /* TXJT, LC, EC, FUE */
66 #define MAX_PACKET_SIZE 1514
67 #define ULI5261_MAX_MULTICAST 14
68 #define RX_COPY_SIZE	100
69 #define MAX_CHECK_PACKET 0x8000
70 
71 #define ULI526X_10MHF      0
72 #define ULI526X_100MHF     1
73 #define ULI526X_10MFD      4
74 #define ULI526X_100MFD     5
75 #define ULI526X_AUTO       8
76 
77 #define ULI526X_TXTH_72	0x400000	/* TX TH 72 byte */
78 #define ULI526X_TXTH_96	0x404000	/* TX TH 96 byte */
79 #define ULI526X_TXTH_128	0x0000		/* TX TH 128 byte */
80 #define ULI526X_TXTH_256	0x4000		/* TX TH 256 byte */
81 #define ULI526X_TXTH_512	0x8000		/* TX TH 512 byte */
82 #define ULI526X_TXTH_1K	0xC000		/* TX TH 1K  byte */
83 
84 #define ULI526X_TIMER_WUT  (jiffies + HZ * 1)/* timer wakeup time : 1 second */
85 #define ULI526X_TX_TIMEOUT ((16*HZ)/2)	/* tx packet time-out time 8 s" */
86 #define ULI526X_TX_KICK 	(4*HZ/2)	/* tx packet Kick-out time 2 s" */
87 
88 #define ULI526X_DBUG(dbug_now, msg, value)			\
89 do {								\
90 	if (uli526x_debug || (dbug_now))			\
91 		pr_err("%s %lx\n", (msg), (long) (value));	\
92 } while (0)
93 
94 #define SHOW_MEDIA_TYPE(mode)					\
95 	pr_err("Change Speed to %sMhz %s duplex\n",		\
96 	       mode & 1 ? "100" : "10",				\
97 	       mode & 4 ? "full" : "half");
98 
99 
100 /* CR9 definition: SROM/MII */
101 #define CR9_SROM_READ   0x4800
102 #define CR9_SRCS        0x1
103 #define CR9_SRCLK       0x2
104 #define CR9_CRDOUT      0x8
105 #define SROM_DATA_0     0x0
106 #define SROM_DATA_1     0x4
107 #define PHY_DATA_1      0x20000
108 #define PHY_DATA_0      0x00000
109 #define MDCLKH          0x10000
110 
111 #define PHY_POWER_DOWN	0x800
112 
113 #define SROM_V41_CODE   0x14
114 
115 /* Structure/enum declaration ------------------------------- */
116 struct tx_desc {
117         __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
118         char *tx_buf_ptr;               /* Data for us */
119         struct tx_desc *next_tx_desc;
120 } __attribute__(( aligned(32) ));
121 
122 struct rx_desc {
123 	__le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
124 	struct sk_buff *rx_skb_ptr;	/* Data for us */
125 	struct rx_desc *next_rx_desc;
126 } __attribute__(( aligned(32) ));
127 
128 struct uli526x_board_info {
129 	struct uli_phy_ops {
130 		void (*write)(struct uli526x_board_info *, u8, u8, u16);
131 		u16 (*read)(struct uli526x_board_info *, u8, u8);
132 	} phy;
133 	struct net_device *next_dev;	/* next device */
134 	struct pci_dev *pdev;		/* PCI device */
135 	spinlock_t lock;
136 
137 	void __iomem *ioaddr;		/* I/O base address */
138 	u32 cr0_data;
139 	u32 cr5_data;
140 	u32 cr6_data;
141 	u32 cr7_data;
142 	u32 cr15_data;
143 
144 	/* pointer for memory physical address */
145 	dma_addr_t buf_pool_dma_ptr;	/* Tx buffer pool memory */
146 	dma_addr_t buf_pool_dma_start;	/* Tx buffer pool align dword */
147 	dma_addr_t desc_pool_dma_ptr;	/* descriptor pool memory */
148 	dma_addr_t first_tx_desc_dma;
149 	dma_addr_t first_rx_desc_dma;
150 
151 	/* descriptor pointer */
152 	unsigned char *buf_pool_ptr;	/* Tx buffer pool memory */
153 	unsigned char *buf_pool_start;	/* Tx buffer pool align dword */
154 	unsigned char *desc_pool_ptr;	/* descriptor pool memory */
155 	struct tx_desc *first_tx_desc;
156 	struct tx_desc *tx_insert_ptr;
157 	struct tx_desc *tx_remove_ptr;
158 	struct rx_desc *first_rx_desc;
159 	struct rx_desc *rx_insert_ptr;
160 	struct rx_desc *rx_ready_ptr;	/* packet come pointer */
161 	unsigned long tx_packet_cnt;	/* transmitted packet count */
162 	unsigned long rx_avail_cnt;	/* available rx descriptor count */
163 	unsigned long interval_rx_cnt;	/* rx packet count a callback time */
164 
165 	u16 dbug_cnt;
166 	u16 NIC_capability;		/* NIC media capability */
167 	u16 PHY_reg4;			/* Saved Phyxcer register 4 value */
168 
169 	u8 media_mode;			/* user specify media mode */
170 	u8 op_mode;			/* real work media mode */
171 	u8 phy_addr;
172 	u8 link_failed;			/* Ever link failed */
173 	u8 wait_reset;			/* Hardware failed, need to reset */
174 	struct timer_list timer;
175 
176 	/* Driver defined statistic counter */
177 	unsigned long tx_fifo_underrun;
178 	unsigned long tx_loss_carrier;
179 	unsigned long tx_no_carrier;
180 	unsigned long tx_late_collision;
181 	unsigned long tx_excessive_collision;
182 	unsigned long tx_jabber_timeout;
183 	unsigned long reset_count;
184 	unsigned long reset_cr8;
185 	unsigned long reset_fatal;
186 	unsigned long reset_TXtimeout;
187 
188 	/* NIC SROM data */
189 	unsigned char srom[128];
190 	u8 init;
191 };
192 
193 enum uli526x_offsets {
194 	DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
195 	DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
196 	DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
197 	DCR15 = 0x78
198 };
199 
200 enum uli526x_CR6_bits {
201 	CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
202 	CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
203 	CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
204 };
205 
206 /* Global variable declaration ----------------------------- */
207 static int printed_version;
208 static const char version[] =
209 	"ULi M5261/M5263 net driver, version " DRV_VERSION " (" DRV_RELDATE ")";
210 
211 static int uli526x_debug;
212 static unsigned char uli526x_media_mode = ULI526X_AUTO;
213 static u32 uli526x_cr6_user_set;
214 
215 /* For module input parameter */
216 static int debug;
217 static u32 cr6set;
218 static int mode = 8;
219 
220 /* function declaration ------------------------------------- */
221 static int uli526x_open(struct net_device *);
222 static netdev_tx_t uli526x_start_xmit(struct sk_buff *,
223 					    struct net_device *);
224 static int uli526x_stop(struct net_device *);
225 static void uli526x_set_filter_mode(struct net_device *);
226 static const struct ethtool_ops netdev_ethtool_ops;
227 static u16 read_srom_word(struct uli526x_board_info *, int);
228 static irqreturn_t uli526x_interrupt(int, void *);
229 #ifdef CONFIG_NET_POLL_CONTROLLER
230 static void uli526x_poll(struct net_device *dev);
231 #endif
232 static void uli526x_descriptor_init(struct net_device *, void __iomem *);
233 static void allocate_rx_buffer(struct net_device *);
234 static void update_cr6(u32, void __iomem *);
235 static void send_filter_frame(struct net_device *, int);
236 static u16 phy_readby_cr9(struct uli526x_board_info *, u8, u8);
237 static u16 phy_readby_cr10(struct uli526x_board_info *, u8, u8);
238 static void phy_writeby_cr9(struct uli526x_board_info *, u8, u8, u16);
239 static void phy_writeby_cr10(struct uli526x_board_info *, u8, u8, u16);
240 static void phy_write_1bit(struct uli526x_board_info *db, u32);
241 static u16 phy_read_1bit(struct uli526x_board_info *db);
242 static u8 uli526x_sense_speed(struct uli526x_board_info *);
243 static void uli526x_process_mode(struct uli526x_board_info *);
244 static void uli526x_timer(unsigned long);
245 static void uli526x_rx_packet(struct net_device *, struct uli526x_board_info *);
246 static void uli526x_free_tx_pkt(struct net_device *, struct uli526x_board_info *);
247 static void uli526x_reuse_skb(struct uli526x_board_info *, struct sk_buff *);
248 static void uli526x_dynamic_reset(struct net_device *);
249 static void uli526x_free_rxbuffer(struct uli526x_board_info *);
250 static void uli526x_init(struct net_device *);
251 static void uli526x_set_phyxcer(struct uli526x_board_info *);
252 
253 static void srom_clk_write(struct uli526x_board_info *db, u32 data)
254 {
255 	void __iomem *ioaddr = db->ioaddr;
256 
257 	uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS);
258 	udelay(5);
259 	uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);
260 	udelay(5);
261 	uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS);
262 	udelay(5);
263 }
264 
265 /* ULI526X network board routine ---------------------------- */
266 
267 static const struct net_device_ops netdev_ops = {
268 	.ndo_open		= uli526x_open,
269 	.ndo_stop		= uli526x_stop,
270 	.ndo_start_xmit		= uli526x_start_xmit,
271 	.ndo_set_rx_mode	= uli526x_set_filter_mode,
272 	.ndo_change_mtu		= eth_change_mtu,
273 	.ndo_set_mac_address	= eth_mac_addr,
274 	.ndo_validate_addr	= eth_validate_addr,
275 #ifdef CONFIG_NET_POLL_CONTROLLER
276 	.ndo_poll_controller 	= uli526x_poll,
277 #endif
278 };
279 
280 /*
281  *	Search ULI526X board, allocate space and register it
282  */
283 
284 static int uli526x_init_one(struct pci_dev *pdev,
285 			    const struct pci_device_id *ent)
286 {
287 	struct uli526x_board_info *db;	/* board information structure */
288 	struct net_device *dev;
289 	void __iomem *ioaddr;
290 	int i, err;
291 
292 	ULI526X_DBUG(0, "uli526x_init_one()", 0);
293 
294 	if (!printed_version++)
295 		pr_info("%s\n", version);
296 
297 	/* Init network device */
298 	dev = alloc_etherdev(sizeof(*db));
299 	if (dev == NULL)
300 		return -ENOMEM;
301 	SET_NETDEV_DEV(dev, &pdev->dev);
302 
303 	if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
304 		pr_warn("32-bit PCI DMA not available\n");
305 		err = -ENODEV;
306 		goto err_out_free;
307 	}
308 
309 	/* Enable Master/IO access, Disable memory access */
310 	err = pci_enable_device(pdev);
311 	if (err)
312 		goto err_out_free;
313 
314 	if (!pci_resource_start(pdev, 0)) {
315 		pr_err("I/O base is zero\n");
316 		err = -ENODEV;
317 		goto err_out_disable;
318 	}
319 
320 	if (pci_resource_len(pdev, 0) < (ULI526X_IO_SIZE) ) {
321 		pr_err("Allocated I/O size too small\n");
322 		err = -ENODEV;
323 		goto err_out_disable;
324 	}
325 
326 	err = pci_request_regions(pdev, DRV_NAME);
327 	if (err < 0) {
328 		pr_err("Failed to request PCI regions\n");
329 		goto err_out_disable;
330 	}
331 
332 	/* Init system & device */
333 	db = netdev_priv(dev);
334 
335 	/* Allocate Tx/Rx descriptor memory */
336 	err = -ENOMEM;
337 
338 	db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
339 	if (!db->desc_pool_ptr)
340 		goto err_out_release;
341 
342 	db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
343 	if (!db->buf_pool_ptr)
344 		goto err_out_free_tx_desc;
345 
346 	db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
347 	db->first_tx_desc_dma = db->desc_pool_dma_ptr;
348 	db->buf_pool_start = db->buf_pool_ptr;
349 	db->buf_pool_dma_start = db->buf_pool_dma_ptr;
350 
351 	switch (ent->driver_data) {
352 	case PCI_ULI5263_ID:
353 		db->phy.write	= phy_writeby_cr10;
354 		db->phy.read	= phy_readby_cr10;
355 		break;
356 	default:
357 		db->phy.write	= phy_writeby_cr9;
358 		db->phy.read	= phy_readby_cr9;
359 		break;
360 	}
361 
362 	/* IO region. */
363 	ioaddr = pci_iomap(pdev, 0, 0);
364 	if (!ioaddr)
365 		goto err_out_free_tx_buf;
366 
367 	db->ioaddr = ioaddr;
368 	db->pdev = pdev;
369 	db->init = 1;
370 
371 	pci_set_drvdata(pdev, dev);
372 
373 	/* Register some necessary functions */
374 	dev->netdev_ops = &netdev_ops;
375 	dev->ethtool_ops = &netdev_ethtool_ops;
376 
377 	spin_lock_init(&db->lock);
378 
379 
380 	/* read 64 word srom data */
381 	for (i = 0; i < 64; i++)
382 		((__le16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db, i));
383 
384 	/* Set Node address */
385 	if(((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0)		/* SROM absent, so read MAC address from ID Table */
386 	{
387 		uw32(DCR0, 0x10000);	//Diagnosis mode
388 		uw32(DCR13, 0x1c0);	//Reset dianostic pointer port
389 		uw32(DCR14, 0);		//Clear reset port
390 		uw32(DCR14, 0x10);	//Reset ID Table pointer
391 		uw32(DCR14, 0);		//Clear reset port
392 		uw32(DCR13, 0);		//Clear CR13
393 		uw32(DCR13, 0x1b0);	//Select ID Table access port
394 		//Read MAC address from CR14
395 		for (i = 0; i < 6; i++)
396 			dev->dev_addr[i] = ur32(DCR14);
397 		//Read end
398 		uw32(DCR13, 0);		//Clear CR13
399 		uw32(DCR0, 0);		//Clear CR0
400 		udelay(10);
401 	}
402 	else		/*Exist SROM*/
403 	{
404 		for (i = 0; i < 6; i++)
405 			dev->dev_addr[i] = db->srom[20 + i];
406 	}
407 	err = register_netdev (dev);
408 	if (err)
409 		goto err_out_unmap;
410 
411 	netdev_info(dev, "ULi M%04lx at pci%s, %pM, irq %d\n",
412 		    ent->driver_data >> 16, pci_name(pdev),
413 		    dev->dev_addr, pdev->irq);
414 
415 	pci_set_master(pdev);
416 
417 	return 0;
418 
419 err_out_unmap:
420 	pci_iounmap(pdev, db->ioaddr);
421 err_out_free_tx_buf:
422 	pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
423 			    db->buf_pool_ptr, db->buf_pool_dma_ptr);
424 err_out_free_tx_desc:
425 	pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
426 			    db->desc_pool_ptr, db->desc_pool_dma_ptr);
427 err_out_release:
428 	pci_release_regions(pdev);
429 err_out_disable:
430 	pci_disable_device(pdev);
431 err_out_free:
432 	free_netdev(dev);
433 
434 	return err;
435 }
436 
437 
438 static void uli526x_remove_one(struct pci_dev *pdev)
439 {
440 	struct net_device *dev = pci_get_drvdata(pdev);
441 	struct uli526x_board_info *db = netdev_priv(dev);
442 
443 	unregister_netdev(dev);
444 	pci_iounmap(pdev, db->ioaddr);
445 	pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
446 				DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
447  				db->desc_pool_dma_ptr);
448 	pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
449 				db->buf_pool_ptr, db->buf_pool_dma_ptr);
450 	pci_release_regions(pdev);
451 	pci_disable_device(pdev);
452 	free_netdev(dev);
453 }
454 
455 
456 /*
457  *	Open the interface.
458  *	The interface is opened whenever "ifconfig" activates it.
459  */
460 
461 static int uli526x_open(struct net_device *dev)
462 {
463 	int ret;
464 	struct uli526x_board_info *db = netdev_priv(dev);
465 
466 	ULI526X_DBUG(0, "uli526x_open", 0);
467 
468 	/* system variable init */
469 	db->cr6_data = CR6_DEFAULT | uli526x_cr6_user_set;
470 	db->tx_packet_cnt = 0;
471 	db->rx_avail_cnt = 0;
472 	db->link_failed = 1;
473 	netif_carrier_off(dev);
474 	db->wait_reset = 0;
475 
476 	db->NIC_capability = 0xf;	/* All capability*/
477 	db->PHY_reg4 = 0x1e0;
478 
479 	/* CR6 operation mode decision */
480 	db->cr6_data |= ULI526X_TXTH_256;
481 	db->cr0_data = CR0_DEFAULT;
482 
483 	/* Initialize ULI526X board */
484 	uli526x_init(dev);
485 
486 	ret = request_irq(db->pdev->irq, uli526x_interrupt, IRQF_SHARED,
487 			  dev->name, dev);
488 	if (ret)
489 		return ret;
490 
491 	/* Active System Interface */
492 	netif_wake_queue(dev);
493 
494 	/* set and active a timer process */
495 	init_timer(&db->timer);
496 	db->timer.expires = ULI526X_TIMER_WUT + HZ * 2;
497 	db->timer.data = (unsigned long)dev;
498 	db->timer.function = uli526x_timer;
499 	add_timer(&db->timer);
500 
501 	return 0;
502 }
503 
504 
505 /*	Initialize ULI526X board
506  *	Reset ULI526X board
507  *	Initialize TX/Rx descriptor chain structure
508  *	Send the set-up frame
509  *	Enable Tx/Rx machine
510  */
511 
512 static void uli526x_init(struct net_device *dev)
513 {
514 	struct uli526x_board_info *db = netdev_priv(dev);
515 	struct uli_phy_ops *phy = &db->phy;
516 	void __iomem *ioaddr = db->ioaddr;
517 	u8	phy_tmp;
518 	u8	timeout;
519 	u16 phy_reg_reset;
520 
521 
522 	ULI526X_DBUG(0, "uli526x_init()", 0);
523 
524 	/* Reset M526x MAC controller */
525 	uw32(DCR0, ULI526X_RESET);	/* RESET MAC */
526 	udelay(100);
527 	uw32(DCR0, db->cr0_data);
528 	udelay(5);
529 
530 	/* Phy addr : In some boards,M5261/M5263 phy address != 1 */
531 	db->phy_addr = 1;
532 	for (phy_tmp = 0; phy_tmp < 32; phy_tmp++) {
533 		u16 phy_value;
534 
535 		phy_value = phy->read(db, phy_tmp, 3);	//peer add
536 		if (phy_value != 0xffff && phy_value != 0) {
537 			db->phy_addr = phy_tmp;
538 			break;
539 		}
540 	}
541 
542 	if (phy_tmp == 32)
543 		pr_warn("Can not find the phy address!!!\n");
544 	/* Parser SROM and media mode */
545 	db->media_mode = uli526x_media_mode;
546 
547 	/* phyxcer capability setting */
548 	phy_reg_reset = phy->read(db, db->phy_addr, 0);
549 	phy_reg_reset = (phy_reg_reset | 0x8000);
550 	phy->write(db, db->phy_addr, 0, phy_reg_reset);
551 
552 	/* See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management
553 	 * functions") or phy data sheet for details on phy reset
554 	 */
555 	udelay(500);
556 	timeout = 10;
557 	while (timeout-- && phy->read(db, db->phy_addr, 0) & 0x8000)
558 		udelay(100);
559 
560 	/* Process Phyxcer Media Mode */
561 	uli526x_set_phyxcer(db);
562 
563 	/* Media Mode Process */
564 	if ( !(db->media_mode & ULI526X_AUTO) )
565 		db->op_mode = db->media_mode;		/* Force Mode */
566 
567 	/* Initialize Transmit/Receive descriptor and CR3/4 */
568 	uli526x_descriptor_init(dev, ioaddr);
569 
570 	/* Init CR6 to program M526X operation */
571 	update_cr6(db->cr6_data, ioaddr);
572 
573 	/* Send setup frame */
574 	send_filter_frame(dev, netdev_mc_count(dev));	/* M5261/M5263 */
575 
576 	/* Init CR7, interrupt active bit */
577 	db->cr7_data = CR7_DEFAULT;
578 	uw32(DCR7, db->cr7_data);
579 
580 	/* Init CR15, Tx jabber and Rx watchdog timer */
581 	uw32(DCR15, db->cr15_data);
582 
583 	/* Enable ULI526X Tx/Rx function */
584 	db->cr6_data |= CR6_RXSC | CR6_TXSC;
585 	update_cr6(db->cr6_data, ioaddr);
586 }
587 
588 
589 /*
590  *	Hardware start transmission.
591  *	Send a packet to media from the upper layer.
592  */
593 
594 static netdev_tx_t uli526x_start_xmit(struct sk_buff *skb,
595 					    struct net_device *dev)
596 {
597 	struct uli526x_board_info *db = netdev_priv(dev);
598 	void __iomem *ioaddr = db->ioaddr;
599 	struct tx_desc *txptr;
600 	unsigned long flags;
601 
602 	ULI526X_DBUG(0, "uli526x_start_xmit", 0);
603 
604 	/* Resource flag check */
605 	netif_stop_queue(dev);
606 
607 	/* Too large packet check */
608 	if (skb->len > MAX_PACKET_SIZE) {
609 		netdev_err(dev, "big packet = %d\n", (u16)skb->len);
610 		dev_kfree_skb_any(skb);
611 		return NETDEV_TX_OK;
612 	}
613 
614 	spin_lock_irqsave(&db->lock, flags);
615 
616 	/* No Tx resource check, it never happen nromally */
617 	if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
618 		spin_unlock_irqrestore(&db->lock, flags);
619 		netdev_err(dev, "No Tx resource %ld\n", db->tx_packet_cnt);
620 		return NETDEV_TX_BUSY;
621 	}
622 
623 	/* Disable NIC interrupt */
624 	uw32(DCR7, 0);
625 
626 	/* transmit this packet */
627 	txptr = db->tx_insert_ptr;
628 	skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
629 	txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
630 
631 	/* Point to next transmit free descriptor */
632 	db->tx_insert_ptr = txptr->next_tx_desc;
633 
634 	/* Transmit Packet Process */
635 	if (db->tx_packet_cnt < TX_DESC_CNT) {
636 		txptr->tdes0 = cpu_to_le32(0x80000000);	/* Set owner bit */
637 		db->tx_packet_cnt++;			/* Ready to send */
638 		uw32(DCR1, 0x1);			/* Issue Tx polling */
639 		dev->trans_start = jiffies;		/* saved time stamp */
640 	}
641 
642 	/* Tx resource check */
643 	if ( db->tx_packet_cnt < TX_FREE_DESC_CNT )
644 		netif_wake_queue(dev);
645 
646 	/* Restore CR7 to enable interrupt */
647 	spin_unlock_irqrestore(&db->lock, flags);
648 	uw32(DCR7, db->cr7_data);
649 
650 	/* free this SKB */
651 	dev_consume_skb_any(skb);
652 
653 	return NETDEV_TX_OK;
654 }
655 
656 
657 /*
658  *	Stop the interface.
659  *	The interface is stopped when it is brought.
660  */
661 
662 static int uli526x_stop(struct net_device *dev)
663 {
664 	struct uli526x_board_info *db = netdev_priv(dev);
665 	void __iomem *ioaddr = db->ioaddr;
666 
667 	/* disable system */
668 	netif_stop_queue(dev);
669 
670 	/* deleted timer */
671 	del_timer_sync(&db->timer);
672 
673 	/* Reset & stop ULI526X board */
674 	uw32(DCR0, ULI526X_RESET);
675 	udelay(5);
676 	db->phy.write(db, db->phy_addr, 0, 0x8000);
677 
678 	/* free interrupt */
679 	free_irq(db->pdev->irq, dev);
680 
681 	/* free allocated rx buffer */
682 	uli526x_free_rxbuffer(db);
683 
684 	return 0;
685 }
686 
687 
688 /*
689  *	M5261/M5263 insterrupt handler
690  *	receive the packet to upper layer, free the transmitted packet
691  */
692 
693 static irqreturn_t uli526x_interrupt(int irq, void *dev_id)
694 {
695 	struct net_device *dev = dev_id;
696 	struct uli526x_board_info *db = netdev_priv(dev);
697 	void __iomem *ioaddr = db->ioaddr;
698 	unsigned long flags;
699 
700 	spin_lock_irqsave(&db->lock, flags);
701 	uw32(DCR7, 0);
702 
703 	/* Got ULI526X status */
704 	db->cr5_data = ur32(DCR5);
705 	uw32(DCR5, db->cr5_data);
706 	if ( !(db->cr5_data & 0x180c1) ) {
707 		/* Restore CR7 to enable interrupt mask */
708 		uw32(DCR7, db->cr7_data);
709 		spin_unlock_irqrestore(&db->lock, flags);
710 		return IRQ_HANDLED;
711 	}
712 
713 	/* Check system status */
714 	if (db->cr5_data & 0x2000) {
715 		/* system bus error happen */
716 		ULI526X_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
717 		db->reset_fatal++;
718 		db->wait_reset = 1;	/* Need to RESET */
719 		spin_unlock_irqrestore(&db->lock, flags);
720 		return IRQ_HANDLED;
721 	}
722 
723 	 /* Received the coming packet */
724 	if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
725 		uli526x_rx_packet(dev, db);
726 
727 	/* reallocate rx descriptor buffer */
728 	if (db->rx_avail_cnt<RX_DESC_CNT)
729 		allocate_rx_buffer(dev);
730 
731 	/* Free the transmitted descriptor */
732 	if ( db->cr5_data & 0x01)
733 		uli526x_free_tx_pkt(dev, db);
734 
735 	/* Restore CR7 to enable interrupt mask */
736 	uw32(DCR7, db->cr7_data);
737 
738 	spin_unlock_irqrestore(&db->lock, flags);
739 	return IRQ_HANDLED;
740 }
741 
742 #ifdef CONFIG_NET_POLL_CONTROLLER
743 static void uli526x_poll(struct net_device *dev)
744 {
745 	struct uli526x_board_info *db = netdev_priv(dev);
746 
747 	/* ISR grabs the irqsave lock, so this should be safe */
748 	uli526x_interrupt(db->pdev->irq, dev);
749 }
750 #endif
751 
752 /*
753  *	Free TX resource after TX complete
754  */
755 
756 static void uli526x_free_tx_pkt(struct net_device *dev,
757 				struct uli526x_board_info * db)
758 {
759 	struct tx_desc *txptr;
760 	u32 tdes0;
761 
762 	txptr = db->tx_remove_ptr;
763 	while(db->tx_packet_cnt) {
764 		tdes0 = le32_to_cpu(txptr->tdes0);
765 		if (tdes0 & 0x80000000)
766 			break;
767 
768 		/* A packet sent completed */
769 		db->tx_packet_cnt--;
770 		dev->stats.tx_packets++;
771 
772 		/* Transmit statistic counter */
773 		if ( tdes0 != 0x7fffffff ) {
774 			dev->stats.collisions += (tdes0 >> 3) & 0xf;
775 			dev->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
776 			if (tdes0 & TDES0_ERR_MASK) {
777 				dev->stats.tx_errors++;
778 				if (tdes0 & 0x0002) {	/* UnderRun */
779 					db->tx_fifo_underrun++;
780 					if ( !(db->cr6_data & CR6_SFT) ) {
781 						db->cr6_data = db->cr6_data | CR6_SFT;
782 						update_cr6(db->cr6_data, db->ioaddr);
783 					}
784 				}
785 				if (tdes0 & 0x0100)
786 					db->tx_excessive_collision++;
787 				if (tdes0 & 0x0200)
788 					db->tx_late_collision++;
789 				if (tdes0 & 0x0400)
790 					db->tx_no_carrier++;
791 				if (tdes0 & 0x0800)
792 					db->tx_loss_carrier++;
793 				if (tdes0 & 0x4000)
794 					db->tx_jabber_timeout++;
795 			}
796 		}
797 
798     		txptr = txptr->next_tx_desc;
799 	}/* End of while */
800 
801 	/* Update TX remove pointer to next */
802 	db->tx_remove_ptr = txptr;
803 
804 	/* Resource available check */
805 	if ( db->tx_packet_cnt < TX_WAKE_DESC_CNT )
806 		netif_wake_queue(dev);	/* Active upper layer, send again */
807 }
808 
809 
810 /*
811  *	Receive the come packet and pass to upper layer
812  */
813 
814 static void uli526x_rx_packet(struct net_device *dev, struct uli526x_board_info * db)
815 {
816 	struct rx_desc *rxptr;
817 	struct sk_buff *skb;
818 	int rxlen;
819 	u32 rdes0;
820 
821 	rxptr = db->rx_ready_ptr;
822 
823 	while(db->rx_avail_cnt) {
824 		rdes0 = le32_to_cpu(rxptr->rdes0);
825 		if (rdes0 & 0x80000000)	/* packet owner check */
826 		{
827 			break;
828 		}
829 
830 		db->rx_avail_cnt--;
831 		db->interval_rx_cnt++;
832 
833 		pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2), RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
834 		if ( (rdes0 & 0x300) != 0x300) {
835 			/* A packet without First/Last flag */
836 			/* reuse this SKB */
837 			ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
838 			uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
839 		} else {
840 			/* A packet with First/Last flag */
841 			rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
842 
843 			/* error summary bit check */
844 			if (rdes0 & 0x8000) {
845 				/* This is a error packet */
846 				dev->stats.rx_errors++;
847 				if (rdes0 & 1)
848 					dev->stats.rx_fifo_errors++;
849 				if (rdes0 & 2)
850 					dev->stats.rx_crc_errors++;
851 				if (rdes0 & 0x80)
852 					dev->stats.rx_length_errors++;
853 			}
854 
855 			if ( !(rdes0 & 0x8000) ||
856 				((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
857 				struct sk_buff *new_skb = NULL;
858 
859 				skb = rxptr->rx_skb_ptr;
860 
861 				/* Good packet, send to upper layer */
862 				/* Shorst packet used new SKB */
863 				if ((rxlen < RX_COPY_SIZE) &&
864 				    (((new_skb = netdev_alloc_skb(dev, rxlen + 2)) != NULL))) {
865 					skb = new_skb;
866 					/* size less than COPY_SIZE, allocate a rxlen SKB */
867 					skb_reserve(skb, 2); /* 16byte align */
868 					memcpy(skb_put(skb, rxlen),
869 					       skb_tail_pointer(rxptr->rx_skb_ptr),
870 					       rxlen);
871 					uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
872 				} else
873 					skb_put(skb, rxlen);
874 
875 				skb->protocol = eth_type_trans(skb, dev);
876 				netif_rx(skb);
877 				dev->stats.rx_packets++;
878 				dev->stats.rx_bytes += rxlen;
879 
880 			} else {
881 				/* Reuse SKB buffer when the packet is error */
882 				ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
883 				uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
884 			}
885 		}
886 
887 		rxptr = rxptr->next_rx_desc;
888 	}
889 
890 	db->rx_ready_ptr = rxptr;
891 }
892 
893 
894 /*
895  * Set ULI526X multicast address
896  */
897 
898 static void uli526x_set_filter_mode(struct net_device * dev)
899 {
900 	struct uli526x_board_info *db = netdev_priv(dev);
901 	unsigned long flags;
902 
903 	ULI526X_DBUG(0, "uli526x_set_filter_mode()", 0);
904 	spin_lock_irqsave(&db->lock, flags);
905 
906 	if (dev->flags & IFF_PROMISC) {
907 		ULI526X_DBUG(0, "Enable PROM Mode", 0);
908 		db->cr6_data |= CR6_PM | CR6_PBF;
909 		update_cr6(db->cr6_data, db->ioaddr);
910 		spin_unlock_irqrestore(&db->lock, flags);
911 		return;
912 	}
913 
914 	if (dev->flags & IFF_ALLMULTI ||
915 	    netdev_mc_count(dev) > ULI5261_MAX_MULTICAST) {
916 		ULI526X_DBUG(0, "Pass all multicast address",
917 			     netdev_mc_count(dev));
918 		db->cr6_data &= ~(CR6_PM | CR6_PBF);
919 		db->cr6_data |= CR6_PAM;
920 		spin_unlock_irqrestore(&db->lock, flags);
921 		return;
922 	}
923 
924 	ULI526X_DBUG(0, "Set multicast address", netdev_mc_count(dev));
925 	send_filter_frame(dev, netdev_mc_count(dev)); 	/* M5261/M5263 */
926 	spin_unlock_irqrestore(&db->lock, flags);
927 }
928 
929 static void
930 ULi_ethtool_gset(struct uli526x_board_info *db, struct ethtool_cmd *ecmd)
931 {
932 	ecmd->supported = (SUPPORTED_10baseT_Half |
933 	                   SUPPORTED_10baseT_Full |
934 	                   SUPPORTED_100baseT_Half |
935 	                   SUPPORTED_100baseT_Full |
936 	                   SUPPORTED_Autoneg |
937 	                   SUPPORTED_MII);
938 
939 	ecmd->advertising = (ADVERTISED_10baseT_Half |
940 	                   ADVERTISED_10baseT_Full |
941 	                   ADVERTISED_100baseT_Half |
942 	                   ADVERTISED_100baseT_Full |
943 	                   ADVERTISED_Autoneg |
944 	                   ADVERTISED_MII);
945 
946 
947 	ecmd->port = PORT_MII;
948 	ecmd->phy_address = db->phy_addr;
949 
950 	ecmd->transceiver = XCVR_EXTERNAL;
951 
952 	ethtool_cmd_speed_set(ecmd, SPEED_10);
953 	ecmd->duplex = DUPLEX_HALF;
954 
955 	if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
956 	{
957 		ethtool_cmd_speed_set(ecmd, SPEED_100);
958 	}
959 	if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
960 	{
961 		ecmd->duplex = DUPLEX_FULL;
962 	}
963 	if(db->link_failed)
964 	{
965 		ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN);
966 		ecmd->duplex = DUPLEX_UNKNOWN;
967 	}
968 
969 	if (db->media_mode & ULI526X_AUTO)
970 	{
971 		ecmd->autoneg = AUTONEG_ENABLE;
972 	}
973 }
974 
975 static void netdev_get_drvinfo(struct net_device *dev,
976 			       struct ethtool_drvinfo *info)
977 {
978 	struct uli526x_board_info *np = netdev_priv(dev);
979 
980 	strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
981 	strlcpy(info->version, DRV_VERSION, sizeof(info->version));
982 	strlcpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info));
983 }
984 
985 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) {
986 	struct uli526x_board_info *np = netdev_priv(dev);
987 
988 	ULi_ethtool_gset(np, cmd);
989 
990 	return 0;
991 }
992 
993 static u32 netdev_get_link(struct net_device *dev) {
994 	struct uli526x_board_info *np = netdev_priv(dev);
995 
996 	if(np->link_failed)
997 		return 0;
998 	else
999 		return 1;
1000 }
1001 
1002 static void uli526x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1003 {
1004 	wol->supported = WAKE_PHY | WAKE_MAGIC;
1005 	wol->wolopts = 0;
1006 }
1007 
1008 static const struct ethtool_ops netdev_ethtool_ops = {
1009 	.get_drvinfo		= netdev_get_drvinfo,
1010 	.get_settings		= netdev_get_settings,
1011 	.get_link		= netdev_get_link,
1012 	.get_wol		= uli526x_get_wol,
1013 };
1014 
1015 /*
1016  *	A periodic timer routine
1017  *	Dynamic media sense, allocate Rx buffer...
1018  */
1019 
1020 static void uli526x_timer(unsigned long data)
1021 {
1022 	struct net_device *dev = (struct net_device *) data;
1023 	struct uli526x_board_info *db = netdev_priv(dev);
1024 	struct uli_phy_ops *phy = &db->phy;
1025 	void __iomem *ioaddr = db->ioaddr;
1026  	unsigned long flags;
1027 	u8 tmp_cr12 = 0;
1028 	u32 tmp_cr8;
1029 
1030 	//ULI526X_DBUG(0, "uli526x_timer()", 0);
1031 	spin_lock_irqsave(&db->lock, flags);
1032 
1033 
1034 	/* Dynamic reset ULI526X : system error or transmit time-out */
1035 	tmp_cr8 = ur32(DCR8);
1036 	if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1037 		db->reset_cr8++;
1038 		db->wait_reset = 1;
1039 	}
1040 	db->interval_rx_cnt = 0;
1041 
1042 	/* TX polling kick monitor */
1043 	if ( db->tx_packet_cnt &&
1044 	     time_after(jiffies, dev_trans_start(dev) + ULI526X_TX_KICK) ) {
1045 		uw32(DCR1, 0x1);   // Tx polling again
1046 
1047 		// TX Timeout
1048 		if ( time_after(jiffies, dev_trans_start(dev) + ULI526X_TX_TIMEOUT) ) {
1049 			db->reset_TXtimeout++;
1050 			db->wait_reset = 1;
1051 			netdev_err(dev, " Tx timeout - resetting\n");
1052 		}
1053 	}
1054 
1055 	if (db->wait_reset) {
1056 		ULI526X_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1057 		db->reset_count++;
1058 		uli526x_dynamic_reset(dev);
1059 		db->timer.expires = ULI526X_TIMER_WUT;
1060 		add_timer(&db->timer);
1061 		spin_unlock_irqrestore(&db->lock, flags);
1062 		return;
1063 	}
1064 
1065 	/* Link status check, Dynamic media type change */
1066 	if ((phy->read(db, db->phy_addr, 5) & 0x01e0)!=0)
1067 		tmp_cr12 = 3;
1068 
1069 	if ( !(tmp_cr12 & 0x3) && !db->link_failed ) {
1070 		/* Link Failed */
1071 		ULI526X_DBUG(0, "Link Failed", tmp_cr12);
1072 		netif_carrier_off(dev);
1073 		netdev_info(dev, "NIC Link is Down\n");
1074 		db->link_failed = 1;
1075 
1076 		/* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1077 		/* AUTO don't need */
1078 		if ( !(db->media_mode & 0x8) )
1079 			phy->write(db, db->phy_addr, 0, 0x1000);
1080 
1081 		/* AUTO mode, if INT phyxcer link failed, select EXT device */
1082 		if (db->media_mode & ULI526X_AUTO) {
1083 			db->cr6_data&=~0x00000200;	/* bit9=0, HD mode */
1084 			update_cr6(db->cr6_data, db->ioaddr);
1085 		}
1086 	} else
1087 		if ((tmp_cr12 & 0x3) && db->link_failed) {
1088 			ULI526X_DBUG(0, "Link link OK", tmp_cr12);
1089 			db->link_failed = 0;
1090 
1091 			/* Auto Sense Speed */
1092 			if ( (db->media_mode & ULI526X_AUTO) &&
1093 				uli526x_sense_speed(db) )
1094 				db->link_failed = 1;
1095 			uli526x_process_mode(db);
1096 
1097 			if(db->link_failed==0)
1098 			{
1099 				netdev_info(dev, "NIC Link is Up %d Mbps %s duplex\n",
1100 					    (db->op_mode == ULI526X_100MHF ||
1101 					     db->op_mode == ULI526X_100MFD)
1102 					    ? 100 : 10,
1103 					    (db->op_mode == ULI526X_10MFD ||
1104 					     db->op_mode == ULI526X_100MFD)
1105 					    ? "Full" : "Half");
1106 				netif_carrier_on(dev);
1107 			}
1108 			/* SHOW_MEDIA_TYPE(db->op_mode); */
1109 		}
1110 		else if(!(tmp_cr12 & 0x3) && db->link_failed)
1111 		{
1112 			if(db->init==1)
1113 			{
1114 				netdev_info(dev, "NIC Link is Down\n");
1115 				netif_carrier_off(dev);
1116 			}
1117 		}
1118 	db->init = 0;
1119 
1120 	/* Timer active again */
1121 	db->timer.expires = ULI526X_TIMER_WUT;
1122 	add_timer(&db->timer);
1123 	spin_unlock_irqrestore(&db->lock, flags);
1124 }
1125 
1126 
1127 /*
1128  *	Stop ULI526X board
1129  *	Free Tx/Rx allocated memory
1130  *	Init system variable
1131  */
1132 
1133 static void uli526x_reset_prepare(struct net_device *dev)
1134 {
1135 	struct uli526x_board_info *db = netdev_priv(dev);
1136 	void __iomem *ioaddr = db->ioaddr;
1137 
1138 	/* Sopt MAC controller */
1139 	db->cr6_data &= ~(CR6_RXSC | CR6_TXSC);	/* Disable Tx/Rx */
1140 	update_cr6(db->cr6_data, ioaddr);
1141 	uw32(DCR7, 0);				/* Disable Interrupt */
1142 	uw32(DCR5, ur32(DCR5));
1143 
1144 	/* Disable upper layer interface */
1145 	netif_stop_queue(dev);
1146 
1147 	/* Free Rx Allocate buffer */
1148 	uli526x_free_rxbuffer(db);
1149 
1150 	/* system variable init */
1151 	db->tx_packet_cnt = 0;
1152 	db->rx_avail_cnt = 0;
1153 	db->link_failed = 1;
1154 	db->init=1;
1155 	db->wait_reset = 0;
1156 }
1157 
1158 
1159 /*
1160  *	Dynamic reset the ULI526X board
1161  *	Stop ULI526X board
1162  *	Free Tx/Rx allocated memory
1163  *	Reset ULI526X board
1164  *	Re-initialize ULI526X board
1165  */
1166 
1167 static void uli526x_dynamic_reset(struct net_device *dev)
1168 {
1169 	ULI526X_DBUG(0, "uli526x_dynamic_reset()", 0);
1170 
1171 	uli526x_reset_prepare(dev);
1172 
1173 	/* Re-initialize ULI526X board */
1174 	uli526x_init(dev);
1175 
1176 	/* Restart upper layer interface */
1177 	netif_wake_queue(dev);
1178 }
1179 
1180 
1181 #ifdef CONFIG_PM
1182 
1183 /*
1184  *	Suspend the interface.
1185  */
1186 
1187 static int uli526x_suspend(struct pci_dev *pdev, pm_message_t state)
1188 {
1189 	struct net_device *dev = pci_get_drvdata(pdev);
1190 	pci_power_t power_state;
1191 	int err;
1192 
1193 	ULI526X_DBUG(0, "uli526x_suspend", 0);
1194 
1195 	pci_save_state(pdev);
1196 
1197 	if (!netif_running(dev))
1198 		return 0;
1199 
1200 	netif_device_detach(dev);
1201 	uli526x_reset_prepare(dev);
1202 
1203 	power_state = pci_choose_state(pdev, state);
1204 	pci_enable_wake(pdev, power_state, 0);
1205 	err = pci_set_power_state(pdev, power_state);
1206 	if (err) {
1207 		netif_device_attach(dev);
1208 		/* Re-initialize ULI526X board */
1209 		uli526x_init(dev);
1210 		/* Restart upper layer interface */
1211 		netif_wake_queue(dev);
1212 	}
1213 
1214 	return err;
1215 }
1216 
1217 /*
1218  *	Resume the interface.
1219  */
1220 
1221 static int uli526x_resume(struct pci_dev *pdev)
1222 {
1223 	struct net_device *dev = pci_get_drvdata(pdev);
1224 	int err;
1225 
1226 	ULI526X_DBUG(0, "uli526x_resume", 0);
1227 
1228 	pci_restore_state(pdev);
1229 
1230 	if (!netif_running(dev))
1231 		return 0;
1232 
1233 	err = pci_set_power_state(pdev, PCI_D0);
1234 	if (err) {
1235 		netdev_warn(dev, "Could not put device into D0\n");
1236 		return err;
1237 	}
1238 
1239 	netif_device_attach(dev);
1240 	/* Re-initialize ULI526X board */
1241 	uli526x_init(dev);
1242 	/* Restart upper layer interface */
1243 	netif_wake_queue(dev);
1244 
1245 	return 0;
1246 }
1247 
1248 #else /* !CONFIG_PM */
1249 
1250 #define uli526x_suspend	NULL
1251 #define uli526x_resume	NULL
1252 
1253 #endif /* !CONFIG_PM */
1254 
1255 
1256 /*
1257  *	free all allocated rx buffer
1258  */
1259 
1260 static void uli526x_free_rxbuffer(struct uli526x_board_info * db)
1261 {
1262 	ULI526X_DBUG(0, "uli526x_free_rxbuffer()", 0);
1263 
1264 	/* free allocated rx buffer */
1265 	while (db->rx_avail_cnt) {
1266 		dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1267 		db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1268 		db->rx_avail_cnt--;
1269 	}
1270 }
1271 
1272 
1273 /*
1274  *	Reuse the SK buffer
1275  */
1276 
1277 static void uli526x_reuse_skb(struct uli526x_board_info *db, struct sk_buff * skb)
1278 {
1279 	struct rx_desc *rxptr = db->rx_insert_ptr;
1280 
1281 	if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1282 		rxptr->rx_skb_ptr = skb;
1283 		rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1284 							  skb_tail_pointer(skb),
1285 							  RX_ALLOC_SIZE,
1286 							  PCI_DMA_FROMDEVICE));
1287 		wmb();
1288 		rxptr->rdes0 = cpu_to_le32(0x80000000);
1289 		db->rx_avail_cnt++;
1290 		db->rx_insert_ptr = rxptr->next_rx_desc;
1291 	} else
1292 		ULI526X_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1293 }
1294 
1295 
1296 /*
1297  *	Initialize transmit/Receive descriptor
1298  *	Using Chain structure, and allocate Tx/Rx buffer
1299  */
1300 
1301 static void uli526x_descriptor_init(struct net_device *dev, void __iomem *ioaddr)
1302 {
1303 	struct uli526x_board_info *db = netdev_priv(dev);
1304 	struct tx_desc *tmp_tx;
1305 	struct rx_desc *tmp_rx;
1306 	unsigned char *tmp_buf;
1307 	dma_addr_t tmp_tx_dma, tmp_rx_dma;
1308 	dma_addr_t tmp_buf_dma;
1309 	int i;
1310 
1311 	ULI526X_DBUG(0, "uli526x_descriptor_init()", 0);
1312 
1313 	/* tx descriptor start pointer */
1314 	db->tx_insert_ptr = db->first_tx_desc;
1315 	db->tx_remove_ptr = db->first_tx_desc;
1316 	uw32(DCR4, db->first_tx_desc_dma);	/* TX DESC address */
1317 
1318 	/* rx descriptor start pointer */
1319 	db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT;
1320 	db->first_rx_desc_dma =  db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT;
1321 	db->rx_insert_ptr = db->first_rx_desc;
1322 	db->rx_ready_ptr = db->first_rx_desc;
1323 	uw32(DCR3, db->first_rx_desc_dma);	/* RX DESC address */
1324 
1325 	/* Init Transmit chain */
1326 	tmp_buf = db->buf_pool_start;
1327 	tmp_buf_dma = db->buf_pool_dma_start;
1328 	tmp_tx_dma = db->first_tx_desc_dma;
1329 	for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1330 		tmp_tx->tx_buf_ptr = tmp_buf;
1331 		tmp_tx->tdes0 = cpu_to_le32(0);
1332 		tmp_tx->tdes1 = cpu_to_le32(0x81000000);	/* IC, chain */
1333 		tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1334 		tmp_tx_dma += sizeof(struct tx_desc);
1335 		tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1336 		tmp_tx->next_tx_desc = tmp_tx + 1;
1337 		tmp_buf = tmp_buf + TX_BUF_ALLOC;
1338 		tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1339 	}
1340 	(--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1341 	tmp_tx->next_tx_desc = db->first_tx_desc;
1342 
1343 	 /* Init Receive descriptor chain */
1344 	tmp_rx_dma=db->first_rx_desc_dma;
1345 	for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1346 		tmp_rx->rdes0 = cpu_to_le32(0);
1347 		tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1348 		tmp_rx_dma += sizeof(struct rx_desc);
1349 		tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1350 		tmp_rx->next_rx_desc = tmp_rx + 1;
1351 	}
1352 	(--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1353 	tmp_rx->next_rx_desc = db->first_rx_desc;
1354 
1355 	/* pre-allocate Rx buffer */
1356 	allocate_rx_buffer(dev);
1357 }
1358 
1359 
1360 /*
1361  *	Update CR6 value
1362  *	Firstly stop ULI526X, then written value and start
1363  */
1364 static void update_cr6(u32 cr6_data, void __iomem *ioaddr)
1365 {
1366 	uw32(DCR6, cr6_data);
1367 	udelay(5);
1368 }
1369 
1370 
1371 /*
1372  *	Send a setup frame for M5261/M5263
1373  *	This setup frame initialize ULI526X address filter mode
1374  */
1375 
1376 #ifdef __BIG_ENDIAN
1377 #define FLT_SHIFT 16
1378 #else
1379 #define FLT_SHIFT 0
1380 #endif
1381 
1382 static void send_filter_frame(struct net_device *dev, int mc_cnt)
1383 {
1384 	struct uli526x_board_info *db = netdev_priv(dev);
1385 	void __iomem *ioaddr = db->ioaddr;
1386 	struct netdev_hw_addr *ha;
1387 	struct tx_desc *txptr;
1388 	u16 * addrptr;
1389 	u32 * suptr;
1390 	int i;
1391 
1392 	ULI526X_DBUG(0, "send_filter_frame()", 0);
1393 
1394 	txptr = db->tx_insert_ptr;
1395 	suptr = (u32 *) txptr->tx_buf_ptr;
1396 
1397 	/* Node address */
1398 	addrptr = (u16 *) dev->dev_addr;
1399 	*suptr++ = addrptr[0] << FLT_SHIFT;
1400 	*suptr++ = addrptr[1] << FLT_SHIFT;
1401 	*suptr++ = addrptr[2] << FLT_SHIFT;
1402 
1403 	/* broadcast address */
1404 	*suptr++ = 0xffff << FLT_SHIFT;
1405 	*suptr++ = 0xffff << FLT_SHIFT;
1406 	*suptr++ = 0xffff << FLT_SHIFT;
1407 
1408 	/* fit the multicast address */
1409 	netdev_for_each_mc_addr(ha, dev) {
1410 		addrptr = (u16 *) ha->addr;
1411 		*suptr++ = addrptr[0] << FLT_SHIFT;
1412 		*suptr++ = addrptr[1] << FLT_SHIFT;
1413 		*suptr++ = addrptr[2] << FLT_SHIFT;
1414 	}
1415 
1416 	for (i = netdev_mc_count(dev); i < 14; i++) {
1417 		*suptr++ = 0xffff << FLT_SHIFT;
1418 		*suptr++ = 0xffff << FLT_SHIFT;
1419 		*suptr++ = 0xffff << FLT_SHIFT;
1420 	}
1421 
1422 	/* prepare the setup frame */
1423 	db->tx_insert_ptr = txptr->next_tx_desc;
1424 	txptr->tdes1 = cpu_to_le32(0x890000c0);
1425 
1426 	/* Resource Check and Send the setup packet */
1427 	if (db->tx_packet_cnt < TX_DESC_CNT) {
1428 		/* Resource Empty */
1429 		db->tx_packet_cnt++;
1430 		txptr->tdes0 = cpu_to_le32(0x80000000);
1431 		update_cr6(db->cr6_data | 0x2000, ioaddr);
1432 		uw32(DCR1, 0x1);	/* Issue Tx polling */
1433 		update_cr6(db->cr6_data, ioaddr);
1434 		dev->trans_start = jiffies;
1435 	} else
1436 		netdev_err(dev, "No Tx resource - Send_filter_frame!\n");
1437 }
1438 
1439 
1440 /*
1441  *	Allocate rx buffer,
1442  *	As possible as allocate maxiumn Rx buffer
1443  */
1444 
1445 static void allocate_rx_buffer(struct net_device *dev)
1446 {
1447 	struct uli526x_board_info *db = netdev_priv(dev);
1448 	struct rx_desc *rxptr;
1449 	struct sk_buff *skb;
1450 
1451 	rxptr = db->rx_insert_ptr;
1452 
1453 	while(db->rx_avail_cnt < RX_DESC_CNT) {
1454 		skb = netdev_alloc_skb(dev, RX_ALLOC_SIZE);
1455 		if (skb == NULL)
1456 			break;
1457 		rxptr->rx_skb_ptr = skb; /* FIXME (?) */
1458 		rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1459 							  skb_tail_pointer(skb),
1460 							  RX_ALLOC_SIZE,
1461 							  PCI_DMA_FROMDEVICE));
1462 		wmb();
1463 		rxptr->rdes0 = cpu_to_le32(0x80000000);
1464 		rxptr = rxptr->next_rx_desc;
1465 		db->rx_avail_cnt++;
1466 	}
1467 
1468 	db->rx_insert_ptr = rxptr;
1469 }
1470 
1471 
1472 /*
1473  *	Read one word data from the serial ROM
1474  */
1475 
1476 static u16 read_srom_word(struct uli526x_board_info *db, int offset)
1477 {
1478 	void __iomem *ioaddr = db->ioaddr;
1479 	u16 srom_data = 0;
1480 	int i;
1481 
1482 	uw32(DCR9, CR9_SROM_READ);
1483 	uw32(DCR9, CR9_SROM_READ | CR9_SRCS);
1484 
1485 	/* Send the Read Command 110b */
1486 	srom_clk_write(db, SROM_DATA_1);
1487 	srom_clk_write(db, SROM_DATA_1);
1488 	srom_clk_write(db, SROM_DATA_0);
1489 
1490 	/* Send the offset */
1491 	for (i = 5; i >= 0; i--) {
1492 		srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1493 		srom_clk_write(db, srom_data);
1494 	}
1495 
1496 	uw32(DCR9, CR9_SROM_READ | CR9_SRCS);
1497 
1498 	for (i = 16; i > 0; i--) {
1499 		uw32(DCR9, CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);
1500 		udelay(5);
1501 		srom_data = (srom_data << 1) |
1502 			    ((ur32(DCR9) & CR9_CRDOUT) ? 1 : 0);
1503 		uw32(DCR9, CR9_SROM_READ | CR9_SRCS);
1504 		udelay(5);
1505 	}
1506 
1507 	uw32(DCR9, CR9_SROM_READ);
1508 	return srom_data;
1509 }
1510 
1511 
1512 /*
1513  *	Auto sense the media mode
1514  */
1515 
1516 static u8 uli526x_sense_speed(struct uli526x_board_info * db)
1517 {
1518 	struct uli_phy_ops *phy = &db->phy;
1519 	u8 ErrFlag = 0;
1520 	u16 phy_mode;
1521 
1522 	phy_mode = phy->read(db, db->phy_addr, 1);
1523 	phy_mode = phy->read(db, db->phy_addr, 1);
1524 
1525 	if ( (phy_mode & 0x24) == 0x24 ) {
1526 
1527 		phy_mode = ((phy->read(db, db->phy_addr, 5) & 0x01e0)<<7);
1528 		if(phy_mode&0x8000)
1529 			phy_mode = 0x8000;
1530 		else if(phy_mode&0x4000)
1531 			phy_mode = 0x4000;
1532 		else if(phy_mode&0x2000)
1533 			phy_mode = 0x2000;
1534 		else
1535 			phy_mode = 0x1000;
1536 
1537 		switch (phy_mode) {
1538 		case 0x1000: db->op_mode = ULI526X_10MHF; break;
1539 		case 0x2000: db->op_mode = ULI526X_10MFD; break;
1540 		case 0x4000: db->op_mode = ULI526X_100MHF; break;
1541 		case 0x8000: db->op_mode = ULI526X_100MFD; break;
1542 		default: db->op_mode = ULI526X_10MHF; ErrFlag = 1; break;
1543 		}
1544 	} else {
1545 		db->op_mode = ULI526X_10MHF;
1546 		ULI526X_DBUG(0, "Link Failed :", phy_mode);
1547 		ErrFlag = 1;
1548 	}
1549 
1550 	return ErrFlag;
1551 }
1552 
1553 
1554 /*
1555  *	Set 10/100 phyxcer capability
1556  *	AUTO mode : phyxcer register4 is NIC capability
1557  *	Force mode: phyxcer register4 is the force media
1558  */
1559 
1560 static void uli526x_set_phyxcer(struct uli526x_board_info *db)
1561 {
1562 	struct uli_phy_ops *phy = &db->phy;
1563 	u16 phy_reg;
1564 
1565 	/* Phyxcer capability setting */
1566 	phy_reg = phy->read(db, db->phy_addr, 4) & ~0x01e0;
1567 
1568 	if (db->media_mode & ULI526X_AUTO) {
1569 		/* AUTO Mode */
1570 		phy_reg |= db->PHY_reg4;
1571 	} else {
1572 		/* Force Mode */
1573 		switch(db->media_mode) {
1574 		case ULI526X_10MHF: phy_reg |= 0x20; break;
1575 		case ULI526X_10MFD: phy_reg |= 0x40; break;
1576 		case ULI526X_100MHF: phy_reg |= 0x80; break;
1577 		case ULI526X_100MFD: phy_reg |= 0x100; break;
1578 		}
1579 
1580 	}
1581 
1582   	/* Write new capability to Phyxcer Reg4 */
1583 	if ( !(phy_reg & 0x01e0)) {
1584 		phy_reg|=db->PHY_reg4;
1585 		db->media_mode|=ULI526X_AUTO;
1586 	}
1587 	phy->write(db, db->phy_addr, 4, phy_reg);
1588 
1589  	/* Restart Auto-Negotiation */
1590 	phy->write(db, db->phy_addr, 0, 0x1200);
1591 	udelay(50);
1592 }
1593 
1594 
1595 /*
1596  *	Process op-mode
1597  	AUTO mode : PHY controller in Auto-negotiation Mode
1598  *	Force mode: PHY controller in force mode with HUB
1599  *			N-way force capability with SWITCH
1600  */
1601 
1602 static void uli526x_process_mode(struct uli526x_board_info *db)
1603 {
1604 	struct uli_phy_ops *phy = &db->phy;
1605 	u16 phy_reg;
1606 
1607 	/* Full Duplex Mode Check */
1608 	if (db->op_mode & 0x4)
1609 		db->cr6_data |= CR6_FDM;	/* Set Full Duplex Bit */
1610 	else
1611 		db->cr6_data &= ~CR6_FDM;	/* Clear Full Duplex Bit */
1612 
1613 	update_cr6(db->cr6_data, db->ioaddr);
1614 
1615 	/* 10/100M phyxcer force mode need */
1616 	if (!(db->media_mode & 0x8)) {
1617 		/* Forece Mode */
1618 		phy_reg = phy->read(db, db->phy_addr, 6);
1619 		if (!(phy_reg & 0x1)) {
1620 			/* parter without N-Way capability */
1621 			phy_reg = 0x0;
1622 			switch(db->op_mode) {
1623 			case ULI526X_10MHF: phy_reg = 0x0; break;
1624 			case ULI526X_10MFD: phy_reg = 0x100; break;
1625 			case ULI526X_100MHF: phy_reg = 0x2000; break;
1626 			case ULI526X_100MFD: phy_reg = 0x2100; break;
1627 			}
1628 			phy->write(db, db->phy_addr, 0, phy_reg);
1629 		}
1630 	}
1631 }
1632 
1633 
1634 /* M5261/M5263 Chip */
1635 static void phy_writeby_cr9(struct uli526x_board_info *db, u8 phy_addr,
1636 			    u8 offset, u16 phy_data)
1637 {
1638 	u16 i;
1639 
1640 	/* Send 33 synchronization clock to Phy controller */
1641 	for (i = 0; i < 35; i++)
1642 		phy_write_1bit(db, PHY_DATA_1);
1643 
1644 	/* Send start command(01) to Phy */
1645 	phy_write_1bit(db, PHY_DATA_0);
1646 	phy_write_1bit(db, PHY_DATA_1);
1647 
1648 	/* Send write command(01) to Phy */
1649 	phy_write_1bit(db, PHY_DATA_0);
1650 	phy_write_1bit(db, PHY_DATA_1);
1651 
1652 	/* Send Phy address */
1653 	for (i = 0x10; i > 0; i = i >> 1)
1654 		phy_write_1bit(db, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1655 
1656 	/* Send register address */
1657 	for (i = 0x10; i > 0; i = i >> 1)
1658 		phy_write_1bit(db, offset & i ? PHY_DATA_1 : PHY_DATA_0);
1659 
1660 	/* written trasnition */
1661 	phy_write_1bit(db, PHY_DATA_1);
1662 	phy_write_1bit(db, PHY_DATA_0);
1663 
1664 	/* Write a word data to PHY controller */
1665 	for (i = 0x8000; i > 0; i >>= 1)
1666 		phy_write_1bit(db, phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
1667 }
1668 
1669 static u16 phy_readby_cr9(struct uli526x_board_info *db, u8 phy_addr, u8 offset)
1670 {
1671 	u16 phy_data;
1672 	int i;
1673 
1674 	/* Send 33 synchronization clock to Phy controller */
1675 	for (i = 0; i < 35; i++)
1676 		phy_write_1bit(db, PHY_DATA_1);
1677 
1678 	/* Send start command(01) to Phy */
1679 	phy_write_1bit(db, PHY_DATA_0);
1680 	phy_write_1bit(db, PHY_DATA_1);
1681 
1682 	/* Send read command(10) to Phy */
1683 	phy_write_1bit(db, PHY_DATA_1);
1684 	phy_write_1bit(db, PHY_DATA_0);
1685 
1686 	/* Send Phy address */
1687 	for (i = 0x10; i > 0; i = i >> 1)
1688 		phy_write_1bit(db, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1689 
1690 	/* Send register address */
1691 	for (i = 0x10; i > 0; i = i >> 1)
1692 		phy_write_1bit(db, offset & i ? PHY_DATA_1 : PHY_DATA_0);
1693 
1694 	/* Skip transition state */
1695 	phy_read_1bit(db);
1696 
1697 	/* read 16bit data */
1698 	for (phy_data = 0, i = 0; i < 16; i++) {
1699 		phy_data <<= 1;
1700 		phy_data |= phy_read_1bit(db);
1701 	}
1702 
1703 	return phy_data;
1704 }
1705 
1706 static u16 phy_readby_cr10(struct uli526x_board_info *db, u8 phy_addr,
1707 			   u8 offset)
1708 {
1709 	void __iomem *ioaddr = db->ioaddr;
1710 	u32 cr10_value = phy_addr;
1711 
1712 	cr10_value = (cr10_value <<  5) + offset;
1713 	cr10_value = (cr10_value << 16) + 0x08000000;
1714 	uw32(DCR10, cr10_value);
1715 	udelay(1);
1716 	while (1) {
1717 		cr10_value = ur32(DCR10);
1718 		if (cr10_value & 0x10000000)
1719 			break;
1720 	}
1721 	return cr10_value & 0x0ffff;
1722 }
1723 
1724 static void phy_writeby_cr10(struct uli526x_board_info *db, u8 phy_addr,
1725 			     u8 offset, u16 phy_data)
1726 {
1727 	void __iomem *ioaddr = db->ioaddr;
1728 	u32 cr10_value = phy_addr;
1729 
1730 	cr10_value = (cr10_value <<  5) + offset;
1731 	cr10_value = (cr10_value << 16) + 0x04000000 + phy_data;
1732 	uw32(DCR10, cr10_value);
1733 	udelay(1);
1734 }
1735 /*
1736  *	Write one bit data to Phy Controller
1737  */
1738 
1739 static void phy_write_1bit(struct uli526x_board_info *db, u32 data)
1740 {
1741 	void __iomem *ioaddr = db->ioaddr;
1742 
1743 	uw32(DCR9, data);		/* MII Clock Low */
1744 	udelay(1);
1745 	uw32(DCR9, data | MDCLKH);	/* MII Clock High */
1746 	udelay(1);
1747 	uw32(DCR9, data);		/* MII Clock Low */
1748 	udelay(1);
1749 }
1750 
1751 
1752 /*
1753  *	Read one bit phy data from PHY controller
1754  */
1755 
1756 static u16 phy_read_1bit(struct uli526x_board_info *db)
1757 {
1758 	void __iomem *ioaddr = db->ioaddr;
1759 	u16 phy_data;
1760 
1761 	uw32(DCR9, 0x50000);
1762 	udelay(1);
1763 	phy_data = (ur32(DCR9) >> 19) & 0x1;
1764 	uw32(DCR9, 0x40000);
1765 	udelay(1);
1766 
1767 	return phy_data;
1768 }
1769 
1770 
1771 static const struct pci_device_id uli526x_pci_tbl[] = {
1772 	{ 0x10B9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5261_ID },
1773 	{ 0x10B9, 0x5263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5263_ID },
1774 	{ 0, }
1775 };
1776 MODULE_DEVICE_TABLE(pci, uli526x_pci_tbl);
1777 
1778 
1779 static struct pci_driver uli526x_driver = {
1780 	.name		= "uli526x",
1781 	.id_table	= uli526x_pci_tbl,
1782 	.probe		= uli526x_init_one,
1783 	.remove		= uli526x_remove_one,
1784 	.suspend	= uli526x_suspend,
1785 	.resume		= uli526x_resume,
1786 };
1787 
1788 MODULE_AUTHOR("Peer Chen, peer.chen@uli.com.tw");
1789 MODULE_DESCRIPTION("ULi M5261/M5263 fast ethernet driver");
1790 MODULE_LICENSE("GPL");
1791 
1792 module_param(debug, int, 0644);
1793 module_param(mode, int, 0);
1794 module_param(cr6set, int, 0);
1795 MODULE_PARM_DESC(debug, "ULi M5261/M5263 enable debugging (0-1)");
1796 MODULE_PARM_DESC(mode, "ULi M5261/M5263: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
1797 
1798 /*	Description:
1799  *	when user used insmod to add module, system invoked init_module()
1800  *	to register the services.
1801  */
1802 
1803 static int __init uli526x_init_module(void)
1804 {
1805 
1806 	pr_info("%s\n", version);
1807 	printed_version = 1;
1808 
1809 	ULI526X_DBUG(0, "init_module() ", debug);
1810 
1811 	if (debug)
1812 		uli526x_debug = debug;	/* set debug flag */
1813 	if (cr6set)
1814 		uli526x_cr6_user_set = cr6set;
1815 
1816  	switch (mode) {
1817    	case ULI526X_10MHF:
1818 	case ULI526X_100MHF:
1819 	case ULI526X_10MFD:
1820 	case ULI526X_100MFD:
1821 		uli526x_media_mode = mode;
1822 		break;
1823 	default:
1824 		uli526x_media_mode = ULI526X_AUTO;
1825 		break;
1826 	}
1827 
1828 	return pci_register_driver(&uli526x_driver);
1829 }
1830 
1831 
1832 /*
1833  *	Description:
1834  *	when user used rmmod to delete module, system invoked clean_module()
1835  *	to un-register all registered services.
1836  */
1837 
1838 static void __exit uli526x_cleanup_module(void)
1839 {
1840 	ULI526X_DBUG(0, "uli526x_cleanup_module() ", debug);
1841 	pci_unregister_driver(&uli526x_driver);
1842 }
1843 
1844 module_init(uli526x_init_module);
1845 module_exit(uli526x_cleanup_module);
1846