1 /* 2 This program is free software; you can redistribute it and/or 3 modify it under the terms of the GNU General Public License 4 as published by the Free Software Foundation; either version 2 5 of the License, or (at your option) any later version. 6 7 This program is distributed in the hope that it will be useful, 8 but WITHOUT ANY WARRANTY; without even the implied warranty of 9 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 GNU General Public License for more details. 11 12 13 */ 14 15 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 16 17 #define DRV_NAME "uli526x" 18 #define DRV_VERSION "0.9.3" 19 #define DRV_RELDATE "2005-7-29" 20 21 #include <linux/module.h> 22 23 #include <linux/kernel.h> 24 #include <linux/string.h> 25 #include <linux/timer.h> 26 #include <linux/errno.h> 27 #include <linux/ioport.h> 28 #include <linux/interrupt.h> 29 #include <linux/pci.h> 30 #include <linux/init.h> 31 #include <linux/netdevice.h> 32 #include <linux/etherdevice.h> 33 #include <linux/ethtool.h> 34 #include <linux/skbuff.h> 35 #include <linux/delay.h> 36 #include <linux/spinlock.h> 37 #include <linux/dma-mapping.h> 38 #include <linux/bitops.h> 39 40 #include <asm/processor.h> 41 #include <asm/io.h> 42 #include <asm/dma.h> 43 #include <asm/uaccess.h> 44 45 #define uw32(reg, val) iowrite32(val, ioaddr + (reg)) 46 #define ur32(reg) ioread32(ioaddr + (reg)) 47 48 /* Board/System/Debug information/definition ---------------- */ 49 #define PCI_ULI5261_ID 0x526110B9 /* ULi M5261 ID*/ 50 #define PCI_ULI5263_ID 0x526310B9 /* ULi M5263 ID*/ 51 52 #define ULI526X_IO_SIZE 0x100 53 #define TX_DESC_CNT 0x20 /* Allocated Tx descriptors */ 54 #define RX_DESC_CNT 0x30 /* Allocated Rx descriptors */ 55 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */ 56 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */ 57 #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT) 58 #define TX_BUF_ALLOC 0x600 59 #define RX_ALLOC_SIZE 0x620 60 #define ULI526X_RESET 1 61 #define CR0_DEFAULT 0 62 #define CR6_DEFAULT 0x22200000 63 #define CR7_DEFAULT 0x180c1 64 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */ 65 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */ 66 #define MAX_PACKET_SIZE 1514 67 #define ULI5261_MAX_MULTICAST 14 68 #define RX_COPY_SIZE 100 69 #define MAX_CHECK_PACKET 0x8000 70 71 #define ULI526X_10MHF 0 72 #define ULI526X_100MHF 1 73 #define ULI526X_10MFD 4 74 #define ULI526X_100MFD 5 75 #define ULI526X_AUTO 8 76 77 #define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */ 78 #define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */ 79 #define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */ 80 #define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */ 81 #define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */ 82 #define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */ 83 84 #define ULI526X_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */ 85 #define ULI526X_TX_TIMEOUT ((16*HZ)/2) /* tx packet time-out time 8 s" */ 86 #define ULI526X_TX_KICK (4*HZ/2) /* tx packet Kick-out time 2 s" */ 87 88 #define ULI526X_DBUG(dbug_now, msg, value) \ 89 do { \ 90 if (uli526x_debug || (dbug_now)) \ 91 pr_err("%s %lx\n", (msg), (long) (value)); \ 92 } while (0) 93 94 #define SHOW_MEDIA_TYPE(mode) \ 95 pr_err("Change Speed to %sMhz %s duplex\n", \ 96 mode & 1 ? "100" : "10", \ 97 mode & 4 ? "full" : "half"); 98 99 100 /* CR9 definition: SROM/MII */ 101 #define CR9_SROM_READ 0x4800 102 #define CR9_SRCS 0x1 103 #define CR9_SRCLK 0x2 104 #define CR9_CRDOUT 0x8 105 #define SROM_DATA_0 0x0 106 #define SROM_DATA_1 0x4 107 #define PHY_DATA_1 0x20000 108 #define PHY_DATA_0 0x00000 109 #define MDCLKH 0x10000 110 111 #define PHY_POWER_DOWN 0x800 112 113 #define SROM_V41_CODE 0x14 114 115 /* Structure/enum declaration ------------------------------- */ 116 struct tx_desc { 117 __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */ 118 char *tx_buf_ptr; /* Data for us */ 119 struct tx_desc *next_tx_desc; 120 } __attribute__(( aligned(32) )); 121 122 struct rx_desc { 123 __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */ 124 struct sk_buff *rx_skb_ptr; /* Data for us */ 125 struct rx_desc *next_rx_desc; 126 } __attribute__(( aligned(32) )); 127 128 struct uli526x_board_info { 129 struct uli_phy_ops { 130 void (*write)(struct uli526x_board_info *, u8, u8, u16); 131 u16 (*read)(struct uli526x_board_info *, u8, u8); 132 } phy; 133 struct net_device *next_dev; /* next device */ 134 struct pci_dev *pdev; /* PCI device */ 135 spinlock_t lock; 136 137 void __iomem *ioaddr; /* I/O base address */ 138 u32 cr0_data; 139 u32 cr5_data; 140 u32 cr6_data; 141 u32 cr7_data; 142 u32 cr15_data; 143 144 /* pointer for memory physical address */ 145 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */ 146 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */ 147 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */ 148 dma_addr_t first_tx_desc_dma; 149 dma_addr_t first_rx_desc_dma; 150 151 /* descriptor pointer */ 152 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */ 153 unsigned char *buf_pool_start; /* Tx buffer pool align dword */ 154 unsigned char *desc_pool_ptr; /* descriptor pool memory */ 155 struct tx_desc *first_tx_desc; 156 struct tx_desc *tx_insert_ptr; 157 struct tx_desc *tx_remove_ptr; 158 struct rx_desc *first_rx_desc; 159 struct rx_desc *rx_insert_ptr; 160 struct rx_desc *rx_ready_ptr; /* packet come pointer */ 161 unsigned long tx_packet_cnt; /* transmitted packet count */ 162 unsigned long rx_avail_cnt; /* available rx descriptor count */ 163 unsigned long interval_rx_cnt; /* rx packet count a callback time */ 164 165 u16 dbug_cnt; 166 u16 NIC_capability; /* NIC media capability */ 167 u16 PHY_reg4; /* Saved Phyxcer register 4 value */ 168 169 u8 media_mode; /* user specify media mode */ 170 u8 op_mode; /* real work media mode */ 171 u8 phy_addr; 172 u8 link_failed; /* Ever link failed */ 173 u8 wait_reset; /* Hardware failed, need to reset */ 174 struct timer_list timer; 175 176 /* Driver defined statistic counter */ 177 unsigned long tx_fifo_underrun; 178 unsigned long tx_loss_carrier; 179 unsigned long tx_no_carrier; 180 unsigned long tx_late_collision; 181 unsigned long tx_excessive_collision; 182 unsigned long tx_jabber_timeout; 183 unsigned long reset_count; 184 unsigned long reset_cr8; 185 unsigned long reset_fatal; 186 unsigned long reset_TXtimeout; 187 188 /* NIC SROM data */ 189 unsigned char srom[128]; 190 u8 init; 191 }; 192 193 enum uli526x_offsets { 194 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20, 195 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48, 196 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70, 197 DCR15 = 0x78 198 }; 199 200 enum uli526x_CR6_bits { 201 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80, 202 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000, 203 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000 204 }; 205 206 /* Global variable declaration ----------------------------- */ 207 static int printed_version; 208 static const char version[] = 209 "ULi M5261/M5263 net driver, version " DRV_VERSION " (" DRV_RELDATE ")"; 210 211 static int uli526x_debug; 212 static unsigned char uli526x_media_mode = ULI526X_AUTO; 213 static u32 uli526x_cr6_user_set; 214 215 /* For module input parameter */ 216 static int debug; 217 static u32 cr6set; 218 static int mode = 8; 219 220 /* function declaration ------------------------------------- */ 221 static int uli526x_open(struct net_device *); 222 static netdev_tx_t uli526x_start_xmit(struct sk_buff *, 223 struct net_device *); 224 static int uli526x_stop(struct net_device *); 225 static void uli526x_set_filter_mode(struct net_device *); 226 static const struct ethtool_ops netdev_ethtool_ops; 227 static u16 read_srom_word(struct uli526x_board_info *, int); 228 static irqreturn_t uli526x_interrupt(int, void *); 229 #ifdef CONFIG_NET_POLL_CONTROLLER 230 static void uli526x_poll(struct net_device *dev); 231 #endif 232 static void uli526x_descriptor_init(struct net_device *, void __iomem *); 233 static void allocate_rx_buffer(struct net_device *); 234 static void update_cr6(u32, void __iomem *); 235 static void send_filter_frame(struct net_device *, int); 236 static u16 phy_readby_cr9(struct uli526x_board_info *, u8, u8); 237 static u16 phy_readby_cr10(struct uli526x_board_info *, u8, u8); 238 static void phy_writeby_cr9(struct uli526x_board_info *, u8, u8, u16); 239 static void phy_writeby_cr10(struct uli526x_board_info *, u8, u8, u16); 240 static void phy_write_1bit(struct uli526x_board_info *db, u32); 241 static u16 phy_read_1bit(struct uli526x_board_info *db); 242 static u8 uli526x_sense_speed(struct uli526x_board_info *); 243 static void uli526x_process_mode(struct uli526x_board_info *); 244 static void uli526x_timer(unsigned long); 245 static void uli526x_rx_packet(struct net_device *, struct uli526x_board_info *); 246 static void uli526x_free_tx_pkt(struct net_device *, struct uli526x_board_info *); 247 static void uli526x_reuse_skb(struct uli526x_board_info *, struct sk_buff *); 248 static void uli526x_dynamic_reset(struct net_device *); 249 static void uli526x_free_rxbuffer(struct uli526x_board_info *); 250 static void uli526x_init(struct net_device *); 251 static void uli526x_set_phyxcer(struct uli526x_board_info *); 252 253 static void srom_clk_write(struct uli526x_board_info *db, u32 data) 254 { 255 void __iomem *ioaddr = db->ioaddr; 256 257 uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS); 258 udelay(5); 259 uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS | CR9_SRCLK); 260 udelay(5); 261 uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS); 262 udelay(5); 263 } 264 265 /* ULI526X network board routine ---------------------------- */ 266 267 static const struct net_device_ops netdev_ops = { 268 .ndo_open = uli526x_open, 269 .ndo_stop = uli526x_stop, 270 .ndo_start_xmit = uli526x_start_xmit, 271 .ndo_set_rx_mode = uli526x_set_filter_mode, 272 .ndo_change_mtu = eth_change_mtu, 273 .ndo_set_mac_address = eth_mac_addr, 274 .ndo_validate_addr = eth_validate_addr, 275 #ifdef CONFIG_NET_POLL_CONTROLLER 276 .ndo_poll_controller = uli526x_poll, 277 #endif 278 }; 279 280 /* 281 * Search ULI526X board, allocate space and register it 282 */ 283 284 static int uli526x_init_one(struct pci_dev *pdev, 285 const struct pci_device_id *ent) 286 { 287 struct uli526x_board_info *db; /* board information structure */ 288 struct net_device *dev; 289 void __iomem *ioaddr; 290 int i, err; 291 292 ULI526X_DBUG(0, "uli526x_init_one()", 0); 293 294 if (!printed_version++) 295 pr_info("%s\n", version); 296 297 /* Init network device */ 298 dev = alloc_etherdev(sizeof(*db)); 299 if (dev == NULL) 300 return -ENOMEM; 301 SET_NETDEV_DEV(dev, &pdev->dev); 302 303 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { 304 pr_warn("32-bit PCI DMA not available\n"); 305 err = -ENODEV; 306 goto err_out_free; 307 } 308 309 /* Enable Master/IO access, Disable memory access */ 310 err = pci_enable_device(pdev); 311 if (err) 312 goto err_out_free; 313 314 if (!pci_resource_start(pdev, 0)) { 315 pr_err("I/O base is zero\n"); 316 err = -ENODEV; 317 goto err_out_disable; 318 } 319 320 if (pci_resource_len(pdev, 0) < (ULI526X_IO_SIZE) ) { 321 pr_err("Allocated I/O size too small\n"); 322 err = -ENODEV; 323 goto err_out_disable; 324 } 325 326 err = pci_request_regions(pdev, DRV_NAME); 327 if (err < 0) { 328 pr_err("Failed to request PCI regions\n"); 329 goto err_out_disable; 330 } 331 332 /* Init system & device */ 333 db = netdev_priv(dev); 334 335 /* Allocate Tx/Rx descriptor memory */ 336 err = -ENOMEM; 337 338 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr); 339 if (!db->desc_pool_ptr) 340 goto err_out_release; 341 342 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr); 343 if (!db->buf_pool_ptr) 344 goto err_out_free_tx_desc; 345 346 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr; 347 db->first_tx_desc_dma = db->desc_pool_dma_ptr; 348 db->buf_pool_start = db->buf_pool_ptr; 349 db->buf_pool_dma_start = db->buf_pool_dma_ptr; 350 351 switch (ent->driver_data) { 352 case PCI_ULI5263_ID: 353 db->phy.write = phy_writeby_cr10; 354 db->phy.read = phy_readby_cr10; 355 break; 356 default: 357 db->phy.write = phy_writeby_cr9; 358 db->phy.read = phy_readby_cr9; 359 break; 360 } 361 362 /* IO region. */ 363 ioaddr = pci_iomap(pdev, 0, 0); 364 if (!ioaddr) 365 goto err_out_free_tx_buf; 366 367 db->ioaddr = ioaddr; 368 db->pdev = pdev; 369 db->init = 1; 370 371 pci_set_drvdata(pdev, dev); 372 373 /* Register some necessary functions */ 374 dev->netdev_ops = &netdev_ops; 375 dev->ethtool_ops = &netdev_ethtool_ops; 376 377 spin_lock_init(&db->lock); 378 379 380 /* read 64 word srom data */ 381 for (i = 0; i < 64; i++) 382 ((__le16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db, i)); 383 384 /* Set Node address */ 385 if(((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0) /* SROM absent, so read MAC address from ID Table */ 386 { 387 uw32(DCR0, 0x10000); //Diagnosis mode 388 uw32(DCR13, 0x1c0); //Reset dianostic pointer port 389 uw32(DCR14, 0); //Clear reset port 390 uw32(DCR14, 0x10); //Reset ID Table pointer 391 uw32(DCR14, 0); //Clear reset port 392 uw32(DCR13, 0); //Clear CR13 393 uw32(DCR13, 0x1b0); //Select ID Table access port 394 //Read MAC address from CR14 395 for (i = 0; i < 6; i++) 396 dev->dev_addr[i] = ur32(DCR14); 397 //Read end 398 uw32(DCR13, 0); //Clear CR13 399 uw32(DCR0, 0); //Clear CR0 400 udelay(10); 401 } 402 else /*Exist SROM*/ 403 { 404 for (i = 0; i < 6; i++) 405 dev->dev_addr[i] = db->srom[20 + i]; 406 } 407 err = register_netdev (dev); 408 if (err) 409 goto err_out_unmap; 410 411 netdev_info(dev, "ULi M%04lx at pci%s, %pM, irq %d\n", 412 ent->driver_data >> 16, pci_name(pdev), 413 dev->dev_addr, pdev->irq); 414 415 pci_set_master(pdev); 416 417 return 0; 418 419 err_out_unmap: 420 pci_iounmap(pdev, db->ioaddr); 421 err_out_free_tx_buf: 422 pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, 423 db->buf_pool_ptr, db->buf_pool_dma_ptr); 424 err_out_free_tx_desc: 425 pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, 426 db->desc_pool_ptr, db->desc_pool_dma_ptr); 427 err_out_release: 428 pci_release_regions(pdev); 429 err_out_disable: 430 pci_disable_device(pdev); 431 err_out_free: 432 pci_set_drvdata(pdev, NULL); 433 free_netdev(dev); 434 435 return err; 436 } 437 438 439 static void uli526x_remove_one(struct pci_dev *pdev) 440 { 441 struct net_device *dev = pci_get_drvdata(pdev); 442 struct uli526x_board_info *db = netdev_priv(dev); 443 444 unregister_netdev(dev); 445 pci_iounmap(pdev, db->ioaddr); 446 pci_free_consistent(db->pdev, sizeof(struct tx_desc) * 447 DESC_ALL_CNT + 0x20, db->desc_pool_ptr, 448 db->desc_pool_dma_ptr); 449 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, 450 db->buf_pool_ptr, db->buf_pool_dma_ptr); 451 pci_release_regions(pdev); 452 pci_disable_device(pdev); 453 pci_set_drvdata(pdev, NULL); 454 free_netdev(dev); 455 } 456 457 458 /* 459 * Open the interface. 460 * The interface is opened whenever "ifconfig" activates it. 461 */ 462 463 static int uli526x_open(struct net_device *dev) 464 { 465 int ret; 466 struct uli526x_board_info *db = netdev_priv(dev); 467 468 ULI526X_DBUG(0, "uli526x_open", 0); 469 470 /* system variable init */ 471 db->cr6_data = CR6_DEFAULT | uli526x_cr6_user_set; 472 db->tx_packet_cnt = 0; 473 db->rx_avail_cnt = 0; 474 db->link_failed = 1; 475 netif_carrier_off(dev); 476 db->wait_reset = 0; 477 478 db->NIC_capability = 0xf; /* All capability*/ 479 db->PHY_reg4 = 0x1e0; 480 481 /* CR6 operation mode decision */ 482 db->cr6_data |= ULI526X_TXTH_256; 483 db->cr0_data = CR0_DEFAULT; 484 485 /* Initialize ULI526X board */ 486 uli526x_init(dev); 487 488 ret = request_irq(db->pdev->irq, uli526x_interrupt, IRQF_SHARED, 489 dev->name, dev); 490 if (ret) 491 return ret; 492 493 /* Active System Interface */ 494 netif_wake_queue(dev); 495 496 /* set and active a timer process */ 497 init_timer(&db->timer); 498 db->timer.expires = ULI526X_TIMER_WUT + HZ * 2; 499 db->timer.data = (unsigned long)dev; 500 db->timer.function = uli526x_timer; 501 add_timer(&db->timer); 502 503 return 0; 504 } 505 506 507 /* Initialize ULI526X board 508 * Reset ULI526X board 509 * Initialize TX/Rx descriptor chain structure 510 * Send the set-up frame 511 * Enable Tx/Rx machine 512 */ 513 514 static void uli526x_init(struct net_device *dev) 515 { 516 struct uli526x_board_info *db = netdev_priv(dev); 517 struct uli_phy_ops *phy = &db->phy; 518 void __iomem *ioaddr = db->ioaddr; 519 u8 phy_tmp; 520 u8 timeout; 521 u16 phy_reg_reset; 522 523 524 ULI526X_DBUG(0, "uli526x_init()", 0); 525 526 /* Reset M526x MAC controller */ 527 uw32(DCR0, ULI526X_RESET); /* RESET MAC */ 528 udelay(100); 529 uw32(DCR0, db->cr0_data); 530 udelay(5); 531 532 /* Phy addr : In some boards,M5261/M5263 phy address != 1 */ 533 db->phy_addr = 1; 534 for (phy_tmp = 0; phy_tmp < 32; phy_tmp++) { 535 u16 phy_value; 536 537 phy_value = phy->read(db, phy_tmp, 3); //peer add 538 if (phy_value != 0xffff && phy_value != 0) { 539 db->phy_addr = phy_tmp; 540 break; 541 } 542 } 543 544 if (phy_tmp == 32) 545 pr_warn("Can not find the phy address!!!\n"); 546 /* Parser SROM and media mode */ 547 db->media_mode = uli526x_media_mode; 548 549 /* phyxcer capability setting */ 550 phy_reg_reset = phy->read(db, db->phy_addr, 0); 551 phy_reg_reset = (phy_reg_reset | 0x8000); 552 phy->write(db, db->phy_addr, 0, phy_reg_reset); 553 554 /* See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management 555 * functions") or phy data sheet for details on phy reset 556 */ 557 udelay(500); 558 timeout = 10; 559 while (timeout-- && phy->read(db, db->phy_addr, 0) & 0x8000) 560 udelay(100); 561 562 /* Process Phyxcer Media Mode */ 563 uli526x_set_phyxcer(db); 564 565 /* Media Mode Process */ 566 if ( !(db->media_mode & ULI526X_AUTO) ) 567 db->op_mode = db->media_mode; /* Force Mode */ 568 569 /* Initialize Transmit/Receive decriptor and CR3/4 */ 570 uli526x_descriptor_init(dev, ioaddr); 571 572 /* Init CR6 to program M526X operation */ 573 update_cr6(db->cr6_data, ioaddr); 574 575 /* Send setup frame */ 576 send_filter_frame(dev, netdev_mc_count(dev)); /* M5261/M5263 */ 577 578 /* Init CR7, interrupt active bit */ 579 db->cr7_data = CR7_DEFAULT; 580 uw32(DCR7, db->cr7_data); 581 582 /* Init CR15, Tx jabber and Rx watchdog timer */ 583 uw32(DCR15, db->cr15_data); 584 585 /* Enable ULI526X Tx/Rx function */ 586 db->cr6_data |= CR6_RXSC | CR6_TXSC; 587 update_cr6(db->cr6_data, ioaddr); 588 } 589 590 591 /* 592 * Hardware start transmission. 593 * Send a packet to media from the upper layer. 594 */ 595 596 static netdev_tx_t uli526x_start_xmit(struct sk_buff *skb, 597 struct net_device *dev) 598 { 599 struct uli526x_board_info *db = netdev_priv(dev); 600 void __iomem *ioaddr = db->ioaddr; 601 struct tx_desc *txptr; 602 unsigned long flags; 603 604 ULI526X_DBUG(0, "uli526x_start_xmit", 0); 605 606 /* Resource flag check */ 607 netif_stop_queue(dev); 608 609 /* Too large packet check */ 610 if (skb->len > MAX_PACKET_SIZE) { 611 netdev_err(dev, "big packet = %d\n", (u16)skb->len); 612 dev_kfree_skb(skb); 613 return NETDEV_TX_OK; 614 } 615 616 spin_lock_irqsave(&db->lock, flags); 617 618 /* No Tx resource check, it never happen nromally */ 619 if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) { 620 spin_unlock_irqrestore(&db->lock, flags); 621 netdev_err(dev, "No Tx resource %ld\n", db->tx_packet_cnt); 622 return NETDEV_TX_BUSY; 623 } 624 625 /* Disable NIC interrupt */ 626 uw32(DCR7, 0); 627 628 /* transmit this packet */ 629 txptr = db->tx_insert_ptr; 630 skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len); 631 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len); 632 633 /* Point to next transmit free descriptor */ 634 db->tx_insert_ptr = txptr->next_tx_desc; 635 636 /* Transmit Packet Process */ 637 if (db->tx_packet_cnt < TX_DESC_CNT) { 638 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */ 639 db->tx_packet_cnt++; /* Ready to send */ 640 uw32(DCR1, 0x1); /* Issue Tx polling */ 641 dev->trans_start = jiffies; /* saved time stamp */ 642 } 643 644 /* Tx resource check */ 645 if ( db->tx_packet_cnt < TX_FREE_DESC_CNT ) 646 netif_wake_queue(dev); 647 648 /* Restore CR7 to enable interrupt */ 649 spin_unlock_irqrestore(&db->lock, flags); 650 uw32(DCR7, db->cr7_data); 651 652 /* free this SKB */ 653 dev_kfree_skb(skb); 654 655 return NETDEV_TX_OK; 656 } 657 658 659 /* 660 * Stop the interface. 661 * The interface is stopped when it is brought. 662 */ 663 664 static int uli526x_stop(struct net_device *dev) 665 { 666 struct uli526x_board_info *db = netdev_priv(dev); 667 void __iomem *ioaddr = db->ioaddr; 668 669 /* disable system */ 670 netif_stop_queue(dev); 671 672 /* deleted timer */ 673 del_timer_sync(&db->timer); 674 675 /* Reset & stop ULI526X board */ 676 uw32(DCR0, ULI526X_RESET); 677 udelay(5); 678 db->phy.write(db, db->phy_addr, 0, 0x8000); 679 680 /* free interrupt */ 681 free_irq(db->pdev->irq, dev); 682 683 /* free allocated rx buffer */ 684 uli526x_free_rxbuffer(db); 685 686 return 0; 687 } 688 689 690 /* 691 * M5261/M5263 insterrupt handler 692 * receive the packet to upper layer, free the transmitted packet 693 */ 694 695 static irqreturn_t uli526x_interrupt(int irq, void *dev_id) 696 { 697 struct net_device *dev = dev_id; 698 struct uli526x_board_info *db = netdev_priv(dev); 699 void __iomem *ioaddr = db->ioaddr; 700 unsigned long flags; 701 702 spin_lock_irqsave(&db->lock, flags); 703 uw32(DCR7, 0); 704 705 /* Got ULI526X status */ 706 db->cr5_data = ur32(DCR5); 707 uw32(DCR5, db->cr5_data); 708 if ( !(db->cr5_data & 0x180c1) ) { 709 /* Restore CR7 to enable interrupt mask */ 710 uw32(DCR7, db->cr7_data); 711 spin_unlock_irqrestore(&db->lock, flags); 712 return IRQ_HANDLED; 713 } 714 715 /* Check system status */ 716 if (db->cr5_data & 0x2000) { 717 /* system bus error happen */ 718 ULI526X_DBUG(1, "System bus error happen. CR5=", db->cr5_data); 719 db->reset_fatal++; 720 db->wait_reset = 1; /* Need to RESET */ 721 spin_unlock_irqrestore(&db->lock, flags); 722 return IRQ_HANDLED; 723 } 724 725 /* Received the coming packet */ 726 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt ) 727 uli526x_rx_packet(dev, db); 728 729 /* reallocate rx descriptor buffer */ 730 if (db->rx_avail_cnt<RX_DESC_CNT) 731 allocate_rx_buffer(dev); 732 733 /* Free the transmitted descriptor */ 734 if ( db->cr5_data & 0x01) 735 uli526x_free_tx_pkt(dev, db); 736 737 /* Restore CR7 to enable interrupt mask */ 738 uw32(DCR7, db->cr7_data); 739 740 spin_unlock_irqrestore(&db->lock, flags); 741 return IRQ_HANDLED; 742 } 743 744 #ifdef CONFIG_NET_POLL_CONTROLLER 745 static void uli526x_poll(struct net_device *dev) 746 { 747 struct uli526x_board_info *db = netdev_priv(dev); 748 749 /* ISR grabs the irqsave lock, so this should be safe */ 750 uli526x_interrupt(db->pdev->irq, dev); 751 } 752 #endif 753 754 /* 755 * Free TX resource after TX complete 756 */ 757 758 static void uli526x_free_tx_pkt(struct net_device *dev, 759 struct uli526x_board_info * db) 760 { 761 struct tx_desc *txptr; 762 u32 tdes0; 763 764 txptr = db->tx_remove_ptr; 765 while(db->tx_packet_cnt) { 766 tdes0 = le32_to_cpu(txptr->tdes0); 767 if (tdes0 & 0x80000000) 768 break; 769 770 /* A packet sent completed */ 771 db->tx_packet_cnt--; 772 dev->stats.tx_packets++; 773 774 /* Transmit statistic counter */ 775 if ( tdes0 != 0x7fffffff ) { 776 dev->stats.collisions += (tdes0 >> 3) & 0xf; 777 dev->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff; 778 if (tdes0 & TDES0_ERR_MASK) { 779 dev->stats.tx_errors++; 780 if (tdes0 & 0x0002) { /* UnderRun */ 781 db->tx_fifo_underrun++; 782 if ( !(db->cr6_data & CR6_SFT) ) { 783 db->cr6_data = db->cr6_data | CR6_SFT; 784 update_cr6(db->cr6_data, db->ioaddr); 785 } 786 } 787 if (tdes0 & 0x0100) 788 db->tx_excessive_collision++; 789 if (tdes0 & 0x0200) 790 db->tx_late_collision++; 791 if (tdes0 & 0x0400) 792 db->tx_no_carrier++; 793 if (tdes0 & 0x0800) 794 db->tx_loss_carrier++; 795 if (tdes0 & 0x4000) 796 db->tx_jabber_timeout++; 797 } 798 } 799 800 txptr = txptr->next_tx_desc; 801 }/* End of while */ 802 803 /* Update TX remove pointer to next */ 804 db->tx_remove_ptr = txptr; 805 806 /* Resource available check */ 807 if ( db->tx_packet_cnt < TX_WAKE_DESC_CNT ) 808 netif_wake_queue(dev); /* Active upper layer, send again */ 809 } 810 811 812 /* 813 * Receive the come packet and pass to upper layer 814 */ 815 816 static void uli526x_rx_packet(struct net_device *dev, struct uli526x_board_info * db) 817 { 818 struct rx_desc *rxptr; 819 struct sk_buff *skb; 820 int rxlen; 821 u32 rdes0; 822 823 rxptr = db->rx_ready_ptr; 824 825 while(db->rx_avail_cnt) { 826 rdes0 = le32_to_cpu(rxptr->rdes0); 827 if (rdes0 & 0x80000000) /* packet owner check */ 828 { 829 break; 830 } 831 832 db->rx_avail_cnt--; 833 db->interval_rx_cnt++; 834 835 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2), RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE); 836 if ( (rdes0 & 0x300) != 0x300) { 837 /* A packet without First/Last flag */ 838 /* reuse this SKB */ 839 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0); 840 uli526x_reuse_skb(db, rxptr->rx_skb_ptr); 841 } else { 842 /* A packet with First/Last flag */ 843 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4; 844 845 /* error summary bit check */ 846 if (rdes0 & 0x8000) { 847 /* This is a error packet */ 848 dev->stats.rx_errors++; 849 if (rdes0 & 1) 850 dev->stats.rx_fifo_errors++; 851 if (rdes0 & 2) 852 dev->stats.rx_crc_errors++; 853 if (rdes0 & 0x80) 854 dev->stats.rx_length_errors++; 855 } 856 857 if ( !(rdes0 & 0x8000) || 858 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) { 859 struct sk_buff *new_skb = NULL; 860 861 skb = rxptr->rx_skb_ptr; 862 863 /* Good packet, send to upper layer */ 864 /* Shorst packet used new SKB */ 865 if ((rxlen < RX_COPY_SIZE) && 866 (((new_skb = netdev_alloc_skb(dev, rxlen + 2)) != NULL))) { 867 skb = new_skb; 868 /* size less than COPY_SIZE, allocate a rxlen SKB */ 869 skb_reserve(skb, 2); /* 16byte align */ 870 memcpy(skb_put(skb, rxlen), 871 skb_tail_pointer(rxptr->rx_skb_ptr), 872 rxlen); 873 uli526x_reuse_skb(db, rxptr->rx_skb_ptr); 874 } else 875 skb_put(skb, rxlen); 876 877 skb->protocol = eth_type_trans(skb, dev); 878 netif_rx(skb); 879 dev->stats.rx_packets++; 880 dev->stats.rx_bytes += rxlen; 881 882 } else { 883 /* Reuse SKB buffer when the packet is error */ 884 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0); 885 uli526x_reuse_skb(db, rxptr->rx_skb_ptr); 886 } 887 } 888 889 rxptr = rxptr->next_rx_desc; 890 } 891 892 db->rx_ready_ptr = rxptr; 893 } 894 895 896 /* 897 * Set ULI526X multicast address 898 */ 899 900 static void uli526x_set_filter_mode(struct net_device * dev) 901 { 902 struct uli526x_board_info *db = netdev_priv(dev); 903 unsigned long flags; 904 905 ULI526X_DBUG(0, "uli526x_set_filter_mode()", 0); 906 spin_lock_irqsave(&db->lock, flags); 907 908 if (dev->flags & IFF_PROMISC) { 909 ULI526X_DBUG(0, "Enable PROM Mode", 0); 910 db->cr6_data |= CR6_PM | CR6_PBF; 911 update_cr6(db->cr6_data, db->ioaddr); 912 spin_unlock_irqrestore(&db->lock, flags); 913 return; 914 } 915 916 if (dev->flags & IFF_ALLMULTI || 917 netdev_mc_count(dev) > ULI5261_MAX_MULTICAST) { 918 ULI526X_DBUG(0, "Pass all multicast address", 919 netdev_mc_count(dev)); 920 db->cr6_data &= ~(CR6_PM | CR6_PBF); 921 db->cr6_data |= CR6_PAM; 922 spin_unlock_irqrestore(&db->lock, flags); 923 return; 924 } 925 926 ULI526X_DBUG(0, "Set multicast address", netdev_mc_count(dev)); 927 send_filter_frame(dev, netdev_mc_count(dev)); /* M5261/M5263 */ 928 spin_unlock_irqrestore(&db->lock, flags); 929 } 930 931 static void 932 ULi_ethtool_gset(struct uli526x_board_info *db, struct ethtool_cmd *ecmd) 933 { 934 ecmd->supported = (SUPPORTED_10baseT_Half | 935 SUPPORTED_10baseT_Full | 936 SUPPORTED_100baseT_Half | 937 SUPPORTED_100baseT_Full | 938 SUPPORTED_Autoneg | 939 SUPPORTED_MII); 940 941 ecmd->advertising = (ADVERTISED_10baseT_Half | 942 ADVERTISED_10baseT_Full | 943 ADVERTISED_100baseT_Half | 944 ADVERTISED_100baseT_Full | 945 ADVERTISED_Autoneg | 946 ADVERTISED_MII); 947 948 949 ecmd->port = PORT_MII; 950 ecmd->phy_address = db->phy_addr; 951 952 ecmd->transceiver = XCVR_EXTERNAL; 953 954 ethtool_cmd_speed_set(ecmd, SPEED_10); 955 ecmd->duplex = DUPLEX_HALF; 956 957 if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD) 958 { 959 ethtool_cmd_speed_set(ecmd, SPEED_100); 960 } 961 if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD) 962 { 963 ecmd->duplex = DUPLEX_FULL; 964 } 965 if(db->link_failed) 966 { 967 ethtool_cmd_speed_set(ecmd, -1); 968 ecmd->duplex = -1; 969 } 970 971 if (db->media_mode & ULI526X_AUTO) 972 { 973 ecmd->autoneg = AUTONEG_ENABLE; 974 } 975 } 976 977 static void netdev_get_drvinfo(struct net_device *dev, 978 struct ethtool_drvinfo *info) 979 { 980 struct uli526x_board_info *np = netdev_priv(dev); 981 982 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 983 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 984 strlcpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info)); 985 } 986 987 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) { 988 struct uli526x_board_info *np = netdev_priv(dev); 989 990 ULi_ethtool_gset(np, cmd); 991 992 return 0; 993 } 994 995 static u32 netdev_get_link(struct net_device *dev) { 996 struct uli526x_board_info *np = netdev_priv(dev); 997 998 if(np->link_failed) 999 return 0; 1000 else 1001 return 1; 1002 } 1003 1004 static void uli526x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1005 { 1006 wol->supported = WAKE_PHY | WAKE_MAGIC; 1007 wol->wolopts = 0; 1008 } 1009 1010 static const struct ethtool_ops netdev_ethtool_ops = { 1011 .get_drvinfo = netdev_get_drvinfo, 1012 .get_settings = netdev_get_settings, 1013 .get_link = netdev_get_link, 1014 .get_wol = uli526x_get_wol, 1015 }; 1016 1017 /* 1018 * A periodic timer routine 1019 * Dynamic media sense, allocate Rx buffer... 1020 */ 1021 1022 static void uli526x_timer(unsigned long data) 1023 { 1024 struct net_device *dev = (struct net_device *) data; 1025 struct uli526x_board_info *db = netdev_priv(dev); 1026 struct uli_phy_ops *phy = &db->phy; 1027 void __iomem *ioaddr = db->ioaddr; 1028 unsigned long flags; 1029 u8 tmp_cr12 = 0; 1030 u32 tmp_cr8; 1031 1032 //ULI526X_DBUG(0, "uli526x_timer()", 0); 1033 spin_lock_irqsave(&db->lock, flags); 1034 1035 1036 /* Dynamic reset ULI526X : system error or transmit time-out */ 1037 tmp_cr8 = ur32(DCR8); 1038 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) { 1039 db->reset_cr8++; 1040 db->wait_reset = 1; 1041 } 1042 db->interval_rx_cnt = 0; 1043 1044 /* TX polling kick monitor */ 1045 if ( db->tx_packet_cnt && 1046 time_after(jiffies, dev_trans_start(dev) + ULI526X_TX_KICK) ) { 1047 uw32(DCR1, 0x1); // Tx polling again 1048 1049 // TX Timeout 1050 if ( time_after(jiffies, dev_trans_start(dev) + ULI526X_TX_TIMEOUT) ) { 1051 db->reset_TXtimeout++; 1052 db->wait_reset = 1; 1053 netdev_err(dev, " Tx timeout - resetting\n"); 1054 } 1055 } 1056 1057 if (db->wait_reset) { 1058 ULI526X_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt); 1059 db->reset_count++; 1060 uli526x_dynamic_reset(dev); 1061 db->timer.expires = ULI526X_TIMER_WUT; 1062 add_timer(&db->timer); 1063 spin_unlock_irqrestore(&db->lock, flags); 1064 return; 1065 } 1066 1067 /* Link status check, Dynamic media type change */ 1068 if ((phy->read(db, db->phy_addr, 5) & 0x01e0)!=0) 1069 tmp_cr12 = 3; 1070 1071 if ( !(tmp_cr12 & 0x3) && !db->link_failed ) { 1072 /* Link Failed */ 1073 ULI526X_DBUG(0, "Link Failed", tmp_cr12); 1074 netif_carrier_off(dev); 1075 netdev_info(dev, "NIC Link is Down\n"); 1076 db->link_failed = 1; 1077 1078 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */ 1079 /* AUTO don't need */ 1080 if ( !(db->media_mode & 0x8) ) 1081 phy->write(db, db->phy_addr, 0, 0x1000); 1082 1083 /* AUTO mode, if INT phyxcer link failed, select EXT device */ 1084 if (db->media_mode & ULI526X_AUTO) { 1085 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */ 1086 update_cr6(db->cr6_data, db->ioaddr); 1087 } 1088 } else 1089 if ((tmp_cr12 & 0x3) && db->link_failed) { 1090 ULI526X_DBUG(0, "Link link OK", tmp_cr12); 1091 db->link_failed = 0; 1092 1093 /* Auto Sense Speed */ 1094 if ( (db->media_mode & ULI526X_AUTO) && 1095 uli526x_sense_speed(db) ) 1096 db->link_failed = 1; 1097 uli526x_process_mode(db); 1098 1099 if(db->link_failed==0) 1100 { 1101 netdev_info(dev, "NIC Link is Up %d Mbps %s duplex\n", 1102 (db->op_mode == ULI526X_100MHF || 1103 db->op_mode == ULI526X_100MFD) 1104 ? 100 : 10, 1105 (db->op_mode == ULI526X_10MFD || 1106 db->op_mode == ULI526X_100MFD) 1107 ? "Full" : "Half"); 1108 netif_carrier_on(dev); 1109 } 1110 /* SHOW_MEDIA_TYPE(db->op_mode); */ 1111 } 1112 else if(!(tmp_cr12 & 0x3) && db->link_failed) 1113 { 1114 if(db->init==1) 1115 { 1116 netdev_info(dev, "NIC Link is Down\n"); 1117 netif_carrier_off(dev); 1118 } 1119 } 1120 db->init=0; 1121 1122 /* Timer active again */ 1123 db->timer.expires = ULI526X_TIMER_WUT; 1124 add_timer(&db->timer); 1125 spin_unlock_irqrestore(&db->lock, flags); 1126 } 1127 1128 1129 /* 1130 * Stop ULI526X board 1131 * Free Tx/Rx allocated memory 1132 * Init system variable 1133 */ 1134 1135 static void uli526x_reset_prepare(struct net_device *dev) 1136 { 1137 struct uli526x_board_info *db = netdev_priv(dev); 1138 void __iomem *ioaddr = db->ioaddr; 1139 1140 /* Sopt MAC controller */ 1141 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */ 1142 update_cr6(db->cr6_data, ioaddr); 1143 uw32(DCR7, 0); /* Disable Interrupt */ 1144 uw32(DCR5, ur32(DCR5)); 1145 1146 /* Disable upper layer interface */ 1147 netif_stop_queue(dev); 1148 1149 /* Free Rx Allocate buffer */ 1150 uli526x_free_rxbuffer(db); 1151 1152 /* system variable init */ 1153 db->tx_packet_cnt = 0; 1154 db->rx_avail_cnt = 0; 1155 db->link_failed = 1; 1156 db->init=1; 1157 db->wait_reset = 0; 1158 } 1159 1160 1161 /* 1162 * Dynamic reset the ULI526X board 1163 * Stop ULI526X board 1164 * Free Tx/Rx allocated memory 1165 * Reset ULI526X board 1166 * Re-initialize ULI526X board 1167 */ 1168 1169 static void uli526x_dynamic_reset(struct net_device *dev) 1170 { 1171 ULI526X_DBUG(0, "uli526x_dynamic_reset()", 0); 1172 1173 uli526x_reset_prepare(dev); 1174 1175 /* Re-initialize ULI526X board */ 1176 uli526x_init(dev); 1177 1178 /* Restart upper layer interface */ 1179 netif_wake_queue(dev); 1180 } 1181 1182 1183 #ifdef CONFIG_PM 1184 1185 /* 1186 * Suspend the interface. 1187 */ 1188 1189 static int uli526x_suspend(struct pci_dev *pdev, pm_message_t state) 1190 { 1191 struct net_device *dev = pci_get_drvdata(pdev); 1192 pci_power_t power_state; 1193 int err; 1194 1195 ULI526X_DBUG(0, "uli526x_suspend", 0); 1196 1197 if (!netdev_priv(dev)) 1198 return 0; 1199 1200 pci_save_state(pdev); 1201 1202 if (!netif_running(dev)) 1203 return 0; 1204 1205 netif_device_detach(dev); 1206 uli526x_reset_prepare(dev); 1207 1208 power_state = pci_choose_state(pdev, state); 1209 pci_enable_wake(pdev, power_state, 0); 1210 err = pci_set_power_state(pdev, power_state); 1211 if (err) { 1212 netif_device_attach(dev); 1213 /* Re-initialize ULI526X board */ 1214 uli526x_init(dev); 1215 /* Restart upper layer interface */ 1216 netif_wake_queue(dev); 1217 } 1218 1219 return err; 1220 } 1221 1222 /* 1223 * Resume the interface. 1224 */ 1225 1226 static int uli526x_resume(struct pci_dev *pdev) 1227 { 1228 struct net_device *dev = pci_get_drvdata(pdev); 1229 int err; 1230 1231 ULI526X_DBUG(0, "uli526x_resume", 0); 1232 1233 if (!netdev_priv(dev)) 1234 return 0; 1235 1236 pci_restore_state(pdev); 1237 1238 if (!netif_running(dev)) 1239 return 0; 1240 1241 err = pci_set_power_state(pdev, PCI_D0); 1242 if (err) { 1243 netdev_warn(dev, "Could not put device into D0\n"); 1244 return err; 1245 } 1246 1247 netif_device_attach(dev); 1248 /* Re-initialize ULI526X board */ 1249 uli526x_init(dev); 1250 /* Restart upper layer interface */ 1251 netif_wake_queue(dev); 1252 1253 return 0; 1254 } 1255 1256 #else /* !CONFIG_PM */ 1257 1258 #define uli526x_suspend NULL 1259 #define uli526x_resume NULL 1260 1261 #endif /* !CONFIG_PM */ 1262 1263 1264 /* 1265 * free all allocated rx buffer 1266 */ 1267 1268 static void uli526x_free_rxbuffer(struct uli526x_board_info * db) 1269 { 1270 ULI526X_DBUG(0, "uli526x_free_rxbuffer()", 0); 1271 1272 /* free allocated rx buffer */ 1273 while (db->rx_avail_cnt) { 1274 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr); 1275 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc; 1276 db->rx_avail_cnt--; 1277 } 1278 } 1279 1280 1281 /* 1282 * Reuse the SK buffer 1283 */ 1284 1285 static void uli526x_reuse_skb(struct uli526x_board_info *db, struct sk_buff * skb) 1286 { 1287 struct rx_desc *rxptr = db->rx_insert_ptr; 1288 1289 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) { 1290 rxptr->rx_skb_ptr = skb; 1291 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev, 1292 skb_tail_pointer(skb), 1293 RX_ALLOC_SIZE, 1294 PCI_DMA_FROMDEVICE)); 1295 wmb(); 1296 rxptr->rdes0 = cpu_to_le32(0x80000000); 1297 db->rx_avail_cnt++; 1298 db->rx_insert_ptr = rxptr->next_rx_desc; 1299 } else 1300 ULI526X_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt); 1301 } 1302 1303 1304 /* 1305 * Initialize transmit/Receive descriptor 1306 * Using Chain structure, and allocate Tx/Rx buffer 1307 */ 1308 1309 static void uli526x_descriptor_init(struct net_device *dev, void __iomem *ioaddr) 1310 { 1311 struct uli526x_board_info *db = netdev_priv(dev); 1312 struct tx_desc *tmp_tx; 1313 struct rx_desc *tmp_rx; 1314 unsigned char *tmp_buf; 1315 dma_addr_t tmp_tx_dma, tmp_rx_dma; 1316 dma_addr_t tmp_buf_dma; 1317 int i; 1318 1319 ULI526X_DBUG(0, "uli526x_descriptor_init()", 0); 1320 1321 /* tx descriptor start pointer */ 1322 db->tx_insert_ptr = db->first_tx_desc; 1323 db->tx_remove_ptr = db->first_tx_desc; 1324 uw32(DCR4, db->first_tx_desc_dma); /* TX DESC address */ 1325 1326 /* rx descriptor start pointer */ 1327 db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT; 1328 db->first_rx_desc_dma = db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT; 1329 db->rx_insert_ptr = db->first_rx_desc; 1330 db->rx_ready_ptr = db->first_rx_desc; 1331 uw32(DCR3, db->first_rx_desc_dma); /* RX DESC address */ 1332 1333 /* Init Transmit chain */ 1334 tmp_buf = db->buf_pool_start; 1335 tmp_buf_dma = db->buf_pool_dma_start; 1336 tmp_tx_dma = db->first_tx_desc_dma; 1337 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) { 1338 tmp_tx->tx_buf_ptr = tmp_buf; 1339 tmp_tx->tdes0 = cpu_to_le32(0); 1340 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */ 1341 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma); 1342 tmp_tx_dma += sizeof(struct tx_desc); 1343 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma); 1344 tmp_tx->next_tx_desc = tmp_tx + 1; 1345 tmp_buf = tmp_buf + TX_BUF_ALLOC; 1346 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC; 1347 } 1348 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma); 1349 tmp_tx->next_tx_desc = db->first_tx_desc; 1350 1351 /* Init Receive descriptor chain */ 1352 tmp_rx_dma=db->first_rx_desc_dma; 1353 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) { 1354 tmp_rx->rdes0 = cpu_to_le32(0); 1355 tmp_rx->rdes1 = cpu_to_le32(0x01000600); 1356 tmp_rx_dma += sizeof(struct rx_desc); 1357 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma); 1358 tmp_rx->next_rx_desc = tmp_rx + 1; 1359 } 1360 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma); 1361 tmp_rx->next_rx_desc = db->first_rx_desc; 1362 1363 /* pre-allocate Rx buffer */ 1364 allocate_rx_buffer(dev); 1365 } 1366 1367 1368 /* 1369 * Update CR6 value 1370 * Firstly stop ULI526X, then written value and start 1371 */ 1372 static void update_cr6(u32 cr6_data, void __iomem *ioaddr) 1373 { 1374 uw32(DCR6, cr6_data); 1375 udelay(5); 1376 } 1377 1378 1379 /* 1380 * Send a setup frame for M5261/M5263 1381 * This setup frame initialize ULI526X address filter mode 1382 */ 1383 1384 #ifdef __BIG_ENDIAN 1385 #define FLT_SHIFT 16 1386 #else 1387 #define FLT_SHIFT 0 1388 #endif 1389 1390 static void send_filter_frame(struct net_device *dev, int mc_cnt) 1391 { 1392 struct uli526x_board_info *db = netdev_priv(dev); 1393 void __iomem *ioaddr = db->ioaddr; 1394 struct netdev_hw_addr *ha; 1395 struct tx_desc *txptr; 1396 u16 * addrptr; 1397 u32 * suptr; 1398 int i; 1399 1400 ULI526X_DBUG(0, "send_filter_frame()", 0); 1401 1402 txptr = db->tx_insert_ptr; 1403 suptr = (u32 *) txptr->tx_buf_ptr; 1404 1405 /* Node address */ 1406 addrptr = (u16 *) dev->dev_addr; 1407 *suptr++ = addrptr[0] << FLT_SHIFT; 1408 *suptr++ = addrptr[1] << FLT_SHIFT; 1409 *suptr++ = addrptr[2] << FLT_SHIFT; 1410 1411 /* broadcast address */ 1412 *suptr++ = 0xffff << FLT_SHIFT; 1413 *suptr++ = 0xffff << FLT_SHIFT; 1414 *suptr++ = 0xffff << FLT_SHIFT; 1415 1416 /* fit the multicast address */ 1417 netdev_for_each_mc_addr(ha, dev) { 1418 addrptr = (u16 *) ha->addr; 1419 *suptr++ = addrptr[0] << FLT_SHIFT; 1420 *suptr++ = addrptr[1] << FLT_SHIFT; 1421 *suptr++ = addrptr[2] << FLT_SHIFT; 1422 } 1423 1424 for (i = netdev_mc_count(dev); i < 14; i++) { 1425 *suptr++ = 0xffff << FLT_SHIFT; 1426 *suptr++ = 0xffff << FLT_SHIFT; 1427 *suptr++ = 0xffff << FLT_SHIFT; 1428 } 1429 1430 /* prepare the setup frame */ 1431 db->tx_insert_ptr = txptr->next_tx_desc; 1432 txptr->tdes1 = cpu_to_le32(0x890000c0); 1433 1434 /* Resource Check and Send the setup packet */ 1435 if (db->tx_packet_cnt < TX_DESC_CNT) { 1436 /* Resource Empty */ 1437 db->tx_packet_cnt++; 1438 txptr->tdes0 = cpu_to_le32(0x80000000); 1439 update_cr6(db->cr6_data | 0x2000, ioaddr); 1440 uw32(DCR1, 0x1); /* Issue Tx polling */ 1441 update_cr6(db->cr6_data, ioaddr); 1442 dev->trans_start = jiffies; 1443 } else 1444 netdev_err(dev, "No Tx resource - Send_filter_frame!\n"); 1445 } 1446 1447 1448 /* 1449 * Allocate rx buffer, 1450 * As possible as allocate maxiumn Rx buffer 1451 */ 1452 1453 static void allocate_rx_buffer(struct net_device *dev) 1454 { 1455 struct uli526x_board_info *db = netdev_priv(dev); 1456 struct rx_desc *rxptr; 1457 struct sk_buff *skb; 1458 1459 rxptr = db->rx_insert_ptr; 1460 1461 while(db->rx_avail_cnt < RX_DESC_CNT) { 1462 skb = netdev_alloc_skb(dev, RX_ALLOC_SIZE); 1463 if (skb == NULL) 1464 break; 1465 rxptr->rx_skb_ptr = skb; /* FIXME (?) */ 1466 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev, 1467 skb_tail_pointer(skb), 1468 RX_ALLOC_SIZE, 1469 PCI_DMA_FROMDEVICE)); 1470 wmb(); 1471 rxptr->rdes0 = cpu_to_le32(0x80000000); 1472 rxptr = rxptr->next_rx_desc; 1473 db->rx_avail_cnt++; 1474 } 1475 1476 db->rx_insert_ptr = rxptr; 1477 } 1478 1479 1480 /* 1481 * Read one word data from the serial ROM 1482 */ 1483 1484 static u16 read_srom_word(struct uli526x_board_info *db, int offset) 1485 { 1486 void __iomem *ioaddr = db->ioaddr; 1487 u16 srom_data = 0; 1488 int i; 1489 1490 uw32(DCR9, CR9_SROM_READ); 1491 uw32(DCR9, CR9_SROM_READ | CR9_SRCS); 1492 1493 /* Send the Read Command 110b */ 1494 srom_clk_write(db, SROM_DATA_1); 1495 srom_clk_write(db, SROM_DATA_1); 1496 srom_clk_write(db, SROM_DATA_0); 1497 1498 /* Send the offset */ 1499 for (i = 5; i >= 0; i--) { 1500 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0; 1501 srom_clk_write(db, srom_data); 1502 } 1503 1504 uw32(DCR9, CR9_SROM_READ | CR9_SRCS); 1505 1506 for (i = 16; i > 0; i--) { 1507 uw32(DCR9, CR9_SROM_READ | CR9_SRCS | CR9_SRCLK); 1508 udelay(5); 1509 srom_data = (srom_data << 1) | 1510 ((ur32(DCR9) & CR9_CRDOUT) ? 1 : 0); 1511 uw32(DCR9, CR9_SROM_READ | CR9_SRCS); 1512 udelay(5); 1513 } 1514 1515 uw32(DCR9, CR9_SROM_READ); 1516 return srom_data; 1517 } 1518 1519 1520 /* 1521 * Auto sense the media mode 1522 */ 1523 1524 static u8 uli526x_sense_speed(struct uli526x_board_info * db) 1525 { 1526 struct uli_phy_ops *phy = &db->phy; 1527 u8 ErrFlag = 0; 1528 u16 phy_mode; 1529 1530 phy_mode = phy->read(db, db->phy_addr, 1); 1531 phy_mode = phy->read(db, db->phy_addr, 1); 1532 1533 if ( (phy_mode & 0x24) == 0x24 ) { 1534 1535 phy_mode = ((phy->read(db, db->phy_addr, 5) & 0x01e0)<<7); 1536 if(phy_mode&0x8000) 1537 phy_mode = 0x8000; 1538 else if(phy_mode&0x4000) 1539 phy_mode = 0x4000; 1540 else if(phy_mode&0x2000) 1541 phy_mode = 0x2000; 1542 else 1543 phy_mode = 0x1000; 1544 1545 switch (phy_mode) { 1546 case 0x1000: db->op_mode = ULI526X_10MHF; break; 1547 case 0x2000: db->op_mode = ULI526X_10MFD; break; 1548 case 0x4000: db->op_mode = ULI526X_100MHF; break; 1549 case 0x8000: db->op_mode = ULI526X_100MFD; break; 1550 default: db->op_mode = ULI526X_10MHF; ErrFlag = 1; break; 1551 } 1552 } else { 1553 db->op_mode = ULI526X_10MHF; 1554 ULI526X_DBUG(0, "Link Failed :", phy_mode); 1555 ErrFlag = 1; 1556 } 1557 1558 return ErrFlag; 1559 } 1560 1561 1562 /* 1563 * Set 10/100 phyxcer capability 1564 * AUTO mode : phyxcer register4 is NIC capability 1565 * Force mode: phyxcer register4 is the force media 1566 */ 1567 1568 static void uli526x_set_phyxcer(struct uli526x_board_info *db) 1569 { 1570 struct uli_phy_ops *phy = &db->phy; 1571 u16 phy_reg; 1572 1573 /* Phyxcer capability setting */ 1574 phy_reg = phy->read(db, db->phy_addr, 4) & ~0x01e0; 1575 1576 if (db->media_mode & ULI526X_AUTO) { 1577 /* AUTO Mode */ 1578 phy_reg |= db->PHY_reg4; 1579 } else { 1580 /* Force Mode */ 1581 switch(db->media_mode) { 1582 case ULI526X_10MHF: phy_reg |= 0x20; break; 1583 case ULI526X_10MFD: phy_reg |= 0x40; break; 1584 case ULI526X_100MHF: phy_reg |= 0x80; break; 1585 case ULI526X_100MFD: phy_reg |= 0x100; break; 1586 } 1587 1588 } 1589 1590 /* Write new capability to Phyxcer Reg4 */ 1591 if ( !(phy_reg & 0x01e0)) { 1592 phy_reg|=db->PHY_reg4; 1593 db->media_mode|=ULI526X_AUTO; 1594 } 1595 phy->write(db, db->phy_addr, 4, phy_reg); 1596 1597 /* Restart Auto-Negotiation */ 1598 phy->write(db, db->phy_addr, 0, 0x1200); 1599 udelay(50); 1600 } 1601 1602 1603 /* 1604 * Process op-mode 1605 AUTO mode : PHY controller in Auto-negotiation Mode 1606 * Force mode: PHY controller in force mode with HUB 1607 * N-way force capability with SWITCH 1608 */ 1609 1610 static void uli526x_process_mode(struct uli526x_board_info *db) 1611 { 1612 struct uli_phy_ops *phy = &db->phy; 1613 u16 phy_reg; 1614 1615 /* Full Duplex Mode Check */ 1616 if (db->op_mode & 0x4) 1617 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */ 1618 else 1619 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */ 1620 1621 update_cr6(db->cr6_data, db->ioaddr); 1622 1623 /* 10/100M phyxcer force mode need */ 1624 if (!(db->media_mode & 0x8)) { 1625 /* Forece Mode */ 1626 phy_reg = phy->read(db, db->phy_addr, 6); 1627 if (!(phy_reg & 0x1)) { 1628 /* parter without N-Way capability */ 1629 phy_reg = 0x0; 1630 switch(db->op_mode) { 1631 case ULI526X_10MHF: phy_reg = 0x0; break; 1632 case ULI526X_10MFD: phy_reg = 0x100; break; 1633 case ULI526X_100MHF: phy_reg = 0x2000; break; 1634 case ULI526X_100MFD: phy_reg = 0x2100; break; 1635 } 1636 phy->write(db, db->phy_addr, 0, phy_reg); 1637 } 1638 } 1639 } 1640 1641 1642 /* M5261/M5263 Chip */ 1643 static void phy_writeby_cr9(struct uli526x_board_info *db, u8 phy_addr, 1644 u8 offset, u16 phy_data) 1645 { 1646 u16 i; 1647 1648 /* Send 33 synchronization clock to Phy controller */ 1649 for (i = 0; i < 35; i++) 1650 phy_write_1bit(db, PHY_DATA_1); 1651 1652 /* Send start command(01) to Phy */ 1653 phy_write_1bit(db, PHY_DATA_0); 1654 phy_write_1bit(db, PHY_DATA_1); 1655 1656 /* Send write command(01) to Phy */ 1657 phy_write_1bit(db, PHY_DATA_0); 1658 phy_write_1bit(db, PHY_DATA_1); 1659 1660 /* Send Phy address */ 1661 for (i = 0x10; i > 0; i = i >> 1) 1662 phy_write_1bit(db, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0); 1663 1664 /* Send register address */ 1665 for (i = 0x10; i > 0; i = i >> 1) 1666 phy_write_1bit(db, offset & i ? PHY_DATA_1 : PHY_DATA_0); 1667 1668 /* written trasnition */ 1669 phy_write_1bit(db, PHY_DATA_1); 1670 phy_write_1bit(db, PHY_DATA_0); 1671 1672 /* Write a word data to PHY controller */ 1673 for (i = 0x8000; i > 0; i >>= 1) 1674 phy_write_1bit(db, phy_data & i ? PHY_DATA_1 : PHY_DATA_0); 1675 } 1676 1677 static u16 phy_readby_cr9(struct uli526x_board_info *db, u8 phy_addr, u8 offset) 1678 { 1679 u16 phy_data; 1680 int i; 1681 1682 /* Send 33 synchronization clock to Phy controller */ 1683 for (i = 0; i < 35; i++) 1684 phy_write_1bit(db, PHY_DATA_1); 1685 1686 /* Send start command(01) to Phy */ 1687 phy_write_1bit(db, PHY_DATA_0); 1688 phy_write_1bit(db, PHY_DATA_1); 1689 1690 /* Send read command(10) to Phy */ 1691 phy_write_1bit(db, PHY_DATA_1); 1692 phy_write_1bit(db, PHY_DATA_0); 1693 1694 /* Send Phy address */ 1695 for (i = 0x10; i > 0; i = i >> 1) 1696 phy_write_1bit(db, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0); 1697 1698 /* Send register address */ 1699 for (i = 0x10; i > 0; i = i >> 1) 1700 phy_write_1bit(db, offset & i ? PHY_DATA_1 : PHY_DATA_0); 1701 1702 /* Skip transition state */ 1703 phy_read_1bit(db); 1704 1705 /* read 16bit data */ 1706 for (phy_data = 0, i = 0; i < 16; i++) { 1707 phy_data <<= 1; 1708 phy_data |= phy_read_1bit(db); 1709 } 1710 1711 return phy_data; 1712 } 1713 1714 static u16 phy_readby_cr10(struct uli526x_board_info *db, u8 phy_addr, 1715 u8 offset) 1716 { 1717 void __iomem *ioaddr = db->ioaddr; 1718 u32 cr10_value = phy_addr; 1719 1720 cr10_value = (cr10_value << 5) + offset; 1721 cr10_value = (cr10_value << 16) + 0x08000000; 1722 uw32(DCR10, cr10_value); 1723 udelay(1); 1724 while (1) { 1725 cr10_value = ur32(DCR10); 1726 if (cr10_value & 0x10000000) 1727 break; 1728 } 1729 return cr10_value & 0x0ffff; 1730 } 1731 1732 static void phy_writeby_cr10(struct uli526x_board_info *db, u8 phy_addr, 1733 u8 offset, u16 phy_data) 1734 { 1735 void __iomem *ioaddr = db->ioaddr; 1736 u32 cr10_value = phy_addr; 1737 1738 cr10_value = (cr10_value << 5) + offset; 1739 cr10_value = (cr10_value << 16) + 0x04000000 + phy_data; 1740 uw32(DCR10, cr10_value); 1741 udelay(1); 1742 } 1743 /* 1744 * Write one bit data to Phy Controller 1745 */ 1746 1747 static void phy_write_1bit(struct uli526x_board_info *db, u32 data) 1748 { 1749 void __iomem *ioaddr = db->ioaddr; 1750 1751 uw32(DCR9, data); /* MII Clock Low */ 1752 udelay(1); 1753 uw32(DCR9, data | MDCLKH); /* MII Clock High */ 1754 udelay(1); 1755 uw32(DCR9, data); /* MII Clock Low */ 1756 udelay(1); 1757 } 1758 1759 1760 /* 1761 * Read one bit phy data from PHY controller 1762 */ 1763 1764 static u16 phy_read_1bit(struct uli526x_board_info *db) 1765 { 1766 void __iomem *ioaddr = db->ioaddr; 1767 u16 phy_data; 1768 1769 uw32(DCR9, 0x50000); 1770 udelay(1); 1771 phy_data = (ur32(DCR9) >> 19) & 0x1; 1772 uw32(DCR9, 0x40000); 1773 udelay(1); 1774 1775 return phy_data; 1776 } 1777 1778 1779 static DEFINE_PCI_DEVICE_TABLE(uli526x_pci_tbl) = { 1780 { 0x10B9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5261_ID }, 1781 { 0x10B9, 0x5263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5263_ID }, 1782 { 0, } 1783 }; 1784 MODULE_DEVICE_TABLE(pci, uli526x_pci_tbl); 1785 1786 1787 static struct pci_driver uli526x_driver = { 1788 .name = "uli526x", 1789 .id_table = uli526x_pci_tbl, 1790 .probe = uli526x_init_one, 1791 .remove = uli526x_remove_one, 1792 .suspend = uli526x_suspend, 1793 .resume = uli526x_resume, 1794 }; 1795 1796 MODULE_AUTHOR("Peer Chen, peer.chen@uli.com.tw"); 1797 MODULE_DESCRIPTION("ULi M5261/M5263 fast ethernet driver"); 1798 MODULE_LICENSE("GPL"); 1799 1800 module_param(debug, int, 0644); 1801 module_param(mode, int, 0); 1802 module_param(cr6set, int, 0); 1803 MODULE_PARM_DESC(debug, "ULi M5261/M5263 enable debugging (0-1)"); 1804 MODULE_PARM_DESC(mode, "ULi M5261/M5263: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA"); 1805 1806 /* Description: 1807 * when user used insmod to add module, system invoked init_module() 1808 * to register the services. 1809 */ 1810 1811 static int __init uli526x_init_module(void) 1812 { 1813 1814 pr_info("%s\n", version); 1815 printed_version = 1; 1816 1817 ULI526X_DBUG(0, "init_module() ", debug); 1818 1819 if (debug) 1820 uli526x_debug = debug; /* set debug flag */ 1821 if (cr6set) 1822 uli526x_cr6_user_set = cr6set; 1823 1824 switch (mode) { 1825 case ULI526X_10MHF: 1826 case ULI526X_100MHF: 1827 case ULI526X_10MFD: 1828 case ULI526X_100MFD: 1829 uli526x_media_mode = mode; 1830 break; 1831 default: 1832 uli526x_media_mode = ULI526X_AUTO; 1833 break; 1834 } 1835 1836 return pci_register_driver(&uli526x_driver); 1837 } 1838 1839 1840 /* 1841 * Description: 1842 * when user used rmmod to delete module, system invoked clean_module() 1843 * to un-register all registered services. 1844 */ 1845 1846 static void __exit uli526x_cleanup_module(void) 1847 { 1848 ULI526X_DBUG(0, "uli526x_clean_module() ", debug); 1849 pci_unregister_driver(&uli526x_driver); 1850 } 1851 1852 module_init(uli526x_init_module); 1853 module_exit(uli526x_cleanup_module); 1854