1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 
4 
5 */
6 
7 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8 
9 #define DRV_NAME	"uli526x"
10 
11 #include <linux/module.h>
12 
13 #include <linux/kernel.h>
14 #include <linux/string.h>
15 #include <linux/timer.h>
16 #include <linux/errno.h>
17 #include <linux/ioport.h>
18 #include <linux/interrupt.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/ethtool.h>
24 #include <linux/skbuff.h>
25 #include <linux/delay.h>
26 #include <linux/spinlock.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/bitops.h>
29 
30 #include <asm/processor.h>
31 #include <asm/io.h>
32 #include <asm/dma.h>
33 #include <linux/uaccess.h>
34 
35 #define uw32(reg, val)	iowrite32(val, ioaddr + (reg))
36 #define ur32(reg)	ioread32(ioaddr + (reg))
37 
38 /* Board/System/Debug information/definition ---------------- */
39 #define PCI_ULI5261_ID  0x526110B9	/* ULi M5261 ID*/
40 #define PCI_ULI5263_ID  0x526310B9	/* ULi M5263 ID*/
41 
42 #define ULI526X_IO_SIZE 0x100
43 #define TX_DESC_CNT     0x20            /* Allocated Tx descriptors */
44 #define RX_DESC_CNT     0x30            /* Allocated Rx descriptors */
45 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2)	/* Max TX packet count */
46 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3)	/* TX wakeup count */
47 #define DESC_ALL_CNT    (TX_DESC_CNT + RX_DESC_CNT)
48 #define TX_BUF_ALLOC    0x600
49 #define RX_ALLOC_SIZE   0x620
50 #define ULI526X_RESET    1
51 #define CR0_DEFAULT     0
52 #define CR6_DEFAULT     0x22200000
53 #define CR7_DEFAULT     0x180c1
54 #define CR15_DEFAULT    0x06            /* TxJabber RxWatchdog */
55 #define TDES0_ERR_MASK  0x4302          /* TXJT, LC, EC, FUE */
56 #define MAX_PACKET_SIZE 1514
57 #define ULI5261_MAX_MULTICAST 14
58 #define RX_COPY_SIZE	100
59 #define MAX_CHECK_PACKET 0x8000
60 
61 #define ULI526X_10MHF      0
62 #define ULI526X_100MHF     1
63 #define ULI526X_10MFD      4
64 #define ULI526X_100MFD     5
65 #define ULI526X_AUTO       8
66 
67 #define ULI526X_TXTH_72	0x400000	/* TX TH 72 byte */
68 #define ULI526X_TXTH_96	0x404000	/* TX TH 96 byte */
69 #define ULI526X_TXTH_128	0x0000		/* TX TH 128 byte */
70 #define ULI526X_TXTH_256	0x4000		/* TX TH 256 byte */
71 #define ULI526X_TXTH_512	0x8000		/* TX TH 512 byte */
72 #define ULI526X_TXTH_1K	0xC000		/* TX TH 1K  byte */
73 
74 #define ULI526X_TIMER_WUT  (jiffies + HZ * 1)/* timer wakeup time : 1 second */
75 #define ULI526X_TX_TIMEOUT ((16*HZ)/2)	/* tx packet time-out time 8 s" */
76 #define ULI526X_TX_KICK 	(4*HZ/2)	/* tx packet Kick-out time 2 s" */
77 
78 #define ULI526X_DBUG(dbug_now, msg, value)			\
79 do {								\
80 	if (uli526x_debug || (dbug_now))			\
81 		pr_err("%s %lx\n", (msg), (long) (value));	\
82 } while (0)
83 
84 #define SHOW_MEDIA_TYPE(mode)					\
85 	pr_err("Change Speed to %sMhz %s duplex\n",		\
86 	       mode & 1 ? "100" : "10",				\
87 	       mode & 4 ? "full" : "half");
88 
89 
90 /* CR9 definition: SROM/MII */
91 #define CR9_SROM_READ   0x4800
92 #define CR9_SRCS        0x1
93 #define CR9_SRCLK       0x2
94 #define CR9_CRDOUT      0x8
95 #define SROM_DATA_0     0x0
96 #define SROM_DATA_1     0x4
97 #define PHY_DATA_1      0x20000
98 #define PHY_DATA_0      0x00000
99 #define MDCLKH          0x10000
100 
101 #define PHY_POWER_DOWN	0x800
102 
103 #define SROM_V41_CODE   0x14
104 
105 /* Structure/enum declaration ------------------------------- */
106 struct tx_desc {
107         __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
108         char *tx_buf_ptr;               /* Data for us */
109         struct tx_desc *next_tx_desc;
110 } __attribute__(( aligned(32) ));
111 
112 struct rx_desc {
113 	__le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
114 	struct sk_buff *rx_skb_ptr;	/* Data for us */
115 	struct rx_desc *next_rx_desc;
116 } __attribute__(( aligned(32) ));
117 
118 struct uli526x_board_info {
119 	struct uli_phy_ops {
120 		void (*write)(struct uli526x_board_info *, u8, u8, u16);
121 		u16 (*read)(struct uli526x_board_info *, u8, u8);
122 	} phy;
123 	struct net_device *next_dev;	/* next device */
124 	struct pci_dev *pdev;		/* PCI device */
125 	spinlock_t lock;
126 
127 	void __iomem *ioaddr;		/* I/O base address */
128 	u32 cr0_data;
129 	u32 cr5_data;
130 	u32 cr6_data;
131 	u32 cr7_data;
132 	u32 cr15_data;
133 
134 	/* pointer for memory physical address */
135 	dma_addr_t buf_pool_dma_ptr;	/* Tx buffer pool memory */
136 	dma_addr_t buf_pool_dma_start;	/* Tx buffer pool align dword */
137 	dma_addr_t desc_pool_dma_ptr;	/* descriptor pool memory */
138 	dma_addr_t first_tx_desc_dma;
139 	dma_addr_t first_rx_desc_dma;
140 
141 	/* descriptor pointer */
142 	unsigned char *buf_pool_ptr;	/* Tx buffer pool memory */
143 	unsigned char *buf_pool_start;	/* Tx buffer pool align dword */
144 	unsigned char *desc_pool_ptr;	/* descriptor pool memory */
145 	struct tx_desc *first_tx_desc;
146 	struct tx_desc *tx_insert_ptr;
147 	struct tx_desc *tx_remove_ptr;
148 	struct rx_desc *first_rx_desc;
149 	struct rx_desc *rx_insert_ptr;
150 	struct rx_desc *rx_ready_ptr;	/* packet come pointer */
151 	unsigned long tx_packet_cnt;	/* transmitted packet count */
152 	unsigned long rx_avail_cnt;	/* available rx descriptor count */
153 	unsigned long interval_rx_cnt;	/* rx packet count a callback time */
154 
155 	u16 dbug_cnt;
156 	u16 NIC_capability;		/* NIC media capability */
157 	u16 PHY_reg4;			/* Saved Phyxcer register 4 value */
158 
159 	u8 media_mode;			/* user specify media mode */
160 	u8 op_mode;			/* real work media mode */
161 	u8 phy_addr;
162 	u8 link_failed;			/* Ever link failed */
163 	u8 wait_reset;			/* Hardware failed, need to reset */
164 	struct timer_list timer;
165 
166 	/* Driver defined statistic counter */
167 	unsigned long tx_fifo_underrun;
168 	unsigned long tx_loss_carrier;
169 	unsigned long tx_no_carrier;
170 	unsigned long tx_late_collision;
171 	unsigned long tx_excessive_collision;
172 	unsigned long tx_jabber_timeout;
173 	unsigned long reset_count;
174 	unsigned long reset_cr8;
175 	unsigned long reset_fatal;
176 	unsigned long reset_TXtimeout;
177 
178 	/* NIC SROM data */
179 	unsigned char srom[128];
180 	u8 init;
181 };
182 
183 enum uli526x_offsets {
184 	DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
185 	DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
186 	DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
187 	DCR15 = 0x78
188 };
189 
190 enum uli526x_CR6_bits {
191 	CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
192 	CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
193 	CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
194 };
195 
196 /* Global variable declaration ----------------------------- */
197 static int uli526x_debug;
198 static unsigned char uli526x_media_mode = ULI526X_AUTO;
199 static u32 uli526x_cr6_user_set;
200 
201 /* For module input parameter */
202 static int debug;
203 static u32 cr6set;
204 static int mode = 8;
205 
206 /* function declaration ------------------------------------- */
207 static int uli526x_open(struct net_device *);
208 static netdev_tx_t uli526x_start_xmit(struct sk_buff *,
209 					    struct net_device *);
210 static int uli526x_stop(struct net_device *);
211 static void uli526x_set_filter_mode(struct net_device *);
212 static const struct ethtool_ops netdev_ethtool_ops;
213 static u16 read_srom_word(struct uli526x_board_info *, int);
214 static irqreturn_t uli526x_interrupt(int, void *);
215 #ifdef CONFIG_NET_POLL_CONTROLLER
216 static void uli526x_poll(struct net_device *dev);
217 #endif
218 static void uli526x_descriptor_init(struct net_device *, void __iomem *);
219 static void allocate_rx_buffer(struct net_device *);
220 static void update_cr6(u32, void __iomem *);
221 static void send_filter_frame(struct net_device *, int);
222 static u16 phy_readby_cr9(struct uli526x_board_info *, u8, u8);
223 static u16 phy_readby_cr10(struct uli526x_board_info *, u8, u8);
224 static void phy_writeby_cr9(struct uli526x_board_info *, u8, u8, u16);
225 static void phy_writeby_cr10(struct uli526x_board_info *, u8, u8, u16);
226 static void phy_write_1bit(struct uli526x_board_info *db, u32);
227 static u16 phy_read_1bit(struct uli526x_board_info *db);
228 static u8 uli526x_sense_speed(struct uli526x_board_info *);
229 static void uli526x_process_mode(struct uli526x_board_info *);
230 static void uli526x_timer(struct timer_list *t);
231 static void uli526x_rx_packet(struct net_device *, struct uli526x_board_info *);
232 static void uli526x_free_tx_pkt(struct net_device *, struct uli526x_board_info *);
233 static void uli526x_reuse_skb(struct uli526x_board_info *, struct sk_buff *);
234 static void uli526x_dynamic_reset(struct net_device *);
235 static void uli526x_free_rxbuffer(struct uli526x_board_info *);
236 static void uli526x_init(struct net_device *);
237 static void uli526x_set_phyxcer(struct uli526x_board_info *);
238 
239 static void srom_clk_write(struct uli526x_board_info *db, u32 data)
240 {
241 	void __iomem *ioaddr = db->ioaddr;
242 
243 	uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS);
244 	udelay(5);
245 	uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);
246 	udelay(5);
247 	uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS);
248 	udelay(5);
249 }
250 
251 /* ULI526X network board routine ---------------------------- */
252 
253 static const struct net_device_ops netdev_ops = {
254 	.ndo_open		= uli526x_open,
255 	.ndo_stop		= uli526x_stop,
256 	.ndo_start_xmit		= uli526x_start_xmit,
257 	.ndo_set_rx_mode	= uli526x_set_filter_mode,
258 	.ndo_set_mac_address	= eth_mac_addr,
259 	.ndo_validate_addr	= eth_validate_addr,
260 #ifdef CONFIG_NET_POLL_CONTROLLER
261 	.ndo_poll_controller 	= uli526x_poll,
262 #endif
263 };
264 
265 /*
266  *	Search ULI526X board, allocate space and register it
267  */
268 
269 static int uli526x_init_one(struct pci_dev *pdev,
270 			    const struct pci_device_id *ent)
271 {
272 	struct uli526x_board_info *db;	/* board information structure */
273 	struct net_device *dev;
274 	void __iomem *ioaddr;
275 	u8 addr[ETH_ALEN];
276 	int i, err;
277 
278 	ULI526X_DBUG(0, "uli526x_init_one()", 0);
279 
280 	/* Init network device */
281 	dev = alloc_etherdev(sizeof(*db));
282 	if (dev == NULL)
283 		return -ENOMEM;
284 	SET_NETDEV_DEV(dev, &pdev->dev);
285 
286 	if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
287 		pr_warn("32-bit PCI DMA not available\n");
288 		err = -ENODEV;
289 		goto err_out_free;
290 	}
291 
292 	/* Enable Master/IO access, Disable memory access */
293 	err = pci_enable_device(pdev);
294 	if (err)
295 		goto err_out_free;
296 
297 	if (!pci_resource_start(pdev, 0)) {
298 		pr_err("I/O base is zero\n");
299 		err = -ENODEV;
300 		goto err_out_disable;
301 	}
302 
303 	if (pci_resource_len(pdev, 0) < (ULI526X_IO_SIZE) ) {
304 		pr_err("Allocated I/O size too small\n");
305 		err = -ENODEV;
306 		goto err_out_disable;
307 	}
308 
309 	err = pci_request_regions(pdev, DRV_NAME);
310 	if (err < 0) {
311 		pr_err("Failed to request PCI regions\n");
312 		goto err_out_disable;
313 	}
314 
315 	/* Init system & device */
316 	db = netdev_priv(dev);
317 
318 	/* Allocate Tx/Rx descriptor memory */
319 	err = -ENOMEM;
320 
321 	db->desc_pool_ptr = dma_alloc_coherent(&pdev->dev,
322 					       sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
323 					       &db->desc_pool_dma_ptr, GFP_KERNEL);
324 	if (!db->desc_pool_ptr)
325 		goto err_out_release;
326 
327 	db->buf_pool_ptr = dma_alloc_coherent(&pdev->dev,
328 					      TX_BUF_ALLOC * TX_DESC_CNT + 4,
329 					      &db->buf_pool_dma_ptr, GFP_KERNEL);
330 	if (!db->buf_pool_ptr)
331 		goto err_out_free_tx_desc;
332 
333 	db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
334 	db->first_tx_desc_dma = db->desc_pool_dma_ptr;
335 	db->buf_pool_start = db->buf_pool_ptr;
336 	db->buf_pool_dma_start = db->buf_pool_dma_ptr;
337 
338 	switch (ent->driver_data) {
339 	case PCI_ULI5263_ID:
340 		db->phy.write	= phy_writeby_cr10;
341 		db->phy.read	= phy_readby_cr10;
342 		break;
343 	default:
344 		db->phy.write	= phy_writeby_cr9;
345 		db->phy.read	= phy_readby_cr9;
346 		break;
347 	}
348 
349 	/* IO region. */
350 	ioaddr = pci_iomap(pdev, 0, 0);
351 	if (!ioaddr)
352 		goto err_out_free_tx_buf;
353 
354 	db->ioaddr = ioaddr;
355 	db->pdev = pdev;
356 	db->init = 1;
357 
358 	pci_set_drvdata(pdev, dev);
359 
360 	/* Register some necessary functions */
361 	dev->netdev_ops = &netdev_ops;
362 	dev->ethtool_ops = &netdev_ethtool_ops;
363 
364 	spin_lock_init(&db->lock);
365 
366 
367 	/* read 64 word srom data */
368 	for (i = 0; i < 64; i++)
369 		((__le16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db, i));
370 
371 	/* Set Node address */
372 	if(((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0)		/* SROM absent, so read MAC address from ID Table */
373 	{
374 		uw32(DCR0, 0x10000);	//Diagnosis mode
375 		uw32(DCR13, 0x1c0);	//Reset dianostic pointer port
376 		uw32(DCR14, 0);		//Clear reset port
377 		uw32(DCR14, 0x10);	//Reset ID Table pointer
378 		uw32(DCR14, 0);		//Clear reset port
379 		uw32(DCR13, 0);		//Clear CR13
380 		uw32(DCR13, 0x1b0);	//Select ID Table access port
381 		//Read MAC address from CR14
382 		for (i = 0; i < 6; i++)
383 			addr[i] = ur32(DCR14);
384 		//Read end
385 		uw32(DCR13, 0);		//Clear CR13
386 		uw32(DCR0, 0);		//Clear CR0
387 		udelay(10);
388 	}
389 	else		/*Exist SROM*/
390 	{
391 		for (i = 0; i < 6; i++)
392 			addr[i] = db->srom[20 + i];
393 	}
394 	eth_hw_addr_set(dev, addr);
395 
396 	err = register_netdev (dev);
397 	if (err)
398 		goto err_out_unmap;
399 
400 	netdev_info(dev, "ULi M%04lx at pci%s, %pM, irq %d\n",
401 		    ent->driver_data >> 16, pci_name(pdev),
402 		    dev->dev_addr, pdev->irq);
403 
404 	pci_set_master(pdev);
405 
406 	return 0;
407 
408 err_out_unmap:
409 	pci_iounmap(pdev, db->ioaddr);
410 err_out_free_tx_buf:
411 	dma_free_coherent(&pdev->dev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
412 			  db->buf_pool_ptr, db->buf_pool_dma_ptr);
413 err_out_free_tx_desc:
414 	dma_free_coherent(&pdev->dev,
415 			  sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
416 			  db->desc_pool_ptr, db->desc_pool_dma_ptr);
417 err_out_release:
418 	pci_release_regions(pdev);
419 err_out_disable:
420 	pci_disable_device(pdev);
421 err_out_free:
422 	free_netdev(dev);
423 
424 	return err;
425 }
426 
427 
428 static void uli526x_remove_one(struct pci_dev *pdev)
429 {
430 	struct net_device *dev = pci_get_drvdata(pdev);
431 	struct uli526x_board_info *db = netdev_priv(dev);
432 
433 	unregister_netdev(dev);
434 	pci_iounmap(pdev, db->ioaddr);
435 	dma_free_coherent(&db->pdev->dev,
436 			  sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
437 			  db->desc_pool_ptr, db->desc_pool_dma_ptr);
438 	dma_free_coherent(&db->pdev->dev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
439 			  db->buf_pool_ptr, db->buf_pool_dma_ptr);
440 	pci_release_regions(pdev);
441 	pci_disable_device(pdev);
442 	free_netdev(dev);
443 }
444 
445 
446 /*
447  *	Open the interface.
448  *	The interface is opened whenever "ifconfig" activates it.
449  */
450 
451 static int uli526x_open(struct net_device *dev)
452 {
453 	int ret;
454 	struct uli526x_board_info *db = netdev_priv(dev);
455 
456 	ULI526X_DBUG(0, "uli526x_open", 0);
457 
458 	/* system variable init */
459 	db->cr6_data = CR6_DEFAULT | uli526x_cr6_user_set;
460 	db->tx_packet_cnt = 0;
461 	db->rx_avail_cnt = 0;
462 	db->link_failed = 1;
463 	netif_carrier_off(dev);
464 	db->wait_reset = 0;
465 
466 	db->NIC_capability = 0xf;	/* All capability*/
467 	db->PHY_reg4 = 0x1e0;
468 
469 	/* CR6 operation mode decision */
470 	db->cr6_data |= ULI526X_TXTH_256;
471 	db->cr0_data = CR0_DEFAULT;
472 
473 	/* Initialize ULI526X board */
474 	uli526x_init(dev);
475 
476 	ret = request_irq(db->pdev->irq, uli526x_interrupt, IRQF_SHARED,
477 			  dev->name, dev);
478 	if (ret)
479 		return ret;
480 
481 	/* Active System Interface */
482 	netif_wake_queue(dev);
483 
484 	/* set and active a timer process */
485 	timer_setup(&db->timer, uli526x_timer, 0);
486 	db->timer.expires = ULI526X_TIMER_WUT + HZ * 2;
487 	add_timer(&db->timer);
488 
489 	return 0;
490 }
491 
492 
493 /*	Initialize ULI526X board
494  *	Reset ULI526X board
495  *	Initialize TX/Rx descriptor chain structure
496  *	Send the set-up frame
497  *	Enable Tx/Rx machine
498  */
499 
500 static void uli526x_init(struct net_device *dev)
501 {
502 	struct uli526x_board_info *db = netdev_priv(dev);
503 	struct uli_phy_ops *phy = &db->phy;
504 	void __iomem *ioaddr = db->ioaddr;
505 	u8	phy_tmp;
506 	u8	timeout;
507 	u16 phy_reg_reset;
508 
509 
510 	ULI526X_DBUG(0, "uli526x_init()", 0);
511 
512 	/* Reset M526x MAC controller */
513 	uw32(DCR0, ULI526X_RESET);	/* RESET MAC */
514 	udelay(100);
515 	uw32(DCR0, db->cr0_data);
516 	udelay(5);
517 
518 	/* Phy addr : In some boards,M5261/M5263 phy address != 1 */
519 	db->phy_addr = 1;
520 	for (phy_tmp = 0; phy_tmp < 32; phy_tmp++) {
521 		u16 phy_value;
522 
523 		phy_value = phy->read(db, phy_tmp, 3);	//peer add
524 		if (phy_value != 0xffff && phy_value != 0) {
525 			db->phy_addr = phy_tmp;
526 			break;
527 		}
528 	}
529 
530 	if (phy_tmp == 32)
531 		pr_warn("Can not find the phy address!!!\n");
532 	/* Parser SROM and media mode */
533 	db->media_mode = uli526x_media_mode;
534 
535 	/* phyxcer capability setting */
536 	phy_reg_reset = phy->read(db, db->phy_addr, 0);
537 	phy_reg_reset = (phy_reg_reset | 0x8000);
538 	phy->write(db, db->phy_addr, 0, phy_reg_reset);
539 
540 	/* See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management
541 	 * functions") or phy data sheet for details on phy reset
542 	 */
543 	udelay(500);
544 	timeout = 10;
545 	while (timeout-- && phy->read(db, db->phy_addr, 0) & 0x8000)
546 		udelay(100);
547 
548 	/* Process Phyxcer Media Mode */
549 	uli526x_set_phyxcer(db);
550 
551 	/* Media Mode Process */
552 	if ( !(db->media_mode & ULI526X_AUTO) )
553 		db->op_mode = db->media_mode;		/* Force Mode */
554 
555 	/* Initialize Transmit/Receive descriptor and CR3/4 */
556 	uli526x_descriptor_init(dev, ioaddr);
557 
558 	/* Init CR6 to program M526X operation */
559 	update_cr6(db->cr6_data, ioaddr);
560 
561 	/* Send setup frame */
562 	send_filter_frame(dev, netdev_mc_count(dev));	/* M5261/M5263 */
563 
564 	/* Init CR7, interrupt active bit */
565 	db->cr7_data = CR7_DEFAULT;
566 	uw32(DCR7, db->cr7_data);
567 
568 	/* Init CR15, Tx jabber and Rx watchdog timer */
569 	uw32(DCR15, db->cr15_data);
570 
571 	/* Enable ULI526X Tx/Rx function */
572 	db->cr6_data |= CR6_RXSC | CR6_TXSC;
573 	update_cr6(db->cr6_data, ioaddr);
574 }
575 
576 
577 /*
578  *	Hardware start transmission.
579  *	Send a packet to media from the upper layer.
580  */
581 
582 static netdev_tx_t uli526x_start_xmit(struct sk_buff *skb,
583 					    struct net_device *dev)
584 {
585 	struct uli526x_board_info *db = netdev_priv(dev);
586 	void __iomem *ioaddr = db->ioaddr;
587 	struct tx_desc *txptr;
588 	unsigned long flags;
589 
590 	ULI526X_DBUG(0, "uli526x_start_xmit", 0);
591 
592 	/* Resource flag check */
593 	netif_stop_queue(dev);
594 
595 	/* Too large packet check */
596 	if (skb->len > MAX_PACKET_SIZE) {
597 		netdev_err(dev, "big packet = %d\n", (u16)skb->len);
598 		dev_kfree_skb_any(skb);
599 		return NETDEV_TX_OK;
600 	}
601 
602 	spin_lock_irqsave(&db->lock, flags);
603 
604 	/* No Tx resource check, it never happen nromally */
605 	if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
606 		spin_unlock_irqrestore(&db->lock, flags);
607 		netdev_err(dev, "No Tx resource %ld\n", db->tx_packet_cnt);
608 		return NETDEV_TX_BUSY;
609 	}
610 
611 	/* Disable NIC interrupt */
612 	uw32(DCR7, 0);
613 
614 	/* transmit this packet */
615 	txptr = db->tx_insert_ptr;
616 	skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
617 	txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
618 
619 	/* Point to next transmit free descriptor */
620 	db->tx_insert_ptr = txptr->next_tx_desc;
621 
622 	/* Transmit Packet Process */
623 	if (db->tx_packet_cnt < TX_DESC_CNT) {
624 		txptr->tdes0 = cpu_to_le32(0x80000000);	/* Set owner bit */
625 		db->tx_packet_cnt++;			/* Ready to send */
626 		uw32(DCR1, 0x1);			/* Issue Tx polling */
627 		netif_trans_update(dev);		/* saved time stamp */
628 	}
629 
630 	/* Tx resource check */
631 	if ( db->tx_packet_cnt < TX_FREE_DESC_CNT )
632 		netif_wake_queue(dev);
633 
634 	/* Restore CR7 to enable interrupt */
635 	spin_unlock_irqrestore(&db->lock, flags);
636 	uw32(DCR7, db->cr7_data);
637 
638 	/* free this SKB */
639 	dev_consume_skb_any(skb);
640 
641 	return NETDEV_TX_OK;
642 }
643 
644 
645 /*
646  *	Stop the interface.
647  *	The interface is stopped when it is brought.
648  */
649 
650 static int uli526x_stop(struct net_device *dev)
651 {
652 	struct uli526x_board_info *db = netdev_priv(dev);
653 	void __iomem *ioaddr = db->ioaddr;
654 
655 	/* disable system */
656 	netif_stop_queue(dev);
657 
658 	/* deleted timer */
659 	del_timer_sync(&db->timer);
660 
661 	/* Reset & stop ULI526X board */
662 	uw32(DCR0, ULI526X_RESET);
663 	udelay(5);
664 	db->phy.write(db, db->phy_addr, 0, 0x8000);
665 
666 	/* free interrupt */
667 	free_irq(db->pdev->irq, dev);
668 
669 	/* free allocated rx buffer */
670 	uli526x_free_rxbuffer(db);
671 
672 	return 0;
673 }
674 
675 
676 /*
677  *	M5261/M5263 insterrupt handler
678  *	receive the packet to upper layer, free the transmitted packet
679  */
680 
681 static irqreturn_t uli526x_interrupt(int irq, void *dev_id)
682 {
683 	struct net_device *dev = dev_id;
684 	struct uli526x_board_info *db = netdev_priv(dev);
685 	void __iomem *ioaddr = db->ioaddr;
686 	unsigned long flags;
687 
688 	spin_lock_irqsave(&db->lock, flags);
689 	uw32(DCR7, 0);
690 
691 	/* Got ULI526X status */
692 	db->cr5_data = ur32(DCR5);
693 	uw32(DCR5, db->cr5_data);
694 	if ( !(db->cr5_data & 0x180c1) ) {
695 		/* Restore CR7 to enable interrupt mask */
696 		uw32(DCR7, db->cr7_data);
697 		spin_unlock_irqrestore(&db->lock, flags);
698 		return IRQ_HANDLED;
699 	}
700 
701 	/* Check system status */
702 	if (db->cr5_data & 0x2000) {
703 		/* system bus error happen */
704 		ULI526X_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
705 		db->reset_fatal++;
706 		db->wait_reset = 1;	/* Need to RESET */
707 		spin_unlock_irqrestore(&db->lock, flags);
708 		return IRQ_HANDLED;
709 	}
710 
711 	 /* Received the coming packet */
712 	if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
713 		uli526x_rx_packet(dev, db);
714 
715 	/* reallocate rx descriptor buffer */
716 	if (db->rx_avail_cnt<RX_DESC_CNT)
717 		allocate_rx_buffer(dev);
718 
719 	/* Free the transmitted descriptor */
720 	if ( db->cr5_data & 0x01)
721 		uli526x_free_tx_pkt(dev, db);
722 
723 	/* Restore CR7 to enable interrupt mask */
724 	uw32(DCR7, db->cr7_data);
725 
726 	spin_unlock_irqrestore(&db->lock, flags);
727 	return IRQ_HANDLED;
728 }
729 
730 #ifdef CONFIG_NET_POLL_CONTROLLER
731 static void uli526x_poll(struct net_device *dev)
732 {
733 	struct uli526x_board_info *db = netdev_priv(dev);
734 
735 	/* ISR grabs the irqsave lock, so this should be safe */
736 	uli526x_interrupt(db->pdev->irq, dev);
737 }
738 #endif
739 
740 /*
741  *	Free TX resource after TX complete
742  */
743 
744 static void uli526x_free_tx_pkt(struct net_device *dev,
745 				struct uli526x_board_info * db)
746 {
747 	struct tx_desc *txptr;
748 	u32 tdes0;
749 
750 	txptr = db->tx_remove_ptr;
751 	while(db->tx_packet_cnt) {
752 		tdes0 = le32_to_cpu(txptr->tdes0);
753 		if (tdes0 & 0x80000000)
754 			break;
755 
756 		/* A packet sent completed */
757 		db->tx_packet_cnt--;
758 		dev->stats.tx_packets++;
759 
760 		/* Transmit statistic counter */
761 		if ( tdes0 != 0x7fffffff ) {
762 			dev->stats.collisions += (tdes0 >> 3) & 0xf;
763 			dev->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
764 			if (tdes0 & TDES0_ERR_MASK) {
765 				dev->stats.tx_errors++;
766 				if (tdes0 & 0x0002) {	/* UnderRun */
767 					db->tx_fifo_underrun++;
768 					if ( !(db->cr6_data & CR6_SFT) ) {
769 						db->cr6_data = db->cr6_data | CR6_SFT;
770 						update_cr6(db->cr6_data, db->ioaddr);
771 					}
772 				}
773 				if (tdes0 & 0x0100)
774 					db->tx_excessive_collision++;
775 				if (tdes0 & 0x0200)
776 					db->tx_late_collision++;
777 				if (tdes0 & 0x0400)
778 					db->tx_no_carrier++;
779 				if (tdes0 & 0x0800)
780 					db->tx_loss_carrier++;
781 				if (tdes0 & 0x4000)
782 					db->tx_jabber_timeout++;
783 			}
784 		}
785 
786 		txptr = txptr->next_tx_desc;
787 	}/* End of while */
788 
789 	/* Update TX remove pointer to next */
790 	db->tx_remove_ptr = txptr;
791 
792 	/* Resource available check */
793 	if ( db->tx_packet_cnt < TX_WAKE_DESC_CNT )
794 		netif_wake_queue(dev);	/* Active upper layer, send again */
795 }
796 
797 
798 /*
799  *	Receive the come packet and pass to upper layer
800  */
801 
802 static void uli526x_rx_packet(struct net_device *dev, struct uli526x_board_info * db)
803 {
804 	struct rx_desc *rxptr;
805 	struct sk_buff *skb;
806 	int rxlen;
807 	u32 rdes0;
808 
809 	rxptr = db->rx_ready_ptr;
810 
811 	while(db->rx_avail_cnt) {
812 		rdes0 = le32_to_cpu(rxptr->rdes0);
813 		if (rdes0 & 0x80000000)	/* packet owner check */
814 		{
815 			break;
816 		}
817 
818 		db->rx_avail_cnt--;
819 		db->interval_rx_cnt++;
820 
821 		dma_unmap_single(&db->pdev->dev, le32_to_cpu(rxptr->rdes2),
822 				 RX_ALLOC_SIZE, DMA_FROM_DEVICE);
823 		if ( (rdes0 & 0x300) != 0x300) {
824 			/* A packet without First/Last flag */
825 			/* reuse this SKB */
826 			ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
827 			uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
828 		} else {
829 			/* A packet with First/Last flag */
830 			rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
831 
832 			/* error summary bit check */
833 			if (rdes0 & 0x8000) {
834 				/* This is a error packet */
835 				dev->stats.rx_errors++;
836 				if (rdes0 & 1)
837 					dev->stats.rx_fifo_errors++;
838 				if (rdes0 & 2)
839 					dev->stats.rx_crc_errors++;
840 				if (rdes0 & 0x80)
841 					dev->stats.rx_length_errors++;
842 			}
843 
844 			if ( !(rdes0 & 0x8000) ||
845 				((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
846 				struct sk_buff *new_skb = NULL;
847 
848 				skb = rxptr->rx_skb_ptr;
849 
850 				/* Good packet, send to upper layer */
851 				/* Shorst packet used new SKB */
852 				if ((rxlen < RX_COPY_SIZE) &&
853 				    (((new_skb = netdev_alloc_skb(dev, rxlen + 2)) != NULL))) {
854 					skb = new_skb;
855 					/* size less than COPY_SIZE, allocate a rxlen SKB */
856 					skb_reserve(skb, 2); /* 16byte align */
857 					skb_put_data(skb,
858 						     skb_tail_pointer(rxptr->rx_skb_ptr),
859 						     rxlen);
860 					uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
861 				} else
862 					skb_put(skb, rxlen);
863 
864 				skb->protocol = eth_type_trans(skb, dev);
865 				netif_rx(skb);
866 				dev->stats.rx_packets++;
867 				dev->stats.rx_bytes += rxlen;
868 
869 			} else {
870 				/* Reuse SKB buffer when the packet is error */
871 				ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
872 				uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
873 			}
874 		}
875 
876 		rxptr = rxptr->next_rx_desc;
877 	}
878 
879 	db->rx_ready_ptr = rxptr;
880 }
881 
882 
883 /*
884  * Set ULI526X multicast address
885  */
886 
887 static void uli526x_set_filter_mode(struct net_device * dev)
888 {
889 	struct uli526x_board_info *db = netdev_priv(dev);
890 	unsigned long flags;
891 
892 	ULI526X_DBUG(0, "uli526x_set_filter_mode()", 0);
893 	spin_lock_irqsave(&db->lock, flags);
894 
895 	if (dev->flags & IFF_PROMISC) {
896 		ULI526X_DBUG(0, "Enable PROM Mode", 0);
897 		db->cr6_data |= CR6_PM | CR6_PBF;
898 		update_cr6(db->cr6_data, db->ioaddr);
899 		spin_unlock_irqrestore(&db->lock, flags);
900 		return;
901 	}
902 
903 	if (dev->flags & IFF_ALLMULTI ||
904 	    netdev_mc_count(dev) > ULI5261_MAX_MULTICAST) {
905 		ULI526X_DBUG(0, "Pass all multicast address",
906 			     netdev_mc_count(dev));
907 		db->cr6_data &= ~(CR6_PM | CR6_PBF);
908 		db->cr6_data |= CR6_PAM;
909 		spin_unlock_irqrestore(&db->lock, flags);
910 		return;
911 	}
912 
913 	ULI526X_DBUG(0, "Set multicast address", netdev_mc_count(dev));
914 	send_filter_frame(dev, netdev_mc_count(dev)); 	/* M5261/M5263 */
915 	spin_unlock_irqrestore(&db->lock, flags);
916 }
917 
918 static void
919 ULi_ethtool_get_link_ksettings(struct uli526x_board_info *db,
920 			       struct ethtool_link_ksettings *cmd)
921 {
922 	u32 supported, advertising;
923 
924 	supported = (SUPPORTED_10baseT_Half |
925 	                   SUPPORTED_10baseT_Full |
926 	                   SUPPORTED_100baseT_Half |
927 	                   SUPPORTED_100baseT_Full |
928 	                   SUPPORTED_Autoneg |
929 	                   SUPPORTED_MII);
930 
931 	advertising = (ADVERTISED_10baseT_Half |
932 	                   ADVERTISED_10baseT_Full |
933 	                   ADVERTISED_100baseT_Half |
934 	                   ADVERTISED_100baseT_Full |
935 	                   ADVERTISED_Autoneg |
936 	                   ADVERTISED_MII);
937 
938 	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
939 						supported);
940 	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
941 						advertising);
942 
943 	cmd->base.port = PORT_MII;
944 	cmd->base.phy_address = db->phy_addr;
945 
946 	cmd->base.speed = SPEED_10;
947 	cmd->base.duplex = DUPLEX_HALF;
948 
949 	if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
950 	{
951 		cmd->base.speed = SPEED_100;
952 	}
953 	if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
954 	{
955 		cmd->base.duplex = DUPLEX_FULL;
956 	}
957 	if(db->link_failed)
958 	{
959 		cmd->base.speed = SPEED_UNKNOWN;
960 		cmd->base.duplex = DUPLEX_UNKNOWN;
961 	}
962 
963 	if (db->media_mode & ULI526X_AUTO)
964 	{
965 		cmd->base.autoneg = AUTONEG_ENABLE;
966 	}
967 }
968 
969 static void netdev_get_drvinfo(struct net_device *dev,
970 			       struct ethtool_drvinfo *info)
971 {
972 	struct uli526x_board_info *np = netdev_priv(dev);
973 
974 	strscpy(info->driver, DRV_NAME, sizeof(info->driver));
975 	strscpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info));
976 }
977 
978 static int netdev_get_link_ksettings(struct net_device *dev,
979 				     struct ethtool_link_ksettings *cmd)
980 {
981 	struct uli526x_board_info *np = netdev_priv(dev);
982 
983 	ULi_ethtool_get_link_ksettings(np, cmd);
984 
985 	return 0;
986 }
987 
988 static u32 netdev_get_link(struct net_device *dev) {
989 	struct uli526x_board_info *np = netdev_priv(dev);
990 
991 	if(np->link_failed)
992 		return 0;
993 	else
994 		return 1;
995 }
996 
997 static void uli526x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
998 {
999 	wol->supported = WAKE_PHY | WAKE_MAGIC;
1000 	wol->wolopts = 0;
1001 }
1002 
1003 static const struct ethtool_ops netdev_ethtool_ops = {
1004 	.get_drvinfo		= netdev_get_drvinfo,
1005 	.get_link		= netdev_get_link,
1006 	.get_wol		= uli526x_get_wol,
1007 	.get_link_ksettings	= netdev_get_link_ksettings,
1008 };
1009 
1010 /*
1011  *	A periodic timer routine
1012  *	Dynamic media sense, allocate Rx buffer...
1013  */
1014 
1015 static void uli526x_timer(struct timer_list *t)
1016 {
1017 	struct uli526x_board_info *db = from_timer(db, t, timer);
1018 	struct net_device *dev = pci_get_drvdata(db->pdev);
1019 	struct uli_phy_ops *phy = &db->phy;
1020 	void __iomem *ioaddr = db->ioaddr;
1021 	unsigned long flags;
1022 	u8 tmp_cr12 = 0;
1023 	u32 tmp_cr8;
1024 
1025 	//ULI526X_DBUG(0, "uli526x_timer()", 0);
1026 	spin_lock_irqsave(&db->lock, flags);
1027 
1028 
1029 	/* Dynamic reset ULI526X : system error or transmit time-out */
1030 	tmp_cr8 = ur32(DCR8);
1031 	if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1032 		db->reset_cr8++;
1033 		db->wait_reset = 1;
1034 	}
1035 	db->interval_rx_cnt = 0;
1036 
1037 	/* TX polling kick monitor */
1038 	if ( db->tx_packet_cnt &&
1039 	     time_after(jiffies, dev_trans_start(dev) + ULI526X_TX_KICK) ) {
1040 		uw32(DCR1, 0x1);   // Tx polling again
1041 
1042 		// TX Timeout
1043 		if ( time_after(jiffies, dev_trans_start(dev) + ULI526X_TX_TIMEOUT) ) {
1044 			db->reset_TXtimeout++;
1045 			db->wait_reset = 1;
1046 			netdev_err(dev, " Tx timeout - resetting\n");
1047 		}
1048 	}
1049 
1050 	if (db->wait_reset) {
1051 		ULI526X_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1052 		db->reset_count++;
1053 		uli526x_dynamic_reset(dev);
1054 		db->timer.expires = ULI526X_TIMER_WUT;
1055 		add_timer(&db->timer);
1056 		spin_unlock_irqrestore(&db->lock, flags);
1057 		return;
1058 	}
1059 
1060 	/* Link status check, Dynamic media type change */
1061 	if ((phy->read(db, db->phy_addr, 5) & 0x01e0)!=0)
1062 		tmp_cr12 = 3;
1063 
1064 	if ( !(tmp_cr12 & 0x3) && !db->link_failed ) {
1065 		/* Link Failed */
1066 		ULI526X_DBUG(0, "Link Failed", tmp_cr12);
1067 		netif_carrier_off(dev);
1068 		netdev_info(dev, "NIC Link is Down\n");
1069 		db->link_failed = 1;
1070 
1071 		/* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1072 		/* AUTO don't need */
1073 		if ( !(db->media_mode & 0x8) )
1074 			phy->write(db, db->phy_addr, 0, 0x1000);
1075 
1076 		/* AUTO mode, if INT phyxcer link failed, select EXT device */
1077 		if (db->media_mode & ULI526X_AUTO) {
1078 			db->cr6_data&=~0x00000200;	/* bit9=0, HD mode */
1079 			update_cr6(db->cr6_data, db->ioaddr);
1080 		}
1081 	} else
1082 		if ((tmp_cr12 & 0x3) && db->link_failed) {
1083 			ULI526X_DBUG(0, "Link link OK", tmp_cr12);
1084 			db->link_failed = 0;
1085 
1086 			/* Auto Sense Speed */
1087 			if ( (db->media_mode & ULI526X_AUTO) &&
1088 				uli526x_sense_speed(db) )
1089 				db->link_failed = 1;
1090 			uli526x_process_mode(db);
1091 
1092 			if(db->link_failed==0)
1093 			{
1094 				netdev_info(dev, "NIC Link is Up %d Mbps %s duplex\n",
1095 					    (db->op_mode == ULI526X_100MHF ||
1096 					     db->op_mode == ULI526X_100MFD)
1097 					    ? 100 : 10,
1098 					    (db->op_mode == ULI526X_10MFD ||
1099 					     db->op_mode == ULI526X_100MFD)
1100 					    ? "Full" : "Half");
1101 				netif_carrier_on(dev);
1102 			}
1103 			/* SHOW_MEDIA_TYPE(db->op_mode); */
1104 		}
1105 		else if(!(tmp_cr12 & 0x3) && db->link_failed)
1106 		{
1107 			if(db->init==1)
1108 			{
1109 				netdev_info(dev, "NIC Link is Down\n");
1110 				netif_carrier_off(dev);
1111 			}
1112 		}
1113 	db->init = 0;
1114 
1115 	/* Timer active again */
1116 	db->timer.expires = ULI526X_TIMER_WUT;
1117 	add_timer(&db->timer);
1118 	spin_unlock_irqrestore(&db->lock, flags);
1119 }
1120 
1121 
1122 /*
1123  *	Stop ULI526X board
1124  *	Free Tx/Rx allocated memory
1125  *	Init system variable
1126  */
1127 
1128 static void uli526x_reset_prepare(struct net_device *dev)
1129 {
1130 	struct uli526x_board_info *db = netdev_priv(dev);
1131 	void __iomem *ioaddr = db->ioaddr;
1132 
1133 	/* Sopt MAC controller */
1134 	db->cr6_data &= ~(CR6_RXSC | CR6_TXSC);	/* Disable Tx/Rx */
1135 	update_cr6(db->cr6_data, ioaddr);
1136 	uw32(DCR7, 0);				/* Disable Interrupt */
1137 	uw32(DCR5, ur32(DCR5));
1138 
1139 	/* Disable upper layer interface */
1140 	netif_stop_queue(dev);
1141 
1142 	/* Free Rx Allocate buffer */
1143 	uli526x_free_rxbuffer(db);
1144 
1145 	/* system variable init */
1146 	db->tx_packet_cnt = 0;
1147 	db->rx_avail_cnt = 0;
1148 	db->link_failed = 1;
1149 	db->init=1;
1150 	db->wait_reset = 0;
1151 }
1152 
1153 
1154 /*
1155  *	Dynamic reset the ULI526X board
1156  *	Stop ULI526X board
1157  *	Free Tx/Rx allocated memory
1158  *	Reset ULI526X board
1159  *	Re-initialize ULI526X board
1160  */
1161 
1162 static void uli526x_dynamic_reset(struct net_device *dev)
1163 {
1164 	ULI526X_DBUG(0, "uli526x_dynamic_reset()", 0);
1165 
1166 	uli526x_reset_prepare(dev);
1167 
1168 	/* Re-initialize ULI526X board */
1169 	uli526x_init(dev);
1170 
1171 	/* Restart upper layer interface */
1172 	netif_wake_queue(dev);
1173 }
1174 
1175 /*
1176  *	Suspend the interface.
1177  */
1178 
1179 static int __maybe_unused uli526x_suspend(struct device *dev_d)
1180 {
1181 	struct net_device *dev = dev_get_drvdata(dev_d);
1182 
1183 	ULI526X_DBUG(0, "uli526x_suspend", 0);
1184 
1185 	if (!netif_running(dev))
1186 		return 0;
1187 
1188 	netif_device_detach(dev);
1189 	uli526x_reset_prepare(dev);
1190 
1191 	device_set_wakeup_enable(dev_d, 0);
1192 
1193 	return 0;
1194 }
1195 
1196 /*
1197  *	Resume the interface.
1198  */
1199 
1200 static int __maybe_unused uli526x_resume(struct device *dev_d)
1201 {
1202 	struct net_device *dev = dev_get_drvdata(dev_d);
1203 
1204 	ULI526X_DBUG(0, "uli526x_resume", 0);
1205 
1206 
1207 	if (!netif_running(dev))
1208 		return 0;
1209 
1210 	netif_device_attach(dev);
1211 	/* Re-initialize ULI526X board */
1212 	uli526x_init(dev);
1213 	/* Restart upper layer interface */
1214 	netif_wake_queue(dev);
1215 
1216 	return 0;
1217 }
1218 
1219 /*
1220  *	free all allocated rx buffer
1221  */
1222 
1223 static void uli526x_free_rxbuffer(struct uli526x_board_info * db)
1224 {
1225 	ULI526X_DBUG(0, "uli526x_free_rxbuffer()", 0);
1226 
1227 	/* free allocated rx buffer */
1228 	while (db->rx_avail_cnt) {
1229 		dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1230 		db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1231 		db->rx_avail_cnt--;
1232 	}
1233 }
1234 
1235 
1236 /*
1237  *	Reuse the SK buffer
1238  */
1239 
1240 static void uli526x_reuse_skb(struct uli526x_board_info *db, struct sk_buff * skb)
1241 {
1242 	struct rx_desc *rxptr = db->rx_insert_ptr;
1243 
1244 	if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1245 		rxptr->rx_skb_ptr = skb;
1246 		rxptr->rdes2 = cpu_to_le32(dma_map_single(&db->pdev->dev, skb_tail_pointer(skb),
1247 							  RX_ALLOC_SIZE, DMA_FROM_DEVICE));
1248 		wmb();
1249 		rxptr->rdes0 = cpu_to_le32(0x80000000);
1250 		db->rx_avail_cnt++;
1251 		db->rx_insert_ptr = rxptr->next_rx_desc;
1252 	} else
1253 		ULI526X_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1254 }
1255 
1256 
1257 /*
1258  *	Initialize transmit/Receive descriptor
1259  *	Using Chain structure, and allocate Tx/Rx buffer
1260  */
1261 
1262 static void uli526x_descriptor_init(struct net_device *dev, void __iomem *ioaddr)
1263 {
1264 	struct uli526x_board_info *db = netdev_priv(dev);
1265 	struct tx_desc *tmp_tx;
1266 	struct rx_desc *tmp_rx;
1267 	unsigned char *tmp_buf;
1268 	dma_addr_t tmp_tx_dma, tmp_rx_dma;
1269 	dma_addr_t tmp_buf_dma;
1270 	int i;
1271 
1272 	ULI526X_DBUG(0, "uli526x_descriptor_init()", 0);
1273 
1274 	/* tx descriptor start pointer */
1275 	db->tx_insert_ptr = db->first_tx_desc;
1276 	db->tx_remove_ptr = db->first_tx_desc;
1277 	uw32(DCR4, db->first_tx_desc_dma);	/* TX DESC address */
1278 
1279 	/* rx descriptor start pointer */
1280 	db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT;
1281 	db->first_rx_desc_dma =  db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT;
1282 	db->rx_insert_ptr = db->first_rx_desc;
1283 	db->rx_ready_ptr = db->first_rx_desc;
1284 	uw32(DCR3, db->first_rx_desc_dma);	/* RX DESC address */
1285 
1286 	/* Init Transmit chain */
1287 	tmp_buf = db->buf_pool_start;
1288 	tmp_buf_dma = db->buf_pool_dma_start;
1289 	tmp_tx_dma = db->first_tx_desc_dma;
1290 	for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1291 		tmp_tx->tx_buf_ptr = tmp_buf;
1292 		tmp_tx->tdes0 = cpu_to_le32(0);
1293 		tmp_tx->tdes1 = cpu_to_le32(0x81000000);	/* IC, chain */
1294 		tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1295 		tmp_tx_dma += sizeof(struct tx_desc);
1296 		tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1297 		tmp_tx->next_tx_desc = tmp_tx + 1;
1298 		tmp_buf = tmp_buf + TX_BUF_ALLOC;
1299 		tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1300 	}
1301 	(--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1302 	tmp_tx->next_tx_desc = db->first_tx_desc;
1303 
1304 	 /* Init Receive descriptor chain */
1305 	tmp_rx_dma=db->first_rx_desc_dma;
1306 	for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1307 		tmp_rx->rdes0 = cpu_to_le32(0);
1308 		tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1309 		tmp_rx_dma += sizeof(struct rx_desc);
1310 		tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1311 		tmp_rx->next_rx_desc = tmp_rx + 1;
1312 	}
1313 	(--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1314 	tmp_rx->next_rx_desc = db->first_rx_desc;
1315 
1316 	/* pre-allocate Rx buffer */
1317 	allocate_rx_buffer(dev);
1318 }
1319 
1320 
1321 /*
1322  *	Update CR6 value
1323  *	Firstly stop ULI526X, then written value and start
1324  */
1325 static void update_cr6(u32 cr6_data, void __iomem *ioaddr)
1326 {
1327 	uw32(DCR6, cr6_data);
1328 	udelay(5);
1329 }
1330 
1331 
1332 /*
1333  *	Send a setup frame for M5261/M5263
1334  *	This setup frame initialize ULI526X address filter mode
1335  */
1336 
1337 #ifdef __BIG_ENDIAN
1338 #define FLT_SHIFT 16
1339 #else
1340 #define FLT_SHIFT 0
1341 #endif
1342 
1343 static void send_filter_frame(struct net_device *dev, int mc_cnt)
1344 {
1345 	struct uli526x_board_info *db = netdev_priv(dev);
1346 	void __iomem *ioaddr = db->ioaddr;
1347 	struct netdev_hw_addr *ha;
1348 	struct tx_desc *txptr;
1349 	const u16 * addrptr;
1350 	u32 * suptr;
1351 	int i;
1352 
1353 	ULI526X_DBUG(0, "send_filter_frame()", 0);
1354 
1355 	txptr = db->tx_insert_ptr;
1356 	suptr = (u32 *) txptr->tx_buf_ptr;
1357 
1358 	/* Node address */
1359 	addrptr = (const u16 *) dev->dev_addr;
1360 	*suptr++ = addrptr[0] << FLT_SHIFT;
1361 	*suptr++ = addrptr[1] << FLT_SHIFT;
1362 	*suptr++ = addrptr[2] << FLT_SHIFT;
1363 
1364 	/* broadcast address */
1365 	*suptr++ = 0xffff << FLT_SHIFT;
1366 	*suptr++ = 0xffff << FLT_SHIFT;
1367 	*suptr++ = 0xffff << FLT_SHIFT;
1368 
1369 	/* fit the multicast address */
1370 	netdev_for_each_mc_addr(ha, dev) {
1371 		addrptr = (u16 *) ha->addr;
1372 		*suptr++ = addrptr[0] << FLT_SHIFT;
1373 		*suptr++ = addrptr[1] << FLT_SHIFT;
1374 		*suptr++ = addrptr[2] << FLT_SHIFT;
1375 	}
1376 
1377 	for (i = netdev_mc_count(dev); i < 14; i++) {
1378 		*suptr++ = 0xffff << FLT_SHIFT;
1379 		*suptr++ = 0xffff << FLT_SHIFT;
1380 		*suptr++ = 0xffff << FLT_SHIFT;
1381 	}
1382 
1383 	/* prepare the setup frame */
1384 	db->tx_insert_ptr = txptr->next_tx_desc;
1385 	txptr->tdes1 = cpu_to_le32(0x890000c0);
1386 
1387 	/* Resource Check and Send the setup packet */
1388 	if (db->tx_packet_cnt < TX_DESC_CNT) {
1389 		/* Resource Empty */
1390 		db->tx_packet_cnt++;
1391 		txptr->tdes0 = cpu_to_le32(0x80000000);
1392 		update_cr6(db->cr6_data | 0x2000, ioaddr);
1393 		uw32(DCR1, 0x1);	/* Issue Tx polling */
1394 		update_cr6(db->cr6_data, ioaddr);
1395 		netif_trans_update(dev);
1396 	} else
1397 		netdev_err(dev, "No Tx resource - Send_filter_frame!\n");
1398 }
1399 
1400 
1401 /*
1402  *	Allocate rx buffer,
1403  *	As possible as allocate maxiumn Rx buffer
1404  */
1405 
1406 static void allocate_rx_buffer(struct net_device *dev)
1407 {
1408 	struct uli526x_board_info *db = netdev_priv(dev);
1409 	struct rx_desc *rxptr;
1410 	struct sk_buff *skb;
1411 
1412 	rxptr = db->rx_insert_ptr;
1413 
1414 	while(db->rx_avail_cnt < RX_DESC_CNT) {
1415 		skb = netdev_alloc_skb(dev, RX_ALLOC_SIZE);
1416 		if (skb == NULL)
1417 			break;
1418 		rxptr->rx_skb_ptr = skb; /* FIXME (?) */
1419 		rxptr->rdes2 = cpu_to_le32(dma_map_single(&db->pdev->dev, skb_tail_pointer(skb),
1420 							  RX_ALLOC_SIZE, DMA_FROM_DEVICE));
1421 		wmb();
1422 		rxptr->rdes0 = cpu_to_le32(0x80000000);
1423 		rxptr = rxptr->next_rx_desc;
1424 		db->rx_avail_cnt++;
1425 	}
1426 
1427 	db->rx_insert_ptr = rxptr;
1428 }
1429 
1430 
1431 /*
1432  *	Read one word data from the serial ROM
1433  */
1434 
1435 static u16 read_srom_word(struct uli526x_board_info *db, int offset)
1436 {
1437 	void __iomem *ioaddr = db->ioaddr;
1438 	u16 srom_data = 0;
1439 	int i;
1440 
1441 	uw32(DCR9, CR9_SROM_READ);
1442 	uw32(DCR9, CR9_SROM_READ | CR9_SRCS);
1443 
1444 	/* Send the Read Command 110b */
1445 	srom_clk_write(db, SROM_DATA_1);
1446 	srom_clk_write(db, SROM_DATA_1);
1447 	srom_clk_write(db, SROM_DATA_0);
1448 
1449 	/* Send the offset */
1450 	for (i = 5; i >= 0; i--) {
1451 		srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1452 		srom_clk_write(db, srom_data);
1453 	}
1454 
1455 	uw32(DCR9, CR9_SROM_READ | CR9_SRCS);
1456 
1457 	for (i = 16; i > 0; i--) {
1458 		uw32(DCR9, CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);
1459 		udelay(5);
1460 		srom_data = (srom_data << 1) |
1461 			    ((ur32(DCR9) & CR9_CRDOUT) ? 1 : 0);
1462 		uw32(DCR9, CR9_SROM_READ | CR9_SRCS);
1463 		udelay(5);
1464 	}
1465 
1466 	uw32(DCR9, CR9_SROM_READ);
1467 	return srom_data;
1468 }
1469 
1470 
1471 /*
1472  *	Auto sense the media mode
1473  */
1474 
1475 static u8 uli526x_sense_speed(struct uli526x_board_info * db)
1476 {
1477 	struct uli_phy_ops *phy = &db->phy;
1478 	u8 ErrFlag = 0;
1479 	u16 phy_mode;
1480 
1481 	phy_mode = phy->read(db, db->phy_addr, 1);
1482 	phy_mode = phy->read(db, db->phy_addr, 1);
1483 
1484 	if ( (phy_mode & 0x24) == 0x24 ) {
1485 
1486 		phy_mode = ((phy->read(db, db->phy_addr, 5) & 0x01e0)<<7);
1487 		if(phy_mode&0x8000)
1488 			phy_mode = 0x8000;
1489 		else if(phy_mode&0x4000)
1490 			phy_mode = 0x4000;
1491 		else if(phy_mode&0x2000)
1492 			phy_mode = 0x2000;
1493 		else
1494 			phy_mode = 0x1000;
1495 
1496 		switch (phy_mode) {
1497 		case 0x1000: db->op_mode = ULI526X_10MHF; break;
1498 		case 0x2000: db->op_mode = ULI526X_10MFD; break;
1499 		case 0x4000: db->op_mode = ULI526X_100MHF; break;
1500 		case 0x8000: db->op_mode = ULI526X_100MFD; break;
1501 		default: db->op_mode = ULI526X_10MHF; ErrFlag = 1; break;
1502 		}
1503 	} else {
1504 		db->op_mode = ULI526X_10MHF;
1505 		ULI526X_DBUG(0, "Link Failed :", phy_mode);
1506 		ErrFlag = 1;
1507 	}
1508 
1509 	return ErrFlag;
1510 }
1511 
1512 
1513 /*
1514  *	Set 10/100 phyxcer capability
1515  *	AUTO mode : phyxcer register4 is NIC capability
1516  *	Force mode: phyxcer register4 is the force media
1517  */
1518 
1519 static void uli526x_set_phyxcer(struct uli526x_board_info *db)
1520 {
1521 	struct uli_phy_ops *phy = &db->phy;
1522 	u16 phy_reg;
1523 
1524 	/* Phyxcer capability setting */
1525 	phy_reg = phy->read(db, db->phy_addr, 4) & ~0x01e0;
1526 
1527 	if (db->media_mode & ULI526X_AUTO) {
1528 		/* AUTO Mode */
1529 		phy_reg |= db->PHY_reg4;
1530 	} else {
1531 		/* Force Mode */
1532 		switch(db->media_mode) {
1533 		case ULI526X_10MHF: phy_reg |= 0x20; break;
1534 		case ULI526X_10MFD: phy_reg |= 0x40; break;
1535 		case ULI526X_100MHF: phy_reg |= 0x80; break;
1536 		case ULI526X_100MFD: phy_reg |= 0x100; break;
1537 		}
1538 
1539 	}
1540 
1541 	/* Write new capability to Phyxcer Reg4 */
1542 	if ( !(phy_reg & 0x01e0)) {
1543 		phy_reg|=db->PHY_reg4;
1544 		db->media_mode|=ULI526X_AUTO;
1545 	}
1546 	phy->write(db, db->phy_addr, 4, phy_reg);
1547 
1548 	/* Restart Auto-Negotiation */
1549 	phy->write(db, db->phy_addr, 0, 0x1200);
1550 	udelay(50);
1551 }
1552 
1553 
1554 /*
1555  *	Process op-mode
1556 	AUTO mode : PHY controller in Auto-negotiation Mode
1557  *	Force mode: PHY controller in force mode with HUB
1558  *			N-way force capability with SWITCH
1559  */
1560 
1561 static void uli526x_process_mode(struct uli526x_board_info *db)
1562 {
1563 	struct uli_phy_ops *phy = &db->phy;
1564 	u16 phy_reg;
1565 
1566 	/* Full Duplex Mode Check */
1567 	if (db->op_mode & 0x4)
1568 		db->cr6_data |= CR6_FDM;	/* Set Full Duplex Bit */
1569 	else
1570 		db->cr6_data &= ~CR6_FDM;	/* Clear Full Duplex Bit */
1571 
1572 	update_cr6(db->cr6_data, db->ioaddr);
1573 
1574 	/* 10/100M phyxcer force mode need */
1575 	if (!(db->media_mode & 0x8)) {
1576 		/* Forece Mode */
1577 		phy_reg = phy->read(db, db->phy_addr, 6);
1578 		if (!(phy_reg & 0x1)) {
1579 			/* parter without N-Way capability */
1580 			phy_reg = 0x0;
1581 			switch(db->op_mode) {
1582 			case ULI526X_10MHF: phy_reg = 0x0; break;
1583 			case ULI526X_10MFD: phy_reg = 0x100; break;
1584 			case ULI526X_100MHF: phy_reg = 0x2000; break;
1585 			case ULI526X_100MFD: phy_reg = 0x2100; break;
1586 			}
1587 			phy->write(db, db->phy_addr, 0, phy_reg);
1588 		}
1589 	}
1590 }
1591 
1592 
1593 /* M5261/M5263 Chip */
1594 static void phy_writeby_cr9(struct uli526x_board_info *db, u8 phy_addr,
1595 			    u8 offset, u16 phy_data)
1596 {
1597 	u16 i;
1598 
1599 	/* Send 33 synchronization clock to Phy controller */
1600 	for (i = 0; i < 35; i++)
1601 		phy_write_1bit(db, PHY_DATA_1);
1602 
1603 	/* Send start command(01) to Phy */
1604 	phy_write_1bit(db, PHY_DATA_0);
1605 	phy_write_1bit(db, PHY_DATA_1);
1606 
1607 	/* Send write command(01) to Phy */
1608 	phy_write_1bit(db, PHY_DATA_0);
1609 	phy_write_1bit(db, PHY_DATA_1);
1610 
1611 	/* Send Phy address */
1612 	for (i = 0x10; i > 0; i = i >> 1)
1613 		phy_write_1bit(db, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1614 
1615 	/* Send register address */
1616 	for (i = 0x10; i > 0; i = i >> 1)
1617 		phy_write_1bit(db, offset & i ? PHY_DATA_1 : PHY_DATA_0);
1618 
1619 	/* written trasnition */
1620 	phy_write_1bit(db, PHY_DATA_1);
1621 	phy_write_1bit(db, PHY_DATA_0);
1622 
1623 	/* Write a word data to PHY controller */
1624 	for (i = 0x8000; i > 0; i >>= 1)
1625 		phy_write_1bit(db, phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
1626 }
1627 
1628 static u16 phy_readby_cr9(struct uli526x_board_info *db, u8 phy_addr, u8 offset)
1629 {
1630 	u16 phy_data;
1631 	int i;
1632 
1633 	/* Send 33 synchronization clock to Phy controller */
1634 	for (i = 0; i < 35; i++)
1635 		phy_write_1bit(db, PHY_DATA_1);
1636 
1637 	/* Send start command(01) to Phy */
1638 	phy_write_1bit(db, PHY_DATA_0);
1639 	phy_write_1bit(db, PHY_DATA_1);
1640 
1641 	/* Send read command(10) to Phy */
1642 	phy_write_1bit(db, PHY_DATA_1);
1643 	phy_write_1bit(db, PHY_DATA_0);
1644 
1645 	/* Send Phy address */
1646 	for (i = 0x10; i > 0; i = i >> 1)
1647 		phy_write_1bit(db, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1648 
1649 	/* Send register address */
1650 	for (i = 0x10; i > 0; i = i >> 1)
1651 		phy_write_1bit(db, offset & i ? PHY_DATA_1 : PHY_DATA_0);
1652 
1653 	/* Skip transition state */
1654 	phy_read_1bit(db);
1655 
1656 	/* read 16bit data */
1657 	for (phy_data = 0, i = 0; i < 16; i++) {
1658 		phy_data <<= 1;
1659 		phy_data |= phy_read_1bit(db);
1660 	}
1661 
1662 	return phy_data;
1663 }
1664 
1665 static u16 phy_readby_cr10(struct uli526x_board_info *db, u8 phy_addr,
1666 			   u8 offset)
1667 {
1668 	void __iomem *ioaddr = db->ioaddr;
1669 	u32 cr10_value = phy_addr;
1670 
1671 	cr10_value = (cr10_value <<  5) + offset;
1672 	cr10_value = (cr10_value << 16) + 0x08000000;
1673 	uw32(DCR10, cr10_value);
1674 	udelay(1);
1675 	while (1) {
1676 		cr10_value = ur32(DCR10);
1677 		if (cr10_value & 0x10000000)
1678 			break;
1679 	}
1680 	return cr10_value & 0x0ffff;
1681 }
1682 
1683 static void phy_writeby_cr10(struct uli526x_board_info *db, u8 phy_addr,
1684 			     u8 offset, u16 phy_data)
1685 {
1686 	void __iomem *ioaddr = db->ioaddr;
1687 	u32 cr10_value = phy_addr;
1688 
1689 	cr10_value = (cr10_value <<  5) + offset;
1690 	cr10_value = (cr10_value << 16) + 0x04000000 + phy_data;
1691 	uw32(DCR10, cr10_value);
1692 	udelay(1);
1693 }
1694 /*
1695  *	Write one bit data to Phy Controller
1696  */
1697 
1698 static void phy_write_1bit(struct uli526x_board_info *db, u32 data)
1699 {
1700 	void __iomem *ioaddr = db->ioaddr;
1701 
1702 	uw32(DCR9, data);		/* MII Clock Low */
1703 	udelay(1);
1704 	uw32(DCR9, data | MDCLKH);	/* MII Clock High */
1705 	udelay(1);
1706 	uw32(DCR9, data);		/* MII Clock Low */
1707 	udelay(1);
1708 }
1709 
1710 
1711 /*
1712  *	Read one bit phy data from PHY controller
1713  */
1714 
1715 static u16 phy_read_1bit(struct uli526x_board_info *db)
1716 {
1717 	void __iomem *ioaddr = db->ioaddr;
1718 	u16 phy_data;
1719 
1720 	uw32(DCR9, 0x50000);
1721 	udelay(1);
1722 	phy_data = (ur32(DCR9) >> 19) & 0x1;
1723 	uw32(DCR9, 0x40000);
1724 	udelay(1);
1725 
1726 	return phy_data;
1727 }
1728 
1729 
1730 static const struct pci_device_id uli526x_pci_tbl[] = {
1731 	{ 0x10B9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5261_ID },
1732 	{ 0x10B9, 0x5263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5263_ID },
1733 	{ 0, }
1734 };
1735 MODULE_DEVICE_TABLE(pci, uli526x_pci_tbl);
1736 
1737 static SIMPLE_DEV_PM_OPS(uli526x_pm_ops, uli526x_suspend, uli526x_resume);
1738 
1739 static struct pci_driver uli526x_driver = {
1740 	.name		= "uli526x",
1741 	.id_table	= uli526x_pci_tbl,
1742 	.probe		= uli526x_init_one,
1743 	.remove		= uli526x_remove_one,
1744 	.driver.pm	= &uli526x_pm_ops,
1745 };
1746 
1747 MODULE_AUTHOR("Peer Chen, peer.chen@uli.com.tw");
1748 MODULE_DESCRIPTION("ULi M5261/M5263 fast ethernet driver");
1749 MODULE_LICENSE("GPL");
1750 
1751 module_param(debug, int, 0644);
1752 module_param(mode, int, 0);
1753 module_param(cr6set, int, 0);
1754 MODULE_PARM_DESC(debug, "ULi M5261/M5263 enable debugging (0-1)");
1755 MODULE_PARM_DESC(mode, "ULi M5261/M5263: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
1756 
1757 /*	Description:
1758  *	when user used insmod to add module, system invoked init_module()
1759  *	to register the services.
1760  */
1761 
1762 static int __init uli526x_init_module(void)
1763 {
1764 
1765 	ULI526X_DBUG(0, "init_module() ", debug);
1766 
1767 	if (debug)
1768 		uli526x_debug = debug;	/* set debug flag */
1769 	if (cr6set)
1770 		uli526x_cr6_user_set = cr6set;
1771 
1772 	switch (mode) {
1773 	case ULI526X_10MHF:
1774 	case ULI526X_100MHF:
1775 	case ULI526X_10MFD:
1776 	case ULI526X_100MFD:
1777 		uli526x_media_mode = mode;
1778 		break;
1779 	default:
1780 		uli526x_media_mode = ULI526X_AUTO;
1781 		break;
1782 	}
1783 
1784 	return pci_register_driver(&uli526x_driver);
1785 }
1786 
1787 
1788 /*
1789  *	Description:
1790  *	when user used rmmod to delete module, system invoked clean_module()
1791  *	to un-register all registered services.
1792  */
1793 
1794 static void __exit uli526x_cleanup_module(void)
1795 {
1796 	ULI526X_DBUG(0, "uli526x_cleanup_module() ", debug);
1797 	pci_unregister_driver(&uli526x_driver);
1798 }
1799 
1800 module_init(uli526x_init_module);
1801 module_exit(uli526x_cleanup_module);
1802