1a88394cfSJeff Kirsher /* 2a88394cfSJeff Kirsher drivers/net/tulip/tulip.h 3a88394cfSJeff Kirsher 4a88394cfSJeff Kirsher Copyright 2000,2001 The Linux Kernel Team 5a88394cfSJeff Kirsher Written/copyright 1994-2001 by Donald Becker. 6a88394cfSJeff Kirsher 7a88394cfSJeff Kirsher This software may be used and distributed according to the terms 8a88394cfSJeff Kirsher of the GNU General Public License, incorporated herein by reference. 9a88394cfSJeff Kirsher 10a88394cfSJeff Kirsher Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html} 11a88394cfSJeff Kirsher for more information on this driver. 12a88394cfSJeff Kirsher 13a88394cfSJeff Kirsher Please submit bugs to http://bugzilla.kernel.org/ . 14a88394cfSJeff Kirsher */ 15a88394cfSJeff Kirsher 16a88394cfSJeff Kirsher #ifndef __NET_TULIP_H__ 17a88394cfSJeff Kirsher #define __NET_TULIP_H__ 18a88394cfSJeff Kirsher 19a88394cfSJeff Kirsher #include <linux/kernel.h> 20a88394cfSJeff Kirsher #include <linux/types.h> 21a88394cfSJeff Kirsher #include <linux/spinlock.h> 22a88394cfSJeff Kirsher #include <linux/netdevice.h> 23a88394cfSJeff Kirsher #include <linux/ethtool.h> 24a88394cfSJeff Kirsher #include <linux/timer.h> 25a88394cfSJeff Kirsher #include <linux/delay.h> 26a88394cfSJeff Kirsher #include <linux/pci.h> 27a88394cfSJeff Kirsher #include <asm/io.h> 28a88394cfSJeff Kirsher #include <asm/irq.h> 29a88394cfSJeff Kirsher #include <asm/unaligned.h> 30a88394cfSJeff Kirsher 31a88394cfSJeff Kirsher 32a88394cfSJeff Kirsher 33a88394cfSJeff Kirsher /* undefine, or define to various debugging levels (>4 == obscene levels) */ 34a88394cfSJeff Kirsher #define TULIP_DEBUG 1 35a88394cfSJeff Kirsher 36a88394cfSJeff Kirsher #ifdef CONFIG_TULIP_MMIO 37a88394cfSJeff Kirsher #define TULIP_BAR 1 /* CBMA */ 38a88394cfSJeff Kirsher #else 39a88394cfSJeff Kirsher #define TULIP_BAR 0 /* CBIO */ 40a88394cfSJeff Kirsher #endif 41a88394cfSJeff Kirsher 42a88394cfSJeff Kirsher 43a88394cfSJeff Kirsher 44a88394cfSJeff Kirsher struct tulip_chip_table { 45a88394cfSJeff Kirsher char *chip_name; 46a88394cfSJeff Kirsher int io_size; 47a88394cfSJeff Kirsher int valid_intrs; /* CSR7 interrupt enable settings */ 48a88394cfSJeff Kirsher int flags; 49a88394cfSJeff Kirsher void (*media_timer) (unsigned long); 50a88394cfSJeff Kirsher work_func_t media_task; 51a88394cfSJeff Kirsher }; 52a88394cfSJeff Kirsher 53a88394cfSJeff Kirsher 54a88394cfSJeff Kirsher enum tbl_flag { 55a88394cfSJeff Kirsher HAS_MII = 0x00001, 56a88394cfSJeff Kirsher HAS_MEDIA_TABLE = 0x00002, 57a88394cfSJeff Kirsher CSR12_IN_SROM = 0x00004, 58a88394cfSJeff Kirsher ALWAYS_CHECK_MII = 0x00008, 59a88394cfSJeff Kirsher HAS_ACPI = 0x00010, 60a88394cfSJeff Kirsher MC_HASH_ONLY = 0x00020, /* Hash-only multicast filter. */ 61a88394cfSJeff Kirsher HAS_PNICNWAY = 0x00080, 62a88394cfSJeff Kirsher HAS_NWAY = 0x00040, /* Uses internal NWay xcvr. */ 63a88394cfSJeff Kirsher HAS_INTR_MITIGATION = 0x00100, 64a88394cfSJeff Kirsher IS_ASIX = 0x00200, 65a88394cfSJeff Kirsher HAS_8023X = 0x00400, 66a88394cfSJeff Kirsher COMET_MAC_ADDR = 0x00800, 67a88394cfSJeff Kirsher HAS_PCI_MWI = 0x01000, 68a88394cfSJeff Kirsher HAS_PHY_IRQ = 0x02000, 69a88394cfSJeff Kirsher HAS_SWAPPED_SEEPROM = 0x04000, 70a88394cfSJeff Kirsher NEEDS_FAKE_MEDIA_TABLE = 0x08000, 71a88394cfSJeff Kirsher COMET_PM = 0x10000, 72a88394cfSJeff Kirsher }; 73a88394cfSJeff Kirsher 74a88394cfSJeff Kirsher 75a88394cfSJeff Kirsher /* chip types. careful! order is VERY IMPORTANT here, as these 76a88394cfSJeff Kirsher * are used throughout the driver as indices into arrays */ 77a88394cfSJeff Kirsher /* Note 21142 == 21143. */ 78a88394cfSJeff Kirsher enum chips { 79a88394cfSJeff Kirsher DC21040 = 0, 80a88394cfSJeff Kirsher DC21041 = 1, 81a88394cfSJeff Kirsher DC21140 = 2, 82a88394cfSJeff Kirsher DC21142 = 3, DC21143 = 3, 83a88394cfSJeff Kirsher LC82C168, 84a88394cfSJeff Kirsher MX98713, 85a88394cfSJeff Kirsher MX98715, 86a88394cfSJeff Kirsher MX98725, 87a88394cfSJeff Kirsher AX88140, 88a88394cfSJeff Kirsher PNIC2, 89a88394cfSJeff Kirsher COMET, 90a88394cfSJeff Kirsher COMPEX9881, 91a88394cfSJeff Kirsher I21145, 92a88394cfSJeff Kirsher DM910X, 93a88394cfSJeff Kirsher CONEXANT, 94a88394cfSJeff Kirsher }; 95a88394cfSJeff Kirsher 96a88394cfSJeff Kirsher 97a88394cfSJeff Kirsher enum MediaIs { 98a88394cfSJeff Kirsher MediaIsFD = 1, 99a88394cfSJeff Kirsher MediaAlwaysFD = 2, 100a88394cfSJeff Kirsher MediaIsMII = 4, 101a88394cfSJeff Kirsher MediaIsFx = 8, 102a88394cfSJeff Kirsher MediaIs100 = 16 103a88394cfSJeff Kirsher }; 104a88394cfSJeff Kirsher 105a88394cfSJeff Kirsher 106a88394cfSJeff Kirsher /* Offsets to the Command and Status Registers, "CSRs". All accesses 107a88394cfSJeff Kirsher must be longword instructions and quadword aligned. */ 108a88394cfSJeff Kirsher enum tulip_offsets { 109a88394cfSJeff Kirsher CSR0 = 0, 110a88394cfSJeff Kirsher CSR1 = 0x08, 111a88394cfSJeff Kirsher CSR2 = 0x10, 112a88394cfSJeff Kirsher CSR3 = 0x18, 113a88394cfSJeff Kirsher CSR4 = 0x20, 114a88394cfSJeff Kirsher CSR5 = 0x28, 115a88394cfSJeff Kirsher CSR6 = 0x30, 116a88394cfSJeff Kirsher CSR7 = 0x38, 117a88394cfSJeff Kirsher CSR8 = 0x40, 118a88394cfSJeff Kirsher CSR9 = 0x48, 119a88394cfSJeff Kirsher CSR10 = 0x50, 120a88394cfSJeff Kirsher CSR11 = 0x58, 121a88394cfSJeff Kirsher CSR12 = 0x60, 122a88394cfSJeff Kirsher CSR13 = 0x68, 123a88394cfSJeff Kirsher CSR14 = 0x70, 124a88394cfSJeff Kirsher CSR15 = 0x78, 125a88394cfSJeff Kirsher CSR18 = 0x88, 126a88394cfSJeff Kirsher CSR19 = 0x8c, 127a88394cfSJeff Kirsher CSR20 = 0x90, 128a88394cfSJeff Kirsher CSR27 = 0xAC, 129a88394cfSJeff Kirsher CSR28 = 0xB0, 130a88394cfSJeff Kirsher }; 131a88394cfSJeff Kirsher 132a88394cfSJeff Kirsher /* register offset and bits for CFDD PCI config reg */ 133a88394cfSJeff Kirsher enum pci_cfg_driver_reg { 134a88394cfSJeff Kirsher CFDD = 0x40, 135a88394cfSJeff Kirsher CFDD_Sleep = (1 << 31), 136a88394cfSJeff Kirsher CFDD_Snooze = (1 << 30), 137a88394cfSJeff Kirsher }; 138a88394cfSJeff Kirsher 139a88394cfSJeff Kirsher #define RxPollInt (RxIntr|RxNoBuf|RxDied|RxJabber) 140a88394cfSJeff Kirsher 141a88394cfSJeff Kirsher /* The bits in the CSR5 status registers, mostly interrupt sources. */ 142a88394cfSJeff Kirsher enum status_bits { 143a88394cfSJeff Kirsher TimerInt = 0x800, 144a88394cfSJeff Kirsher SystemError = 0x2000, 145a88394cfSJeff Kirsher TPLnkFail = 0x1000, 146a88394cfSJeff Kirsher TPLnkPass = 0x10, 147a88394cfSJeff Kirsher NormalIntr = 0x10000, 148a88394cfSJeff Kirsher AbnormalIntr = 0x8000, 149a88394cfSJeff Kirsher RxJabber = 0x200, 150a88394cfSJeff Kirsher RxDied = 0x100, 151a88394cfSJeff Kirsher RxNoBuf = 0x80, 152a88394cfSJeff Kirsher RxIntr = 0x40, 153a88394cfSJeff Kirsher TxFIFOUnderflow = 0x20, 154a88394cfSJeff Kirsher RxErrIntr = 0x10, 155a88394cfSJeff Kirsher TxJabber = 0x08, 156a88394cfSJeff Kirsher TxNoBuf = 0x04, 157a88394cfSJeff Kirsher TxDied = 0x02, 158a88394cfSJeff Kirsher TxIntr = 0x01, 159a88394cfSJeff Kirsher }; 160a88394cfSJeff Kirsher 161a88394cfSJeff Kirsher /* bit mask for CSR5 TX/RX process state */ 162a88394cfSJeff Kirsher #define CSR5_TS 0x00700000 163a88394cfSJeff Kirsher #define CSR5_RS 0x000e0000 164a88394cfSJeff Kirsher 165a88394cfSJeff Kirsher enum tulip_mode_bits { 166a88394cfSJeff Kirsher TxThreshold = (1 << 22), 167a88394cfSJeff Kirsher FullDuplex = (1 << 9), 168a88394cfSJeff Kirsher TxOn = 0x2000, 169a88394cfSJeff Kirsher AcceptBroadcast = 0x0100, 170a88394cfSJeff Kirsher AcceptAllMulticast = 0x0080, 171a88394cfSJeff Kirsher AcceptAllPhys = 0x0040, 172a88394cfSJeff Kirsher AcceptRunt = 0x0008, 173a88394cfSJeff Kirsher RxOn = 0x0002, 174a88394cfSJeff Kirsher RxTx = (TxOn | RxOn), 175a88394cfSJeff Kirsher }; 176a88394cfSJeff Kirsher 177a88394cfSJeff Kirsher 178a88394cfSJeff Kirsher enum tulip_busconfig_bits { 179a88394cfSJeff Kirsher MWI = (1 << 24), 180a88394cfSJeff Kirsher MRL = (1 << 23), 181a88394cfSJeff Kirsher MRM = (1 << 21), 182a88394cfSJeff Kirsher CALShift = 14, 183a88394cfSJeff Kirsher BurstLenShift = 8, 184a88394cfSJeff Kirsher }; 185a88394cfSJeff Kirsher 186a88394cfSJeff Kirsher 187a88394cfSJeff Kirsher /* The Tulip Rx and Tx buffer descriptors. */ 188a88394cfSJeff Kirsher struct tulip_rx_desc { 189a88394cfSJeff Kirsher __le32 status; 190a88394cfSJeff Kirsher __le32 length; 191a88394cfSJeff Kirsher __le32 buffer1; 192a88394cfSJeff Kirsher __le32 buffer2; 193a88394cfSJeff Kirsher }; 194a88394cfSJeff Kirsher 195a88394cfSJeff Kirsher 196a88394cfSJeff Kirsher struct tulip_tx_desc { 197a88394cfSJeff Kirsher __le32 status; 198a88394cfSJeff Kirsher __le32 length; 199a88394cfSJeff Kirsher __le32 buffer1; 200a88394cfSJeff Kirsher __le32 buffer2; /* We use only buffer 1. */ 201a88394cfSJeff Kirsher }; 202a88394cfSJeff Kirsher 203a88394cfSJeff Kirsher 204a88394cfSJeff Kirsher enum desc_status_bits { 205a88394cfSJeff Kirsher DescOwned = 0x80000000, 206a88394cfSJeff Kirsher DescWholePkt = 0x60000000, 207a88394cfSJeff Kirsher DescEndPkt = 0x40000000, 208a88394cfSJeff Kirsher DescStartPkt = 0x20000000, 209a88394cfSJeff Kirsher DescEndRing = 0x02000000, 210a88394cfSJeff Kirsher DescUseLink = 0x01000000, 211a88394cfSJeff Kirsher 212a88394cfSJeff Kirsher /* 213a88394cfSJeff Kirsher * Error summary flag is logical or of 'CRC Error', 'Collision Seen', 214a88394cfSJeff Kirsher * 'Frame Too Long', 'Runt' and 'Descriptor Error' flags generated 215a88394cfSJeff Kirsher * within tulip chip. 216a88394cfSJeff Kirsher */ 217a88394cfSJeff Kirsher RxDescErrorSummary = 0x8000, 218a88394cfSJeff Kirsher RxDescCRCError = 0x0002, 219a88394cfSJeff Kirsher RxDescCollisionSeen = 0x0040, 220a88394cfSJeff Kirsher 221a88394cfSJeff Kirsher /* 222a88394cfSJeff Kirsher * 'Frame Too Long' flag is set if packet length including CRC exceeds 223a88394cfSJeff Kirsher * 1518. However, a full sized VLAN tagged frame is 1522 bytes 224a88394cfSJeff Kirsher * including CRC. 225a88394cfSJeff Kirsher * 226a88394cfSJeff Kirsher * The tulip chip does not block oversized frames, and if this flag is 227a88394cfSJeff Kirsher * set on a receive descriptor it does not indicate the frame has been 228a88394cfSJeff Kirsher * truncated. The receive descriptor also includes the actual length. 229a88394cfSJeff Kirsher * Therefore we can safety ignore this flag and check the length 230a88394cfSJeff Kirsher * ourselves. 231a88394cfSJeff Kirsher */ 232a88394cfSJeff Kirsher RxDescFrameTooLong = 0x0080, 233a88394cfSJeff Kirsher RxDescRunt = 0x0800, 234a88394cfSJeff Kirsher RxDescDescErr = 0x4000, 235a88394cfSJeff Kirsher RxWholePkt = 0x00000300, 236a88394cfSJeff Kirsher /* 237a88394cfSJeff Kirsher * Top three bits of 14 bit frame length (status bits 27-29) should 238a88394cfSJeff Kirsher * never be set as that would make frame over 2047 bytes. The Receive 239a88394cfSJeff Kirsher * Watchdog flag (bit 4) may indicate the length is over 2048 and the 240a88394cfSJeff Kirsher * length field is invalid. 241a88394cfSJeff Kirsher */ 242a88394cfSJeff Kirsher RxLengthOver2047 = 0x38000010 243a88394cfSJeff Kirsher }; 244a88394cfSJeff Kirsher 245a88394cfSJeff Kirsher 246a88394cfSJeff Kirsher enum t21143_csr6_bits { 247a88394cfSJeff Kirsher csr6_sc = (1<<31), 248a88394cfSJeff Kirsher csr6_ra = (1<<30), 249a88394cfSJeff Kirsher csr6_ign_dest_msb = (1<<26), 250a88394cfSJeff Kirsher csr6_mbo = (1<<25), 251a88394cfSJeff Kirsher csr6_scr = (1<<24), /* scramble mode flag: can't be set */ 252a88394cfSJeff Kirsher csr6_pcs = (1<<23), /* Enables PCS functions (symbol mode requires csr6_ps be set) default is set */ 253a88394cfSJeff Kirsher csr6_ttm = (1<<22), /* Transmit Threshold Mode, set for 10baseT, 0 for 100BaseTX */ 254a88394cfSJeff Kirsher csr6_sf = (1<<21), /* Store and forward. If set ignores TR bits */ 255a88394cfSJeff Kirsher csr6_hbd = (1<<19), /* Heart beat disable. Disables SQE function in 10baseT */ 256a88394cfSJeff Kirsher csr6_ps = (1<<18), /* Port Select. 0 (defualt) = 10baseT, 1 = 100baseTX: can't be set */ 257a88394cfSJeff Kirsher csr6_ca = (1<<17), /* Collision Offset Enable. If set uses special algorithm in low collision situations */ 258a88394cfSJeff Kirsher csr6_trh = (1<<15), /* Transmit Threshold high bit */ 259a88394cfSJeff Kirsher csr6_trl = (1<<14), /* Transmit Threshold low bit */ 260a88394cfSJeff Kirsher 261a88394cfSJeff Kirsher /*************************************************************** 262a88394cfSJeff Kirsher * This table shows transmit threshold values based on media * 263a88394cfSJeff Kirsher * and these two registers (from PNIC1 & 2 docs) Note: this is * 264a88394cfSJeff Kirsher * all meaningless if sf is set. * 265a88394cfSJeff Kirsher ***************************************************************/ 266a88394cfSJeff Kirsher 267a88394cfSJeff Kirsher /*********************************** 268a88394cfSJeff Kirsher * (trh,trl) * 100BaseTX * 10BaseT * 269a88394cfSJeff Kirsher *********************************** 270a88394cfSJeff Kirsher * (0,0) * 128 * 72 * 271a88394cfSJeff Kirsher * (0,1) * 256 * 96 * 272a88394cfSJeff Kirsher * (1,0) * 512 * 128 * 273a88394cfSJeff Kirsher * (1,1) * 1024 * 160 * 274a88394cfSJeff Kirsher ***********************************/ 275a88394cfSJeff Kirsher 276a88394cfSJeff Kirsher csr6_fc = (1<<12), /* Forces a collision in next transmission (for testing in loopback mode) */ 277a88394cfSJeff Kirsher csr6_om_int_loop = (1<<10), /* internal (FIFO) loopback flag */ 278a88394cfSJeff Kirsher csr6_om_ext_loop = (1<<11), /* external (PMD) loopback flag */ 279a88394cfSJeff Kirsher /* set both and you get (PHY) loopback */ 280a88394cfSJeff Kirsher csr6_fd = (1<<9), /* Full duplex mode, disables hearbeat, no loopback */ 281a88394cfSJeff Kirsher csr6_pm = (1<<7), /* Pass All Multicast */ 282a88394cfSJeff Kirsher csr6_pr = (1<<6), /* Promiscuous mode */ 283a88394cfSJeff Kirsher csr6_sb = (1<<5), /* Start(1)/Stop(0) backoff counter */ 284a88394cfSJeff Kirsher csr6_if = (1<<4), /* Inverse Filtering, rejects only addresses in address table: can't be set */ 285a88394cfSJeff Kirsher csr6_pb = (1<<3), /* Pass Bad Frames, (1) causes even bad frames to be passed on */ 286a88394cfSJeff Kirsher csr6_ho = (1<<2), /* Hash-only filtering mode: can't be set */ 287a88394cfSJeff Kirsher csr6_hp = (1<<0), /* Hash/Perfect Receive Filtering Mode: can't be set */ 288a88394cfSJeff Kirsher 289a88394cfSJeff Kirsher csr6_mask_capture = (csr6_sc | csr6_ca), 290a88394cfSJeff Kirsher csr6_mask_defstate = (csr6_mask_capture | csr6_mbo), 291a88394cfSJeff Kirsher csr6_mask_hdcap = (csr6_mask_defstate | csr6_hbd | csr6_ps), 292a88394cfSJeff Kirsher csr6_mask_hdcaptt = (csr6_mask_hdcap | csr6_trh | csr6_trl), 293a88394cfSJeff Kirsher csr6_mask_fullcap = (csr6_mask_hdcaptt | csr6_fd), 294a88394cfSJeff Kirsher csr6_mask_fullpromisc = (csr6_pr | csr6_pm), 295a88394cfSJeff Kirsher csr6_mask_filters = (csr6_hp | csr6_ho | csr6_if), 296a88394cfSJeff Kirsher csr6_mask_100bt = (csr6_scr | csr6_pcs | csr6_hbd), 297a88394cfSJeff Kirsher }; 298a88394cfSJeff Kirsher 299a88394cfSJeff Kirsher enum tulip_comet_csr13_bits { 300a88394cfSJeff Kirsher /* The LINKOFFE and LINKONE work in conjunction with LSCE, i.e. they 301a88394cfSJeff Kirsher * determine which link status transition wakes up if LSCE is 302a88394cfSJeff Kirsher * enabled */ 303a88394cfSJeff Kirsher comet_csr13_linkoffe = (1 << 17), 304a88394cfSJeff Kirsher comet_csr13_linkone = (1 << 16), 305a88394cfSJeff Kirsher comet_csr13_wfre = (1 << 10), 306a88394cfSJeff Kirsher comet_csr13_mpre = (1 << 9), 307a88394cfSJeff Kirsher comet_csr13_lsce = (1 << 8), 308a88394cfSJeff Kirsher comet_csr13_wfr = (1 << 2), 309a88394cfSJeff Kirsher comet_csr13_mpr = (1 << 1), 310a88394cfSJeff Kirsher comet_csr13_lsc = (1 << 0), 311a88394cfSJeff Kirsher }; 312a88394cfSJeff Kirsher 313a88394cfSJeff Kirsher enum tulip_comet_csr18_bits { 314a88394cfSJeff Kirsher comet_csr18_pmes_sticky = (1 << 24), 315a88394cfSJeff Kirsher comet_csr18_pm_mode = (1 << 19), 316a88394cfSJeff Kirsher comet_csr18_apm_mode = (1 << 18), 317a88394cfSJeff Kirsher comet_csr18_d3a = (1 << 7) 318a88394cfSJeff Kirsher }; 319a88394cfSJeff Kirsher 320a88394cfSJeff Kirsher enum tulip_comet_csr20_bits { 321a88394cfSJeff Kirsher comet_csr20_pmes = (1 << 15), 322a88394cfSJeff Kirsher }; 323a88394cfSJeff Kirsher 324a88394cfSJeff Kirsher /* Keep the ring sizes a power of two for efficiency. 325a88394cfSJeff Kirsher Making the Tx ring too large decreases the effectiveness of channel 326a88394cfSJeff Kirsher bonding and packet priority. 327a88394cfSJeff Kirsher There are no ill effects from too-large receive rings. */ 328a88394cfSJeff Kirsher 329a88394cfSJeff Kirsher #define TX_RING_SIZE 32 330a88394cfSJeff Kirsher #define RX_RING_SIZE 128 331a88394cfSJeff Kirsher #define MEDIA_MASK 31 332a88394cfSJeff Kirsher 333a88394cfSJeff Kirsher /* The receiver on the DC21143 rev 65 can fail to close the last 334a88394cfSJeff Kirsher * receive descriptor in certain circumstances (see errata) when 335a88394cfSJeff Kirsher * using MWI. This can only occur if the receive buffer ends on 336a88394cfSJeff Kirsher * a cache line boundary, so the "+ 4" below ensures it doesn't. 337a88394cfSJeff Kirsher */ 338a88394cfSJeff Kirsher #define PKT_BUF_SZ (1536 + 4) /* Size of each temporary Rx buffer. */ 339a88394cfSJeff Kirsher 340a88394cfSJeff Kirsher #define TULIP_MIN_CACHE_LINE 8 /* in units of 32-bit words */ 341a88394cfSJeff Kirsher 342a88394cfSJeff Kirsher #if defined(__sparc__) || defined(__hppa__) 343a88394cfSJeff Kirsher /* The UltraSparc PCI controllers will disconnect at every 64-byte 344a88394cfSJeff Kirsher * crossing anyways so it makes no sense to tell Tulip to burst 345a88394cfSJeff Kirsher * any more than that. 346a88394cfSJeff Kirsher */ 347a88394cfSJeff Kirsher #define TULIP_MAX_CACHE_LINE 16 /* in units of 32-bit words */ 348a88394cfSJeff Kirsher #else 349a88394cfSJeff Kirsher #define TULIP_MAX_CACHE_LINE 32 /* in units of 32-bit words */ 350a88394cfSJeff Kirsher #endif 351a88394cfSJeff Kirsher 352a88394cfSJeff Kirsher 353a88394cfSJeff Kirsher /* Ring-wrap flag in length field, use for last ring entry. 354a88394cfSJeff Kirsher 0x01000000 means chain on buffer2 address, 355a88394cfSJeff Kirsher 0x02000000 means use the ring start address in CSR2/3. 356a88394cfSJeff Kirsher Note: Some work-alike chips do not function correctly in chained mode. 357a88394cfSJeff Kirsher The ASIX chip works only in chained mode. 358a88394cfSJeff Kirsher Thus we indicates ring mode, but always write the 'next' field for 359a88394cfSJeff Kirsher chained mode as well. 360a88394cfSJeff Kirsher */ 361a88394cfSJeff Kirsher #define DESC_RING_WRAP 0x02000000 362a88394cfSJeff Kirsher 363a88394cfSJeff Kirsher 364a88394cfSJeff Kirsher #define EEPROM_SIZE 512 /* 2 << EEPROM_ADDRLEN */ 365a88394cfSJeff Kirsher 366a88394cfSJeff Kirsher 367a88394cfSJeff Kirsher #define RUN_AT(x) (jiffies + (x)) 368a88394cfSJeff Kirsher 369a88394cfSJeff Kirsher #define get_u16(ptr) get_unaligned_le16((ptr)) 370a88394cfSJeff Kirsher 371a88394cfSJeff Kirsher struct medialeaf { 372a88394cfSJeff Kirsher u8 type; 373a88394cfSJeff Kirsher u8 media; 374a88394cfSJeff Kirsher unsigned char *leafdata; 375a88394cfSJeff Kirsher }; 376a88394cfSJeff Kirsher 377a88394cfSJeff Kirsher 378a88394cfSJeff Kirsher struct mediatable { 379a88394cfSJeff Kirsher u16 defaultmedia; 380a88394cfSJeff Kirsher u8 leafcount; 381a88394cfSJeff Kirsher u8 csr12dir; /* General purpose pin directions. */ 382a88394cfSJeff Kirsher unsigned has_mii:1; 383a88394cfSJeff Kirsher unsigned has_nonmii:1; 384a88394cfSJeff Kirsher unsigned has_reset:6; 385a88394cfSJeff Kirsher u32 csr15dir; 386a88394cfSJeff Kirsher u32 csr15val; /* 21143 NWay setting. */ 387a88394cfSJeff Kirsher struct medialeaf mleaf[0]; 388a88394cfSJeff Kirsher }; 389a88394cfSJeff Kirsher 390a88394cfSJeff Kirsher 391a88394cfSJeff Kirsher struct mediainfo { 392a88394cfSJeff Kirsher struct mediainfo *next; 393a88394cfSJeff Kirsher int info_type; 394a88394cfSJeff Kirsher int index; 395a88394cfSJeff Kirsher unsigned char *info; 396a88394cfSJeff Kirsher }; 397a88394cfSJeff Kirsher 398a88394cfSJeff Kirsher struct ring_info { 399a88394cfSJeff Kirsher struct sk_buff *skb; 400a88394cfSJeff Kirsher dma_addr_t mapping; 401a88394cfSJeff Kirsher }; 402a88394cfSJeff Kirsher 403a88394cfSJeff Kirsher 404a88394cfSJeff Kirsher struct tulip_private { 405a88394cfSJeff Kirsher const char *product_name; 406a88394cfSJeff Kirsher struct net_device *next_module; 407a88394cfSJeff Kirsher struct tulip_rx_desc *rx_ring; 408a88394cfSJeff Kirsher struct tulip_tx_desc *tx_ring; 409a88394cfSJeff Kirsher dma_addr_t rx_ring_dma; 410a88394cfSJeff Kirsher dma_addr_t tx_ring_dma; 411a88394cfSJeff Kirsher /* The saved address of a sent-in-place packet/buffer, for skfree(). */ 412a88394cfSJeff Kirsher struct ring_info tx_buffers[TX_RING_SIZE]; 413a88394cfSJeff Kirsher /* The addresses of receive-in-place skbuffs. */ 414a88394cfSJeff Kirsher struct ring_info rx_buffers[RX_RING_SIZE]; 415a88394cfSJeff Kirsher u16 setup_frame[96]; /* Pseudo-Tx frame to init address table. */ 416a88394cfSJeff Kirsher int chip_id; 417a88394cfSJeff Kirsher int revision; 418a88394cfSJeff Kirsher int flags; 419a88394cfSJeff Kirsher struct napi_struct napi; 420a88394cfSJeff Kirsher struct timer_list timer; /* Media selection timer. */ 421a88394cfSJeff Kirsher struct timer_list oom_timer; /* Out of memory timer. */ 422a88394cfSJeff Kirsher u32 mc_filter[2]; 423a88394cfSJeff Kirsher spinlock_t lock; 424a88394cfSJeff Kirsher spinlock_t mii_lock; 425a88394cfSJeff Kirsher unsigned int cur_rx, cur_tx; /* The next free ring entry */ 426a88394cfSJeff Kirsher unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */ 427a88394cfSJeff Kirsher 428a88394cfSJeff Kirsher #ifdef CONFIG_TULIP_NAPI_HW_MITIGATION 429a88394cfSJeff Kirsher int mit_on; 430a88394cfSJeff Kirsher #endif 431a88394cfSJeff Kirsher unsigned int full_duplex:1; /* Full-duplex operation requested. */ 432a88394cfSJeff Kirsher unsigned int full_duplex_lock:1; 433a88394cfSJeff Kirsher unsigned int fake_addr:1; /* Multiport board faked address. */ 434a88394cfSJeff Kirsher unsigned int default_port:4; /* Last dev->if_port value. */ 435a88394cfSJeff Kirsher unsigned int media2:4; /* Secondary monitored media port. */ 436a88394cfSJeff Kirsher unsigned int medialock:1; /* Don't sense media type. */ 437a88394cfSJeff Kirsher unsigned int mediasense:1; /* Media sensing in progress. */ 438a88394cfSJeff Kirsher unsigned int nway:1, nwayset:1; /* 21143 internal NWay. */ 439a88394cfSJeff Kirsher unsigned int timeout_recovery:1; 440a88394cfSJeff Kirsher unsigned int csr0; /* CSR0 setting. */ 441a88394cfSJeff Kirsher unsigned int csr6; /* Current CSR6 control settings. */ 442a88394cfSJeff Kirsher unsigned char eeprom[EEPROM_SIZE]; /* Serial EEPROM contents. */ 443a88394cfSJeff Kirsher void (*link_change) (struct net_device * dev, int csr5); 444a88394cfSJeff Kirsher struct ethtool_wolinfo wolinfo; /* WOL settings */ 445a88394cfSJeff Kirsher u16 sym_advertise, mii_advertise; /* NWay capabilities advertised. */ 446a88394cfSJeff Kirsher u16 lpar; /* 21143 Link partner ability. */ 447a88394cfSJeff Kirsher u16 advertising[4]; 448a88394cfSJeff Kirsher signed char phys[4], mii_cnt; /* MII device addresses. */ 449a88394cfSJeff Kirsher struct mediatable *mtable; 450a88394cfSJeff Kirsher int cur_index; /* Current media index. */ 451a88394cfSJeff Kirsher int saved_if_port; 452a88394cfSJeff Kirsher struct pci_dev *pdev; 453a88394cfSJeff Kirsher int ttimer; 454a88394cfSJeff Kirsher int susp_rx; 455a88394cfSJeff Kirsher unsigned long nir; 456a88394cfSJeff Kirsher void __iomem *base_addr; 457a88394cfSJeff Kirsher int csr12_shadow; 458a88394cfSJeff Kirsher int pad0; /* Used for 8-byte alignment */ 459a88394cfSJeff Kirsher struct work_struct media_work; 460a88394cfSJeff Kirsher struct net_device *dev; 461a88394cfSJeff Kirsher }; 462a88394cfSJeff Kirsher 463a88394cfSJeff Kirsher 464a88394cfSJeff Kirsher struct eeprom_fixup { 465a88394cfSJeff Kirsher char *name; 466a88394cfSJeff Kirsher unsigned char addr0; 467a88394cfSJeff Kirsher unsigned char addr1; 468a88394cfSJeff Kirsher unsigned char addr2; 469a88394cfSJeff Kirsher u16 newtable[32]; /* Max length below. */ 470a88394cfSJeff Kirsher }; 471a88394cfSJeff Kirsher 472a88394cfSJeff Kirsher 473a88394cfSJeff Kirsher /* 21142.c */ 474a88394cfSJeff Kirsher extern u16 t21142_csr14[]; 475a88394cfSJeff Kirsher void t21142_media_task(struct work_struct *work); 476a88394cfSJeff Kirsher void t21142_start_nway(struct net_device *dev); 477a88394cfSJeff Kirsher void t21142_lnk_change(struct net_device *dev, int csr5); 478a88394cfSJeff Kirsher 479a88394cfSJeff Kirsher 480a88394cfSJeff Kirsher /* PNIC2.c */ 481a88394cfSJeff Kirsher void pnic2_lnk_change(struct net_device *dev, int csr5); 482a88394cfSJeff Kirsher void pnic2_timer(unsigned long data); 483a88394cfSJeff Kirsher void pnic2_start_nway(struct net_device *dev); 484a88394cfSJeff Kirsher void pnic2_lnk_change(struct net_device *dev, int csr5); 485a88394cfSJeff Kirsher 486a88394cfSJeff Kirsher /* eeprom.c */ 487a88394cfSJeff Kirsher void tulip_parse_eeprom(struct net_device *dev); 488a88394cfSJeff Kirsher int tulip_read_eeprom(struct net_device *dev, int location, int addr_len); 489a88394cfSJeff Kirsher 490a88394cfSJeff Kirsher /* interrupt.c */ 491a88394cfSJeff Kirsher extern unsigned int tulip_max_interrupt_work; 492a88394cfSJeff Kirsher extern int tulip_rx_copybreak; 493a88394cfSJeff Kirsher irqreturn_t tulip_interrupt(int irq, void *dev_instance); 494a88394cfSJeff Kirsher int tulip_refill_rx(struct net_device *dev); 495a88394cfSJeff Kirsher #ifdef CONFIG_TULIP_NAPI 496a88394cfSJeff Kirsher int tulip_poll(struct napi_struct *napi, int budget); 497a88394cfSJeff Kirsher #endif 498a88394cfSJeff Kirsher 499a88394cfSJeff Kirsher 500a88394cfSJeff Kirsher /* media.c */ 501a88394cfSJeff Kirsher int tulip_mdio_read(struct net_device *dev, int phy_id, int location); 502a88394cfSJeff Kirsher void tulip_mdio_write(struct net_device *dev, int phy_id, int location, int value); 503a88394cfSJeff Kirsher void tulip_select_media(struct net_device *dev, int startup); 504a88394cfSJeff Kirsher int tulip_check_duplex(struct net_device *dev); 505a88394cfSJeff Kirsher void tulip_find_mii (struct net_device *dev, int board_idx); 506a88394cfSJeff Kirsher 507a88394cfSJeff Kirsher /* pnic.c */ 508a88394cfSJeff Kirsher void pnic_do_nway(struct net_device *dev); 509a88394cfSJeff Kirsher void pnic_lnk_change(struct net_device *dev, int csr5); 510a88394cfSJeff Kirsher void pnic_timer(unsigned long data); 511a88394cfSJeff Kirsher 512a88394cfSJeff Kirsher /* timer.c */ 513a88394cfSJeff Kirsher void tulip_media_task(struct work_struct *work); 514a88394cfSJeff Kirsher void mxic_timer(unsigned long data); 515a88394cfSJeff Kirsher void comet_timer(unsigned long data); 516a88394cfSJeff Kirsher 517a88394cfSJeff Kirsher /* tulip_core.c */ 518a88394cfSJeff Kirsher extern int tulip_debug; 519a88394cfSJeff Kirsher extern const char * const medianame[]; 520a88394cfSJeff Kirsher extern const char tulip_media_cap[]; 521a88394cfSJeff Kirsher extern struct tulip_chip_table tulip_tbl[]; 522a88394cfSJeff Kirsher void oom_timer(unsigned long data); 523a88394cfSJeff Kirsher extern u8 t21040_csr13[]; 524a88394cfSJeff Kirsher 525a88394cfSJeff Kirsher static inline void tulip_start_rxtx(struct tulip_private *tp) 526a88394cfSJeff Kirsher { 527a88394cfSJeff Kirsher void __iomem *ioaddr = tp->base_addr; 528a88394cfSJeff Kirsher iowrite32(tp->csr6 | RxTx, ioaddr + CSR6); 529a88394cfSJeff Kirsher barrier(); 530a88394cfSJeff Kirsher (void) ioread32(ioaddr + CSR6); /* mmio sync */ 531a88394cfSJeff Kirsher } 532a88394cfSJeff Kirsher 533a88394cfSJeff Kirsher static inline void tulip_stop_rxtx(struct tulip_private *tp) 534a88394cfSJeff Kirsher { 535a88394cfSJeff Kirsher void __iomem *ioaddr = tp->base_addr; 536a88394cfSJeff Kirsher u32 csr6 = ioread32(ioaddr + CSR6); 537a88394cfSJeff Kirsher 538a88394cfSJeff Kirsher if (csr6 & RxTx) { 539a88394cfSJeff Kirsher unsigned i=1300/10; 540a88394cfSJeff Kirsher iowrite32(csr6 & ~RxTx, ioaddr + CSR6); 541a88394cfSJeff Kirsher barrier(); 542a88394cfSJeff Kirsher /* wait until in-flight frame completes. 543a88394cfSJeff Kirsher * Max time @ 10BT: 1500*8b/10Mbps == 1200us (+ 100us margin) 544a88394cfSJeff Kirsher * Typically expect this loop to end in < 50 us on 100BT. 545a88394cfSJeff Kirsher */ 546a88394cfSJeff Kirsher while (--i && (ioread32(ioaddr + CSR5) & (CSR5_TS|CSR5_RS))) 547a88394cfSJeff Kirsher udelay(10); 548a88394cfSJeff Kirsher 549a88394cfSJeff Kirsher if (!i) 550a88394cfSJeff Kirsher netdev_dbg(tp->dev, "tulip_stop_rxtx() failed (CSR5 0x%x CSR6 0x%x)\n", 551a88394cfSJeff Kirsher ioread32(ioaddr + CSR5), 552a88394cfSJeff Kirsher ioread32(ioaddr + CSR6)); 553a88394cfSJeff Kirsher } 554a88394cfSJeff Kirsher } 555a88394cfSJeff Kirsher 556a88394cfSJeff Kirsher static inline void tulip_restart_rxtx(struct tulip_private *tp) 557a88394cfSJeff Kirsher { 558a88394cfSJeff Kirsher tulip_stop_rxtx(tp); 559a88394cfSJeff Kirsher udelay(5); 560a88394cfSJeff Kirsher tulip_start_rxtx(tp); 561a88394cfSJeff Kirsher } 562a88394cfSJeff Kirsher 563a88394cfSJeff Kirsher static inline void tulip_tx_timeout_complete(struct tulip_private *tp, void __iomem *ioaddr) 564a88394cfSJeff Kirsher { 565a88394cfSJeff Kirsher /* Stop and restart the chip's Tx processes. */ 566a88394cfSJeff Kirsher tulip_restart_rxtx(tp); 567a88394cfSJeff Kirsher /* Trigger an immediate transmit demand. */ 568a88394cfSJeff Kirsher iowrite32(0, ioaddr + CSR1); 569a88394cfSJeff Kirsher 570a88394cfSJeff Kirsher tp->dev->stats.tx_errors++; 571a88394cfSJeff Kirsher } 572a88394cfSJeff Kirsher 573a88394cfSJeff Kirsher #endif /* __NET_TULIP_H__ */ 574