1 /* 2 * Davicom DM9000 Fast Ethernet driver for Linux. 3 * Copyright (C) 1997 Sten Wang 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 2 8 * of the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * (C) Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved. 16 * 17 * Additional updates, Copyright: 18 * Ben Dooks <ben@simtec.co.uk> 19 * Sascha Hauer <s.hauer@pengutronix.de> 20 */ 21 22 #include <linux/module.h> 23 #include <linux/ioport.h> 24 #include <linux/netdevice.h> 25 #include <linux/etherdevice.h> 26 #include <linux/init.h> 27 #include <linux/interrupt.h> 28 #include <linux/skbuff.h> 29 #include <linux/spinlock.h> 30 #include <linux/crc32.h> 31 #include <linux/mii.h> 32 #include <linux/of.h> 33 #include <linux/of_net.h> 34 #include <linux/ethtool.h> 35 #include <linux/dm9000.h> 36 #include <linux/delay.h> 37 #include <linux/platform_device.h> 38 #include <linux/irq.h> 39 #include <linux/slab.h> 40 41 #include <asm/delay.h> 42 #include <asm/irq.h> 43 #include <asm/io.h> 44 45 #include "dm9000.h" 46 47 /* Board/System/Debug information/definition ---------------- */ 48 49 #define DM9000_PHY 0x40 /* PHY address 0x01 */ 50 51 #define CARDNAME "dm9000" 52 #define DRV_VERSION "1.31" 53 54 /* 55 * Transmit timeout, default 5 seconds. 56 */ 57 static int watchdog = 5000; 58 module_param(watchdog, int, 0400); 59 MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds"); 60 61 /* 62 * Debug messages level 63 */ 64 static int debug; 65 module_param(debug, int, 0644); 66 MODULE_PARM_DESC(debug, "dm9000 debug level (0-4)"); 67 68 /* DM9000 register address locking. 69 * 70 * The DM9000 uses an address register to control where data written 71 * to the data register goes. This means that the address register 72 * must be preserved over interrupts or similar calls. 73 * 74 * During interrupt and other critical calls, a spinlock is used to 75 * protect the system, but the calls themselves save the address 76 * in the address register in case they are interrupting another 77 * access to the device. 78 * 79 * For general accesses a lock is provided so that calls which are 80 * allowed to sleep are serialised so that the address register does 81 * not need to be saved. This lock also serves to serialise access 82 * to the EEPROM and PHY access registers which are shared between 83 * these two devices. 84 */ 85 86 /* The driver supports the original DM9000E, and now the two newer 87 * devices, DM9000A and DM9000B. 88 */ 89 90 enum dm9000_type { 91 TYPE_DM9000E, /* original DM9000 */ 92 TYPE_DM9000A, 93 TYPE_DM9000B 94 }; 95 96 /* Structure/enum declaration ------------------------------- */ 97 typedef struct board_info { 98 99 void __iomem *io_addr; /* Register I/O base address */ 100 void __iomem *io_data; /* Data I/O address */ 101 u16 irq; /* IRQ */ 102 103 u16 tx_pkt_cnt; 104 u16 queue_pkt_len; 105 u16 queue_start_addr; 106 u16 queue_ip_summed; 107 u16 dbug_cnt; 108 u8 io_mode; /* 0:word, 2:byte */ 109 u8 phy_addr; 110 u8 imr_all; 111 112 unsigned int flags; 113 unsigned int in_suspend :1; 114 unsigned int wake_supported :1; 115 116 enum dm9000_type type; 117 118 void (*inblk)(void __iomem *port, void *data, int length); 119 void (*outblk)(void __iomem *port, void *data, int length); 120 void (*dumpblk)(void __iomem *port, int length); 121 122 struct device *dev; /* parent device */ 123 124 struct resource *addr_res; /* resources found */ 125 struct resource *data_res; 126 struct resource *addr_req; /* resources requested */ 127 struct resource *data_req; 128 struct resource *irq_res; 129 130 int irq_wake; 131 132 struct mutex addr_lock; /* phy and eeprom access lock */ 133 134 struct delayed_work phy_poll; 135 struct net_device *ndev; 136 137 spinlock_t lock; 138 139 struct mii_if_info mii; 140 u32 msg_enable; 141 u32 wake_state; 142 143 int ip_summed; 144 } board_info_t; 145 146 /* debug code */ 147 148 #define dm9000_dbg(db, lev, msg...) do { \ 149 if ((lev) < debug) { \ 150 dev_dbg(db->dev, msg); \ 151 } \ 152 } while (0) 153 154 static inline board_info_t *to_dm9000_board(struct net_device *dev) 155 { 156 return netdev_priv(dev); 157 } 158 159 /* DM9000 network board routine ---------------------------- */ 160 161 static void 162 dm9000_reset(board_info_t * db) 163 { 164 dev_dbg(db->dev, "resetting device\n"); 165 166 /* RESET device */ 167 writeb(DM9000_NCR, db->io_addr); 168 udelay(200); 169 writeb(NCR_RST, db->io_data); 170 udelay(200); 171 } 172 173 /* 174 * Read a byte from I/O port 175 */ 176 static u8 177 ior(board_info_t * db, int reg) 178 { 179 writeb(reg, db->io_addr); 180 return readb(db->io_data); 181 } 182 183 /* 184 * Write a byte to I/O port 185 */ 186 187 static void 188 iow(board_info_t * db, int reg, int value) 189 { 190 writeb(reg, db->io_addr); 191 writeb(value, db->io_data); 192 } 193 194 /* routines for sending block to chip */ 195 196 static void dm9000_outblk_8bit(void __iomem *reg, void *data, int count) 197 { 198 iowrite8_rep(reg, data, count); 199 } 200 201 static void dm9000_outblk_16bit(void __iomem *reg, void *data, int count) 202 { 203 iowrite16_rep(reg, data, (count+1) >> 1); 204 } 205 206 static void dm9000_outblk_32bit(void __iomem *reg, void *data, int count) 207 { 208 iowrite32_rep(reg, data, (count+3) >> 2); 209 } 210 211 /* input block from chip to memory */ 212 213 static void dm9000_inblk_8bit(void __iomem *reg, void *data, int count) 214 { 215 ioread8_rep(reg, data, count); 216 } 217 218 219 static void dm9000_inblk_16bit(void __iomem *reg, void *data, int count) 220 { 221 ioread16_rep(reg, data, (count+1) >> 1); 222 } 223 224 static void dm9000_inblk_32bit(void __iomem *reg, void *data, int count) 225 { 226 ioread32_rep(reg, data, (count+3) >> 2); 227 } 228 229 /* dump block from chip to null */ 230 231 static void dm9000_dumpblk_8bit(void __iomem *reg, int count) 232 { 233 int i; 234 int tmp; 235 236 for (i = 0; i < count; i++) 237 tmp = readb(reg); 238 } 239 240 static void dm9000_dumpblk_16bit(void __iomem *reg, int count) 241 { 242 int i; 243 int tmp; 244 245 count = (count + 1) >> 1; 246 247 for (i = 0; i < count; i++) 248 tmp = readw(reg); 249 } 250 251 static void dm9000_dumpblk_32bit(void __iomem *reg, int count) 252 { 253 int i; 254 int tmp; 255 256 count = (count + 3) >> 2; 257 258 for (i = 0; i < count; i++) 259 tmp = readl(reg); 260 } 261 262 /* 263 * Sleep, either by using msleep() or if we are suspending, then 264 * use mdelay() to sleep. 265 */ 266 static void dm9000_msleep(board_info_t *db, unsigned int ms) 267 { 268 if (db->in_suspend) 269 mdelay(ms); 270 else 271 msleep(ms); 272 } 273 274 /* Read a word from phyxcer */ 275 static int 276 dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg) 277 { 278 board_info_t *db = netdev_priv(dev); 279 unsigned long flags; 280 unsigned int reg_save; 281 int ret; 282 283 mutex_lock(&db->addr_lock); 284 285 spin_lock_irqsave(&db->lock, flags); 286 287 /* Save previous register address */ 288 reg_save = readb(db->io_addr); 289 290 /* Fill the phyxcer register into REG_0C */ 291 iow(db, DM9000_EPAR, DM9000_PHY | reg); 292 293 /* Issue phyxcer read command */ 294 iow(db, DM9000_EPCR, EPCR_ERPRR | EPCR_EPOS); 295 296 writeb(reg_save, db->io_addr); 297 spin_unlock_irqrestore(&db->lock, flags); 298 299 dm9000_msleep(db, 1); /* Wait read complete */ 300 301 spin_lock_irqsave(&db->lock, flags); 302 reg_save = readb(db->io_addr); 303 304 iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer read command */ 305 306 /* The read data keeps on REG_0D & REG_0E */ 307 ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL); 308 309 /* restore the previous address */ 310 writeb(reg_save, db->io_addr); 311 spin_unlock_irqrestore(&db->lock, flags); 312 313 mutex_unlock(&db->addr_lock); 314 315 dm9000_dbg(db, 5, "phy_read[%02x] -> %04x\n", reg, ret); 316 return ret; 317 } 318 319 /* Write a word to phyxcer */ 320 static void 321 dm9000_phy_write(struct net_device *dev, 322 int phyaddr_unused, int reg, int value) 323 { 324 board_info_t *db = netdev_priv(dev); 325 unsigned long flags; 326 unsigned long reg_save; 327 328 dm9000_dbg(db, 5, "phy_write[%02x] = %04x\n", reg, value); 329 mutex_lock(&db->addr_lock); 330 331 spin_lock_irqsave(&db->lock, flags); 332 333 /* Save previous register address */ 334 reg_save = readb(db->io_addr); 335 336 /* Fill the phyxcer register into REG_0C */ 337 iow(db, DM9000_EPAR, DM9000_PHY | reg); 338 339 /* Fill the written data into REG_0D & REG_0E */ 340 iow(db, DM9000_EPDRL, value); 341 iow(db, DM9000_EPDRH, value >> 8); 342 343 /* Issue phyxcer write command */ 344 iow(db, DM9000_EPCR, EPCR_EPOS | EPCR_ERPRW); 345 346 writeb(reg_save, db->io_addr); 347 spin_unlock_irqrestore(&db->lock, flags); 348 349 dm9000_msleep(db, 1); /* Wait write complete */ 350 351 spin_lock_irqsave(&db->lock, flags); 352 reg_save = readb(db->io_addr); 353 354 iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer write command */ 355 356 /* restore the previous address */ 357 writeb(reg_save, db->io_addr); 358 359 spin_unlock_irqrestore(&db->lock, flags); 360 mutex_unlock(&db->addr_lock); 361 } 362 363 /* dm9000_set_io 364 * 365 * select the specified set of io routines to use with the 366 * device 367 */ 368 369 static void dm9000_set_io(struct board_info *db, int byte_width) 370 { 371 /* use the size of the data resource to work out what IO 372 * routines we want to use 373 */ 374 375 switch (byte_width) { 376 case 1: 377 db->dumpblk = dm9000_dumpblk_8bit; 378 db->outblk = dm9000_outblk_8bit; 379 db->inblk = dm9000_inblk_8bit; 380 break; 381 382 383 case 3: 384 dev_dbg(db->dev, ": 3 byte IO, falling back to 16bit\n"); 385 case 2: 386 db->dumpblk = dm9000_dumpblk_16bit; 387 db->outblk = dm9000_outblk_16bit; 388 db->inblk = dm9000_inblk_16bit; 389 break; 390 391 case 4: 392 default: 393 db->dumpblk = dm9000_dumpblk_32bit; 394 db->outblk = dm9000_outblk_32bit; 395 db->inblk = dm9000_inblk_32bit; 396 break; 397 } 398 } 399 400 static void dm9000_schedule_poll(board_info_t *db) 401 { 402 if (db->type == TYPE_DM9000E) 403 schedule_delayed_work(&db->phy_poll, HZ * 2); 404 } 405 406 static int dm9000_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 407 { 408 board_info_t *dm = to_dm9000_board(dev); 409 410 if (!netif_running(dev)) 411 return -EINVAL; 412 413 return generic_mii_ioctl(&dm->mii, if_mii(req), cmd, NULL); 414 } 415 416 static unsigned int 417 dm9000_read_locked(board_info_t *db, int reg) 418 { 419 unsigned long flags; 420 unsigned int ret; 421 422 spin_lock_irqsave(&db->lock, flags); 423 ret = ior(db, reg); 424 spin_unlock_irqrestore(&db->lock, flags); 425 426 return ret; 427 } 428 429 static int dm9000_wait_eeprom(board_info_t *db) 430 { 431 unsigned int status; 432 int timeout = 8; /* wait max 8msec */ 433 434 /* The DM9000 data sheets say we should be able to 435 * poll the ERRE bit in EPCR to wait for the EEPROM 436 * operation. From testing several chips, this bit 437 * does not seem to work. 438 * 439 * We attempt to use the bit, but fall back to the 440 * timeout (which is why we do not return an error 441 * on expiry) to say that the EEPROM operation has 442 * completed. 443 */ 444 445 while (1) { 446 status = dm9000_read_locked(db, DM9000_EPCR); 447 448 if ((status & EPCR_ERRE) == 0) 449 break; 450 451 msleep(1); 452 453 if (timeout-- < 0) { 454 dev_dbg(db->dev, "timeout waiting EEPROM\n"); 455 break; 456 } 457 } 458 459 return 0; 460 } 461 462 /* 463 * Read a word data from EEPROM 464 */ 465 static void 466 dm9000_read_eeprom(board_info_t *db, int offset, u8 *to) 467 { 468 unsigned long flags; 469 470 if (db->flags & DM9000_PLATF_NO_EEPROM) { 471 to[0] = 0xff; 472 to[1] = 0xff; 473 return; 474 } 475 476 mutex_lock(&db->addr_lock); 477 478 spin_lock_irqsave(&db->lock, flags); 479 480 iow(db, DM9000_EPAR, offset); 481 iow(db, DM9000_EPCR, EPCR_ERPRR); 482 483 spin_unlock_irqrestore(&db->lock, flags); 484 485 dm9000_wait_eeprom(db); 486 487 /* delay for at-least 150uS */ 488 msleep(1); 489 490 spin_lock_irqsave(&db->lock, flags); 491 492 iow(db, DM9000_EPCR, 0x0); 493 494 to[0] = ior(db, DM9000_EPDRL); 495 to[1] = ior(db, DM9000_EPDRH); 496 497 spin_unlock_irqrestore(&db->lock, flags); 498 499 mutex_unlock(&db->addr_lock); 500 } 501 502 /* 503 * Write a word data to SROM 504 */ 505 static void 506 dm9000_write_eeprom(board_info_t *db, int offset, u8 *data) 507 { 508 unsigned long flags; 509 510 if (db->flags & DM9000_PLATF_NO_EEPROM) 511 return; 512 513 mutex_lock(&db->addr_lock); 514 515 spin_lock_irqsave(&db->lock, flags); 516 iow(db, DM9000_EPAR, offset); 517 iow(db, DM9000_EPDRH, data[1]); 518 iow(db, DM9000_EPDRL, data[0]); 519 iow(db, DM9000_EPCR, EPCR_WEP | EPCR_ERPRW); 520 spin_unlock_irqrestore(&db->lock, flags); 521 522 dm9000_wait_eeprom(db); 523 524 mdelay(1); /* wait at least 150uS to clear */ 525 526 spin_lock_irqsave(&db->lock, flags); 527 iow(db, DM9000_EPCR, 0); 528 spin_unlock_irqrestore(&db->lock, flags); 529 530 mutex_unlock(&db->addr_lock); 531 } 532 533 /* ethtool ops */ 534 535 static void dm9000_get_drvinfo(struct net_device *dev, 536 struct ethtool_drvinfo *info) 537 { 538 board_info_t *dm = to_dm9000_board(dev); 539 540 strlcpy(info->driver, CARDNAME, sizeof(info->driver)); 541 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 542 strlcpy(info->bus_info, to_platform_device(dm->dev)->name, 543 sizeof(info->bus_info)); 544 } 545 546 static u32 dm9000_get_msglevel(struct net_device *dev) 547 { 548 board_info_t *dm = to_dm9000_board(dev); 549 550 return dm->msg_enable; 551 } 552 553 static void dm9000_set_msglevel(struct net_device *dev, u32 value) 554 { 555 board_info_t *dm = to_dm9000_board(dev); 556 557 dm->msg_enable = value; 558 } 559 560 static int dm9000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 561 { 562 board_info_t *dm = to_dm9000_board(dev); 563 564 mii_ethtool_gset(&dm->mii, cmd); 565 return 0; 566 } 567 568 static int dm9000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 569 { 570 board_info_t *dm = to_dm9000_board(dev); 571 572 return mii_ethtool_sset(&dm->mii, cmd); 573 } 574 575 static int dm9000_nway_reset(struct net_device *dev) 576 { 577 board_info_t *dm = to_dm9000_board(dev); 578 return mii_nway_restart(&dm->mii); 579 } 580 581 static int dm9000_set_features(struct net_device *dev, 582 netdev_features_t features) 583 { 584 board_info_t *dm = to_dm9000_board(dev); 585 netdev_features_t changed = dev->features ^ features; 586 unsigned long flags; 587 588 if (!(changed & NETIF_F_RXCSUM)) 589 return 0; 590 591 spin_lock_irqsave(&dm->lock, flags); 592 iow(dm, DM9000_RCSR, (features & NETIF_F_RXCSUM) ? RCSR_CSUM : 0); 593 spin_unlock_irqrestore(&dm->lock, flags); 594 595 return 0; 596 } 597 598 static u32 dm9000_get_link(struct net_device *dev) 599 { 600 board_info_t *dm = to_dm9000_board(dev); 601 u32 ret; 602 603 if (dm->flags & DM9000_PLATF_EXT_PHY) 604 ret = mii_link_ok(&dm->mii); 605 else 606 ret = dm9000_read_locked(dm, DM9000_NSR) & NSR_LINKST ? 1 : 0; 607 608 return ret; 609 } 610 611 #define DM_EEPROM_MAGIC (0x444D394B) 612 613 static int dm9000_get_eeprom_len(struct net_device *dev) 614 { 615 return 128; 616 } 617 618 static int dm9000_get_eeprom(struct net_device *dev, 619 struct ethtool_eeprom *ee, u8 *data) 620 { 621 board_info_t *dm = to_dm9000_board(dev); 622 int offset = ee->offset; 623 int len = ee->len; 624 int i; 625 626 /* EEPROM access is aligned to two bytes */ 627 628 if ((len & 1) != 0 || (offset & 1) != 0) 629 return -EINVAL; 630 631 if (dm->flags & DM9000_PLATF_NO_EEPROM) 632 return -ENOENT; 633 634 ee->magic = DM_EEPROM_MAGIC; 635 636 for (i = 0; i < len; i += 2) 637 dm9000_read_eeprom(dm, (offset + i) / 2, data + i); 638 639 return 0; 640 } 641 642 static int dm9000_set_eeprom(struct net_device *dev, 643 struct ethtool_eeprom *ee, u8 *data) 644 { 645 board_info_t *dm = to_dm9000_board(dev); 646 int offset = ee->offset; 647 int len = ee->len; 648 int done; 649 650 /* EEPROM access is aligned to two bytes */ 651 652 if (dm->flags & DM9000_PLATF_NO_EEPROM) 653 return -ENOENT; 654 655 if (ee->magic != DM_EEPROM_MAGIC) 656 return -EINVAL; 657 658 while (len > 0) { 659 if (len & 1 || offset & 1) { 660 int which = offset & 1; 661 u8 tmp[2]; 662 663 dm9000_read_eeprom(dm, offset / 2, tmp); 664 tmp[which] = *data; 665 dm9000_write_eeprom(dm, offset / 2, tmp); 666 667 done = 1; 668 } else { 669 dm9000_write_eeprom(dm, offset / 2, data); 670 done = 2; 671 } 672 673 data += done; 674 offset += done; 675 len -= done; 676 } 677 678 return 0; 679 } 680 681 static void dm9000_get_wol(struct net_device *dev, struct ethtool_wolinfo *w) 682 { 683 board_info_t *dm = to_dm9000_board(dev); 684 685 memset(w, 0, sizeof(struct ethtool_wolinfo)); 686 687 /* note, we could probably support wake-phy too */ 688 w->supported = dm->wake_supported ? WAKE_MAGIC : 0; 689 w->wolopts = dm->wake_state; 690 } 691 692 static int dm9000_set_wol(struct net_device *dev, struct ethtool_wolinfo *w) 693 { 694 board_info_t *dm = to_dm9000_board(dev); 695 unsigned long flags; 696 u32 opts = w->wolopts; 697 u32 wcr = 0; 698 699 if (!dm->wake_supported) 700 return -EOPNOTSUPP; 701 702 if (opts & ~WAKE_MAGIC) 703 return -EINVAL; 704 705 if (opts & WAKE_MAGIC) 706 wcr |= WCR_MAGICEN; 707 708 mutex_lock(&dm->addr_lock); 709 710 spin_lock_irqsave(&dm->lock, flags); 711 iow(dm, DM9000_WCR, wcr); 712 spin_unlock_irqrestore(&dm->lock, flags); 713 714 mutex_unlock(&dm->addr_lock); 715 716 if (dm->wake_state != opts) { 717 /* change in wol state, update IRQ state */ 718 719 if (!dm->wake_state) 720 irq_set_irq_wake(dm->irq_wake, 1); 721 else if (dm->wake_state && !opts) 722 irq_set_irq_wake(dm->irq_wake, 0); 723 } 724 725 dm->wake_state = opts; 726 return 0; 727 } 728 729 static const struct ethtool_ops dm9000_ethtool_ops = { 730 .get_drvinfo = dm9000_get_drvinfo, 731 .get_settings = dm9000_get_settings, 732 .set_settings = dm9000_set_settings, 733 .get_msglevel = dm9000_get_msglevel, 734 .set_msglevel = dm9000_set_msglevel, 735 .nway_reset = dm9000_nway_reset, 736 .get_link = dm9000_get_link, 737 .get_wol = dm9000_get_wol, 738 .set_wol = dm9000_set_wol, 739 .get_eeprom_len = dm9000_get_eeprom_len, 740 .get_eeprom = dm9000_get_eeprom, 741 .set_eeprom = dm9000_set_eeprom, 742 }; 743 744 static void dm9000_show_carrier(board_info_t *db, 745 unsigned carrier, unsigned nsr) 746 { 747 struct net_device *ndev = db->ndev; 748 unsigned ncr = dm9000_read_locked(db, DM9000_NCR); 749 750 if (carrier) 751 dev_info(db->dev, "%s: link up, %dMbps, %s-duplex, no LPA\n", 752 ndev->name, (nsr & NSR_SPEED) ? 10 : 100, 753 (ncr & NCR_FDX) ? "full" : "half"); 754 else 755 dev_info(db->dev, "%s: link down\n", ndev->name); 756 } 757 758 static void 759 dm9000_poll_work(struct work_struct *w) 760 { 761 struct delayed_work *dw = to_delayed_work(w); 762 board_info_t *db = container_of(dw, board_info_t, phy_poll); 763 struct net_device *ndev = db->ndev; 764 765 if (db->flags & DM9000_PLATF_SIMPLE_PHY && 766 !(db->flags & DM9000_PLATF_EXT_PHY)) { 767 unsigned nsr = dm9000_read_locked(db, DM9000_NSR); 768 unsigned old_carrier = netif_carrier_ok(ndev) ? 1 : 0; 769 unsigned new_carrier; 770 771 new_carrier = (nsr & NSR_LINKST) ? 1 : 0; 772 773 if (old_carrier != new_carrier) { 774 if (netif_msg_link(db)) 775 dm9000_show_carrier(db, new_carrier, nsr); 776 777 if (!new_carrier) 778 netif_carrier_off(ndev); 779 else 780 netif_carrier_on(ndev); 781 } 782 } else 783 mii_check_media(&db->mii, netif_msg_link(db), 0); 784 785 if (netif_running(ndev)) 786 dm9000_schedule_poll(db); 787 } 788 789 /* dm9000_release_board 790 * 791 * release a board, and any mapped resources 792 */ 793 794 static void 795 dm9000_release_board(struct platform_device *pdev, struct board_info *db) 796 { 797 /* unmap our resources */ 798 799 iounmap(db->io_addr); 800 iounmap(db->io_data); 801 802 /* release the resources */ 803 804 release_resource(db->data_req); 805 kfree(db->data_req); 806 807 release_resource(db->addr_req); 808 kfree(db->addr_req); 809 } 810 811 static unsigned char dm9000_type_to_char(enum dm9000_type type) 812 { 813 switch (type) { 814 case TYPE_DM9000E: return 'e'; 815 case TYPE_DM9000A: return 'a'; 816 case TYPE_DM9000B: return 'b'; 817 } 818 819 return '?'; 820 } 821 822 /* 823 * Set DM9000 multicast address 824 */ 825 static void 826 dm9000_hash_table_unlocked(struct net_device *dev) 827 { 828 board_info_t *db = netdev_priv(dev); 829 struct netdev_hw_addr *ha; 830 int i, oft; 831 u32 hash_val; 832 u16 hash_table[4] = { 0, 0, 0, 0x8000 }; /* broadcast address */ 833 u8 rcr = RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN; 834 835 dm9000_dbg(db, 1, "entering %s\n", __func__); 836 837 for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++) 838 iow(db, oft, dev->dev_addr[i]); 839 840 if (dev->flags & IFF_PROMISC) 841 rcr |= RCR_PRMSC; 842 843 if (dev->flags & IFF_ALLMULTI) 844 rcr |= RCR_ALL; 845 846 /* the multicast address in Hash Table : 64 bits */ 847 netdev_for_each_mc_addr(ha, dev) { 848 hash_val = ether_crc_le(6, ha->addr) & 0x3f; 849 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16); 850 } 851 852 /* Write the hash table to MAC MD table */ 853 for (i = 0, oft = DM9000_MAR; i < 4; i++) { 854 iow(db, oft++, hash_table[i]); 855 iow(db, oft++, hash_table[i] >> 8); 856 } 857 858 iow(db, DM9000_RCR, rcr); 859 } 860 861 static void 862 dm9000_hash_table(struct net_device *dev) 863 { 864 board_info_t *db = netdev_priv(dev); 865 unsigned long flags; 866 867 spin_lock_irqsave(&db->lock, flags); 868 dm9000_hash_table_unlocked(dev); 869 spin_unlock_irqrestore(&db->lock, flags); 870 } 871 872 /* 873 * Initialize dm9000 board 874 */ 875 static void 876 dm9000_init_dm9000(struct net_device *dev) 877 { 878 board_info_t *db = netdev_priv(dev); 879 unsigned int imr; 880 unsigned int ncr; 881 882 dm9000_dbg(db, 1, "entering %s\n", __func__); 883 884 /* I/O mode */ 885 db->io_mode = ior(db, DM9000_ISR) >> 6; /* ISR bit7:6 keeps I/O mode */ 886 887 /* Checksum mode */ 888 if (dev->hw_features & NETIF_F_RXCSUM) 889 iow(db, DM9000_RCSR, 890 (dev->features & NETIF_F_RXCSUM) ? RCSR_CSUM : 0); 891 892 iow(db, DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */ 893 894 dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); /* PHY RESET */ 895 dm9000_phy_write(dev, 0, MII_DM_DSPCR, DSPCR_INIT_PARAM); /* Init */ 896 897 ncr = (db->flags & DM9000_PLATF_EXT_PHY) ? NCR_EXT_PHY : 0; 898 899 /* if wol is needed, then always set NCR_WAKEEN otherwise we end 900 * up dumping the wake events if we disable this. There is already 901 * a wake-mask in DM9000_WCR */ 902 if (db->wake_supported) 903 ncr |= NCR_WAKEEN; 904 905 iow(db, DM9000_NCR, ncr); 906 907 /* Program operating register */ 908 iow(db, DM9000_TCR, 0); /* TX Polling clear */ 909 iow(db, DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */ 910 iow(db, DM9000_FCR, 0xff); /* Flow Control */ 911 iow(db, DM9000_SMCR, 0); /* Special Mode */ 912 /* clear TX status */ 913 iow(db, DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); 914 iow(db, DM9000_ISR, ISR_CLR_STATUS); /* Clear interrupt status */ 915 916 /* Set address filter table */ 917 dm9000_hash_table_unlocked(dev); 918 919 imr = IMR_PAR | IMR_PTM | IMR_PRM; 920 if (db->type != TYPE_DM9000E) 921 imr |= IMR_LNKCHNG; 922 923 db->imr_all = imr; 924 925 /* Enable TX/RX interrupt mask */ 926 iow(db, DM9000_IMR, imr); 927 928 /* Init Driver variable */ 929 db->tx_pkt_cnt = 0; 930 db->queue_pkt_len = 0; 931 dev->trans_start = jiffies; 932 } 933 934 /* Our watchdog timed out. Called by the networking layer */ 935 static void dm9000_timeout(struct net_device *dev) 936 { 937 board_info_t *db = netdev_priv(dev); 938 u8 reg_save; 939 unsigned long flags; 940 941 /* Save previous register address */ 942 spin_lock_irqsave(&db->lock, flags); 943 reg_save = readb(db->io_addr); 944 945 netif_stop_queue(dev); 946 dm9000_reset(db); 947 dm9000_init_dm9000(dev); 948 /* We can accept TX packets again */ 949 dev->trans_start = jiffies; /* prevent tx timeout */ 950 netif_wake_queue(dev); 951 952 /* Restore previous register address */ 953 writeb(reg_save, db->io_addr); 954 spin_unlock_irqrestore(&db->lock, flags); 955 } 956 957 static void dm9000_send_packet(struct net_device *dev, 958 int ip_summed, 959 u16 pkt_len) 960 { 961 board_info_t *dm = to_dm9000_board(dev); 962 963 /* The DM9000 is not smart enough to leave fragmented packets alone. */ 964 if (dm->ip_summed != ip_summed) { 965 if (ip_summed == CHECKSUM_NONE) 966 iow(dm, DM9000_TCCR, 0); 967 else 968 iow(dm, DM9000_TCCR, TCCR_IP | TCCR_UDP | TCCR_TCP); 969 dm->ip_summed = ip_summed; 970 } 971 972 /* Set TX length to DM9000 */ 973 iow(dm, DM9000_TXPLL, pkt_len); 974 iow(dm, DM9000_TXPLH, pkt_len >> 8); 975 976 /* Issue TX polling command */ 977 iow(dm, DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */ 978 } 979 980 /* 981 * Hardware start transmission. 982 * Send a packet to media from the upper layer. 983 */ 984 static int 985 dm9000_start_xmit(struct sk_buff *skb, struct net_device *dev) 986 { 987 unsigned long flags; 988 board_info_t *db = netdev_priv(dev); 989 990 dm9000_dbg(db, 3, "%s:\n", __func__); 991 992 if (db->tx_pkt_cnt > 1) 993 return NETDEV_TX_BUSY; 994 995 spin_lock_irqsave(&db->lock, flags); 996 997 /* Move data to DM9000 TX RAM */ 998 writeb(DM9000_MWCMD, db->io_addr); 999 1000 (db->outblk)(db->io_data, skb->data, skb->len); 1001 dev->stats.tx_bytes += skb->len; 1002 1003 db->tx_pkt_cnt++; 1004 /* TX control: First packet immediately send, second packet queue */ 1005 if (db->tx_pkt_cnt == 1) { 1006 dm9000_send_packet(dev, skb->ip_summed, skb->len); 1007 } else { 1008 /* Second packet */ 1009 db->queue_pkt_len = skb->len; 1010 db->queue_ip_summed = skb->ip_summed; 1011 netif_stop_queue(dev); 1012 } 1013 1014 spin_unlock_irqrestore(&db->lock, flags); 1015 1016 /* free this SKB */ 1017 dev_kfree_skb(skb); 1018 1019 return NETDEV_TX_OK; 1020 } 1021 1022 /* 1023 * DM9000 interrupt handler 1024 * receive the packet to upper layer, free the transmitted packet 1025 */ 1026 1027 static void dm9000_tx_done(struct net_device *dev, board_info_t *db) 1028 { 1029 int tx_status = ior(db, DM9000_NSR); /* Got TX status */ 1030 1031 if (tx_status & (NSR_TX2END | NSR_TX1END)) { 1032 /* One packet sent complete */ 1033 db->tx_pkt_cnt--; 1034 dev->stats.tx_packets++; 1035 1036 if (netif_msg_tx_done(db)) 1037 dev_dbg(db->dev, "tx done, NSR %02x\n", tx_status); 1038 1039 /* Queue packet check & send */ 1040 if (db->tx_pkt_cnt > 0) 1041 dm9000_send_packet(dev, db->queue_ip_summed, 1042 db->queue_pkt_len); 1043 netif_wake_queue(dev); 1044 } 1045 } 1046 1047 struct dm9000_rxhdr { 1048 u8 RxPktReady; 1049 u8 RxStatus; 1050 __le16 RxLen; 1051 } __packed; 1052 1053 /* 1054 * Received a packet and pass to upper layer 1055 */ 1056 static void 1057 dm9000_rx(struct net_device *dev) 1058 { 1059 board_info_t *db = netdev_priv(dev); 1060 struct dm9000_rxhdr rxhdr; 1061 struct sk_buff *skb; 1062 u8 rxbyte, *rdptr; 1063 bool GoodPacket; 1064 int RxLen; 1065 1066 /* Check packet ready or not */ 1067 do { 1068 ior(db, DM9000_MRCMDX); /* Dummy read */ 1069 1070 /* Get most updated data */ 1071 rxbyte = readb(db->io_data); 1072 1073 /* Status check: this byte must be 0 or 1 */ 1074 if (rxbyte & DM9000_PKT_ERR) { 1075 dev_warn(db->dev, "status check fail: %d\n", rxbyte); 1076 iow(db, DM9000_RCR, 0x00); /* Stop Device */ 1077 iow(db, DM9000_ISR, IMR_PAR); /* Stop INT request */ 1078 return; 1079 } 1080 1081 if (!(rxbyte & DM9000_PKT_RDY)) 1082 return; 1083 1084 /* A packet ready now & Get status/length */ 1085 GoodPacket = true; 1086 writeb(DM9000_MRCMD, db->io_addr); 1087 1088 (db->inblk)(db->io_data, &rxhdr, sizeof(rxhdr)); 1089 1090 RxLen = le16_to_cpu(rxhdr.RxLen); 1091 1092 if (netif_msg_rx_status(db)) 1093 dev_dbg(db->dev, "RX: status %02x, length %04x\n", 1094 rxhdr.RxStatus, RxLen); 1095 1096 /* Packet Status check */ 1097 if (RxLen < 0x40) { 1098 GoodPacket = false; 1099 if (netif_msg_rx_err(db)) 1100 dev_dbg(db->dev, "RX: Bad Packet (runt)\n"); 1101 } 1102 1103 if (RxLen > DM9000_PKT_MAX) { 1104 dev_dbg(db->dev, "RST: RX Len:%x\n", RxLen); 1105 } 1106 1107 /* rxhdr.RxStatus is identical to RSR register. */ 1108 if (rxhdr.RxStatus & (RSR_FOE | RSR_CE | RSR_AE | 1109 RSR_PLE | RSR_RWTO | 1110 RSR_LCS | RSR_RF)) { 1111 GoodPacket = false; 1112 if (rxhdr.RxStatus & RSR_FOE) { 1113 if (netif_msg_rx_err(db)) 1114 dev_dbg(db->dev, "fifo error\n"); 1115 dev->stats.rx_fifo_errors++; 1116 } 1117 if (rxhdr.RxStatus & RSR_CE) { 1118 if (netif_msg_rx_err(db)) 1119 dev_dbg(db->dev, "crc error\n"); 1120 dev->stats.rx_crc_errors++; 1121 } 1122 if (rxhdr.RxStatus & RSR_RF) { 1123 if (netif_msg_rx_err(db)) 1124 dev_dbg(db->dev, "length error\n"); 1125 dev->stats.rx_length_errors++; 1126 } 1127 } 1128 1129 /* Move data from DM9000 */ 1130 if (GoodPacket && 1131 ((skb = netdev_alloc_skb(dev, RxLen + 4)) != NULL)) { 1132 skb_reserve(skb, 2); 1133 rdptr = (u8 *) skb_put(skb, RxLen - 4); 1134 1135 /* Read received packet from RX SRAM */ 1136 1137 (db->inblk)(db->io_data, rdptr, RxLen); 1138 dev->stats.rx_bytes += RxLen; 1139 1140 /* Pass to upper layer */ 1141 skb->protocol = eth_type_trans(skb, dev); 1142 if (dev->features & NETIF_F_RXCSUM) { 1143 if ((((rxbyte & 0x1c) << 3) & rxbyte) == 0) 1144 skb->ip_summed = CHECKSUM_UNNECESSARY; 1145 else 1146 skb_checksum_none_assert(skb); 1147 } 1148 netif_rx(skb); 1149 dev->stats.rx_packets++; 1150 1151 } else { 1152 /* need to dump the packet's data */ 1153 1154 (db->dumpblk)(db->io_data, RxLen); 1155 } 1156 } while (rxbyte & DM9000_PKT_RDY); 1157 } 1158 1159 static irqreturn_t dm9000_interrupt(int irq, void *dev_id) 1160 { 1161 struct net_device *dev = dev_id; 1162 board_info_t *db = netdev_priv(dev); 1163 int int_status; 1164 unsigned long flags; 1165 u8 reg_save; 1166 1167 dm9000_dbg(db, 3, "entering %s\n", __func__); 1168 1169 /* A real interrupt coming */ 1170 1171 /* holders of db->lock must always block IRQs */ 1172 spin_lock_irqsave(&db->lock, flags); 1173 1174 /* Save previous register address */ 1175 reg_save = readb(db->io_addr); 1176 1177 /* Disable all interrupts */ 1178 iow(db, DM9000_IMR, IMR_PAR); 1179 1180 /* Got DM9000 interrupt status */ 1181 int_status = ior(db, DM9000_ISR); /* Got ISR */ 1182 iow(db, DM9000_ISR, int_status); /* Clear ISR status */ 1183 1184 if (netif_msg_intr(db)) 1185 dev_dbg(db->dev, "interrupt status %02x\n", int_status); 1186 1187 /* Received the coming packet */ 1188 if (int_status & ISR_PRS) 1189 dm9000_rx(dev); 1190 1191 /* Trnasmit Interrupt check */ 1192 if (int_status & ISR_PTS) 1193 dm9000_tx_done(dev, db); 1194 1195 if (db->type != TYPE_DM9000E) { 1196 if (int_status & ISR_LNKCHNG) { 1197 /* fire a link-change request */ 1198 schedule_delayed_work(&db->phy_poll, 1); 1199 } 1200 } 1201 1202 /* Re-enable interrupt mask */ 1203 iow(db, DM9000_IMR, db->imr_all); 1204 1205 /* Restore previous register address */ 1206 writeb(reg_save, db->io_addr); 1207 1208 spin_unlock_irqrestore(&db->lock, flags); 1209 1210 return IRQ_HANDLED; 1211 } 1212 1213 static irqreturn_t dm9000_wol_interrupt(int irq, void *dev_id) 1214 { 1215 struct net_device *dev = dev_id; 1216 board_info_t *db = netdev_priv(dev); 1217 unsigned long flags; 1218 unsigned nsr, wcr; 1219 1220 spin_lock_irqsave(&db->lock, flags); 1221 1222 nsr = ior(db, DM9000_NSR); 1223 wcr = ior(db, DM9000_WCR); 1224 1225 dev_dbg(db->dev, "%s: NSR=0x%02x, WCR=0x%02x\n", __func__, nsr, wcr); 1226 1227 if (nsr & NSR_WAKEST) { 1228 /* clear, so we can avoid */ 1229 iow(db, DM9000_NSR, NSR_WAKEST); 1230 1231 if (wcr & WCR_LINKST) 1232 dev_info(db->dev, "wake by link status change\n"); 1233 if (wcr & WCR_SAMPLEST) 1234 dev_info(db->dev, "wake by sample packet\n"); 1235 if (wcr & WCR_MAGICST ) 1236 dev_info(db->dev, "wake by magic packet\n"); 1237 if (!(wcr & (WCR_LINKST | WCR_SAMPLEST | WCR_MAGICST))) 1238 dev_err(db->dev, "wake signalled with no reason? " 1239 "NSR=0x%02x, WSR=0x%02x\n", nsr, wcr); 1240 1241 } 1242 1243 spin_unlock_irqrestore(&db->lock, flags); 1244 1245 return (nsr & NSR_WAKEST) ? IRQ_HANDLED : IRQ_NONE; 1246 } 1247 1248 #ifdef CONFIG_NET_POLL_CONTROLLER 1249 /* 1250 *Used by netconsole 1251 */ 1252 static void dm9000_poll_controller(struct net_device *dev) 1253 { 1254 disable_irq(dev->irq); 1255 dm9000_interrupt(dev->irq, dev); 1256 enable_irq(dev->irq); 1257 } 1258 #endif 1259 1260 /* 1261 * Open the interface. 1262 * The interface is opened whenever "ifconfig" actives it. 1263 */ 1264 static int 1265 dm9000_open(struct net_device *dev) 1266 { 1267 board_info_t *db = netdev_priv(dev); 1268 unsigned long irqflags = db->irq_res->flags & IRQF_TRIGGER_MASK; 1269 1270 if (netif_msg_ifup(db)) 1271 dev_dbg(db->dev, "enabling %s\n", dev->name); 1272 1273 /* If there is no IRQ type specified, default to something that 1274 * may work, and tell the user that this is a problem */ 1275 1276 if (irqflags == IRQF_TRIGGER_NONE) 1277 dev_warn(db->dev, "WARNING: no IRQ resource flags set.\n"); 1278 1279 irqflags |= IRQF_SHARED; 1280 1281 /* GPIO0 on pre-activate PHY, Reg 1F is not set by reset */ 1282 iow(db, DM9000_GPR, 0); /* REG_1F bit0 activate phyxcer */ 1283 mdelay(1); /* delay needs by DM9000B */ 1284 1285 /* Initialize DM9000 board */ 1286 dm9000_reset(db); 1287 dm9000_init_dm9000(dev); 1288 1289 if (request_irq(dev->irq, dm9000_interrupt, irqflags, dev->name, dev)) 1290 return -EAGAIN; 1291 1292 /* Init driver variable */ 1293 db->dbug_cnt = 0; 1294 1295 mii_check_media(&db->mii, netif_msg_link(db), 1); 1296 netif_start_queue(dev); 1297 1298 dm9000_schedule_poll(db); 1299 1300 return 0; 1301 } 1302 1303 static void 1304 dm9000_shutdown(struct net_device *dev) 1305 { 1306 board_info_t *db = netdev_priv(dev); 1307 1308 /* RESET device */ 1309 dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); /* PHY RESET */ 1310 iow(db, DM9000_GPR, 0x01); /* Power-Down PHY */ 1311 iow(db, DM9000_IMR, IMR_PAR); /* Disable all interrupt */ 1312 iow(db, DM9000_RCR, 0x00); /* Disable RX */ 1313 } 1314 1315 /* 1316 * Stop the interface. 1317 * The interface is stopped when it is brought. 1318 */ 1319 static int 1320 dm9000_stop(struct net_device *ndev) 1321 { 1322 board_info_t *db = netdev_priv(ndev); 1323 1324 if (netif_msg_ifdown(db)) 1325 dev_dbg(db->dev, "shutting down %s\n", ndev->name); 1326 1327 cancel_delayed_work_sync(&db->phy_poll); 1328 1329 netif_stop_queue(ndev); 1330 netif_carrier_off(ndev); 1331 1332 /* free interrupt */ 1333 free_irq(ndev->irq, ndev); 1334 1335 dm9000_shutdown(ndev); 1336 1337 return 0; 1338 } 1339 1340 static const struct net_device_ops dm9000_netdev_ops = { 1341 .ndo_open = dm9000_open, 1342 .ndo_stop = dm9000_stop, 1343 .ndo_start_xmit = dm9000_start_xmit, 1344 .ndo_tx_timeout = dm9000_timeout, 1345 .ndo_set_rx_mode = dm9000_hash_table, 1346 .ndo_do_ioctl = dm9000_ioctl, 1347 .ndo_change_mtu = eth_change_mtu, 1348 .ndo_set_features = dm9000_set_features, 1349 .ndo_validate_addr = eth_validate_addr, 1350 .ndo_set_mac_address = eth_mac_addr, 1351 #ifdef CONFIG_NET_POLL_CONTROLLER 1352 .ndo_poll_controller = dm9000_poll_controller, 1353 #endif 1354 }; 1355 1356 static struct dm9000_plat_data *dm9000_parse_dt(struct device *dev) 1357 { 1358 struct dm9000_plat_data *pdata; 1359 struct device_node *np = dev->of_node; 1360 const void *mac_addr; 1361 1362 if (!IS_ENABLED(CONFIG_OF) || !np) 1363 return NULL; 1364 1365 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 1366 if (!pdata) 1367 return ERR_PTR(-ENOMEM); 1368 1369 if (of_find_property(np, "davicom,ext-phy", NULL)) 1370 pdata->flags |= DM9000_PLATF_EXT_PHY; 1371 if (of_find_property(np, "davicom,no-eeprom", NULL)) 1372 pdata->flags |= DM9000_PLATF_NO_EEPROM; 1373 1374 mac_addr = of_get_mac_address(np); 1375 if (mac_addr) 1376 memcpy(pdata->dev_addr, mac_addr, sizeof(pdata->dev_addr)); 1377 1378 return pdata; 1379 } 1380 1381 /* 1382 * Search DM9000 board, allocate space and register it 1383 */ 1384 static int 1385 dm9000_probe(struct platform_device *pdev) 1386 { 1387 struct dm9000_plat_data *pdata = dev_get_platdata(&pdev->dev); 1388 struct board_info *db; /* Point a board information structure */ 1389 struct net_device *ndev; 1390 const unsigned char *mac_src; 1391 int ret = 0; 1392 int iosize; 1393 int i; 1394 u32 id_val; 1395 1396 if (!pdata) { 1397 pdata = dm9000_parse_dt(&pdev->dev); 1398 if (IS_ERR(pdata)) 1399 return PTR_ERR(pdata); 1400 } 1401 1402 /* Init network device */ 1403 ndev = alloc_etherdev(sizeof(struct board_info)); 1404 if (!ndev) 1405 return -ENOMEM; 1406 1407 SET_NETDEV_DEV(ndev, &pdev->dev); 1408 1409 dev_dbg(&pdev->dev, "dm9000_probe()\n"); 1410 1411 /* setup board info structure */ 1412 db = netdev_priv(ndev); 1413 1414 db->dev = &pdev->dev; 1415 db->ndev = ndev; 1416 1417 spin_lock_init(&db->lock); 1418 mutex_init(&db->addr_lock); 1419 1420 INIT_DELAYED_WORK(&db->phy_poll, dm9000_poll_work); 1421 1422 db->addr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1423 db->data_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1424 db->irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1425 1426 if (db->addr_res == NULL || db->data_res == NULL || 1427 db->irq_res == NULL) { 1428 dev_err(db->dev, "insufficient resources\n"); 1429 ret = -ENOENT; 1430 goto out; 1431 } 1432 1433 db->irq_wake = platform_get_irq(pdev, 1); 1434 if (db->irq_wake >= 0) { 1435 dev_dbg(db->dev, "wakeup irq %d\n", db->irq_wake); 1436 1437 ret = request_irq(db->irq_wake, dm9000_wol_interrupt, 1438 IRQF_SHARED, dev_name(db->dev), ndev); 1439 if (ret) { 1440 dev_err(db->dev, "cannot get wakeup irq (%d)\n", ret); 1441 } else { 1442 1443 /* test to see if irq is really wakeup capable */ 1444 ret = irq_set_irq_wake(db->irq_wake, 1); 1445 if (ret) { 1446 dev_err(db->dev, "irq %d cannot set wakeup (%d)\n", 1447 db->irq_wake, ret); 1448 ret = 0; 1449 } else { 1450 irq_set_irq_wake(db->irq_wake, 0); 1451 db->wake_supported = 1; 1452 } 1453 } 1454 } 1455 1456 iosize = resource_size(db->addr_res); 1457 db->addr_req = request_mem_region(db->addr_res->start, iosize, 1458 pdev->name); 1459 1460 if (db->addr_req == NULL) { 1461 dev_err(db->dev, "cannot claim address reg area\n"); 1462 ret = -EIO; 1463 goto out; 1464 } 1465 1466 db->io_addr = ioremap(db->addr_res->start, iosize); 1467 1468 if (db->io_addr == NULL) { 1469 dev_err(db->dev, "failed to ioremap address reg\n"); 1470 ret = -EINVAL; 1471 goto out; 1472 } 1473 1474 iosize = resource_size(db->data_res); 1475 db->data_req = request_mem_region(db->data_res->start, iosize, 1476 pdev->name); 1477 1478 if (db->data_req == NULL) { 1479 dev_err(db->dev, "cannot claim data reg area\n"); 1480 ret = -EIO; 1481 goto out; 1482 } 1483 1484 db->io_data = ioremap(db->data_res->start, iosize); 1485 1486 if (db->io_data == NULL) { 1487 dev_err(db->dev, "failed to ioremap data reg\n"); 1488 ret = -EINVAL; 1489 goto out; 1490 } 1491 1492 /* fill in parameters for net-dev structure */ 1493 ndev->base_addr = (unsigned long)db->io_addr; 1494 ndev->irq = db->irq_res->start; 1495 1496 /* ensure at least we have a default set of IO routines */ 1497 dm9000_set_io(db, iosize); 1498 1499 /* check to see if anything is being over-ridden */ 1500 if (pdata != NULL) { 1501 /* check to see if the driver wants to over-ride the 1502 * default IO width */ 1503 1504 if (pdata->flags & DM9000_PLATF_8BITONLY) 1505 dm9000_set_io(db, 1); 1506 1507 if (pdata->flags & DM9000_PLATF_16BITONLY) 1508 dm9000_set_io(db, 2); 1509 1510 if (pdata->flags & DM9000_PLATF_32BITONLY) 1511 dm9000_set_io(db, 4); 1512 1513 /* check to see if there are any IO routine 1514 * over-rides */ 1515 1516 if (pdata->inblk != NULL) 1517 db->inblk = pdata->inblk; 1518 1519 if (pdata->outblk != NULL) 1520 db->outblk = pdata->outblk; 1521 1522 if (pdata->dumpblk != NULL) 1523 db->dumpblk = pdata->dumpblk; 1524 1525 db->flags = pdata->flags; 1526 } 1527 1528 #ifdef CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL 1529 db->flags |= DM9000_PLATF_SIMPLE_PHY; 1530 #endif 1531 1532 /* Fixing bug on dm9000_probe, takeover dm9000_reset(db), 1533 * Need 'NCR_MAC_LBK' bit to indeed stable our DM9000 fifo 1534 * while probe stage. 1535 */ 1536 1537 iow(db, DM9000_NCR, NCR_MAC_LBK | NCR_RST); 1538 1539 /* try multiple times, DM9000 sometimes gets the read wrong */ 1540 for (i = 0; i < 8; i++) { 1541 id_val = ior(db, DM9000_VIDL); 1542 id_val |= (u32)ior(db, DM9000_VIDH) << 8; 1543 id_val |= (u32)ior(db, DM9000_PIDL) << 16; 1544 id_val |= (u32)ior(db, DM9000_PIDH) << 24; 1545 1546 if (id_val == DM9000_ID) 1547 break; 1548 dev_err(db->dev, "read wrong id 0x%08x\n", id_val); 1549 } 1550 1551 if (id_val != DM9000_ID) { 1552 dev_err(db->dev, "wrong id: 0x%08x\n", id_val); 1553 ret = -ENODEV; 1554 goto out; 1555 } 1556 1557 /* Identify what type of DM9000 we are working on */ 1558 1559 id_val = ior(db, DM9000_CHIPR); 1560 dev_dbg(db->dev, "dm9000 revision 0x%02x\n", id_val); 1561 1562 switch (id_val) { 1563 case CHIPR_DM9000A: 1564 db->type = TYPE_DM9000A; 1565 break; 1566 case CHIPR_DM9000B: 1567 db->type = TYPE_DM9000B; 1568 break; 1569 default: 1570 dev_dbg(db->dev, "ID %02x => defaulting to DM9000E\n", id_val); 1571 db->type = TYPE_DM9000E; 1572 } 1573 1574 /* dm9000a/b are capable of hardware checksum offload */ 1575 if (db->type == TYPE_DM9000A || db->type == TYPE_DM9000B) { 1576 ndev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM; 1577 ndev->features |= ndev->hw_features; 1578 } 1579 1580 /* from this point we assume that we have found a DM9000 */ 1581 1582 /* driver system function */ 1583 ether_setup(ndev); 1584 1585 ndev->netdev_ops = &dm9000_netdev_ops; 1586 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 1587 ndev->ethtool_ops = &dm9000_ethtool_ops; 1588 1589 db->msg_enable = NETIF_MSG_LINK; 1590 db->mii.phy_id_mask = 0x1f; 1591 db->mii.reg_num_mask = 0x1f; 1592 db->mii.force_media = 0; 1593 db->mii.full_duplex = 0; 1594 db->mii.dev = ndev; 1595 db->mii.mdio_read = dm9000_phy_read; 1596 db->mii.mdio_write = dm9000_phy_write; 1597 1598 mac_src = "eeprom"; 1599 1600 /* try reading the node address from the attached EEPROM */ 1601 for (i = 0; i < 6; i += 2) 1602 dm9000_read_eeprom(db, i / 2, ndev->dev_addr+i); 1603 1604 if (!is_valid_ether_addr(ndev->dev_addr) && pdata != NULL) { 1605 mac_src = "platform data"; 1606 memcpy(ndev->dev_addr, pdata->dev_addr, 6); 1607 } 1608 1609 if (!is_valid_ether_addr(ndev->dev_addr)) { 1610 /* try reading from mac */ 1611 1612 mac_src = "chip"; 1613 for (i = 0; i < 6; i++) 1614 ndev->dev_addr[i] = ior(db, i+DM9000_PAR); 1615 } 1616 1617 if (!is_valid_ether_addr(ndev->dev_addr)) { 1618 dev_warn(db->dev, "%s: Invalid ethernet MAC address. Please " 1619 "set using ifconfig\n", ndev->name); 1620 1621 eth_hw_addr_random(ndev); 1622 mac_src = "random"; 1623 } 1624 1625 1626 platform_set_drvdata(pdev, ndev); 1627 ret = register_netdev(ndev); 1628 1629 if (ret == 0) 1630 printk(KERN_INFO "%s: dm9000%c at %p,%p IRQ %d MAC: %pM (%s)\n", 1631 ndev->name, dm9000_type_to_char(db->type), 1632 db->io_addr, db->io_data, ndev->irq, 1633 ndev->dev_addr, mac_src); 1634 return 0; 1635 1636 out: 1637 dev_err(db->dev, "not found (%d).\n", ret); 1638 1639 dm9000_release_board(pdev, db); 1640 free_netdev(ndev); 1641 1642 return ret; 1643 } 1644 1645 static int 1646 dm9000_drv_suspend(struct device *dev) 1647 { 1648 struct platform_device *pdev = to_platform_device(dev); 1649 struct net_device *ndev = platform_get_drvdata(pdev); 1650 board_info_t *db; 1651 1652 if (ndev) { 1653 db = netdev_priv(ndev); 1654 db->in_suspend = 1; 1655 1656 if (!netif_running(ndev)) 1657 return 0; 1658 1659 netif_device_detach(ndev); 1660 1661 /* only shutdown if not using WoL */ 1662 if (!db->wake_state) 1663 dm9000_shutdown(ndev); 1664 } 1665 return 0; 1666 } 1667 1668 static int 1669 dm9000_drv_resume(struct device *dev) 1670 { 1671 struct platform_device *pdev = to_platform_device(dev); 1672 struct net_device *ndev = platform_get_drvdata(pdev); 1673 board_info_t *db = netdev_priv(ndev); 1674 1675 if (ndev) { 1676 if (netif_running(ndev)) { 1677 /* reset if we were not in wake mode to ensure if 1678 * the device was powered off it is in a known state */ 1679 if (!db->wake_state) { 1680 dm9000_reset(db); 1681 dm9000_init_dm9000(ndev); 1682 } 1683 1684 netif_device_attach(ndev); 1685 } 1686 1687 db->in_suspend = 0; 1688 } 1689 return 0; 1690 } 1691 1692 static const struct dev_pm_ops dm9000_drv_pm_ops = { 1693 .suspend = dm9000_drv_suspend, 1694 .resume = dm9000_drv_resume, 1695 }; 1696 1697 static int 1698 dm9000_drv_remove(struct platform_device *pdev) 1699 { 1700 struct net_device *ndev = platform_get_drvdata(pdev); 1701 1702 unregister_netdev(ndev); 1703 dm9000_release_board(pdev, netdev_priv(ndev)); 1704 free_netdev(ndev); /* free device structure */ 1705 1706 dev_dbg(&pdev->dev, "released and freed device\n"); 1707 return 0; 1708 } 1709 1710 #ifdef CONFIG_OF 1711 static const struct of_device_id dm9000_of_matches[] = { 1712 { .compatible = "davicom,dm9000", }, 1713 { /* sentinel */ } 1714 }; 1715 MODULE_DEVICE_TABLE(of, dm9000_of_matches); 1716 #endif 1717 1718 static struct platform_driver dm9000_driver = { 1719 .driver = { 1720 .name = "dm9000", 1721 .owner = THIS_MODULE, 1722 .pm = &dm9000_drv_pm_ops, 1723 .of_match_table = of_match_ptr(dm9000_of_matches), 1724 }, 1725 .probe = dm9000_probe, 1726 .remove = dm9000_drv_remove, 1727 }; 1728 1729 module_platform_driver(dm9000_driver); 1730 1731 MODULE_AUTHOR("Sascha Hauer, Ben Dooks"); 1732 MODULE_DESCRIPTION("Davicom DM9000 network driver"); 1733 MODULE_LICENSE("GPL"); 1734 MODULE_ALIAS("platform:dm9000"); 1735