1 /* 2 * Davicom DM9000 Fast Ethernet driver for Linux. 3 * Copyright (C) 1997 Sten Wang 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 2 8 * of the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * (C) Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved. 16 * 17 * Additional updates, Copyright: 18 * Ben Dooks <ben@simtec.co.uk> 19 * Sascha Hauer <s.hauer@pengutronix.de> 20 */ 21 22 #include <linux/module.h> 23 #include <linux/ioport.h> 24 #include <linux/netdevice.h> 25 #include <linux/etherdevice.h> 26 #include <linux/init.h> 27 #include <linux/interrupt.h> 28 #include <linux/skbuff.h> 29 #include <linux/spinlock.h> 30 #include <linux/crc32.h> 31 #include <linux/mii.h> 32 #include <linux/ethtool.h> 33 #include <linux/dm9000.h> 34 #include <linux/delay.h> 35 #include <linux/platform_device.h> 36 #include <linux/irq.h> 37 #include <linux/slab.h> 38 39 #include <asm/delay.h> 40 #include <asm/irq.h> 41 #include <asm/io.h> 42 43 #include "dm9000.h" 44 45 /* Board/System/Debug information/definition ---------------- */ 46 47 #define DM9000_PHY 0x40 /* PHY address 0x01 */ 48 49 #define CARDNAME "dm9000" 50 #define DRV_VERSION "1.31" 51 52 /* 53 * Transmit timeout, default 5 seconds. 54 */ 55 static int watchdog = 5000; 56 module_param(watchdog, int, 0400); 57 MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds"); 58 59 /* 60 * Debug messages level 61 */ 62 static int debug; 63 module_param(debug, int, 0644); 64 MODULE_PARM_DESC(debug, "dm9000 debug level (0-4)"); 65 66 /* DM9000 register address locking. 67 * 68 * The DM9000 uses an address register to control where data written 69 * to the data register goes. This means that the address register 70 * must be preserved over interrupts or similar calls. 71 * 72 * During interrupt and other critical calls, a spinlock is used to 73 * protect the system, but the calls themselves save the address 74 * in the address register in case they are interrupting another 75 * access to the device. 76 * 77 * For general accesses a lock is provided so that calls which are 78 * allowed to sleep are serialised so that the address register does 79 * not need to be saved. This lock also serves to serialise access 80 * to the EEPROM and PHY access registers which are shared between 81 * these two devices. 82 */ 83 84 /* The driver supports the original DM9000E, and now the two newer 85 * devices, DM9000A and DM9000B. 86 */ 87 88 enum dm9000_type { 89 TYPE_DM9000E, /* original DM9000 */ 90 TYPE_DM9000A, 91 TYPE_DM9000B 92 }; 93 94 /* Structure/enum declaration ------------------------------- */ 95 typedef struct board_info { 96 97 void __iomem *io_addr; /* Register I/O base address */ 98 void __iomem *io_data; /* Data I/O address */ 99 u16 irq; /* IRQ */ 100 101 u16 tx_pkt_cnt; 102 u16 queue_pkt_len; 103 u16 queue_start_addr; 104 u16 queue_ip_summed; 105 u16 dbug_cnt; 106 u8 io_mode; /* 0:word, 2:byte */ 107 u8 phy_addr; 108 u8 imr_all; 109 110 unsigned int flags; 111 unsigned int in_suspend :1; 112 unsigned int wake_supported :1; 113 114 enum dm9000_type type; 115 116 void (*inblk)(void __iomem *port, void *data, int length); 117 void (*outblk)(void __iomem *port, void *data, int length); 118 void (*dumpblk)(void __iomem *port, int length); 119 120 struct device *dev; /* parent device */ 121 122 struct resource *addr_res; /* resources found */ 123 struct resource *data_res; 124 struct resource *addr_req; /* resources requested */ 125 struct resource *data_req; 126 struct resource *irq_res; 127 128 int irq_wake; 129 130 struct mutex addr_lock; /* phy and eeprom access lock */ 131 132 struct delayed_work phy_poll; 133 struct net_device *ndev; 134 135 spinlock_t lock; 136 137 struct mii_if_info mii; 138 u32 msg_enable; 139 u32 wake_state; 140 141 int ip_summed; 142 } board_info_t; 143 144 /* debug code */ 145 146 #define dm9000_dbg(db, lev, msg...) do { \ 147 if ((lev) < debug) { \ 148 dev_dbg(db->dev, msg); \ 149 } \ 150 } while (0) 151 152 static inline board_info_t *to_dm9000_board(struct net_device *dev) 153 { 154 return netdev_priv(dev); 155 } 156 157 /* DM9000 network board routine ---------------------------- */ 158 159 static void 160 dm9000_reset(board_info_t * db) 161 { 162 dev_dbg(db->dev, "resetting device\n"); 163 164 /* RESET device */ 165 writeb(DM9000_NCR, db->io_addr); 166 udelay(200); 167 writeb(NCR_RST, db->io_data); 168 udelay(200); 169 } 170 171 /* 172 * Read a byte from I/O port 173 */ 174 static u8 175 ior(board_info_t * db, int reg) 176 { 177 writeb(reg, db->io_addr); 178 return readb(db->io_data); 179 } 180 181 /* 182 * Write a byte to I/O port 183 */ 184 185 static void 186 iow(board_info_t * db, int reg, int value) 187 { 188 writeb(reg, db->io_addr); 189 writeb(value, db->io_data); 190 } 191 192 /* routines for sending block to chip */ 193 194 static void dm9000_outblk_8bit(void __iomem *reg, void *data, int count) 195 { 196 iowrite8_rep(reg, data, count); 197 } 198 199 static void dm9000_outblk_16bit(void __iomem *reg, void *data, int count) 200 { 201 iowrite16_rep(reg, data, (count+1) >> 1); 202 } 203 204 static void dm9000_outblk_32bit(void __iomem *reg, void *data, int count) 205 { 206 iowrite32_rep(reg, data, (count+3) >> 2); 207 } 208 209 /* input block from chip to memory */ 210 211 static void dm9000_inblk_8bit(void __iomem *reg, void *data, int count) 212 { 213 ioread8_rep(reg, data, count); 214 } 215 216 217 static void dm9000_inblk_16bit(void __iomem *reg, void *data, int count) 218 { 219 ioread16_rep(reg, data, (count+1) >> 1); 220 } 221 222 static void dm9000_inblk_32bit(void __iomem *reg, void *data, int count) 223 { 224 ioread32_rep(reg, data, (count+3) >> 2); 225 } 226 227 /* dump block from chip to null */ 228 229 static void dm9000_dumpblk_8bit(void __iomem *reg, int count) 230 { 231 int i; 232 int tmp; 233 234 for (i = 0; i < count; i++) 235 tmp = readb(reg); 236 } 237 238 static void dm9000_dumpblk_16bit(void __iomem *reg, int count) 239 { 240 int i; 241 int tmp; 242 243 count = (count + 1) >> 1; 244 245 for (i = 0; i < count; i++) 246 tmp = readw(reg); 247 } 248 249 static void dm9000_dumpblk_32bit(void __iomem *reg, int count) 250 { 251 int i; 252 int tmp; 253 254 count = (count + 3) >> 2; 255 256 for (i = 0; i < count; i++) 257 tmp = readl(reg); 258 } 259 260 /* dm9000_set_io 261 * 262 * select the specified set of io routines to use with the 263 * device 264 */ 265 266 static void dm9000_set_io(struct board_info *db, int byte_width) 267 { 268 /* use the size of the data resource to work out what IO 269 * routines we want to use 270 */ 271 272 switch (byte_width) { 273 case 1: 274 db->dumpblk = dm9000_dumpblk_8bit; 275 db->outblk = dm9000_outblk_8bit; 276 db->inblk = dm9000_inblk_8bit; 277 break; 278 279 280 case 3: 281 dev_dbg(db->dev, ": 3 byte IO, falling back to 16bit\n"); 282 case 2: 283 db->dumpblk = dm9000_dumpblk_16bit; 284 db->outblk = dm9000_outblk_16bit; 285 db->inblk = dm9000_inblk_16bit; 286 break; 287 288 case 4: 289 default: 290 db->dumpblk = dm9000_dumpblk_32bit; 291 db->outblk = dm9000_outblk_32bit; 292 db->inblk = dm9000_inblk_32bit; 293 break; 294 } 295 } 296 297 static void dm9000_schedule_poll(board_info_t *db) 298 { 299 if (db->type == TYPE_DM9000E) 300 schedule_delayed_work(&db->phy_poll, HZ * 2); 301 } 302 303 static int dm9000_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 304 { 305 board_info_t *dm = to_dm9000_board(dev); 306 307 if (!netif_running(dev)) 308 return -EINVAL; 309 310 return generic_mii_ioctl(&dm->mii, if_mii(req), cmd, NULL); 311 } 312 313 static unsigned int 314 dm9000_read_locked(board_info_t *db, int reg) 315 { 316 unsigned long flags; 317 unsigned int ret; 318 319 spin_lock_irqsave(&db->lock, flags); 320 ret = ior(db, reg); 321 spin_unlock_irqrestore(&db->lock, flags); 322 323 return ret; 324 } 325 326 static int dm9000_wait_eeprom(board_info_t *db) 327 { 328 unsigned int status; 329 int timeout = 8; /* wait max 8msec */ 330 331 /* The DM9000 data sheets say we should be able to 332 * poll the ERRE bit in EPCR to wait for the EEPROM 333 * operation. From testing several chips, this bit 334 * does not seem to work. 335 * 336 * We attempt to use the bit, but fall back to the 337 * timeout (which is why we do not return an error 338 * on expiry) to say that the EEPROM operation has 339 * completed. 340 */ 341 342 while (1) { 343 status = dm9000_read_locked(db, DM9000_EPCR); 344 345 if ((status & EPCR_ERRE) == 0) 346 break; 347 348 msleep(1); 349 350 if (timeout-- < 0) { 351 dev_dbg(db->dev, "timeout waiting EEPROM\n"); 352 break; 353 } 354 } 355 356 return 0; 357 } 358 359 /* 360 * Read a word data from EEPROM 361 */ 362 static void 363 dm9000_read_eeprom(board_info_t *db, int offset, u8 *to) 364 { 365 unsigned long flags; 366 367 if (db->flags & DM9000_PLATF_NO_EEPROM) { 368 to[0] = 0xff; 369 to[1] = 0xff; 370 return; 371 } 372 373 mutex_lock(&db->addr_lock); 374 375 spin_lock_irqsave(&db->lock, flags); 376 377 iow(db, DM9000_EPAR, offset); 378 iow(db, DM9000_EPCR, EPCR_ERPRR); 379 380 spin_unlock_irqrestore(&db->lock, flags); 381 382 dm9000_wait_eeprom(db); 383 384 /* delay for at-least 150uS */ 385 msleep(1); 386 387 spin_lock_irqsave(&db->lock, flags); 388 389 iow(db, DM9000_EPCR, 0x0); 390 391 to[0] = ior(db, DM9000_EPDRL); 392 to[1] = ior(db, DM9000_EPDRH); 393 394 spin_unlock_irqrestore(&db->lock, flags); 395 396 mutex_unlock(&db->addr_lock); 397 } 398 399 /* 400 * Write a word data to SROM 401 */ 402 static void 403 dm9000_write_eeprom(board_info_t *db, int offset, u8 *data) 404 { 405 unsigned long flags; 406 407 if (db->flags & DM9000_PLATF_NO_EEPROM) 408 return; 409 410 mutex_lock(&db->addr_lock); 411 412 spin_lock_irqsave(&db->lock, flags); 413 iow(db, DM9000_EPAR, offset); 414 iow(db, DM9000_EPDRH, data[1]); 415 iow(db, DM9000_EPDRL, data[0]); 416 iow(db, DM9000_EPCR, EPCR_WEP | EPCR_ERPRW); 417 spin_unlock_irqrestore(&db->lock, flags); 418 419 dm9000_wait_eeprom(db); 420 421 mdelay(1); /* wait at least 150uS to clear */ 422 423 spin_lock_irqsave(&db->lock, flags); 424 iow(db, DM9000_EPCR, 0); 425 spin_unlock_irqrestore(&db->lock, flags); 426 427 mutex_unlock(&db->addr_lock); 428 } 429 430 /* ethtool ops */ 431 432 static void dm9000_get_drvinfo(struct net_device *dev, 433 struct ethtool_drvinfo *info) 434 { 435 board_info_t *dm = to_dm9000_board(dev); 436 437 strlcpy(info->driver, CARDNAME, sizeof(info->driver)); 438 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 439 strlcpy(info->bus_info, to_platform_device(dm->dev)->name, 440 sizeof(info->bus_info)); 441 } 442 443 static u32 dm9000_get_msglevel(struct net_device *dev) 444 { 445 board_info_t *dm = to_dm9000_board(dev); 446 447 return dm->msg_enable; 448 } 449 450 static void dm9000_set_msglevel(struct net_device *dev, u32 value) 451 { 452 board_info_t *dm = to_dm9000_board(dev); 453 454 dm->msg_enable = value; 455 } 456 457 static int dm9000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 458 { 459 board_info_t *dm = to_dm9000_board(dev); 460 461 mii_ethtool_gset(&dm->mii, cmd); 462 return 0; 463 } 464 465 static int dm9000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 466 { 467 board_info_t *dm = to_dm9000_board(dev); 468 469 return mii_ethtool_sset(&dm->mii, cmd); 470 } 471 472 static int dm9000_nway_reset(struct net_device *dev) 473 { 474 board_info_t *dm = to_dm9000_board(dev); 475 return mii_nway_restart(&dm->mii); 476 } 477 478 static int dm9000_set_features(struct net_device *dev, 479 netdev_features_t features) 480 { 481 board_info_t *dm = to_dm9000_board(dev); 482 netdev_features_t changed = dev->features ^ features; 483 unsigned long flags; 484 485 if (!(changed & NETIF_F_RXCSUM)) 486 return 0; 487 488 spin_lock_irqsave(&dm->lock, flags); 489 iow(dm, DM9000_RCSR, (features & NETIF_F_RXCSUM) ? RCSR_CSUM : 0); 490 spin_unlock_irqrestore(&dm->lock, flags); 491 492 return 0; 493 } 494 495 static u32 dm9000_get_link(struct net_device *dev) 496 { 497 board_info_t *dm = to_dm9000_board(dev); 498 u32 ret; 499 500 if (dm->flags & DM9000_PLATF_EXT_PHY) 501 ret = mii_link_ok(&dm->mii); 502 else 503 ret = dm9000_read_locked(dm, DM9000_NSR) & NSR_LINKST ? 1 : 0; 504 505 return ret; 506 } 507 508 #define DM_EEPROM_MAGIC (0x444D394B) 509 510 static int dm9000_get_eeprom_len(struct net_device *dev) 511 { 512 return 128; 513 } 514 515 static int dm9000_get_eeprom(struct net_device *dev, 516 struct ethtool_eeprom *ee, u8 *data) 517 { 518 board_info_t *dm = to_dm9000_board(dev); 519 int offset = ee->offset; 520 int len = ee->len; 521 int i; 522 523 /* EEPROM access is aligned to two bytes */ 524 525 if ((len & 1) != 0 || (offset & 1) != 0) 526 return -EINVAL; 527 528 if (dm->flags & DM9000_PLATF_NO_EEPROM) 529 return -ENOENT; 530 531 ee->magic = DM_EEPROM_MAGIC; 532 533 for (i = 0; i < len; i += 2) 534 dm9000_read_eeprom(dm, (offset + i) / 2, data + i); 535 536 return 0; 537 } 538 539 static int dm9000_set_eeprom(struct net_device *dev, 540 struct ethtool_eeprom *ee, u8 *data) 541 { 542 board_info_t *dm = to_dm9000_board(dev); 543 int offset = ee->offset; 544 int len = ee->len; 545 int done; 546 547 /* EEPROM access is aligned to two bytes */ 548 549 if (dm->flags & DM9000_PLATF_NO_EEPROM) 550 return -ENOENT; 551 552 if (ee->magic != DM_EEPROM_MAGIC) 553 return -EINVAL; 554 555 while (len > 0) { 556 if (len & 1 || offset & 1) { 557 int which = offset & 1; 558 u8 tmp[2]; 559 560 dm9000_read_eeprom(dm, offset / 2, tmp); 561 tmp[which] = *data; 562 dm9000_write_eeprom(dm, offset / 2, tmp); 563 564 done = 1; 565 } else { 566 dm9000_write_eeprom(dm, offset / 2, data); 567 done = 2; 568 } 569 570 data += done; 571 offset += done; 572 len -= done; 573 } 574 575 return 0; 576 } 577 578 static void dm9000_get_wol(struct net_device *dev, struct ethtool_wolinfo *w) 579 { 580 board_info_t *dm = to_dm9000_board(dev); 581 582 memset(w, 0, sizeof(struct ethtool_wolinfo)); 583 584 /* note, we could probably support wake-phy too */ 585 w->supported = dm->wake_supported ? WAKE_MAGIC : 0; 586 w->wolopts = dm->wake_state; 587 } 588 589 static int dm9000_set_wol(struct net_device *dev, struct ethtool_wolinfo *w) 590 { 591 board_info_t *dm = to_dm9000_board(dev); 592 unsigned long flags; 593 u32 opts = w->wolopts; 594 u32 wcr = 0; 595 596 if (!dm->wake_supported) 597 return -EOPNOTSUPP; 598 599 if (opts & ~WAKE_MAGIC) 600 return -EINVAL; 601 602 if (opts & WAKE_MAGIC) 603 wcr |= WCR_MAGICEN; 604 605 mutex_lock(&dm->addr_lock); 606 607 spin_lock_irqsave(&dm->lock, flags); 608 iow(dm, DM9000_WCR, wcr); 609 spin_unlock_irqrestore(&dm->lock, flags); 610 611 mutex_unlock(&dm->addr_lock); 612 613 if (dm->wake_state != opts) { 614 /* change in wol state, update IRQ state */ 615 616 if (!dm->wake_state) 617 irq_set_irq_wake(dm->irq_wake, 1); 618 else if (dm->wake_state && !opts) 619 irq_set_irq_wake(dm->irq_wake, 0); 620 } 621 622 dm->wake_state = opts; 623 return 0; 624 } 625 626 static const struct ethtool_ops dm9000_ethtool_ops = { 627 .get_drvinfo = dm9000_get_drvinfo, 628 .get_settings = dm9000_get_settings, 629 .set_settings = dm9000_set_settings, 630 .get_msglevel = dm9000_get_msglevel, 631 .set_msglevel = dm9000_set_msglevel, 632 .nway_reset = dm9000_nway_reset, 633 .get_link = dm9000_get_link, 634 .get_wol = dm9000_get_wol, 635 .set_wol = dm9000_set_wol, 636 .get_eeprom_len = dm9000_get_eeprom_len, 637 .get_eeprom = dm9000_get_eeprom, 638 .set_eeprom = dm9000_set_eeprom, 639 }; 640 641 static void dm9000_show_carrier(board_info_t *db, 642 unsigned carrier, unsigned nsr) 643 { 644 struct net_device *ndev = db->ndev; 645 unsigned ncr = dm9000_read_locked(db, DM9000_NCR); 646 647 if (carrier) 648 dev_info(db->dev, "%s: link up, %dMbps, %s-duplex, no LPA\n", 649 ndev->name, (nsr & NSR_SPEED) ? 10 : 100, 650 (ncr & NCR_FDX) ? "full" : "half"); 651 else 652 dev_info(db->dev, "%s: link down\n", ndev->name); 653 } 654 655 static void 656 dm9000_poll_work(struct work_struct *w) 657 { 658 struct delayed_work *dw = to_delayed_work(w); 659 board_info_t *db = container_of(dw, board_info_t, phy_poll); 660 struct net_device *ndev = db->ndev; 661 662 if (db->flags & DM9000_PLATF_SIMPLE_PHY && 663 !(db->flags & DM9000_PLATF_EXT_PHY)) { 664 unsigned nsr = dm9000_read_locked(db, DM9000_NSR); 665 unsigned old_carrier = netif_carrier_ok(ndev) ? 1 : 0; 666 unsigned new_carrier; 667 668 new_carrier = (nsr & NSR_LINKST) ? 1 : 0; 669 670 if (old_carrier != new_carrier) { 671 if (netif_msg_link(db)) 672 dm9000_show_carrier(db, new_carrier, nsr); 673 674 if (!new_carrier) 675 netif_carrier_off(ndev); 676 else 677 netif_carrier_on(ndev); 678 } 679 } else 680 mii_check_media(&db->mii, netif_msg_link(db), 0); 681 682 if (netif_running(ndev)) 683 dm9000_schedule_poll(db); 684 } 685 686 /* dm9000_release_board 687 * 688 * release a board, and any mapped resources 689 */ 690 691 static void 692 dm9000_release_board(struct platform_device *pdev, struct board_info *db) 693 { 694 /* unmap our resources */ 695 696 iounmap(db->io_addr); 697 iounmap(db->io_data); 698 699 /* release the resources */ 700 701 release_resource(db->data_req); 702 kfree(db->data_req); 703 704 release_resource(db->addr_req); 705 kfree(db->addr_req); 706 } 707 708 static unsigned char dm9000_type_to_char(enum dm9000_type type) 709 { 710 switch (type) { 711 case TYPE_DM9000E: return 'e'; 712 case TYPE_DM9000A: return 'a'; 713 case TYPE_DM9000B: return 'b'; 714 } 715 716 return '?'; 717 } 718 719 /* 720 * Set DM9000 multicast address 721 */ 722 static void 723 dm9000_hash_table_unlocked(struct net_device *dev) 724 { 725 board_info_t *db = netdev_priv(dev); 726 struct netdev_hw_addr *ha; 727 int i, oft; 728 u32 hash_val; 729 u16 hash_table[4]; 730 u8 rcr = RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN; 731 732 dm9000_dbg(db, 1, "entering %s\n", __func__); 733 734 for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++) 735 iow(db, oft, dev->dev_addr[i]); 736 737 /* Clear Hash Table */ 738 for (i = 0; i < 4; i++) 739 hash_table[i] = 0x0; 740 741 /* broadcast address */ 742 hash_table[3] = 0x8000; 743 744 if (dev->flags & IFF_PROMISC) 745 rcr |= RCR_PRMSC; 746 747 if (dev->flags & IFF_ALLMULTI) 748 rcr |= RCR_ALL; 749 750 /* the multicast address in Hash Table : 64 bits */ 751 netdev_for_each_mc_addr(ha, dev) { 752 hash_val = ether_crc_le(6, ha->addr) & 0x3f; 753 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16); 754 } 755 756 /* Write the hash table to MAC MD table */ 757 for (i = 0, oft = DM9000_MAR; i < 4; i++) { 758 iow(db, oft++, hash_table[i]); 759 iow(db, oft++, hash_table[i] >> 8); 760 } 761 762 iow(db, DM9000_RCR, rcr); 763 } 764 765 static void 766 dm9000_hash_table(struct net_device *dev) 767 { 768 board_info_t *db = netdev_priv(dev); 769 unsigned long flags; 770 771 spin_lock_irqsave(&db->lock, flags); 772 dm9000_hash_table_unlocked(dev); 773 spin_unlock_irqrestore(&db->lock, flags); 774 } 775 776 /* 777 * Initialize dm9000 board 778 */ 779 static void 780 dm9000_init_dm9000(struct net_device *dev) 781 { 782 board_info_t *db = netdev_priv(dev); 783 unsigned int imr; 784 unsigned int ncr; 785 786 dm9000_dbg(db, 1, "entering %s\n", __func__); 787 788 /* I/O mode */ 789 db->io_mode = ior(db, DM9000_ISR) >> 6; /* ISR bit7:6 keeps I/O mode */ 790 791 /* Checksum mode */ 792 if (dev->hw_features & NETIF_F_RXCSUM) 793 iow(db, DM9000_RCSR, 794 (dev->features & NETIF_F_RXCSUM) ? RCSR_CSUM : 0); 795 796 iow(db, DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */ 797 798 ncr = (db->flags & DM9000_PLATF_EXT_PHY) ? NCR_EXT_PHY : 0; 799 800 /* if wol is needed, then always set NCR_WAKEEN otherwise we end 801 * up dumping the wake events if we disable this. There is already 802 * a wake-mask in DM9000_WCR */ 803 if (db->wake_supported) 804 ncr |= NCR_WAKEEN; 805 806 iow(db, DM9000_NCR, ncr); 807 808 /* Program operating register */ 809 iow(db, DM9000_TCR, 0); /* TX Polling clear */ 810 iow(db, DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */ 811 iow(db, DM9000_FCR, 0xff); /* Flow Control */ 812 iow(db, DM9000_SMCR, 0); /* Special Mode */ 813 /* clear TX status */ 814 iow(db, DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); 815 iow(db, DM9000_ISR, ISR_CLR_STATUS); /* Clear interrupt status */ 816 817 /* Set address filter table */ 818 dm9000_hash_table_unlocked(dev); 819 820 imr = IMR_PAR | IMR_PTM | IMR_PRM; 821 if (db->type != TYPE_DM9000E) 822 imr |= IMR_LNKCHNG; 823 824 db->imr_all = imr; 825 826 /* Enable TX/RX interrupt mask */ 827 iow(db, DM9000_IMR, imr); 828 829 /* Init Driver variable */ 830 db->tx_pkt_cnt = 0; 831 db->queue_pkt_len = 0; 832 dev->trans_start = jiffies; 833 } 834 835 /* Our watchdog timed out. Called by the networking layer */ 836 static void dm9000_timeout(struct net_device *dev) 837 { 838 board_info_t *db = netdev_priv(dev); 839 u8 reg_save; 840 unsigned long flags; 841 842 /* Save previous register address */ 843 spin_lock_irqsave(&db->lock, flags); 844 reg_save = readb(db->io_addr); 845 846 netif_stop_queue(dev); 847 dm9000_reset(db); 848 dm9000_init_dm9000(dev); 849 /* We can accept TX packets again */ 850 dev->trans_start = jiffies; /* prevent tx timeout */ 851 netif_wake_queue(dev); 852 853 /* Restore previous register address */ 854 writeb(reg_save, db->io_addr); 855 spin_unlock_irqrestore(&db->lock, flags); 856 } 857 858 static void dm9000_send_packet(struct net_device *dev, 859 int ip_summed, 860 u16 pkt_len) 861 { 862 board_info_t *dm = to_dm9000_board(dev); 863 864 /* The DM9000 is not smart enough to leave fragmented packets alone. */ 865 if (dm->ip_summed != ip_summed) { 866 if (ip_summed == CHECKSUM_NONE) 867 iow(dm, DM9000_TCCR, 0); 868 else 869 iow(dm, DM9000_TCCR, TCCR_IP | TCCR_UDP | TCCR_TCP); 870 dm->ip_summed = ip_summed; 871 } 872 873 /* Set TX length to DM9000 */ 874 iow(dm, DM9000_TXPLL, pkt_len); 875 iow(dm, DM9000_TXPLH, pkt_len >> 8); 876 877 /* Issue TX polling command */ 878 iow(dm, DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */ 879 } 880 881 /* 882 * Hardware start transmission. 883 * Send a packet to media from the upper layer. 884 */ 885 static int 886 dm9000_start_xmit(struct sk_buff *skb, struct net_device *dev) 887 { 888 unsigned long flags; 889 board_info_t *db = netdev_priv(dev); 890 891 dm9000_dbg(db, 3, "%s:\n", __func__); 892 893 if (db->tx_pkt_cnt > 1) 894 return NETDEV_TX_BUSY; 895 896 spin_lock_irqsave(&db->lock, flags); 897 898 /* Move data to DM9000 TX RAM */ 899 writeb(DM9000_MWCMD, db->io_addr); 900 901 (db->outblk)(db->io_data, skb->data, skb->len); 902 dev->stats.tx_bytes += skb->len; 903 904 db->tx_pkt_cnt++; 905 /* TX control: First packet immediately send, second packet queue */ 906 if (db->tx_pkt_cnt == 1) { 907 dm9000_send_packet(dev, skb->ip_summed, skb->len); 908 } else { 909 /* Second packet */ 910 db->queue_pkt_len = skb->len; 911 db->queue_ip_summed = skb->ip_summed; 912 netif_stop_queue(dev); 913 } 914 915 spin_unlock_irqrestore(&db->lock, flags); 916 917 /* free this SKB */ 918 dev_kfree_skb(skb); 919 920 return NETDEV_TX_OK; 921 } 922 923 /* 924 * DM9000 interrupt handler 925 * receive the packet to upper layer, free the transmitted packet 926 */ 927 928 static void dm9000_tx_done(struct net_device *dev, board_info_t *db) 929 { 930 int tx_status = ior(db, DM9000_NSR); /* Got TX status */ 931 932 if (tx_status & (NSR_TX2END | NSR_TX1END)) { 933 /* One packet sent complete */ 934 db->tx_pkt_cnt--; 935 dev->stats.tx_packets++; 936 937 if (netif_msg_tx_done(db)) 938 dev_dbg(db->dev, "tx done, NSR %02x\n", tx_status); 939 940 /* Queue packet check & send */ 941 if (db->tx_pkt_cnt > 0) 942 dm9000_send_packet(dev, db->queue_ip_summed, 943 db->queue_pkt_len); 944 netif_wake_queue(dev); 945 } 946 } 947 948 struct dm9000_rxhdr { 949 u8 RxPktReady; 950 u8 RxStatus; 951 __le16 RxLen; 952 } __packed; 953 954 /* 955 * Received a packet and pass to upper layer 956 */ 957 static void 958 dm9000_rx(struct net_device *dev) 959 { 960 board_info_t *db = netdev_priv(dev); 961 struct dm9000_rxhdr rxhdr; 962 struct sk_buff *skb; 963 u8 rxbyte, *rdptr; 964 bool GoodPacket; 965 int RxLen; 966 967 /* Check packet ready or not */ 968 do { 969 ior(db, DM9000_MRCMDX); /* Dummy read */ 970 971 /* Get most updated data */ 972 rxbyte = readb(db->io_data); 973 974 /* Status check: this byte must be 0 or 1 */ 975 if (rxbyte & DM9000_PKT_ERR) { 976 dev_warn(db->dev, "status check fail: %d\n", rxbyte); 977 iow(db, DM9000_RCR, 0x00); /* Stop Device */ 978 iow(db, DM9000_ISR, IMR_PAR); /* Stop INT request */ 979 return; 980 } 981 982 if (!(rxbyte & DM9000_PKT_RDY)) 983 return; 984 985 /* A packet ready now & Get status/length */ 986 GoodPacket = true; 987 writeb(DM9000_MRCMD, db->io_addr); 988 989 (db->inblk)(db->io_data, &rxhdr, sizeof(rxhdr)); 990 991 RxLen = le16_to_cpu(rxhdr.RxLen); 992 993 if (netif_msg_rx_status(db)) 994 dev_dbg(db->dev, "RX: status %02x, length %04x\n", 995 rxhdr.RxStatus, RxLen); 996 997 /* Packet Status check */ 998 if (RxLen < 0x40) { 999 GoodPacket = false; 1000 if (netif_msg_rx_err(db)) 1001 dev_dbg(db->dev, "RX: Bad Packet (runt)\n"); 1002 } 1003 1004 if (RxLen > DM9000_PKT_MAX) { 1005 dev_dbg(db->dev, "RST: RX Len:%x\n", RxLen); 1006 } 1007 1008 /* rxhdr.RxStatus is identical to RSR register. */ 1009 if (rxhdr.RxStatus & (RSR_FOE | RSR_CE | RSR_AE | 1010 RSR_PLE | RSR_RWTO | 1011 RSR_LCS | RSR_RF)) { 1012 GoodPacket = false; 1013 if (rxhdr.RxStatus & RSR_FOE) { 1014 if (netif_msg_rx_err(db)) 1015 dev_dbg(db->dev, "fifo error\n"); 1016 dev->stats.rx_fifo_errors++; 1017 } 1018 if (rxhdr.RxStatus & RSR_CE) { 1019 if (netif_msg_rx_err(db)) 1020 dev_dbg(db->dev, "crc error\n"); 1021 dev->stats.rx_crc_errors++; 1022 } 1023 if (rxhdr.RxStatus & RSR_RF) { 1024 if (netif_msg_rx_err(db)) 1025 dev_dbg(db->dev, "length error\n"); 1026 dev->stats.rx_length_errors++; 1027 } 1028 } 1029 1030 /* Move data from DM9000 */ 1031 if (GoodPacket && 1032 ((skb = netdev_alloc_skb(dev, RxLen + 4)) != NULL)) { 1033 skb_reserve(skb, 2); 1034 rdptr = (u8 *) skb_put(skb, RxLen - 4); 1035 1036 /* Read received packet from RX SRAM */ 1037 1038 (db->inblk)(db->io_data, rdptr, RxLen); 1039 dev->stats.rx_bytes += RxLen; 1040 1041 /* Pass to upper layer */ 1042 skb->protocol = eth_type_trans(skb, dev); 1043 if (dev->features & NETIF_F_RXCSUM) { 1044 if ((((rxbyte & 0x1c) << 3) & rxbyte) == 0) 1045 skb->ip_summed = CHECKSUM_UNNECESSARY; 1046 else 1047 skb_checksum_none_assert(skb); 1048 } 1049 netif_rx(skb); 1050 dev->stats.rx_packets++; 1051 1052 } else { 1053 /* need to dump the packet's data */ 1054 1055 (db->dumpblk)(db->io_data, RxLen); 1056 } 1057 } while (rxbyte & DM9000_PKT_RDY); 1058 } 1059 1060 static irqreturn_t dm9000_interrupt(int irq, void *dev_id) 1061 { 1062 struct net_device *dev = dev_id; 1063 board_info_t *db = netdev_priv(dev); 1064 int int_status; 1065 unsigned long flags; 1066 u8 reg_save; 1067 1068 dm9000_dbg(db, 3, "entering %s\n", __func__); 1069 1070 /* A real interrupt coming */ 1071 1072 /* holders of db->lock must always block IRQs */ 1073 spin_lock_irqsave(&db->lock, flags); 1074 1075 /* Save previous register address */ 1076 reg_save = readb(db->io_addr); 1077 1078 /* Disable all interrupts */ 1079 iow(db, DM9000_IMR, IMR_PAR); 1080 1081 /* Got DM9000 interrupt status */ 1082 int_status = ior(db, DM9000_ISR); /* Got ISR */ 1083 iow(db, DM9000_ISR, int_status); /* Clear ISR status */ 1084 1085 if (netif_msg_intr(db)) 1086 dev_dbg(db->dev, "interrupt status %02x\n", int_status); 1087 1088 /* Received the coming packet */ 1089 if (int_status & ISR_PRS) 1090 dm9000_rx(dev); 1091 1092 /* Trnasmit Interrupt check */ 1093 if (int_status & ISR_PTS) 1094 dm9000_tx_done(dev, db); 1095 1096 if (db->type != TYPE_DM9000E) { 1097 if (int_status & ISR_LNKCHNG) { 1098 /* fire a link-change request */ 1099 schedule_delayed_work(&db->phy_poll, 1); 1100 } 1101 } 1102 1103 /* Re-enable interrupt mask */ 1104 iow(db, DM9000_IMR, db->imr_all); 1105 1106 /* Restore previous register address */ 1107 writeb(reg_save, db->io_addr); 1108 1109 spin_unlock_irqrestore(&db->lock, flags); 1110 1111 return IRQ_HANDLED; 1112 } 1113 1114 static irqreturn_t dm9000_wol_interrupt(int irq, void *dev_id) 1115 { 1116 struct net_device *dev = dev_id; 1117 board_info_t *db = netdev_priv(dev); 1118 unsigned long flags; 1119 unsigned nsr, wcr; 1120 1121 spin_lock_irqsave(&db->lock, flags); 1122 1123 nsr = ior(db, DM9000_NSR); 1124 wcr = ior(db, DM9000_WCR); 1125 1126 dev_dbg(db->dev, "%s: NSR=0x%02x, WCR=0x%02x\n", __func__, nsr, wcr); 1127 1128 if (nsr & NSR_WAKEST) { 1129 /* clear, so we can avoid */ 1130 iow(db, DM9000_NSR, NSR_WAKEST); 1131 1132 if (wcr & WCR_LINKST) 1133 dev_info(db->dev, "wake by link status change\n"); 1134 if (wcr & WCR_SAMPLEST) 1135 dev_info(db->dev, "wake by sample packet\n"); 1136 if (wcr & WCR_MAGICST ) 1137 dev_info(db->dev, "wake by magic packet\n"); 1138 if (!(wcr & (WCR_LINKST | WCR_SAMPLEST | WCR_MAGICST))) 1139 dev_err(db->dev, "wake signalled with no reason? " 1140 "NSR=0x%02x, WSR=0x%02x\n", nsr, wcr); 1141 1142 } 1143 1144 spin_unlock_irqrestore(&db->lock, flags); 1145 1146 return (nsr & NSR_WAKEST) ? IRQ_HANDLED : IRQ_NONE; 1147 } 1148 1149 #ifdef CONFIG_NET_POLL_CONTROLLER 1150 /* 1151 *Used by netconsole 1152 */ 1153 static void dm9000_poll_controller(struct net_device *dev) 1154 { 1155 disable_irq(dev->irq); 1156 dm9000_interrupt(dev->irq, dev); 1157 enable_irq(dev->irq); 1158 } 1159 #endif 1160 1161 /* 1162 * Open the interface. 1163 * The interface is opened whenever "ifconfig" actives it. 1164 */ 1165 static int 1166 dm9000_open(struct net_device *dev) 1167 { 1168 board_info_t *db = netdev_priv(dev); 1169 unsigned long irqflags = db->irq_res->flags & IRQF_TRIGGER_MASK; 1170 1171 if (netif_msg_ifup(db)) 1172 dev_dbg(db->dev, "enabling %s\n", dev->name); 1173 1174 /* If there is no IRQ type specified, default to something that 1175 * may work, and tell the user that this is a problem */ 1176 1177 if (irqflags == IRQF_TRIGGER_NONE) 1178 dev_warn(db->dev, "WARNING: no IRQ resource flags set.\n"); 1179 1180 irqflags |= IRQF_SHARED; 1181 1182 /* GPIO0 on pre-activate PHY, Reg 1F is not set by reset */ 1183 iow(db, DM9000_GPR, 0); /* REG_1F bit0 activate phyxcer */ 1184 mdelay(1); /* delay needs by DM9000B */ 1185 1186 /* Initialize DM9000 board */ 1187 dm9000_reset(db); 1188 dm9000_init_dm9000(dev); 1189 1190 if (request_irq(dev->irq, dm9000_interrupt, irqflags, dev->name, dev)) 1191 return -EAGAIN; 1192 1193 /* Init driver variable */ 1194 db->dbug_cnt = 0; 1195 1196 mii_check_media(&db->mii, netif_msg_link(db), 1); 1197 netif_start_queue(dev); 1198 1199 dm9000_schedule_poll(db); 1200 1201 return 0; 1202 } 1203 1204 /* 1205 * Sleep, either by using msleep() or if we are suspending, then 1206 * use mdelay() to sleep. 1207 */ 1208 static void dm9000_msleep(board_info_t *db, unsigned int ms) 1209 { 1210 if (db->in_suspend) 1211 mdelay(ms); 1212 else 1213 msleep(ms); 1214 } 1215 1216 /* 1217 * Read a word from phyxcer 1218 */ 1219 static int 1220 dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg) 1221 { 1222 board_info_t *db = netdev_priv(dev); 1223 unsigned long flags; 1224 unsigned int reg_save; 1225 int ret; 1226 1227 mutex_lock(&db->addr_lock); 1228 1229 spin_lock_irqsave(&db->lock,flags); 1230 1231 /* Save previous register address */ 1232 reg_save = readb(db->io_addr); 1233 1234 /* Fill the phyxcer register into REG_0C */ 1235 iow(db, DM9000_EPAR, DM9000_PHY | reg); 1236 1237 iow(db, DM9000_EPCR, EPCR_ERPRR | EPCR_EPOS); /* Issue phyxcer read command */ 1238 1239 writeb(reg_save, db->io_addr); 1240 spin_unlock_irqrestore(&db->lock,flags); 1241 1242 dm9000_msleep(db, 1); /* Wait read complete */ 1243 1244 spin_lock_irqsave(&db->lock,flags); 1245 reg_save = readb(db->io_addr); 1246 1247 iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer read command */ 1248 1249 /* The read data keeps on REG_0D & REG_0E */ 1250 ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL); 1251 1252 /* restore the previous address */ 1253 writeb(reg_save, db->io_addr); 1254 spin_unlock_irqrestore(&db->lock,flags); 1255 1256 mutex_unlock(&db->addr_lock); 1257 1258 dm9000_dbg(db, 5, "phy_read[%02x] -> %04x\n", reg, ret); 1259 return ret; 1260 } 1261 1262 /* 1263 * Write a word to phyxcer 1264 */ 1265 static void 1266 dm9000_phy_write(struct net_device *dev, 1267 int phyaddr_unused, int reg, int value) 1268 { 1269 board_info_t *db = netdev_priv(dev); 1270 unsigned long flags; 1271 unsigned long reg_save; 1272 1273 dm9000_dbg(db, 5, "phy_write[%02x] = %04x\n", reg, value); 1274 mutex_lock(&db->addr_lock); 1275 1276 spin_lock_irqsave(&db->lock,flags); 1277 1278 /* Save previous register address */ 1279 reg_save = readb(db->io_addr); 1280 1281 /* Fill the phyxcer register into REG_0C */ 1282 iow(db, DM9000_EPAR, DM9000_PHY | reg); 1283 1284 /* Fill the written data into REG_0D & REG_0E */ 1285 iow(db, DM9000_EPDRL, value); 1286 iow(db, DM9000_EPDRH, value >> 8); 1287 1288 iow(db, DM9000_EPCR, EPCR_EPOS | EPCR_ERPRW); /* Issue phyxcer write command */ 1289 1290 writeb(reg_save, db->io_addr); 1291 spin_unlock_irqrestore(&db->lock, flags); 1292 1293 dm9000_msleep(db, 1); /* Wait write complete */ 1294 1295 spin_lock_irqsave(&db->lock,flags); 1296 reg_save = readb(db->io_addr); 1297 1298 iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer write command */ 1299 1300 /* restore the previous address */ 1301 writeb(reg_save, db->io_addr); 1302 1303 spin_unlock_irqrestore(&db->lock, flags); 1304 mutex_unlock(&db->addr_lock); 1305 } 1306 1307 static void 1308 dm9000_shutdown(struct net_device *dev) 1309 { 1310 board_info_t *db = netdev_priv(dev); 1311 1312 /* RESET device */ 1313 dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); /* PHY RESET */ 1314 iow(db, DM9000_GPR, 0x01); /* Power-Down PHY */ 1315 iow(db, DM9000_IMR, IMR_PAR); /* Disable all interrupt */ 1316 iow(db, DM9000_RCR, 0x00); /* Disable RX */ 1317 } 1318 1319 /* 1320 * Stop the interface. 1321 * The interface is stopped when it is brought. 1322 */ 1323 static int 1324 dm9000_stop(struct net_device *ndev) 1325 { 1326 board_info_t *db = netdev_priv(ndev); 1327 1328 if (netif_msg_ifdown(db)) 1329 dev_dbg(db->dev, "shutting down %s\n", ndev->name); 1330 1331 cancel_delayed_work_sync(&db->phy_poll); 1332 1333 netif_stop_queue(ndev); 1334 netif_carrier_off(ndev); 1335 1336 /* free interrupt */ 1337 free_irq(ndev->irq, ndev); 1338 1339 dm9000_shutdown(ndev); 1340 1341 return 0; 1342 } 1343 1344 static const struct net_device_ops dm9000_netdev_ops = { 1345 .ndo_open = dm9000_open, 1346 .ndo_stop = dm9000_stop, 1347 .ndo_start_xmit = dm9000_start_xmit, 1348 .ndo_tx_timeout = dm9000_timeout, 1349 .ndo_set_rx_mode = dm9000_hash_table, 1350 .ndo_do_ioctl = dm9000_ioctl, 1351 .ndo_change_mtu = eth_change_mtu, 1352 .ndo_set_features = dm9000_set_features, 1353 .ndo_validate_addr = eth_validate_addr, 1354 .ndo_set_mac_address = eth_mac_addr, 1355 #ifdef CONFIG_NET_POLL_CONTROLLER 1356 .ndo_poll_controller = dm9000_poll_controller, 1357 #endif 1358 }; 1359 1360 /* 1361 * Search DM9000 board, allocate space and register it 1362 */ 1363 static int 1364 dm9000_probe(struct platform_device *pdev) 1365 { 1366 struct dm9000_plat_data *pdata = pdev->dev.platform_data; 1367 struct board_info *db; /* Point a board information structure */ 1368 struct net_device *ndev; 1369 const unsigned char *mac_src; 1370 int ret = 0; 1371 int iosize; 1372 int i; 1373 u32 id_val; 1374 1375 /* Init network device */ 1376 ndev = alloc_etherdev(sizeof(struct board_info)); 1377 if (!ndev) 1378 return -ENOMEM; 1379 1380 SET_NETDEV_DEV(ndev, &pdev->dev); 1381 1382 dev_dbg(&pdev->dev, "dm9000_probe()\n"); 1383 1384 /* setup board info structure */ 1385 db = netdev_priv(ndev); 1386 1387 db->dev = &pdev->dev; 1388 db->ndev = ndev; 1389 1390 spin_lock_init(&db->lock); 1391 mutex_init(&db->addr_lock); 1392 1393 INIT_DELAYED_WORK(&db->phy_poll, dm9000_poll_work); 1394 1395 db->addr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1396 db->data_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1397 db->irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1398 1399 if (db->addr_res == NULL || db->data_res == NULL || 1400 db->irq_res == NULL) { 1401 dev_err(db->dev, "insufficient resources\n"); 1402 ret = -ENOENT; 1403 goto out; 1404 } 1405 1406 db->irq_wake = platform_get_irq(pdev, 1); 1407 if (db->irq_wake >= 0) { 1408 dev_dbg(db->dev, "wakeup irq %d\n", db->irq_wake); 1409 1410 ret = request_irq(db->irq_wake, dm9000_wol_interrupt, 1411 IRQF_SHARED, dev_name(db->dev), ndev); 1412 if (ret) { 1413 dev_err(db->dev, "cannot get wakeup irq (%d)\n", ret); 1414 } else { 1415 1416 /* test to see if irq is really wakeup capable */ 1417 ret = irq_set_irq_wake(db->irq_wake, 1); 1418 if (ret) { 1419 dev_err(db->dev, "irq %d cannot set wakeup (%d)\n", 1420 db->irq_wake, ret); 1421 ret = 0; 1422 } else { 1423 irq_set_irq_wake(db->irq_wake, 0); 1424 db->wake_supported = 1; 1425 } 1426 } 1427 } 1428 1429 iosize = resource_size(db->addr_res); 1430 db->addr_req = request_mem_region(db->addr_res->start, iosize, 1431 pdev->name); 1432 1433 if (db->addr_req == NULL) { 1434 dev_err(db->dev, "cannot claim address reg area\n"); 1435 ret = -EIO; 1436 goto out; 1437 } 1438 1439 db->io_addr = ioremap(db->addr_res->start, iosize); 1440 1441 if (db->io_addr == NULL) { 1442 dev_err(db->dev, "failed to ioremap address reg\n"); 1443 ret = -EINVAL; 1444 goto out; 1445 } 1446 1447 iosize = resource_size(db->data_res); 1448 db->data_req = request_mem_region(db->data_res->start, iosize, 1449 pdev->name); 1450 1451 if (db->data_req == NULL) { 1452 dev_err(db->dev, "cannot claim data reg area\n"); 1453 ret = -EIO; 1454 goto out; 1455 } 1456 1457 db->io_data = ioremap(db->data_res->start, iosize); 1458 1459 if (db->io_data == NULL) { 1460 dev_err(db->dev, "failed to ioremap data reg\n"); 1461 ret = -EINVAL; 1462 goto out; 1463 } 1464 1465 /* fill in parameters for net-dev structure */ 1466 ndev->base_addr = (unsigned long)db->io_addr; 1467 ndev->irq = db->irq_res->start; 1468 1469 /* ensure at least we have a default set of IO routines */ 1470 dm9000_set_io(db, iosize); 1471 1472 /* check to see if anything is being over-ridden */ 1473 if (pdata != NULL) { 1474 /* check to see if the driver wants to over-ride the 1475 * default IO width */ 1476 1477 if (pdata->flags & DM9000_PLATF_8BITONLY) 1478 dm9000_set_io(db, 1); 1479 1480 if (pdata->flags & DM9000_PLATF_16BITONLY) 1481 dm9000_set_io(db, 2); 1482 1483 if (pdata->flags & DM9000_PLATF_32BITONLY) 1484 dm9000_set_io(db, 4); 1485 1486 /* check to see if there are any IO routine 1487 * over-rides */ 1488 1489 if (pdata->inblk != NULL) 1490 db->inblk = pdata->inblk; 1491 1492 if (pdata->outblk != NULL) 1493 db->outblk = pdata->outblk; 1494 1495 if (pdata->dumpblk != NULL) 1496 db->dumpblk = pdata->dumpblk; 1497 1498 db->flags = pdata->flags; 1499 } 1500 1501 #ifdef CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL 1502 db->flags |= DM9000_PLATF_SIMPLE_PHY; 1503 #endif 1504 1505 dm9000_reset(db); 1506 1507 /* try multiple times, DM9000 sometimes gets the read wrong */ 1508 for (i = 0; i < 8; i++) { 1509 id_val = ior(db, DM9000_VIDL); 1510 id_val |= (u32)ior(db, DM9000_VIDH) << 8; 1511 id_val |= (u32)ior(db, DM9000_PIDL) << 16; 1512 id_val |= (u32)ior(db, DM9000_PIDH) << 24; 1513 1514 if (id_val == DM9000_ID) 1515 break; 1516 dev_err(db->dev, "read wrong id 0x%08x\n", id_val); 1517 } 1518 1519 if (id_val != DM9000_ID) { 1520 dev_err(db->dev, "wrong id: 0x%08x\n", id_val); 1521 ret = -ENODEV; 1522 goto out; 1523 } 1524 1525 /* Identify what type of DM9000 we are working on */ 1526 1527 id_val = ior(db, DM9000_CHIPR); 1528 dev_dbg(db->dev, "dm9000 revision 0x%02x\n", id_val); 1529 1530 switch (id_val) { 1531 case CHIPR_DM9000A: 1532 db->type = TYPE_DM9000A; 1533 break; 1534 case CHIPR_DM9000B: 1535 db->type = TYPE_DM9000B; 1536 break; 1537 default: 1538 dev_dbg(db->dev, "ID %02x => defaulting to DM9000E\n", id_val); 1539 db->type = TYPE_DM9000E; 1540 } 1541 1542 /* dm9000a/b are capable of hardware checksum offload */ 1543 if (db->type == TYPE_DM9000A || db->type == TYPE_DM9000B) { 1544 ndev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM; 1545 ndev->features |= ndev->hw_features; 1546 } 1547 1548 /* from this point we assume that we have found a DM9000 */ 1549 1550 /* driver system function */ 1551 ether_setup(ndev); 1552 1553 ndev->netdev_ops = &dm9000_netdev_ops; 1554 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 1555 ndev->ethtool_ops = &dm9000_ethtool_ops; 1556 1557 db->msg_enable = NETIF_MSG_LINK; 1558 db->mii.phy_id_mask = 0x1f; 1559 db->mii.reg_num_mask = 0x1f; 1560 db->mii.force_media = 0; 1561 db->mii.full_duplex = 0; 1562 db->mii.dev = ndev; 1563 db->mii.mdio_read = dm9000_phy_read; 1564 db->mii.mdio_write = dm9000_phy_write; 1565 1566 mac_src = "eeprom"; 1567 1568 /* try reading the node address from the attached EEPROM */ 1569 for (i = 0; i < 6; i += 2) 1570 dm9000_read_eeprom(db, i / 2, ndev->dev_addr+i); 1571 1572 if (!is_valid_ether_addr(ndev->dev_addr) && pdata != NULL) { 1573 mac_src = "platform data"; 1574 memcpy(ndev->dev_addr, pdata->dev_addr, 6); 1575 } 1576 1577 if (!is_valid_ether_addr(ndev->dev_addr)) { 1578 /* try reading from mac */ 1579 1580 mac_src = "chip"; 1581 for (i = 0; i < 6; i++) 1582 ndev->dev_addr[i] = ior(db, i+DM9000_PAR); 1583 } 1584 1585 if (!is_valid_ether_addr(ndev->dev_addr)) { 1586 dev_warn(db->dev, "%s: Invalid ethernet MAC address. Please " 1587 "set using ifconfig\n", ndev->name); 1588 1589 eth_hw_addr_random(ndev); 1590 mac_src = "random"; 1591 } 1592 1593 1594 platform_set_drvdata(pdev, ndev); 1595 ret = register_netdev(ndev); 1596 1597 if (ret == 0) 1598 printk(KERN_INFO "%s: dm9000%c at %p,%p IRQ %d MAC: %pM (%s)\n", 1599 ndev->name, dm9000_type_to_char(db->type), 1600 db->io_addr, db->io_data, ndev->irq, 1601 ndev->dev_addr, mac_src); 1602 return 0; 1603 1604 out: 1605 dev_err(db->dev, "not found (%d).\n", ret); 1606 1607 dm9000_release_board(pdev, db); 1608 free_netdev(ndev); 1609 1610 return ret; 1611 } 1612 1613 static int 1614 dm9000_drv_suspend(struct device *dev) 1615 { 1616 struct platform_device *pdev = to_platform_device(dev); 1617 struct net_device *ndev = platform_get_drvdata(pdev); 1618 board_info_t *db; 1619 1620 if (ndev) { 1621 db = netdev_priv(ndev); 1622 db->in_suspend = 1; 1623 1624 if (!netif_running(ndev)) 1625 return 0; 1626 1627 netif_device_detach(ndev); 1628 1629 /* only shutdown if not using WoL */ 1630 if (!db->wake_state) 1631 dm9000_shutdown(ndev); 1632 } 1633 return 0; 1634 } 1635 1636 static int 1637 dm9000_drv_resume(struct device *dev) 1638 { 1639 struct platform_device *pdev = to_platform_device(dev); 1640 struct net_device *ndev = platform_get_drvdata(pdev); 1641 board_info_t *db = netdev_priv(ndev); 1642 1643 if (ndev) { 1644 if (netif_running(ndev)) { 1645 /* reset if we were not in wake mode to ensure if 1646 * the device was powered off it is in a known state */ 1647 if (!db->wake_state) { 1648 dm9000_reset(db); 1649 dm9000_init_dm9000(ndev); 1650 } 1651 1652 netif_device_attach(ndev); 1653 } 1654 1655 db->in_suspend = 0; 1656 } 1657 return 0; 1658 } 1659 1660 static const struct dev_pm_ops dm9000_drv_pm_ops = { 1661 .suspend = dm9000_drv_suspend, 1662 .resume = dm9000_drv_resume, 1663 }; 1664 1665 static int 1666 dm9000_drv_remove(struct platform_device *pdev) 1667 { 1668 struct net_device *ndev = platform_get_drvdata(pdev); 1669 1670 platform_set_drvdata(pdev, NULL); 1671 1672 unregister_netdev(ndev); 1673 dm9000_release_board(pdev, netdev_priv(ndev)); 1674 free_netdev(ndev); /* free device structure */ 1675 1676 dev_dbg(&pdev->dev, "released and freed device\n"); 1677 return 0; 1678 } 1679 1680 static struct platform_driver dm9000_driver = { 1681 .driver = { 1682 .name = "dm9000", 1683 .owner = THIS_MODULE, 1684 .pm = &dm9000_drv_pm_ops, 1685 }, 1686 .probe = dm9000_probe, 1687 .remove = dm9000_drv_remove, 1688 }; 1689 1690 static int __init 1691 dm9000_init(void) 1692 { 1693 printk(KERN_INFO "%s Ethernet Driver, V%s\n", CARDNAME, DRV_VERSION); 1694 1695 return platform_driver_register(&dm9000_driver); 1696 } 1697 1698 static void __exit 1699 dm9000_cleanup(void) 1700 { 1701 platform_driver_unregister(&dm9000_driver); 1702 } 1703 1704 module_init(dm9000_init); 1705 module_exit(dm9000_cleanup); 1706 1707 MODULE_AUTHOR("Sascha Hauer, Ben Dooks"); 1708 MODULE_DESCRIPTION("Davicom DM9000 network driver"); 1709 MODULE_LICENSE("GPL"); 1710 MODULE_ALIAS("platform:dm9000"); 1711