1 // SPDX-License-Identifier: GPL-2.0 2 /* Ethernet device driver for Cortina Systems Gemini SoC 3 * Also known as the StorLink SL3512 and SL3516 (SL351x) or Lepus 4 * Net Engine and Gigabit Ethernet MAC (GMAC) 5 * This hardware contains a TCP Offload Engine (TOE) but currently the 6 * driver does not make use of it. 7 * 8 * Authors: 9 * Linus Walleij <linus.walleij@linaro.org> 10 * Tobias Waldvogel <tobias.waldvogel@gmail.com> (OpenWRT) 11 * Michał Mirosław <mirq-linux@rere.qmqm.pl> 12 * Paulius Zaleckas <paulius.zaleckas@gmail.com> 13 * Giuseppe De Robertis <Giuseppe.DeRobertis@ba.infn.it> 14 * Gary Chen & Ch Hsu Storlink Semiconductor 15 */ 16 #include <linux/kernel.h> 17 #include <linux/init.h> 18 #include <linux/module.h> 19 #include <linux/platform_device.h> 20 #include <linux/spinlock.h> 21 #include <linux/slab.h> 22 #include <linux/dma-mapping.h> 23 #include <linux/cache.h> 24 #include <linux/interrupt.h> 25 #include <linux/reset.h> 26 #include <linux/clk.h> 27 #include <linux/of.h> 28 #include <linux/of_mdio.h> 29 #include <linux/of_net.h> 30 #include <linux/of_platform.h> 31 #include <linux/etherdevice.h> 32 #include <linux/if_vlan.h> 33 #include <linux/skbuff.h> 34 #include <linux/phy.h> 35 #include <linux/crc32.h> 36 #include <linux/ethtool.h> 37 #include <linux/tcp.h> 38 #include <linux/u64_stats_sync.h> 39 40 #include <linux/in.h> 41 #include <linux/ip.h> 42 #include <linux/ipv6.h> 43 44 #include "gemini.h" 45 46 #define DRV_NAME "gmac-gemini" 47 #define DRV_VERSION "1.0" 48 49 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) 50 static int debug = -1; 51 module_param(debug, int, 0); 52 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 53 54 #define HSIZE_8 0x00 55 #define HSIZE_16 0x01 56 #define HSIZE_32 0x02 57 58 #define HBURST_SINGLE 0x00 59 #define HBURST_INCR 0x01 60 #define HBURST_INCR4 0x02 61 #define HBURST_INCR8 0x03 62 63 #define HPROT_DATA_CACHE BIT(0) 64 #define HPROT_PRIVILIGED BIT(1) 65 #define HPROT_BUFFERABLE BIT(2) 66 #define HPROT_CACHABLE BIT(3) 67 68 #define DEFAULT_RX_COALESCE_NSECS 0 69 #define DEFAULT_GMAC_RXQ_ORDER 9 70 #define DEFAULT_GMAC_TXQ_ORDER 8 71 #define DEFAULT_RX_BUF_ORDER 11 72 #define DEFAULT_NAPI_WEIGHT 64 73 #define TX_MAX_FRAGS 16 74 #define TX_QUEUE_NUM 1 /* max: 6 */ 75 #define RX_MAX_ALLOC_ORDER 2 76 77 #define GMAC0_IRQ0_2 (GMAC0_TXDERR_INT_BIT | GMAC0_TXPERR_INT_BIT | \ 78 GMAC0_RXDERR_INT_BIT | GMAC0_RXPERR_INT_BIT) 79 #define GMAC0_IRQ0_TXQ0_INTS (GMAC0_SWTQ00_EOF_INT_BIT | \ 80 GMAC0_SWTQ00_FIN_INT_BIT) 81 #define GMAC0_IRQ4_8 (GMAC0_MIB_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT) 82 83 #define GMAC_OFFLOAD_FEATURES (NETIF_F_SG | NETIF_F_IP_CSUM | \ 84 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | \ 85 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6) 86 87 /** 88 * struct gmac_queue_page - page buffer per-page info 89 */ 90 struct gmac_queue_page { 91 struct page *page; 92 dma_addr_t mapping; 93 }; 94 95 struct gmac_txq { 96 struct gmac_txdesc *ring; 97 struct sk_buff **skb; 98 unsigned int cptr; 99 unsigned int noirq_packets; 100 }; 101 102 struct gemini_ethernet; 103 104 struct gemini_ethernet_port { 105 u8 id; /* 0 or 1 */ 106 107 struct gemini_ethernet *geth; 108 struct net_device *netdev; 109 struct device *dev; 110 void __iomem *dma_base; 111 void __iomem *gmac_base; 112 struct clk *pclk; 113 struct reset_control *reset; 114 int irq; 115 __le32 mac_addr[3]; 116 117 void __iomem *rxq_rwptr; 118 struct gmac_rxdesc *rxq_ring; 119 unsigned int rxq_order; 120 121 struct napi_struct napi; 122 struct hrtimer rx_coalesce_timer; 123 unsigned int rx_coalesce_nsecs; 124 unsigned int freeq_refill; 125 struct gmac_txq txq[TX_QUEUE_NUM]; 126 unsigned int txq_order; 127 unsigned int irq_every_tx_packets; 128 129 dma_addr_t rxq_dma_base; 130 dma_addr_t txq_dma_base; 131 132 unsigned int msg_enable; 133 spinlock_t config_lock; /* Locks config register */ 134 135 struct u64_stats_sync tx_stats_syncp; 136 struct u64_stats_sync rx_stats_syncp; 137 struct u64_stats_sync ir_stats_syncp; 138 139 struct rtnl_link_stats64 stats; 140 u64 hw_stats[RX_STATS_NUM]; 141 u64 rx_stats[RX_STATUS_NUM]; 142 u64 rx_csum_stats[RX_CHKSUM_NUM]; 143 u64 rx_napi_exits; 144 u64 tx_frag_stats[TX_MAX_FRAGS]; 145 u64 tx_frags_linearized; 146 u64 tx_hw_csummed; 147 }; 148 149 struct gemini_ethernet { 150 struct device *dev; 151 void __iomem *base; 152 struct gemini_ethernet_port *port0; 153 struct gemini_ethernet_port *port1; 154 bool initialized; 155 156 spinlock_t irq_lock; /* Locks IRQ-related registers */ 157 unsigned int freeq_order; 158 unsigned int freeq_frag_order; 159 struct gmac_rxdesc *freeq_ring; 160 dma_addr_t freeq_dma_base; 161 struct gmac_queue_page *freeq_pages; 162 unsigned int num_freeq_pages; 163 spinlock_t freeq_lock; /* Locks queue from reentrance */ 164 }; 165 166 #define GMAC_STATS_NUM ( \ 167 RX_STATS_NUM + RX_STATUS_NUM + RX_CHKSUM_NUM + 1 + \ 168 TX_MAX_FRAGS + 2) 169 170 static const char gmac_stats_strings[GMAC_STATS_NUM][ETH_GSTRING_LEN] = { 171 "GMAC_IN_DISCARDS", 172 "GMAC_IN_ERRORS", 173 "GMAC_IN_MCAST", 174 "GMAC_IN_BCAST", 175 "GMAC_IN_MAC1", 176 "GMAC_IN_MAC2", 177 "RX_STATUS_GOOD_FRAME", 178 "RX_STATUS_TOO_LONG_GOOD_CRC", 179 "RX_STATUS_RUNT_FRAME", 180 "RX_STATUS_SFD_NOT_FOUND", 181 "RX_STATUS_CRC_ERROR", 182 "RX_STATUS_TOO_LONG_BAD_CRC", 183 "RX_STATUS_ALIGNMENT_ERROR", 184 "RX_STATUS_TOO_LONG_BAD_ALIGN", 185 "RX_STATUS_RX_ERR", 186 "RX_STATUS_DA_FILTERED", 187 "RX_STATUS_BUFFER_FULL", 188 "RX_STATUS_11", 189 "RX_STATUS_12", 190 "RX_STATUS_13", 191 "RX_STATUS_14", 192 "RX_STATUS_15", 193 "RX_CHKSUM_IP_UDP_TCP_OK", 194 "RX_CHKSUM_IP_OK_ONLY", 195 "RX_CHKSUM_NONE", 196 "RX_CHKSUM_3", 197 "RX_CHKSUM_IP_ERR_UNKNOWN", 198 "RX_CHKSUM_IP_ERR", 199 "RX_CHKSUM_TCP_UDP_ERR", 200 "RX_CHKSUM_7", 201 "RX_NAPI_EXITS", 202 "TX_FRAGS[1]", 203 "TX_FRAGS[2]", 204 "TX_FRAGS[3]", 205 "TX_FRAGS[4]", 206 "TX_FRAGS[5]", 207 "TX_FRAGS[6]", 208 "TX_FRAGS[7]", 209 "TX_FRAGS[8]", 210 "TX_FRAGS[9]", 211 "TX_FRAGS[10]", 212 "TX_FRAGS[11]", 213 "TX_FRAGS[12]", 214 "TX_FRAGS[13]", 215 "TX_FRAGS[14]", 216 "TX_FRAGS[15]", 217 "TX_FRAGS[16+]", 218 "TX_FRAGS_LINEARIZED", 219 "TX_HW_CSUMMED", 220 }; 221 222 static void gmac_dump_dma_state(struct net_device *netdev); 223 224 static void gmac_update_config0_reg(struct net_device *netdev, 225 u32 val, u32 vmask) 226 { 227 struct gemini_ethernet_port *port = netdev_priv(netdev); 228 unsigned long flags; 229 u32 reg; 230 231 spin_lock_irqsave(&port->config_lock, flags); 232 233 reg = readl(port->gmac_base + GMAC_CONFIG0); 234 reg = (reg & ~vmask) | val; 235 writel(reg, port->gmac_base + GMAC_CONFIG0); 236 237 spin_unlock_irqrestore(&port->config_lock, flags); 238 } 239 240 static void gmac_enable_tx_rx(struct net_device *netdev) 241 { 242 struct gemini_ethernet_port *port = netdev_priv(netdev); 243 unsigned long flags; 244 u32 reg; 245 246 spin_lock_irqsave(&port->config_lock, flags); 247 248 reg = readl(port->gmac_base + GMAC_CONFIG0); 249 reg &= ~CONFIG0_TX_RX_DISABLE; 250 writel(reg, port->gmac_base + GMAC_CONFIG0); 251 252 spin_unlock_irqrestore(&port->config_lock, flags); 253 } 254 255 static void gmac_disable_tx_rx(struct net_device *netdev) 256 { 257 struct gemini_ethernet_port *port = netdev_priv(netdev); 258 unsigned long flags; 259 u32 val; 260 261 spin_lock_irqsave(&port->config_lock, flags); 262 263 val = readl(port->gmac_base + GMAC_CONFIG0); 264 val |= CONFIG0_TX_RX_DISABLE; 265 writel(val, port->gmac_base + GMAC_CONFIG0); 266 267 spin_unlock_irqrestore(&port->config_lock, flags); 268 269 mdelay(10); /* let GMAC consume packet */ 270 } 271 272 static void gmac_set_flow_control(struct net_device *netdev, bool tx, bool rx) 273 { 274 struct gemini_ethernet_port *port = netdev_priv(netdev); 275 unsigned long flags; 276 u32 val; 277 278 spin_lock_irqsave(&port->config_lock, flags); 279 280 val = readl(port->gmac_base + GMAC_CONFIG0); 281 val &= ~CONFIG0_FLOW_CTL; 282 if (tx) 283 val |= CONFIG0_FLOW_TX; 284 if (rx) 285 val |= CONFIG0_FLOW_RX; 286 writel(val, port->gmac_base + GMAC_CONFIG0); 287 288 spin_unlock_irqrestore(&port->config_lock, flags); 289 } 290 291 static void gmac_speed_set(struct net_device *netdev) 292 { 293 struct gemini_ethernet_port *port = netdev_priv(netdev); 294 struct phy_device *phydev = netdev->phydev; 295 union gmac_status status, old_status; 296 int pause_tx = 0; 297 int pause_rx = 0; 298 299 status.bits32 = readl(port->gmac_base + GMAC_STATUS); 300 old_status.bits32 = status.bits32; 301 status.bits.link = phydev->link; 302 status.bits.duplex = phydev->duplex; 303 304 switch (phydev->speed) { 305 case 1000: 306 status.bits.speed = GMAC_SPEED_1000; 307 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) 308 status.bits.mii_rmii = GMAC_PHY_RGMII_1000; 309 netdev_dbg(netdev, "connect %s to RGMII @ 1Gbit\n", 310 phydev_name(phydev)); 311 break; 312 case 100: 313 status.bits.speed = GMAC_SPEED_100; 314 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) 315 status.bits.mii_rmii = GMAC_PHY_RGMII_100_10; 316 netdev_dbg(netdev, "connect %s to RGMII @ 100 Mbit\n", 317 phydev_name(phydev)); 318 break; 319 case 10: 320 status.bits.speed = GMAC_SPEED_10; 321 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) 322 status.bits.mii_rmii = GMAC_PHY_RGMII_100_10; 323 netdev_dbg(netdev, "connect %s to RGMII @ 10 Mbit\n", 324 phydev_name(phydev)); 325 break; 326 default: 327 netdev_warn(netdev, "Unsupported PHY speed (%d) on %s\n", 328 phydev->speed, phydev_name(phydev)); 329 } 330 331 if (phydev->duplex == DUPLEX_FULL) { 332 u16 lcladv = phy_read(phydev, MII_ADVERTISE); 333 u16 rmtadv = phy_read(phydev, MII_LPA); 334 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv); 335 336 if (cap & FLOW_CTRL_RX) 337 pause_rx = 1; 338 if (cap & FLOW_CTRL_TX) 339 pause_tx = 1; 340 } 341 342 gmac_set_flow_control(netdev, pause_tx, pause_rx); 343 344 if (old_status.bits32 == status.bits32) 345 return; 346 347 if (netif_msg_link(port)) { 348 phy_print_status(phydev); 349 netdev_info(netdev, "link flow control: %s\n", 350 phydev->pause 351 ? (phydev->asym_pause ? "tx" : "both") 352 : (phydev->asym_pause ? "rx" : "none") 353 ); 354 } 355 356 gmac_disable_tx_rx(netdev); 357 writel(status.bits32, port->gmac_base + GMAC_STATUS); 358 gmac_enable_tx_rx(netdev); 359 } 360 361 static int gmac_setup_phy(struct net_device *netdev) 362 { 363 struct gemini_ethernet_port *port = netdev_priv(netdev); 364 union gmac_status status = { .bits32 = 0 }; 365 struct device *dev = port->dev; 366 struct phy_device *phy; 367 368 phy = of_phy_get_and_connect(netdev, 369 dev->of_node, 370 gmac_speed_set); 371 if (!phy) 372 return -ENODEV; 373 netdev->phydev = phy; 374 375 phy->supported &= PHY_GBIT_FEATURES; 376 phy->supported |= SUPPORTED_Asym_Pause | SUPPORTED_Pause; 377 phy->advertising = phy->supported; 378 379 /* set PHY interface type */ 380 switch (phy->interface) { 381 case PHY_INTERFACE_MODE_MII: 382 netdev_dbg(netdev, 383 "MII: set GMAC0 to GMII mode, GMAC1 disabled\n"); 384 status.bits.mii_rmii = GMAC_PHY_MII; 385 break; 386 case PHY_INTERFACE_MODE_GMII: 387 netdev_dbg(netdev, 388 "GMII: set GMAC0 to GMII mode, GMAC1 disabled\n"); 389 status.bits.mii_rmii = GMAC_PHY_GMII; 390 break; 391 case PHY_INTERFACE_MODE_RGMII: 392 netdev_dbg(netdev, 393 "RGMII: set GMAC0 and GMAC1 to MII/RGMII mode\n"); 394 status.bits.mii_rmii = GMAC_PHY_RGMII_100_10; 395 break; 396 default: 397 netdev_err(netdev, "Unsupported MII interface\n"); 398 phy_disconnect(phy); 399 netdev->phydev = NULL; 400 return -EINVAL; 401 } 402 writel(status.bits32, port->gmac_base + GMAC_STATUS); 403 404 if (netif_msg_link(port)) 405 phy_attached_info(phy); 406 407 return 0; 408 } 409 410 /* The maximum frame length is not logically enumerated in the 411 * hardware, so we do a table lookup to find the applicable max 412 * frame length. 413 */ 414 struct gmac_max_framelen { 415 unsigned int max_l3_len; 416 u8 val; 417 }; 418 419 static const struct gmac_max_framelen gmac_maxlens[] = { 420 { 421 .max_l3_len = 1518, 422 .val = CONFIG0_MAXLEN_1518, 423 }, 424 { 425 .max_l3_len = 1522, 426 .val = CONFIG0_MAXLEN_1522, 427 }, 428 { 429 .max_l3_len = 1536, 430 .val = CONFIG0_MAXLEN_1536, 431 }, 432 { 433 .max_l3_len = 1542, 434 .val = CONFIG0_MAXLEN_1542, 435 }, 436 { 437 .max_l3_len = 9212, 438 .val = CONFIG0_MAXLEN_9k, 439 }, 440 { 441 .max_l3_len = 10236, 442 .val = CONFIG0_MAXLEN_10k, 443 }, 444 }; 445 446 static int gmac_pick_rx_max_len(unsigned int max_l3_len) 447 { 448 const struct gmac_max_framelen *maxlen; 449 int maxtot; 450 int i; 451 452 maxtot = max_l3_len + ETH_HLEN + VLAN_HLEN; 453 454 for (i = 0; i < ARRAY_SIZE(gmac_maxlens); i++) { 455 maxlen = &gmac_maxlens[i]; 456 if (maxtot <= maxlen->max_l3_len) 457 return maxlen->val; 458 } 459 460 return -1; 461 } 462 463 static int gmac_init(struct net_device *netdev) 464 { 465 struct gemini_ethernet_port *port = netdev_priv(netdev); 466 union gmac_config0 config0 = { .bits = { 467 .dis_tx = 1, 468 .dis_rx = 1, 469 .ipv4_rx_chksum = 1, 470 .ipv6_rx_chksum = 1, 471 .rx_err_detect = 1, 472 .rgmm_edge = 1, 473 .port0_chk_hwq = 1, 474 .port1_chk_hwq = 1, 475 .port0_chk_toeq = 1, 476 .port1_chk_toeq = 1, 477 .port0_chk_classq = 1, 478 .port1_chk_classq = 1, 479 } }; 480 union gmac_ahb_weight ahb_weight = { .bits = { 481 .rx_weight = 1, 482 .tx_weight = 1, 483 .hash_weight = 1, 484 .pre_req = 0x1f, 485 .tq_dv_threshold = 0, 486 } }; 487 union gmac_tx_wcr0 hw_weigh = { .bits = { 488 .hw_tq3 = 1, 489 .hw_tq2 = 1, 490 .hw_tq1 = 1, 491 .hw_tq0 = 1, 492 } }; 493 union gmac_tx_wcr1 sw_weigh = { .bits = { 494 .sw_tq5 = 1, 495 .sw_tq4 = 1, 496 .sw_tq3 = 1, 497 .sw_tq2 = 1, 498 .sw_tq1 = 1, 499 .sw_tq0 = 1, 500 } }; 501 union gmac_config1 config1 = { .bits = { 502 .set_threshold = 16, 503 .rel_threshold = 24, 504 } }; 505 union gmac_config2 config2 = { .bits = { 506 .set_threshold = 16, 507 .rel_threshold = 32, 508 } }; 509 union gmac_config3 config3 = { .bits = { 510 .set_threshold = 0, 511 .rel_threshold = 0, 512 } }; 513 union gmac_config0 tmp; 514 u32 val; 515 516 config0.bits.max_len = gmac_pick_rx_max_len(netdev->mtu); 517 tmp.bits32 = readl(port->gmac_base + GMAC_CONFIG0); 518 config0.bits.reserved = tmp.bits.reserved; 519 writel(config0.bits32, port->gmac_base + GMAC_CONFIG0); 520 writel(config1.bits32, port->gmac_base + GMAC_CONFIG1); 521 writel(config2.bits32, port->gmac_base + GMAC_CONFIG2); 522 writel(config3.bits32, port->gmac_base + GMAC_CONFIG3); 523 524 val = readl(port->dma_base + GMAC_AHB_WEIGHT_REG); 525 writel(ahb_weight.bits32, port->dma_base + GMAC_AHB_WEIGHT_REG); 526 527 writel(hw_weigh.bits32, 528 port->dma_base + GMAC_TX_WEIGHTING_CTRL_0_REG); 529 writel(sw_weigh.bits32, 530 port->dma_base + GMAC_TX_WEIGHTING_CTRL_1_REG); 531 532 port->rxq_order = DEFAULT_GMAC_RXQ_ORDER; 533 port->txq_order = DEFAULT_GMAC_TXQ_ORDER; 534 port->rx_coalesce_nsecs = DEFAULT_RX_COALESCE_NSECS; 535 536 /* Mark every quarter of the queue a packet for interrupt 537 * in order to be able to wake up the queue if it was stopped 538 */ 539 port->irq_every_tx_packets = 1 << (port->txq_order - 2); 540 541 return 0; 542 } 543 544 static void gmac_uninit(struct net_device *netdev) 545 { 546 if (netdev->phydev) 547 phy_disconnect(netdev->phydev); 548 } 549 550 static int gmac_setup_txqs(struct net_device *netdev) 551 { 552 struct gemini_ethernet_port *port = netdev_priv(netdev); 553 unsigned int n_txq = netdev->num_tx_queues; 554 struct gemini_ethernet *geth = port->geth; 555 size_t entries = 1 << port->txq_order; 556 struct gmac_txq *txq = port->txq; 557 struct gmac_txdesc *desc_ring; 558 size_t len = n_txq * entries; 559 struct sk_buff **skb_tab; 560 void __iomem *rwptr_reg; 561 unsigned int r; 562 int i; 563 564 rwptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG; 565 566 skb_tab = kcalloc(len, sizeof(*skb_tab), GFP_KERNEL); 567 if (!skb_tab) 568 return -ENOMEM; 569 570 desc_ring = dma_alloc_coherent(geth->dev, len * sizeof(*desc_ring), 571 &port->txq_dma_base, GFP_KERNEL); 572 573 if (!desc_ring) { 574 kfree(skb_tab); 575 return -ENOMEM; 576 } 577 578 if (port->txq_dma_base & ~DMA_Q_BASE_MASK) { 579 dev_warn(geth->dev, "TX queue base is not aligned\n"); 580 kfree(skb_tab); 581 return -ENOMEM; 582 } 583 584 writel(port->txq_dma_base | port->txq_order, 585 port->dma_base + GMAC_SW_TX_QUEUE_BASE_REG); 586 587 for (i = 0; i < n_txq; i++) { 588 txq->ring = desc_ring; 589 txq->skb = skb_tab; 590 txq->noirq_packets = 0; 591 592 r = readw(rwptr_reg); 593 rwptr_reg += 2; 594 writew(r, rwptr_reg); 595 rwptr_reg += 2; 596 txq->cptr = r; 597 598 txq++; 599 desc_ring += entries; 600 skb_tab += entries; 601 } 602 603 return 0; 604 } 605 606 static void gmac_clean_txq(struct net_device *netdev, struct gmac_txq *txq, 607 unsigned int r) 608 { 609 struct gemini_ethernet_port *port = netdev_priv(netdev); 610 unsigned int m = (1 << port->txq_order) - 1; 611 struct gemini_ethernet *geth = port->geth; 612 unsigned int c = txq->cptr; 613 union gmac_txdesc_0 word0; 614 union gmac_txdesc_1 word1; 615 unsigned int hwchksum = 0; 616 unsigned long bytes = 0; 617 struct gmac_txdesc *txd; 618 unsigned short nfrags; 619 unsigned int errs = 0; 620 unsigned int pkts = 0; 621 unsigned int word3; 622 dma_addr_t mapping; 623 624 if (c == r) 625 return; 626 627 while (c != r) { 628 txd = txq->ring + c; 629 word0 = txd->word0; 630 word1 = txd->word1; 631 mapping = txd->word2.buf_adr; 632 word3 = txd->word3.bits32; 633 634 dma_unmap_single(geth->dev, mapping, 635 word0.bits.buffer_size, DMA_TO_DEVICE); 636 637 if (word3 & EOF_BIT) 638 dev_kfree_skb(txq->skb[c]); 639 640 c++; 641 c &= m; 642 643 if (!(word3 & SOF_BIT)) 644 continue; 645 646 if (!word0.bits.status_tx_ok) { 647 errs++; 648 continue; 649 } 650 651 pkts++; 652 bytes += txd->word1.bits.byte_count; 653 654 if (word1.bits32 & TSS_CHECKUM_ENABLE) 655 hwchksum++; 656 657 nfrags = word0.bits.desc_count - 1; 658 if (nfrags) { 659 if (nfrags >= TX_MAX_FRAGS) 660 nfrags = TX_MAX_FRAGS - 1; 661 662 u64_stats_update_begin(&port->tx_stats_syncp); 663 port->tx_frag_stats[nfrags]++; 664 u64_stats_update_end(&port->ir_stats_syncp); 665 } 666 } 667 668 u64_stats_update_begin(&port->ir_stats_syncp); 669 port->stats.tx_errors += errs; 670 port->stats.tx_packets += pkts; 671 port->stats.tx_bytes += bytes; 672 port->tx_hw_csummed += hwchksum; 673 u64_stats_update_end(&port->ir_stats_syncp); 674 675 txq->cptr = c; 676 } 677 678 static void gmac_cleanup_txqs(struct net_device *netdev) 679 { 680 struct gemini_ethernet_port *port = netdev_priv(netdev); 681 unsigned int n_txq = netdev->num_tx_queues; 682 struct gemini_ethernet *geth = port->geth; 683 void __iomem *rwptr_reg; 684 unsigned int r, i; 685 686 rwptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG; 687 688 for (i = 0; i < n_txq; i++) { 689 r = readw(rwptr_reg); 690 rwptr_reg += 2; 691 writew(r, rwptr_reg); 692 rwptr_reg += 2; 693 694 gmac_clean_txq(netdev, port->txq + i, r); 695 } 696 writel(0, port->dma_base + GMAC_SW_TX_QUEUE_BASE_REG); 697 698 kfree(port->txq->skb); 699 dma_free_coherent(geth->dev, 700 n_txq * sizeof(*port->txq->ring) << port->txq_order, 701 port->txq->ring, port->txq_dma_base); 702 } 703 704 static int gmac_setup_rxq(struct net_device *netdev) 705 { 706 struct gemini_ethernet_port *port = netdev_priv(netdev); 707 struct gemini_ethernet *geth = port->geth; 708 struct nontoe_qhdr __iomem *qhdr; 709 710 qhdr = geth->base + TOE_DEFAULT_Q_HDR_BASE(netdev->dev_id); 711 port->rxq_rwptr = &qhdr->word1; 712 713 /* Remap a slew of memory to use for the RX queue */ 714 port->rxq_ring = dma_alloc_coherent(geth->dev, 715 sizeof(*port->rxq_ring) << port->rxq_order, 716 &port->rxq_dma_base, GFP_KERNEL); 717 if (!port->rxq_ring) 718 return -ENOMEM; 719 if (port->rxq_dma_base & ~NONTOE_QHDR0_BASE_MASK) { 720 dev_warn(geth->dev, "RX queue base is not aligned\n"); 721 return -ENOMEM; 722 } 723 724 writel(port->rxq_dma_base | port->rxq_order, &qhdr->word0); 725 writel(0, port->rxq_rwptr); 726 return 0; 727 } 728 729 static struct gmac_queue_page * 730 gmac_get_queue_page(struct gemini_ethernet *geth, 731 struct gemini_ethernet_port *port, 732 dma_addr_t addr) 733 { 734 struct gmac_queue_page *gpage; 735 dma_addr_t mapping; 736 int i; 737 738 /* Only look for even pages */ 739 mapping = addr & PAGE_MASK; 740 741 if (!geth->freeq_pages) { 742 dev_err(geth->dev, "try to get page with no page list\n"); 743 return NULL; 744 } 745 746 /* Look up a ring buffer page from virtual mapping */ 747 for (i = 0; i < geth->num_freeq_pages; i++) { 748 gpage = &geth->freeq_pages[i]; 749 if (gpage->mapping == mapping) 750 return gpage; 751 } 752 753 return NULL; 754 } 755 756 static void gmac_cleanup_rxq(struct net_device *netdev) 757 { 758 struct gemini_ethernet_port *port = netdev_priv(netdev); 759 struct gemini_ethernet *geth = port->geth; 760 struct gmac_rxdesc *rxd = port->rxq_ring; 761 static struct gmac_queue_page *gpage; 762 struct nontoe_qhdr __iomem *qhdr; 763 void __iomem *dma_reg; 764 void __iomem *ptr_reg; 765 dma_addr_t mapping; 766 union dma_rwptr rw; 767 unsigned int r, w; 768 769 qhdr = geth->base + 770 TOE_DEFAULT_Q_HDR_BASE(netdev->dev_id); 771 dma_reg = &qhdr->word0; 772 ptr_reg = &qhdr->word1; 773 774 rw.bits32 = readl(ptr_reg); 775 r = rw.bits.rptr; 776 w = rw.bits.wptr; 777 writew(r, ptr_reg + 2); 778 779 writel(0, dma_reg); 780 781 /* Loop from read pointer to write pointer of the RX queue 782 * and free up all pages by the queue. 783 */ 784 while (r != w) { 785 mapping = rxd[r].word2.buf_adr; 786 r++; 787 r &= ((1 << port->rxq_order) - 1); 788 789 if (!mapping) 790 continue; 791 792 /* Freeq pointers are one page off */ 793 gpage = gmac_get_queue_page(geth, port, mapping + PAGE_SIZE); 794 if (!gpage) { 795 dev_err(geth->dev, "could not find page\n"); 796 continue; 797 } 798 /* Release the RX queue reference to the page */ 799 put_page(gpage->page); 800 } 801 802 dma_free_coherent(geth->dev, sizeof(*port->rxq_ring) << port->rxq_order, 803 port->rxq_ring, port->rxq_dma_base); 804 } 805 806 static struct page *geth_freeq_alloc_map_page(struct gemini_ethernet *geth, 807 int pn) 808 { 809 struct gmac_rxdesc *freeq_entry; 810 struct gmac_queue_page *gpage; 811 unsigned int fpp_order; 812 unsigned int frag_len; 813 dma_addr_t mapping; 814 struct page *page; 815 int i; 816 817 /* First allocate and DMA map a single page */ 818 page = alloc_page(GFP_ATOMIC); 819 if (!page) 820 return NULL; 821 822 mapping = dma_map_single(geth->dev, page_address(page), 823 PAGE_SIZE, DMA_FROM_DEVICE); 824 if (dma_mapping_error(geth->dev, mapping)) { 825 put_page(page); 826 return NULL; 827 } 828 829 /* The assign the page mapping (physical address) to the buffer address 830 * in the hardware queue. PAGE_SHIFT on ARM is 12 (1 page is 4096 bytes, 831 * 4k), and the default RX frag order is 11 (fragments are up 20 2048 832 * bytes, 2k) so fpp_order (fragments per page order) is default 1. Thus 833 * each page normally needs two entries in the queue. 834 */ 835 frag_len = 1 << geth->freeq_frag_order; /* Usually 2048 */ 836 fpp_order = PAGE_SHIFT - geth->freeq_frag_order; 837 freeq_entry = geth->freeq_ring + (pn << fpp_order); 838 dev_dbg(geth->dev, "allocate page %d fragment length %d fragments per page %d, freeq entry %p\n", 839 pn, frag_len, (1 << fpp_order), freeq_entry); 840 for (i = (1 << fpp_order); i > 0; i--) { 841 freeq_entry->word2.buf_adr = mapping; 842 freeq_entry++; 843 mapping += frag_len; 844 } 845 846 /* If the freeq entry already has a page mapped, then unmap it. */ 847 gpage = &geth->freeq_pages[pn]; 848 if (gpage->page) { 849 mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr; 850 dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE); 851 /* This should be the last reference to the page so it gets 852 * released 853 */ 854 put_page(gpage->page); 855 } 856 857 /* Then put our new mapping into the page table */ 858 dev_dbg(geth->dev, "page %d, DMA addr: %08x, page %p\n", 859 pn, (unsigned int)mapping, page); 860 gpage->mapping = mapping; 861 gpage->page = page; 862 863 return page; 864 } 865 866 /** 867 * geth_fill_freeq() - Fill the freeq with empty fragments to use 868 * @geth: the ethernet adapter 869 * @refill: whether to reset the queue by filling in all freeq entries or 870 * just refill it, usually the interrupt to refill the queue happens when 871 * the queue is half empty. 872 */ 873 static unsigned int geth_fill_freeq(struct gemini_ethernet *geth, bool refill) 874 { 875 unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order; 876 unsigned int count = 0; 877 unsigned int pn, epn; 878 unsigned long flags; 879 union dma_rwptr rw; 880 unsigned int m_pn; 881 882 /* Mask for page */ 883 m_pn = (1 << (geth->freeq_order - fpp_order)) - 1; 884 885 spin_lock_irqsave(&geth->freeq_lock, flags); 886 887 rw.bits32 = readl(geth->base + GLOBAL_SWFQ_RWPTR_REG); 888 pn = (refill ? rw.bits.wptr : rw.bits.rptr) >> fpp_order; 889 epn = (rw.bits.rptr >> fpp_order) - 1; 890 epn &= m_pn; 891 892 /* Loop over the freeq ring buffer entries */ 893 while (pn != epn) { 894 struct gmac_queue_page *gpage; 895 struct page *page; 896 897 gpage = &geth->freeq_pages[pn]; 898 page = gpage->page; 899 900 dev_dbg(geth->dev, "fill entry %d page ref count %d add %d refs\n", 901 pn, page_ref_count(page), 1 << fpp_order); 902 903 if (page_ref_count(page) > 1) { 904 unsigned int fl = (pn - epn) & m_pn; 905 906 if (fl > 64 >> fpp_order) 907 break; 908 909 page = geth_freeq_alloc_map_page(geth, pn); 910 if (!page) 911 break; 912 } 913 914 /* Add one reference per fragment in the page */ 915 page_ref_add(page, 1 << fpp_order); 916 count += 1 << fpp_order; 917 pn++; 918 pn &= m_pn; 919 } 920 921 writew(pn << fpp_order, geth->base + GLOBAL_SWFQ_RWPTR_REG + 2); 922 923 spin_unlock_irqrestore(&geth->freeq_lock, flags); 924 925 return count; 926 } 927 928 static int geth_setup_freeq(struct gemini_ethernet *geth) 929 { 930 unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order; 931 unsigned int frag_len = 1 << geth->freeq_frag_order; 932 unsigned int len = 1 << geth->freeq_order; 933 unsigned int pages = len >> fpp_order; 934 union queue_threshold qt; 935 union dma_skb_size skbsz; 936 unsigned int filled; 937 unsigned int pn; 938 939 geth->freeq_ring = dma_alloc_coherent(geth->dev, 940 sizeof(*geth->freeq_ring) << geth->freeq_order, 941 &geth->freeq_dma_base, GFP_KERNEL); 942 if (!geth->freeq_ring) 943 return -ENOMEM; 944 if (geth->freeq_dma_base & ~DMA_Q_BASE_MASK) { 945 dev_warn(geth->dev, "queue ring base is not aligned\n"); 946 goto err_freeq; 947 } 948 949 /* Allocate a mapping to page look-up index */ 950 geth->freeq_pages = kcalloc(pages, sizeof(*geth->freeq_pages), 951 GFP_KERNEL); 952 if (!geth->freeq_pages) 953 goto err_freeq; 954 geth->num_freeq_pages = pages; 955 956 dev_info(geth->dev, "allocate %d pages for queue\n", pages); 957 for (pn = 0; pn < pages; pn++) 958 if (!geth_freeq_alloc_map_page(geth, pn)) 959 goto err_freeq_alloc; 960 961 filled = geth_fill_freeq(geth, false); 962 if (!filled) 963 goto err_freeq_alloc; 964 965 qt.bits32 = readl(geth->base + GLOBAL_QUEUE_THRESHOLD_REG); 966 qt.bits.swfq_empty = 32; 967 writel(qt.bits32, geth->base + GLOBAL_QUEUE_THRESHOLD_REG); 968 969 skbsz.bits.sw_skb_size = 1 << geth->freeq_frag_order; 970 writel(skbsz.bits32, geth->base + GLOBAL_DMA_SKB_SIZE_REG); 971 writel(geth->freeq_dma_base | geth->freeq_order, 972 geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG); 973 974 return 0; 975 976 err_freeq_alloc: 977 while (pn > 0) { 978 struct gmac_queue_page *gpage; 979 dma_addr_t mapping; 980 981 --pn; 982 mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr; 983 dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE); 984 gpage = &geth->freeq_pages[pn]; 985 put_page(gpage->page); 986 } 987 988 kfree(geth->freeq_pages); 989 err_freeq: 990 dma_free_coherent(geth->dev, 991 sizeof(*geth->freeq_ring) << geth->freeq_order, 992 geth->freeq_ring, geth->freeq_dma_base); 993 geth->freeq_ring = NULL; 994 return -ENOMEM; 995 } 996 997 /** 998 * geth_cleanup_freeq() - cleanup the DMA mappings and free the queue 999 * @geth: the Gemini global ethernet state 1000 */ 1001 static void geth_cleanup_freeq(struct gemini_ethernet *geth) 1002 { 1003 unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order; 1004 unsigned int frag_len = 1 << geth->freeq_frag_order; 1005 unsigned int len = 1 << geth->freeq_order; 1006 unsigned int pages = len >> fpp_order; 1007 unsigned int pn; 1008 1009 writew(readw(geth->base + GLOBAL_SWFQ_RWPTR_REG), 1010 geth->base + GLOBAL_SWFQ_RWPTR_REG + 2); 1011 writel(0, geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG); 1012 1013 for (pn = 0; pn < pages; pn++) { 1014 struct gmac_queue_page *gpage; 1015 dma_addr_t mapping; 1016 1017 mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr; 1018 dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE); 1019 1020 gpage = &geth->freeq_pages[pn]; 1021 while (page_ref_count(gpage->page) > 0) 1022 put_page(gpage->page); 1023 } 1024 1025 kfree(geth->freeq_pages); 1026 1027 dma_free_coherent(geth->dev, 1028 sizeof(*geth->freeq_ring) << geth->freeq_order, 1029 geth->freeq_ring, geth->freeq_dma_base); 1030 } 1031 1032 /** 1033 * geth_resize_freeq() - resize the software queue depth 1034 * @port: the port requesting the change 1035 * 1036 * This gets called at least once during probe() so the device queue gets 1037 * "resized" from the hardware defaults. Since both ports/net devices share 1038 * the same hardware queue, some synchronization between the ports is 1039 * needed. 1040 */ 1041 static int geth_resize_freeq(struct gemini_ethernet_port *port) 1042 { 1043 struct gemini_ethernet *geth = port->geth; 1044 struct net_device *netdev = port->netdev; 1045 struct gemini_ethernet_port *other_port; 1046 struct net_device *other_netdev; 1047 unsigned int new_size = 0; 1048 unsigned int new_order; 1049 unsigned long flags; 1050 u32 en; 1051 int ret; 1052 1053 if (netdev->dev_id == 0) 1054 other_netdev = geth->port1->netdev; 1055 else 1056 other_netdev = geth->port0->netdev; 1057 1058 if (other_netdev && netif_running(other_netdev)) 1059 return -EBUSY; 1060 1061 new_size = 1 << (port->rxq_order + 1); 1062 netdev_dbg(netdev, "port %d size: %d order %d\n", 1063 netdev->dev_id, 1064 new_size, 1065 port->rxq_order); 1066 if (other_netdev) { 1067 other_port = netdev_priv(other_netdev); 1068 new_size += 1 << (other_port->rxq_order + 1); 1069 netdev_dbg(other_netdev, "port %d size: %d order %d\n", 1070 other_netdev->dev_id, 1071 (1 << (other_port->rxq_order + 1)), 1072 other_port->rxq_order); 1073 } 1074 1075 new_order = min(15, ilog2(new_size - 1) + 1); 1076 dev_dbg(geth->dev, "set shared queue to size %d order %d\n", 1077 new_size, new_order); 1078 if (geth->freeq_order == new_order) 1079 return 0; 1080 1081 spin_lock_irqsave(&geth->irq_lock, flags); 1082 1083 /* Disable the software queue IRQs */ 1084 en = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); 1085 en &= ~SWFQ_EMPTY_INT_BIT; 1086 writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); 1087 spin_unlock_irqrestore(&geth->irq_lock, flags); 1088 1089 /* Drop the old queue */ 1090 if (geth->freeq_ring) 1091 geth_cleanup_freeq(geth); 1092 1093 /* Allocate a new queue with the desired order */ 1094 geth->freeq_order = new_order; 1095 ret = geth_setup_freeq(geth); 1096 1097 /* Restart the interrupts - NOTE if this is the first resize 1098 * after probe(), this is where the interrupts get turned on 1099 * in the first place. 1100 */ 1101 spin_lock_irqsave(&geth->irq_lock, flags); 1102 en |= SWFQ_EMPTY_INT_BIT; 1103 writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); 1104 spin_unlock_irqrestore(&geth->irq_lock, flags); 1105 1106 return ret; 1107 } 1108 1109 static void gmac_tx_irq_enable(struct net_device *netdev, 1110 unsigned int txq, int en) 1111 { 1112 struct gemini_ethernet_port *port = netdev_priv(netdev); 1113 struct gemini_ethernet *geth = port->geth; 1114 u32 val, mask; 1115 1116 netdev_dbg(netdev, "%s device %d\n", __func__, netdev->dev_id); 1117 1118 mask = GMAC0_IRQ0_TXQ0_INTS << (6 * netdev->dev_id + txq); 1119 1120 if (en) 1121 writel(mask, geth->base + GLOBAL_INTERRUPT_STATUS_0_REG); 1122 1123 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG); 1124 val = en ? val | mask : val & ~mask; 1125 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG); 1126 } 1127 1128 static void gmac_tx_irq(struct net_device *netdev, unsigned int txq_num) 1129 { 1130 struct netdev_queue *ntxq = netdev_get_tx_queue(netdev, txq_num); 1131 1132 gmac_tx_irq_enable(netdev, txq_num, 0); 1133 netif_tx_wake_queue(ntxq); 1134 } 1135 1136 static int gmac_map_tx_bufs(struct net_device *netdev, struct sk_buff *skb, 1137 struct gmac_txq *txq, unsigned short *desc) 1138 { 1139 struct gemini_ethernet_port *port = netdev_priv(netdev); 1140 struct skb_shared_info *skb_si = skb_shinfo(skb); 1141 unsigned short m = (1 << port->txq_order) - 1; 1142 short frag, last_frag = skb_si->nr_frags - 1; 1143 struct gemini_ethernet *geth = port->geth; 1144 unsigned int word1, word3, buflen; 1145 unsigned short w = *desc; 1146 struct gmac_txdesc *txd; 1147 skb_frag_t *skb_frag; 1148 dma_addr_t mapping; 1149 unsigned short mtu; 1150 void *buffer; 1151 1152 mtu = ETH_HLEN; 1153 mtu += netdev->mtu; 1154 if (skb->protocol == htons(ETH_P_8021Q)) 1155 mtu += VLAN_HLEN; 1156 1157 word1 = skb->len; 1158 word3 = SOF_BIT; 1159 1160 if (word1 > mtu) { 1161 word1 |= TSS_MTU_ENABLE_BIT; 1162 word3 |= mtu; 1163 } 1164 1165 if (skb->ip_summed != CHECKSUM_NONE) { 1166 int tcp = 0; 1167 1168 if (skb->protocol == htons(ETH_P_IP)) { 1169 word1 |= TSS_IP_CHKSUM_BIT; 1170 tcp = ip_hdr(skb)->protocol == IPPROTO_TCP; 1171 } else { /* IPv6 */ 1172 word1 |= TSS_IPV6_ENABLE_BIT; 1173 tcp = ipv6_hdr(skb)->nexthdr == IPPROTO_TCP; 1174 } 1175 1176 word1 |= tcp ? TSS_TCP_CHKSUM_BIT : TSS_UDP_CHKSUM_BIT; 1177 } 1178 1179 frag = -1; 1180 while (frag <= last_frag) { 1181 if (frag == -1) { 1182 buffer = skb->data; 1183 buflen = skb_headlen(skb); 1184 } else { 1185 skb_frag = skb_si->frags + frag; 1186 buffer = page_address(skb_frag_page(skb_frag)) + 1187 skb_frag->page_offset; 1188 buflen = skb_frag->size; 1189 } 1190 1191 if (frag == last_frag) { 1192 word3 |= EOF_BIT; 1193 txq->skb[w] = skb; 1194 } 1195 1196 mapping = dma_map_single(geth->dev, buffer, buflen, 1197 DMA_TO_DEVICE); 1198 if (dma_mapping_error(geth->dev, mapping)) 1199 goto map_error; 1200 1201 txd = txq->ring + w; 1202 txd->word0.bits32 = buflen; 1203 txd->word1.bits32 = word1; 1204 txd->word2.buf_adr = mapping; 1205 txd->word3.bits32 = word3; 1206 1207 word3 &= MTU_SIZE_BIT_MASK; 1208 w++; 1209 w &= m; 1210 frag++; 1211 } 1212 1213 *desc = w; 1214 return 0; 1215 1216 map_error: 1217 while (w != *desc) { 1218 w--; 1219 w &= m; 1220 1221 dma_unmap_page(geth->dev, txq->ring[w].word2.buf_adr, 1222 txq->ring[w].word0.bits.buffer_size, 1223 DMA_TO_DEVICE); 1224 } 1225 return -ENOMEM; 1226 } 1227 1228 static int gmac_start_xmit(struct sk_buff *skb, struct net_device *netdev) 1229 { 1230 struct gemini_ethernet_port *port = netdev_priv(netdev); 1231 unsigned short m = (1 << port->txq_order) - 1; 1232 struct netdev_queue *ntxq; 1233 unsigned short r, w, d; 1234 void __iomem *ptr_reg; 1235 struct gmac_txq *txq; 1236 int txq_num, nfrags; 1237 union dma_rwptr rw; 1238 1239 SKB_FRAG_ASSERT(skb); 1240 1241 if (skb->len >= 0x10000) 1242 goto out_drop_free; 1243 1244 txq_num = skb_get_queue_mapping(skb); 1245 ptr_reg = port->dma_base + GMAC_SW_TX_QUEUE_PTR_REG(txq_num); 1246 txq = &port->txq[txq_num]; 1247 ntxq = netdev_get_tx_queue(netdev, txq_num); 1248 nfrags = skb_shinfo(skb)->nr_frags; 1249 1250 rw.bits32 = readl(ptr_reg); 1251 r = rw.bits.rptr; 1252 w = rw.bits.wptr; 1253 1254 d = txq->cptr - w - 1; 1255 d &= m; 1256 1257 if (d < nfrags + 2) { 1258 gmac_clean_txq(netdev, txq, r); 1259 d = txq->cptr - w - 1; 1260 d &= m; 1261 1262 if (d < nfrags + 2) { 1263 netif_tx_stop_queue(ntxq); 1264 1265 d = txq->cptr + nfrags + 16; 1266 d &= m; 1267 txq->ring[d].word3.bits.eofie = 1; 1268 gmac_tx_irq_enable(netdev, txq_num, 1); 1269 1270 u64_stats_update_begin(&port->tx_stats_syncp); 1271 netdev->stats.tx_fifo_errors++; 1272 u64_stats_update_end(&port->tx_stats_syncp); 1273 return NETDEV_TX_BUSY; 1274 } 1275 } 1276 1277 if (gmac_map_tx_bufs(netdev, skb, txq, &w)) { 1278 if (skb_linearize(skb)) 1279 goto out_drop; 1280 1281 u64_stats_update_begin(&port->tx_stats_syncp); 1282 port->tx_frags_linearized++; 1283 u64_stats_update_end(&port->tx_stats_syncp); 1284 1285 if (gmac_map_tx_bufs(netdev, skb, txq, &w)) 1286 goto out_drop_free; 1287 } 1288 1289 writew(w, ptr_reg + 2); 1290 1291 gmac_clean_txq(netdev, txq, r); 1292 return NETDEV_TX_OK; 1293 1294 out_drop_free: 1295 dev_kfree_skb(skb); 1296 out_drop: 1297 u64_stats_update_begin(&port->tx_stats_syncp); 1298 port->stats.tx_dropped++; 1299 u64_stats_update_end(&port->tx_stats_syncp); 1300 return NETDEV_TX_OK; 1301 } 1302 1303 static void gmac_tx_timeout(struct net_device *netdev) 1304 { 1305 netdev_err(netdev, "Tx timeout\n"); 1306 gmac_dump_dma_state(netdev); 1307 } 1308 1309 static void gmac_enable_irq(struct net_device *netdev, int enable) 1310 { 1311 struct gemini_ethernet_port *port = netdev_priv(netdev); 1312 struct gemini_ethernet *geth = port->geth; 1313 unsigned long flags; 1314 u32 val, mask; 1315 1316 netdev_dbg(netdev, "%s device %d %s\n", __func__, 1317 netdev->dev_id, enable ? "enable" : "disable"); 1318 spin_lock_irqsave(&geth->irq_lock, flags); 1319 1320 mask = GMAC0_IRQ0_2 << (netdev->dev_id * 2); 1321 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG); 1322 val = enable ? (val | mask) : (val & ~mask); 1323 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG); 1324 1325 mask = DEFAULT_Q0_INT_BIT << netdev->dev_id; 1326 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG); 1327 val = enable ? (val | mask) : (val & ~mask); 1328 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG); 1329 1330 mask = GMAC0_IRQ4_8 << (netdev->dev_id * 8); 1331 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); 1332 val = enable ? (val | mask) : (val & ~mask); 1333 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); 1334 1335 spin_unlock_irqrestore(&geth->irq_lock, flags); 1336 } 1337 1338 static void gmac_enable_rx_irq(struct net_device *netdev, int enable) 1339 { 1340 struct gemini_ethernet_port *port = netdev_priv(netdev); 1341 struct gemini_ethernet *geth = port->geth; 1342 unsigned long flags; 1343 u32 val, mask; 1344 1345 netdev_dbg(netdev, "%s device %d %s\n", __func__, netdev->dev_id, 1346 enable ? "enable" : "disable"); 1347 spin_lock_irqsave(&geth->irq_lock, flags); 1348 mask = DEFAULT_Q0_INT_BIT << netdev->dev_id; 1349 1350 val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG); 1351 val = enable ? (val | mask) : (val & ~mask); 1352 writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG); 1353 1354 spin_unlock_irqrestore(&geth->irq_lock, flags); 1355 } 1356 1357 static struct sk_buff *gmac_skb_if_good_frame(struct gemini_ethernet_port *port, 1358 union gmac_rxdesc_0 word0, 1359 unsigned int frame_len) 1360 { 1361 unsigned int rx_csum = word0.bits.chksum_status; 1362 unsigned int rx_status = word0.bits.status; 1363 struct sk_buff *skb = NULL; 1364 1365 port->rx_stats[rx_status]++; 1366 port->rx_csum_stats[rx_csum]++; 1367 1368 if (word0.bits.derr || word0.bits.perr || 1369 rx_status || frame_len < ETH_ZLEN || 1370 rx_csum >= RX_CHKSUM_IP_ERR_UNKNOWN) { 1371 port->stats.rx_errors++; 1372 1373 if (frame_len < ETH_ZLEN || RX_ERROR_LENGTH(rx_status)) 1374 port->stats.rx_length_errors++; 1375 if (RX_ERROR_OVER(rx_status)) 1376 port->stats.rx_over_errors++; 1377 if (RX_ERROR_CRC(rx_status)) 1378 port->stats.rx_crc_errors++; 1379 if (RX_ERROR_FRAME(rx_status)) 1380 port->stats.rx_frame_errors++; 1381 return NULL; 1382 } 1383 1384 skb = napi_get_frags(&port->napi); 1385 if (!skb) 1386 goto update_exit; 1387 1388 if (rx_csum == RX_CHKSUM_IP_UDP_TCP_OK) 1389 skb->ip_summed = CHECKSUM_UNNECESSARY; 1390 1391 update_exit: 1392 port->stats.rx_bytes += frame_len; 1393 port->stats.rx_packets++; 1394 return skb; 1395 } 1396 1397 static unsigned int gmac_rx(struct net_device *netdev, unsigned int budget) 1398 { 1399 struct gemini_ethernet_port *port = netdev_priv(netdev); 1400 unsigned short m = (1 << port->rxq_order) - 1; 1401 struct gemini_ethernet *geth = port->geth; 1402 void __iomem *ptr_reg = port->rxq_rwptr; 1403 unsigned int frame_len, frag_len; 1404 struct gmac_rxdesc *rx = NULL; 1405 struct gmac_queue_page *gpage; 1406 static struct sk_buff *skb; 1407 union gmac_rxdesc_0 word0; 1408 union gmac_rxdesc_1 word1; 1409 union gmac_rxdesc_3 word3; 1410 struct page *page = NULL; 1411 unsigned int page_offs; 1412 unsigned short r, w; 1413 union dma_rwptr rw; 1414 dma_addr_t mapping; 1415 int frag_nr = 0; 1416 1417 rw.bits32 = readl(ptr_reg); 1418 /* Reset interrupt as all packages until here are taken into account */ 1419 writel(DEFAULT_Q0_INT_BIT << netdev->dev_id, 1420 geth->base + GLOBAL_INTERRUPT_STATUS_1_REG); 1421 r = rw.bits.rptr; 1422 w = rw.bits.wptr; 1423 1424 while (budget && w != r) { 1425 rx = port->rxq_ring + r; 1426 word0 = rx->word0; 1427 word1 = rx->word1; 1428 mapping = rx->word2.buf_adr; 1429 word3 = rx->word3; 1430 1431 r++; 1432 r &= m; 1433 1434 frag_len = word0.bits.buffer_size; 1435 frame_len = word1.bits.byte_count; 1436 page_offs = mapping & ~PAGE_MASK; 1437 1438 if (!mapping) { 1439 netdev_err(netdev, 1440 "rxq[%u]: HW BUG: zero DMA desc\n", r); 1441 goto err_drop; 1442 } 1443 1444 /* Freeq pointers are one page off */ 1445 gpage = gmac_get_queue_page(geth, port, mapping + PAGE_SIZE); 1446 if (!gpage) { 1447 dev_err(geth->dev, "could not find mapping\n"); 1448 continue; 1449 } 1450 page = gpage->page; 1451 1452 if (word3.bits32 & SOF_BIT) { 1453 if (skb) { 1454 napi_free_frags(&port->napi); 1455 port->stats.rx_dropped++; 1456 } 1457 1458 skb = gmac_skb_if_good_frame(port, word0, frame_len); 1459 if (!skb) 1460 goto err_drop; 1461 1462 page_offs += NET_IP_ALIGN; 1463 frag_len -= NET_IP_ALIGN; 1464 frag_nr = 0; 1465 1466 } else if (!skb) { 1467 put_page(page); 1468 continue; 1469 } 1470 1471 if (word3.bits32 & EOF_BIT) 1472 frag_len = frame_len - skb->len; 1473 1474 /* append page frag to skb */ 1475 if (frag_nr == MAX_SKB_FRAGS) 1476 goto err_drop; 1477 1478 if (frag_len == 0) 1479 netdev_err(netdev, "Received fragment with len = 0\n"); 1480 1481 skb_fill_page_desc(skb, frag_nr, page, page_offs, frag_len); 1482 skb->len += frag_len; 1483 skb->data_len += frag_len; 1484 skb->truesize += frag_len; 1485 frag_nr++; 1486 1487 if (word3.bits32 & EOF_BIT) { 1488 napi_gro_frags(&port->napi); 1489 skb = NULL; 1490 --budget; 1491 } 1492 continue; 1493 1494 err_drop: 1495 if (skb) { 1496 napi_free_frags(&port->napi); 1497 skb = NULL; 1498 } 1499 1500 if (mapping) 1501 put_page(page); 1502 1503 port->stats.rx_dropped++; 1504 } 1505 1506 writew(r, ptr_reg); 1507 return budget; 1508 } 1509 1510 static int gmac_napi_poll(struct napi_struct *napi, int budget) 1511 { 1512 struct gemini_ethernet_port *port = netdev_priv(napi->dev); 1513 struct gemini_ethernet *geth = port->geth; 1514 unsigned int freeq_threshold; 1515 unsigned int received; 1516 1517 freeq_threshold = 1 << (geth->freeq_order - 1); 1518 u64_stats_update_begin(&port->rx_stats_syncp); 1519 1520 received = gmac_rx(napi->dev, budget); 1521 if (received < budget) { 1522 napi_gro_flush(napi, false); 1523 napi_complete_done(napi, received); 1524 gmac_enable_rx_irq(napi->dev, 1); 1525 ++port->rx_napi_exits; 1526 } 1527 1528 port->freeq_refill += (budget - received); 1529 if (port->freeq_refill > freeq_threshold) { 1530 port->freeq_refill -= freeq_threshold; 1531 geth_fill_freeq(geth, true); 1532 } 1533 1534 u64_stats_update_end(&port->rx_stats_syncp); 1535 return received; 1536 } 1537 1538 static void gmac_dump_dma_state(struct net_device *netdev) 1539 { 1540 struct gemini_ethernet_port *port = netdev_priv(netdev); 1541 struct gemini_ethernet *geth = port->geth; 1542 void __iomem *ptr_reg; 1543 u32 reg[5]; 1544 1545 /* Interrupt status */ 1546 reg[0] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_0_REG); 1547 reg[1] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_1_REG); 1548 reg[2] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_2_REG); 1549 reg[3] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_3_REG); 1550 reg[4] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_4_REG); 1551 netdev_err(netdev, "IRQ status: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", 1552 reg[0], reg[1], reg[2], reg[3], reg[4]); 1553 1554 /* Interrupt enable */ 1555 reg[0] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG); 1556 reg[1] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG); 1557 reg[2] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_2_REG); 1558 reg[3] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_3_REG); 1559 reg[4] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); 1560 netdev_err(netdev, "IRQ enable: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", 1561 reg[0], reg[1], reg[2], reg[3], reg[4]); 1562 1563 /* RX DMA status */ 1564 reg[0] = readl(port->dma_base + GMAC_DMA_RX_FIRST_DESC_REG); 1565 reg[1] = readl(port->dma_base + GMAC_DMA_RX_CURR_DESC_REG); 1566 reg[2] = GET_RPTR(port->rxq_rwptr); 1567 reg[3] = GET_WPTR(port->rxq_rwptr); 1568 netdev_err(netdev, "RX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n", 1569 reg[0], reg[1], reg[2], reg[3]); 1570 1571 reg[0] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD0_REG); 1572 reg[1] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD1_REG); 1573 reg[2] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD2_REG); 1574 reg[3] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD3_REG); 1575 netdev_err(netdev, "RX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n", 1576 reg[0], reg[1], reg[2], reg[3]); 1577 1578 /* TX DMA status */ 1579 ptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG; 1580 1581 reg[0] = readl(port->dma_base + GMAC_DMA_TX_FIRST_DESC_REG); 1582 reg[1] = readl(port->dma_base + GMAC_DMA_TX_CURR_DESC_REG); 1583 reg[2] = GET_RPTR(ptr_reg); 1584 reg[3] = GET_WPTR(ptr_reg); 1585 netdev_err(netdev, "TX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n", 1586 reg[0], reg[1], reg[2], reg[3]); 1587 1588 reg[0] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD0_REG); 1589 reg[1] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD1_REG); 1590 reg[2] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD2_REG); 1591 reg[3] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD3_REG); 1592 netdev_err(netdev, "TX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n", 1593 reg[0], reg[1], reg[2], reg[3]); 1594 1595 /* FREE queues status */ 1596 ptr_reg = geth->base + GLOBAL_SWFQ_RWPTR_REG; 1597 1598 reg[0] = GET_RPTR(ptr_reg); 1599 reg[1] = GET_WPTR(ptr_reg); 1600 1601 ptr_reg = geth->base + GLOBAL_HWFQ_RWPTR_REG; 1602 1603 reg[2] = GET_RPTR(ptr_reg); 1604 reg[3] = GET_WPTR(ptr_reg); 1605 netdev_err(netdev, "FQ SW ptr: %u %u, HW ptr: %u %u\n", 1606 reg[0], reg[1], reg[2], reg[3]); 1607 } 1608 1609 static void gmac_update_hw_stats(struct net_device *netdev) 1610 { 1611 struct gemini_ethernet_port *port = netdev_priv(netdev); 1612 unsigned int rx_discards, rx_mcast, rx_bcast; 1613 struct gemini_ethernet *geth = port->geth; 1614 unsigned long flags; 1615 1616 spin_lock_irqsave(&geth->irq_lock, flags); 1617 u64_stats_update_begin(&port->ir_stats_syncp); 1618 1619 rx_discards = readl(port->gmac_base + GMAC_IN_DISCARDS); 1620 port->hw_stats[0] += rx_discards; 1621 port->hw_stats[1] += readl(port->gmac_base + GMAC_IN_ERRORS); 1622 rx_mcast = readl(port->gmac_base + GMAC_IN_MCAST); 1623 port->hw_stats[2] += rx_mcast; 1624 rx_bcast = readl(port->gmac_base + GMAC_IN_BCAST); 1625 port->hw_stats[3] += rx_bcast; 1626 port->hw_stats[4] += readl(port->gmac_base + GMAC_IN_MAC1); 1627 port->hw_stats[5] += readl(port->gmac_base + GMAC_IN_MAC2); 1628 1629 port->stats.rx_missed_errors += rx_discards; 1630 port->stats.multicast += rx_mcast; 1631 port->stats.multicast += rx_bcast; 1632 1633 writel(GMAC0_MIB_INT_BIT << (netdev->dev_id * 8), 1634 geth->base + GLOBAL_INTERRUPT_STATUS_4_REG); 1635 1636 u64_stats_update_end(&port->ir_stats_syncp); 1637 spin_unlock_irqrestore(&geth->irq_lock, flags); 1638 } 1639 1640 /** 1641 * gmac_get_intr_flags() - get interrupt status flags for a port from 1642 * @netdev: the net device for the port to get flags from 1643 * @i: the interrupt status register 0..4 1644 */ 1645 static u32 gmac_get_intr_flags(struct net_device *netdev, int i) 1646 { 1647 struct gemini_ethernet_port *port = netdev_priv(netdev); 1648 struct gemini_ethernet *geth = port->geth; 1649 void __iomem *irqif_reg, *irqen_reg; 1650 unsigned int offs, val; 1651 1652 /* Calculate the offset using the stride of the status registers */ 1653 offs = i * (GLOBAL_INTERRUPT_STATUS_1_REG - 1654 GLOBAL_INTERRUPT_STATUS_0_REG); 1655 1656 irqif_reg = geth->base + GLOBAL_INTERRUPT_STATUS_0_REG + offs; 1657 irqen_reg = geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG + offs; 1658 1659 val = readl(irqif_reg) & readl(irqen_reg); 1660 return val; 1661 } 1662 1663 static enum hrtimer_restart gmac_coalesce_delay_expired(struct hrtimer *timer) 1664 { 1665 struct gemini_ethernet_port *port = 1666 container_of(timer, struct gemini_ethernet_port, 1667 rx_coalesce_timer); 1668 1669 napi_schedule(&port->napi); 1670 return HRTIMER_NORESTART; 1671 } 1672 1673 static irqreturn_t gmac_irq(int irq, void *data) 1674 { 1675 struct gemini_ethernet_port *port; 1676 struct net_device *netdev = data; 1677 struct gemini_ethernet *geth; 1678 u32 val, orr = 0; 1679 1680 port = netdev_priv(netdev); 1681 geth = port->geth; 1682 1683 val = gmac_get_intr_flags(netdev, 0); 1684 orr |= val; 1685 1686 if (val & (GMAC0_IRQ0_2 << (netdev->dev_id * 2))) { 1687 /* Oh, crap */ 1688 netdev_err(netdev, "hw failure/sw bug\n"); 1689 gmac_dump_dma_state(netdev); 1690 1691 /* don't know how to recover, just reduce losses */ 1692 gmac_enable_irq(netdev, 0); 1693 return IRQ_HANDLED; 1694 } 1695 1696 if (val & (GMAC0_IRQ0_TXQ0_INTS << (netdev->dev_id * 6))) 1697 gmac_tx_irq(netdev, 0); 1698 1699 val = gmac_get_intr_flags(netdev, 1); 1700 orr |= val; 1701 1702 if (val & (DEFAULT_Q0_INT_BIT << netdev->dev_id)) { 1703 gmac_enable_rx_irq(netdev, 0); 1704 1705 if (!port->rx_coalesce_nsecs) { 1706 napi_schedule(&port->napi); 1707 } else { 1708 ktime_t ktime; 1709 1710 ktime = ktime_set(0, port->rx_coalesce_nsecs); 1711 hrtimer_start(&port->rx_coalesce_timer, ktime, 1712 HRTIMER_MODE_REL); 1713 } 1714 } 1715 1716 val = gmac_get_intr_flags(netdev, 4); 1717 orr |= val; 1718 1719 if (val & (GMAC0_MIB_INT_BIT << (netdev->dev_id * 8))) 1720 gmac_update_hw_stats(netdev); 1721 1722 if (val & (GMAC0_RX_OVERRUN_INT_BIT << (netdev->dev_id * 8))) { 1723 writel(GMAC0_RXDERR_INT_BIT << (netdev->dev_id * 8), 1724 geth->base + GLOBAL_INTERRUPT_STATUS_4_REG); 1725 1726 spin_lock(&geth->irq_lock); 1727 u64_stats_update_begin(&port->ir_stats_syncp); 1728 ++port->stats.rx_fifo_errors; 1729 u64_stats_update_end(&port->ir_stats_syncp); 1730 spin_unlock(&geth->irq_lock); 1731 } 1732 1733 return orr ? IRQ_HANDLED : IRQ_NONE; 1734 } 1735 1736 static void gmac_start_dma(struct gemini_ethernet_port *port) 1737 { 1738 void __iomem *dma_ctrl_reg = port->dma_base + GMAC_DMA_CTRL_REG; 1739 union gmac_dma_ctrl dma_ctrl; 1740 1741 dma_ctrl.bits32 = readl(dma_ctrl_reg); 1742 dma_ctrl.bits.rd_enable = 1; 1743 dma_ctrl.bits.td_enable = 1; 1744 dma_ctrl.bits.loopback = 0; 1745 dma_ctrl.bits.drop_small_ack = 0; 1746 dma_ctrl.bits.rd_insert_bytes = NET_IP_ALIGN; 1747 dma_ctrl.bits.rd_prot = HPROT_DATA_CACHE | HPROT_PRIVILIGED; 1748 dma_ctrl.bits.rd_burst_size = HBURST_INCR8; 1749 dma_ctrl.bits.rd_bus = HSIZE_8; 1750 dma_ctrl.bits.td_prot = HPROT_DATA_CACHE; 1751 dma_ctrl.bits.td_burst_size = HBURST_INCR8; 1752 dma_ctrl.bits.td_bus = HSIZE_8; 1753 1754 writel(dma_ctrl.bits32, dma_ctrl_reg); 1755 } 1756 1757 static void gmac_stop_dma(struct gemini_ethernet_port *port) 1758 { 1759 void __iomem *dma_ctrl_reg = port->dma_base + GMAC_DMA_CTRL_REG; 1760 union gmac_dma_ctrl dma_ctrl; 1761 1762 dma_ctrl.bits32 = readl(dma_ctrl_reg); 1763 dma_ctrl.bits.rd_enable = 0; 1764 dma_ctrl.bits.td_enable = 0; 1765 writel(dma_ctrl.bits32, dma_ctrl_reg); 1766 } 1767 1768 static int gmac_open(struct net_device *netdev) 1769 { 1770 struct gemini_ethernet_port *port = netdev_priv(netdev); 1771 int err; 1772 1773 if (!netdev->phydev) { 1774 err = gmac_setup_phy(netdev); 1775 if (err) { 1776 netif_err(port, ifup, netdev, 1777 "PHY init failed: %d\n", err); 1778 return err; 1779 } 1780 } 1781 1782 err = request_irq(netdev->irq, gmac_irq, 1783 IRQF_SHARED, netdev->name, netdev); 1784 if (err) { 1785 netdev_err(netdev, "no IRQ\n"); 1786 return err; 1787 } 1788 1789 netif_carrier_off(netdev); 1790 phy_start(netdev->phydev); 1791 1792 err = geth_resize_freeq(port); 1793 /* It's fine if it's just busy, the other port has set up 1794 * the freeq in that case. 1795 */ 1796 if (err && (err != -EBUSY)) { 1797 netdev_err(netdev, "could not resize freeq\n"); 1798 goto err_stop_phy; 1799 } 1800 1801 err = gmac_setup_rxq(netdev); 1802 if (err) { 1803 netdev_err(netdev, "could not setup RXQ\n"); 1804 goto err_stop_phy; 1805 } 1806 1807 err = gmac_setup_txqs(netdev); 1808 if (err) { 1809 netdev_err(netdev, "could not setup TXQs\n"); 1810 gmac_cleanup_rxq(netdev); 1811 goto err_stop_phy; 1812 } 1813 1814 napi_enable(&port->napi); 1815 1816 gmac_start_dma(port); 1817 gmac_enable_irq(netdev, 1); 1818 gmac_enable_tx_rx(netdev); 1819 netif_tx_start_all_queues(netdev); 1820 1821 hrtimer_init(&port->rx_coalesce_timer, CLOCK_MONOTONIC, 1822 HRTIMER_MODE_REL); 1823 port->rx_coalesce_timer.function = &gmac_coalesce_delay_expired; 1824 1825 netdev_dbg(netdev, "opened\n"); 1826 1827 return 0; 1828 1829 err_stop_phy: 1830 phy_stop(netdev->phydev); 1831 free_irq(netdev->irq, netdev); 1832 return err; 1833 } 1834 1835 static int gmac_stop(struct net_device *netdev) 1836 { 1837 struct gemini_ethernet_port *port = netdev_priv(netdev); 1838 1839 hrtimer_cancel(&port->rx_coalesce_timer); 1840 netif_tx_stop_all_queues(netdev); 1841 gmac_disable_tx_rx(netdev); 1842 gmac_stop_dma(port); 1843 napi_disable(&port->napi); 1844 1845 gmac_enable_irq(netdev, 0); 1846 gmac_cleanup_rxq(netdev); 1847 gmac_cleanup_txqs(netdev); 1848 1849 phy_stop(netdev->phydev); 1850 free_irq(netdev->irq, netdev); 1851 1852 gmac_update_hw_stats(netdev); 1853 return 0; 1854 } 1855 1856 static void gmac_set_rx_mode(struct net_device *netdev) 1857 { 1858 struct gemini_ethernet_port *port = netdev_priv(netdev); 1859 union gmac_rx_fltr filter = { .bits = { 1860 .broadcast = 1, 1861 .multicast = 1, 1862 .unicast = 1, 1863 } }; 1864 struct netdev_hw_addr *ha; 1865 unsigned int bit_nr; 1866 u32 mc_filter[2]; 1867 1868 mc_filter[1] = 0; 1869 mc_filter[0] = 0; 1870 1871 if (netdev->flags & IFF_PROMISC) { 1872 filter.bits.error = 1; 1873 filter.bits.promiscuous = 1; 1874 mc_filter[1] = ~0; 1875 mc_filter[0] = ~0; 1876 } else if (netdev->flags & IFF_ALLMULTI) { 1877 mc_filter[1] = ~0; 1878 mc_filter[0] = ~0; 1879 } else { 1880 netdev_for_each_mc_addr(ha, netdev) { 1881 bit_nr = ~crc32_le(~0, ha->addr, ETH_ALEN) & 0x3f; 1882 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 0x1f); 1883 } 1884 } 1885 1886 writel(mc_filter[0], port->gmac_base + GMAC_MCAST_FIL0); 1887 writel(mc_filter[1], port->gmac_base + GMAC_MCAST_FIL1); 1888 writel(filter.bits32, port->gmac_base + GMAC_RX_FLTR); 1889 } 1890 1891 static void gmac_write_mac_address(struct net_device *netdev) 1892 { 1893 struct gemini_ethernet_port *port = netdev_priv(netdev); 1894 __le32 addr[3]; 1895 1896 memset(addr, 0, sizeof(addr)); 1897 memcpy(addr, netdev->dev_addr, ETH_ALEN); 1898 1899 writel(le32_to_cpu(addr[0]), port->gmac_base + GMAC_STA_ADD0); 1900 writel(le32_to_cpu(addr[1]), port->gmac_base + GMAC_STA_ADD1); 1901 writel(le32_to_cpu(addr[2]), port->gmac_base + GMAC_STA_ADD2); 1902 } 1903 1904 static int gmac_set_mac_address(struct net_device *netdev, void *addr) 1905 { 1906 struct sockaddr *sa = addr; 1907 1908 memcpy(netdev->dev_addr, sa->sa_data, ETH_ALEN); 1909 gmac_write_mac_address(netdev); 1910 1911 return 0; 1912 } 1913 1914 static void gmac_clear_hw_stats(struct net_device *netdev) 1915 { 1916 struct gemini_ethernet_port *port = netdev_priv(netdev); 1917 1918 readl(port->gmac_base + GMAC_IN_DISCARDS); 1919 readl(port->gmac_base + GMAC_IN_ERRORS); 1920 readl(port->gmac_base + GMAC_IN_MCAST); 1921 readl(port->gmac_base + GMAC_IN_BCAST); 1922 readl(port->gmac_base + GMAC_IN_MAC1); 1923 readl(port->gmac_base + GMAC_IN_MAC2); 1924 } 1925 1926 static void gmac_get_stats64(struct net_device *netdev, 1927 struct rtnl_link_stats64 *stats) 1928 { 1929 struct gemini_ethernet_port *port = netdev_priv(netdev); 1930 unsigned int start; 1931 1932 gmac_update_hw_stats(netdev); 1933 1934 /* Racing with RX NAPI */ 1935 do { 1936 start = u64_stats_fetch_begin(&port->rx_stats_syncp); 1937 1938 stats->rx_packets = port->stats.rx_packets; 1939 stats->rx_bytes = port->stats.rx_bytes; 1940 stats->rx_errors = port->stats.rx_errors; 1941 stats->rx_dropped = port->stats.rx_dropped; 1942 1943 stats->rx_length_errors = port->stats.rx_length_errors; 1944 stats->rx_over_errors = port->stats.rx_over_errors; 1945 stats->rx_crc_errors = port->stats.rx_crc_errors; 1946 stats->rx_frame_errors = port->stats.rx_frame_errors; 1947 1948 } while (u64_stats_fetch_retry(&port->rx_stats_syncp, start)); 1949 1950 /* Racing with MIB and TX completion interrupts */ 1951 do { 1952 start = u64_stats_fetch_begin(&port->ir_stats_syncp); 1953 1954 stats->tx_errors = port->stats.tx_errors; 1955 stats->tx_packets = port->stats.tx_packets; 1956 stats->tx_bytes = port->stats.tx_bytes; 1957 1958 stats->multicast = port->stats.multicast; 1959 stats->rx_missed_errors = port->stats.rx_missed_errors; 1960 stats->rx_fifo_errors = port->stats.rx_fifo_errors; 1961 1962 } while (u64_stats_fetch_retry(&port->ir_stats_syncp, start)); 1963 1964 /* Racing with hard_start_xmit */ 1965 do { 1966 start = u64_stats_fetch_begin(&port->tx_stats_syncp); 1967 1968 stats->tx_dropped = port->stats.tx_dropped; 1969 1970 } while (u64_stats_fetch_retry(&port->tx_stats_syncp, start)); 1971 1972 stats->rx_dropped += stats->rx_missed_errors; 1973 } 1974 1975 static int gmac_change_mtu(struct net_device *netdev, int new_mtu) 1976 { 1977 int max_len = gmac_pick_rx_max_len(new_mtu); 1978 1979 if (max_len < 0) 1980 return -EINVAL; 1981 1982 gmac_disable_tx_rx(netdev); 1983 1984 netdev->mtu = new_mtu; 1985 gmac_update_config0_reg(netdev, max_len << CONFIG0_MAXLEN_SHIFT, 1986 CONFIG0_MAXLEN_MASK); 1987 1988 netdev_update_features(netdev); 1989 1990 gmac_enable_tx_rx(netdev); 1991 1992 return 0; 1993 } 1994 1995 static netdev_features_t gmac_fix_features(struct net_device *netdev, 1996 netdev_features_t features) 1997 { 1998 if (netdev->mtu + ETH_HLEN + VLAN_HLEN > MTU_SIZE_BIT_MASK) 1999 features &= ~GMAC_OFFLOAD_FEATURES; 2000 2001 return features; 2002 } 2003 2004 static int gmac_set_features(struct net_device *netdev, 2005 netdev_features_t features) 2006 { 2007 struct gemini_ethernet_port *port = netdev_priv(netdev); 2008 int enable = features & NETIF_F_RXCSUM; 2009 unsigned long flags; 2010 u32 reg; 2011 2012 spin_lock_irqsave(&port->config_lock, flags); 2013 2014 reg = readl(port->gmac_base + GMAC_CONFIG0); 2015 reg = enable ? reg | CONFIG0_RX_CHKSUM : reg & ~CONFIG0_RX_CHKSUM; 2016 writel(reg, port->gmac_base + GMAC_CONFIG0); 2017 2018 spin_unlock_irqrestore(&port->config_lock, flags); 2019 return 0; 2020 } 2021 2022 static int gmac_get_sset_count(struct net_device *netdev, int sset) 2023 { 2024 return sset == ETH_SS_STATS ? GMAC_STATS_NUM : 0; 2025 } 2026 2027 static void gmac_get_strings(struct net_device *netdev, u32 stringset, u8 *data) 2028 { 2029 if (stringset != ETH_SS_STATS) 2030 return; 2031 2032 memcpy(data, gmac_stats_strings, sizeof(gmac_stats_strings)); 2033 } 2034 2035 static void gmac_get_ethtool_stats(struct net_device *netdev, 2036 struct ethtool_stats *estats, u64 *values) 2037 { 2038 struct gemini_ethernet_port *port = netdev_priv(netdev); 2039 unsigned int start; 2040 u64 *p; 2041 int i; 2042 2043 gmac_update_hw_stats(netdev); 2044 2045 /* Racing with MIB interrupt */ 2046 do { 2047 p = values; 2048 start = u64_stats_fetch_begin(&port->ir_stats_syncp); 2049 2050 for (i = 0; i < RX_STATS_NUM; i++) 2051 *p++ = port->hw_stats[i]; 2052 2053 } while (u64_stats_fetch_retry(&port->ir_stats_syncp, start)); 2054 values = p; 2055 2056 /* Racing with RX NAPI */ 2057 do { 2058 p = values; 2059 start = u64_stats_fetch_begin(&port->rx_stats_syncp); 2060 2061 for (i = 0; i < RX_STATUS_NUM; i++) 2062 *p++ = port->rx_stats[i]; 2063 for (i = 0; i < RX_CHKSUM_NUM; i++) 2064 *p++ = port->rx_csum_stats[i]; 2065 *p++ = port->rx_napi_exits; 2066 2067 } while (u64_stats_fetch_retry(&port->rx_stats_syncp, start)); 2068 values = p; 2069 2070 /* Racing with TX start_xmit */ 2071 do { 2072 p = values; 2073 start = u64_stats_fetch_begin(&port->tx_stats_syncp); 2074 2075 for (i = 0; i < TX_MAX_FRAGS; i++) { 2076 *values++ = port->tx_frag_stats[i]; 2077 port->tx_frag_stats[i] = 0; 2078 } 2079 *values++ = port->tx_frags_linearized; 2080 *values++ = port->tx_hw_csummed; 2081 2082 } while (u64_stats_fetch_retry(&port->tx_stats_syncp, start)); 2083 } 2084 2085 static int gmac_get_ksettings(struct net_device *netdev, 2086 struct ethtool_link_ksettings *cmd) 2087 { 2088 if (!netdev->phydev) 2089 return -ENXIO; 2090 phy_ethtool_ksettings_get(netdev->phydev, cmd); 2091 2092 return 0; 2093 } 2094 2095 static int gmac_set_ksettings(struct net_device *netdev, 2096 const struct ethtool_link_ksettings *cmd) 2097 { 2098 if (!netdev->phydev) 2099 return -ENXIO; 2100 return phy_ethtool_ksettings_set(netdev->phydev, cmd); 2101 } 2102 2103 static int gmac_nway_reset(struct net_device *netdev) 2104 { 2105 if (!netdev->phydev) 2106 return -ENXIO; 2107 return phy_start_aneg(netdev->phydev); 2108 } 2109 2110 static void gmac_get_pauseparam(struct net_device *netdev, 2111 struct ethtool_pauseparam *pparam) 2112 { 2113 struct gemini_ethernet_port *port = netdev_priv(netdev); 2114 union gmac_config0 config0; 2115 2116 config0.bits32 = readl(port->gmac_base + GMAC_CONFIG0); 2117 2118 pparam->rx_pause = config0.bits.rx_fc_en; 2119 pparam->tx_pause = config0.bits.tx_fc_en; 2120 pparam->autoneg = true; 2121 } 2122 2123 static void gmac_get_ringparam(struct net_device *netdev, 2124 struct ethtool_ringparam *rp) 2125 { 2126 struct gemini_ethernet_port *port = netdev_priv(netdev); 2127 union gmac_config0 config0; 2128 2129 config0.bits32 = readl(port->gmac_base + GMAC_CONFIG0); 2130 2131 rp->rx_max_pending = 1 << 15; 2132 rp->rx_mini_max_pending = 0; 2133 rp->rx_jumbo_max_pending = 0; 2134 rp->tx_max_pending = 1 << 15; 2135 2136 rp->rx_pending = 1 << port->rxq_order; 2137 rp->rx_mini_pending = 0; 2138 rp->rx_jumbo_pending = 0; 2139 rp->tx_pending = 1 << port->txq_order; 2140 } 2141 2142 static int gmac_set_ringparam(struct net_device *netdev, 2143 struct ethtool_ringparam *rp) 2144 { 2145 struct gemini_ethernet_port *port = netdev_priv(netdev); 2146 int err = 0; 2147 2148 if (netif_running(netdev)) 2149 return -EBUSY; 2150 2151 if (rp->rx_pending) { 2152 port->rxq_order = min(15, ilog2(rp->rx_pending - 1) + 1); 2153 err = geth_resize_freeq(port); 2154 } 2155 if (rp->tx_pending) { 2156 port->txq_order = min(15, ilog2(rp->tx_pending - 1) + 1); 2157 port->irq_every_tx_packets = 1 << (port->txq_order - 2); 2158 } 2159 2160 return err; 2161 } 2162 2163 static int gmac_get_coalesce(struct net_device *netdev, 2164 struct ethtool_coalesce *ecmd) 2165 { 2166 struct gemini_ethernet_port *port = netdev_priv(netdev); 2167 2168 ecmd->rx_max_coalesced_frames = 1; 2169 ecmd->tx_max_coalesced_frames = port->irq_every_tx_packets; 2170 ecmd->rx_coalesce_usecs = port->rx_coalesce_nsecs / 1000; 2171 2172 return 0; 2173 } 2174 2175 static int gmac_set_coalesce(struct net_device *netdev, 2176 struct ethtool_coalesce *ecmd) 2177 { 2178 struct gemini_ethernet_port *port = netdev_priv(netdev); 2179 2180 if (ecmd->tx_max_coalesced_frames < 1) 2181 return -EINVAL; 2182 if (ecmd->tx_max_coalesced_frames >= 1 << port->txq_order) 2183 return -EINVAL; 2184 2185 port->irq_every_tx_packets = ecmd->tx_max_coalesced_frames; 2186 port->rx_coalesce_nsecs = ecmd->rx_coalesce_usecs * 1000; 2187 2188 return 0; 2189 } 2190 2191 static u32 gmac_get_msglevel(struct net_device *netdev) 2192 { 2193 struct gemini_ethernet_port *port = netdev_priv(netdev); 2194 2195 return port->msg_enable; 2196 } 2197 2198 static void gmac_set_msglevel(struct net_device *netdev, u32 level) 2199 { 2200 struct gemini_ethernet_port *port = netdev_priv(netdev); 2201 2202 port->msg_enable = level; 2203 } 2204 2205 static void gmac_get_drvinfo(struct net_device *netdev, 2206 struct ethtool_drvinfo *info) 2207 { 2208 strcpy(info->driver, DRV_NAME); 2209 strcpy(info->version, DRV_VERSION); 2210 strcpy(info->bus_info, netdev->dev_id ? "1" : "0"); 2211 } 2212 2213 static const struct net_device_ops gmac_351x_ops = { 2214 .ndo_init = gmac_init, 2215 .ndo_uninit = gmac_uninit, 2216 .ndo_open = gmac_open, 2217 .ndo_stop = gmac_stop, 2218 .ndo_start_xmit = gmac_start_xmit, 2219 .ndo_tx_timeout = gmac_tx_timeout, 2220 .ndo_set_rx_mode = gmac_set_rx_mode, 2221 .ndo_set_mac_address = gmac_set_mac_address, 2222 .ndo_get_stats64 = gmac_get_stats64, 2223 .ndo_change_mtu = gmac_change_mtu, 2224 .ndo_fix_features = gmac_fix_features, 2225 .ndo_set_features = gmac_set_features, 2226 }; 2227 2228 static const struct ethtool_ops gmac_351x_ethtool_ops = { 2229 .get_sset_count = gmac_get_sset_count, 2230 .get_strings = gmac_get_strings, 2231 .get_ethtool_stats = gmac_get_ethtool_stats, 2232 .get_link = ethtool_op_get_link, 2233 .get_link_ksettings = gmac_get_ksettings, 2234 .set_link_ksettings = gmac_set_ksettings, 2235 .nway_reset = gmac_nway_reset, 2236 .get_pauseparam = gmac_get_pauseparam, 2237 .get_ringparam = gmac_get_ringparam, 2238 .set_ringparam = gmac_set_ringparam, 2239 .get_coalesce = gmac_get_coalesce, 2240 .set_coalesce = gmac_set_coalesce, 2241 .get_msglevel = gmac_get_msglevel, 2242 .set_msglevel = gmac_set_msglevel, 2243 .get_drvinfo = gmac_get_drvinfo, 2244 }; 2245 2246 static irqreturn_t gemini_port_irq_thread(int irq, void *data) 2247 { 2248 unsigned long irqmask = SWFQ_EMPTY_INT_BIT; 2249 struct gemini_ethernet_port *port = data; 2250 struct gemini_ethernet *geth; 2251 unsigned long flags; 2252 2253 geth = port->geth; 2254 /* The queue is half empty so refill it */ 2255 geth_fill_freeq(geth, true); 2256 2257 spin_lock_irqsave(&geth->irq_lock, flags); 2258 /* ACK queue interrupt */ 2259 writel(irqmask, geth->base + GLOBAL_INTERRUPT_STATUS_4_REG); 2260 /* Enable queue interrupt again */ 2261 irqmask |= readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); 2262 writel(irqmask, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); 2263 spin_unlock_irqrestore(&geth->irq_lock, flags); 2264 2265 return IRQ_HANDLED; 2266 } 2267 2268 static irqreturn_t gemini_port_irq(int irq, void *data) 2269 { 2270 struct gemini_ethernet_port *port = data; 2271 struct gemini_ethernet *geth; 2272 irqreturn_t ret = IRQ_NONE; 2273 u32 val, en; 2274 2275 geth = port->geth; 2276 spin_lock(&geth->irq_lock); 2277 2278 val = readl(geth->base + GLOBAL_INTERRUPT_STATUS_4_REG); 2279 en = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); 2280 2281 if (val & en & SWFQ_EMPTY_INT_BIT) { 2282 /* Disable the queue empty interrupt while we work on 2283 * processing the queue. Also disable overrun interrupts 2284 * as there is not much we can do about it here. 2285 */ 2286 en &= ~(SWFQ_EMPTY_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT 2287 | GMAC1_RX_OVERRUN_INT_BIT); 2288 writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); 2289 ret = IRQ_WAKE_THREAD; 2290 } 2291 2292 spin_unlock(&geth->irq_lock); 2293 2294 return ret; 2295 } 2296 2297 static void gemini_port_remove(struct gemini_ethernet_port *port) 2298 { 2299 if (port->netdev) 2300 unregister_netdev(port->netdev); 2301 clk_disable_unprepare(port->pclk); 2302 geth_cleanup_freeq(port->geth); 2303 } 2304 2305 static void gemini_ethernet_init(struct gemini_ethernet *geth) 2306 { 2307 /* Only do this once both ports are online */ 2308 if (geth->initialized) 2309 return; 2310 if (geth->port0 && geth->port1) 2311 geth->initialized = true; 2312 else 2313 return; 2314 2315 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG); 2316 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG); 2317 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_2_REG); 2318 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_3_REG); 2319 writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); 2320 2321 /* Interrupt config: 2322 * 2323 * GMAC0 intr bits ------> int0 ----> eth0 2324 * GMAC1 intr bits ------> int1 ----> eth1 2325 * TOE intr -------------> int1 ----> eth1 2326 * Classification Intr --> int0 ----> eth0 2327 * Default Q0 -----------> int0 ----> eth0 2328 * Default Q1 -----------> int1 ----> eth1 2329 * FreeQ intr -----------> int1 ----> eth1 2330 */ 2331 writel(0xCCFC0FC0, geth->base + GLOBAL_INTERRUPT_SELECT_0_REG); 2332 writel(0x00F00002, geth->base + GLOBAL_INTERRUPT_SELECT_1_REG); 2333 writel(0xFFFFFFFF, geth->base + GLOBAL_INTERRUPT_SELECT_2_REG); 2334 writel(0xFFFFFFFF, geth->base + GLOBAL_INTERRUPT_SELECT_3_REG); 2335 writel(0xFF000003, geth->base + GLOBAL_INTERRUPT_SELECT_4_REG); 2336 2337 /* edge-triggered interrupts packed to level-triggered one... */ 2338 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_0_REG); 2339 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_1_REG); 2340 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_2_REG); 2341 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_3_REG); 2342 writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_4_REG); 2343 2344 /* Set up queue */ 2345 writel(0, geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG); 2346 writel(0, geth->base + GLOBAL_HW_FREEQ_BASE_SIZE_REG); 2347 writel(0, geth->base + GLOBAL_SWFQ_RWPTR_REG); 2348 writel(0, geth->base + GLOBAL_HWFQ_RWPTR_REG); 2349 2350 geth->freeq_frag_order = DEFAULT_RX_BUF_ORDER; 2351 /* This makes the queue resize on probe() so that we 2352 * set up and enable the queue IRQ. FIXME: fragile. 2353 */ 2354 geth->freeq_order = 1; 2355 } 2356 2357 static void gemini_port_save_mac_addr(struct gemini_ethernet_port *port) 2358 { 2359 port->mac_addr[0] = 2360 cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD0)); 2361 port->mac_addr[1] = 2362 cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD1)); 2363 port->mac_addr[2] = 2364 cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD2)); 2365 } 2366 2367 static int gemini_ethernet_port_probe(struct platform_device *pdev) 2368 { 2369 char *port_names[2] = { "ethernet0", "ethernet1" }; 2370 struct gemini_ethernet_port *port; 2371 struct device *dev = &pdev->dev; 2372 struct gemini_ethernet *geth; 2373 struct net_device *netdev; 2374 struct resource *gmacres; 2375 struct resource *dmares; 2376 struct device *parent; 2377 unsigned int id; 2378 int irq; 2379 int ret; 2380 2381 parent = dev->parent; 2382 geth = dev_get_drvdata(parent); 2383 2384 if (!strcmp(dev_name(dev), "60008000.ethernet-port")) 2385 id = 0; 2386 else if (!strcmp(dev_name(dev), "6000c000.ethernet-port")) 2387 id = 1; 2388 else 2389 return -ENODEV; 2390 2391 dev_info(dev, "probe %s ID %d\n", dev_name(dev), id); 2392 2393 netdev = alloc_etherdev_mq(sizeof(*port), TX_QUEUE_NUM); 2394 if (!netdev) { 2395 dev_err(dev, "Can't allocate ethernet device #%d\n", id); 2396 return -ENOMEM; 2397 } 2398 2399 port = netdev_priv(netdev); 2400 SET_NETDEV_DEV(netdev, dev); 2401 port->netdev = netdev; 2402 port->id = id; 2403 port->geth = geth; 2404 port->dev = dev; 2405 port->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 2406 2407 /* DMA memory */ 2408 dmares = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2409 if (!dmares) { 2410 dev_err(dev, "no DMA resource\n"); 2411 return -ENODEV; 2412 } 2413 port->dma_base = devm_ioremap_resource(dev, dmares); 2414 if (IS_ERR(port->dma_base)) 2415 return PTR_ERR(port->dma_base); 2416 2417 /* GMAC config memory */ 2418 gmacres = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2419 if (!gmacres) { 2420 dev_err(dev, "no GMAC resource\n"); 2421 return -ENODEV; 2422 } 2423 port->gmac_base = devm_ioremap_resource(dev, gmacres); 2424 if (IS_ERR(port->gmac_base)) 2425 return PTR_ERR(port->gmac_base); 2426 2427 /* Interrupt */ 2428 irq = platform_get_irq(pdev, 0); 2429 if (irq <= 0) { 2430 dev_err(dev, "no IRQ\n"); 2431 return irq ? irq : -ENODEV; 2432 } 2433 port->irq = irq; 2434 2435 /* Clock the port */ 2436 port->pclk = devm_clk_get(dev, "PCLK"); 2437 if (IS_ERR(port->pclk)) { 2438 dev_err(dev, "no PCLK\n"); 2439 return PTR_ERR(port->pclk); 2440 } 2441 ret = clk_prepare_enable(port->pclk); 2442 if (ret) 2443 return ret; 2444 2445 /* Maybe there is a nice ethernet address we should use */ 2446 gemini_port_save_mac_addr(port); 2447 2448 /* Reset the port */ 2449 port->reset = devm_reset_control_get_exclusive(dev, NULL); 2450 if (IS_ERR(port->reset)) { 2451 dev_err(dev, "no reset\n"); 2452 return PTR_ERR(port->reset); 2453 } 2454 reset_control_reset(port->reset); 2455 usleep_range(100, 500); 2456 2457 /* Assign pointer in the main state container */ 2458 if (!id) 2459 geth->port0 = port; 2460 else 2461 geth->port1 = port; 2462 2463 /* This will just be done once both ports are up and reset */ 2464 gemini_ethernet_init(geth); 2465 2466 platform_set_drvdata(pdev, port); 2467 2468 /* Set up and register the netdev */ 2469 netdev->dev_id = port->id; 2470 netdev->irq = irq; 2471 netdev->netdev_ops = &gmac_351x_ops; 2472 netdev->ethtool_ops = &gmac_351x_ethtool_ops; 2473 2474 spin_lock_init(&port->config_lock); 2475 gmac_clear_hw_stats(netdev); 2476 2477 netdev->hw_features = GMAC_OFFLOAD_FEATURES; 2478 netdev->features |= GMAC_OFFLOAD_FEATURES | NETIF_F_GRO; 2479 /* We can handle jumbo frames up to 10236 bytes so, let's accept 2480 * payloads of 10236 bytes minus VLAN and ethernet header 2481 */ 2482 netdev->min_mtu = ETH_MIN_MTU; 2483 netdev->max_mtu = 10236 - VLAN_ETH_HLEN; 2484 2485 port->freeq_refill = 0; 2486 netif_napi_add(netdev, &port->napi, gmac_napi_poll, 2487 DEFAULT_NAPI_WEIGHT); 2488 2489 if (is_valid_ether_addr((void *)port->mac_addr)) { 2490 memcpy(netdev->dev_addr, port->mac_addr, ETH_ALEN); 2491 } else { 2492 dev_dbg(dev, "ethernet address 0x%08x%08x%08x invalid\n", 2493 port->mac_addr[0], port->mac_addr[1], 2494 port->mac_addr[2]); 2495 dev_info(dev, "using a random ethernet address\n"); 2496 eth_random_addr(netdev->dev_addr); 2497 } 2498 gmac_write_mac_address(netdev); 2499 2500 ret = devm_request_threaded_irq(port->dev, 2501 port->irq, 2502 gemini_port_irq, 2503 gemini_port_irq_thread, 2504 IRQF_SHARED, 2505 port_names[port->id], 2506 port); 2507 if (ret) 2508 return ret; 2509 2510 ret = register_netdev(netdev); 2511 if (!ret) { 2512 netdev_info(netdev, 2513 "irq %d, DMA @ 0x%pap, GMAC @ 0x%pap\n", 2514 port->irq, &dmares->start, 2515 &gmacres->start); 2516 ret = gmac_setup_phy(netdev); 2517 if (ret) 2518 netdev_info(netdev, 2519 "PHY init failed, deferring to ifup time\n"); 2520 return 0; 2521 } 2522 2523 port->netdev = NULL; 2524 free_netdev(netdev); 2525 return ret; 2526 } 2527 2528 static int gemini_ethernet_port_remove(struct platform_device *pdev) 2529 { 2530 struct gemini_ethernet_port *port = platform_get_drvdata(pdev); 2531 2532 gemini_port_remove(port); 2533 return 0; 2534 } 2535 2536 static const struct of_device_id gemini_ethernet_port_of_match[] = { 2537 { 2538 .compatible = "cortina,gemini-ethernet-port", 2539 }, 2540 {}, 2541 }; 2542 MODULE_DEVICE_TABLE(of, gemini_ethernet_port_of_match); 2543 2544 static struct platform_driver gemini_ethernet_port_driver = { 2545 .driver = { 2546 .name = "gemini-ethernet-port", 2547 .of_match_table = of_match_ptr(gemini_ethernet_port_of_match), 2548 }, 2549 .probe = gemini_ethernet_port_probe, 2550 .remove = gemini_ethernet_port_remove, 2551 }; 2552 2553 static int gemini_ethernet_probe(struct platform_device *pdev) 2554 { 2555 struct device *dev = &pdev->dev; 2556 struct gemini_ethernet *geth; 2557 unsigned int retry = 5; 2558 struct resource *res; 2559 u32 val; 2560 2561 /* Global registers */ 2562 geth = devm_kzalloc(dev, sizeof(*geth), GFP_KERNEL); 2563 if (!geth) 2564 return -ENOMEM; 2565 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2566 if (!res) 2567 return -ENODEV; 2568 geth->base = devm_ioremap_resource(dev, res); 2569 if (IS_ERR(geth->base)) 2570 return PTR_ERR(geth->base); 2571 geth->dev = dev; 2572 2573 /* Wait for ports to stabilize */ 2574 do { 2575 udelay(2); 2576 val = readl(geth->base + GLOBAL_TOE_VERSION_REG); 2577 barrier(); 2578 } while (!val && --retry); 2579 if (!retry) { 2580 dev_err(dev, "failed to reset ethernet\n"); 2581 return -EIO; 2582 } 2583 dev_info(dev, "Ethernet device ID: 0x%03x, revision 0x%01x\n", 2584 (val >> 4) & 0xFFFU, val & 0xFU); 2585 2586 spin_lock_init(&geth->irq_lock); 2587 spin_lock_init(&geth->freeq_lock); 2588 2589 /* The children will use this */ 2590 platform_set_drvdata(pdev, geth); 2591 2592 /* Spawn child devices for the two ports */ 2593 return devm_of_platform_populate(dev); 2594 } 2595 2596 static int gemini_ethernet_remove(struct platform_device *pdev) 2597 { 2598 struct gemini_ethernet *geth = platform_get_drvdata(pdev); 2599 2600 geth_cleanup_freeq(geth); 2601 geth->initialized = false; 2602 2603 return 0; 2604 } 2605 2606 static const struct of_device_id gemini_ethernet_of_match[] = { 2607 { 2608 .compatible = "cortina,gemini-ethernet", 2609 }, 2610 {}, 2611 }; 2612 MODULE_DEVICE_TABLE(of, gemini_ethernet_of_match); 2613 2614 static struct platform_driver gemini_ethernet_driver = { 2615 .driver = { 2616 .name = DRV_NAME, 2617 .of_match_table = of_match_ptr(gemini_ethernet_of_match), 2618 }, 2619 .probe = gemini_ethernet_probe, 2620 .remove = gemini_ethernet_remove, 2621 }; 2622 2623 static int __init gemini_ethernet_module_init(void) 2624 { 2625 int ret; 2626 2627 ret = platform_driver_register(&gemini_ethernet_port_driver); 2628 if (ret) 2629 return ret; 2630 2631 ret = platform_driver_register(&gemini_ethernet_driver); 2632 if (ret) { 2633 platform_driver_unregister(&gemini_ethernet_port_driver); 2634 return ret; 2635 } 2636 2637 return 0; 2638 } 2639 module_init(gemini_ethernet_module_init); 2640 2641 static void __exit gemini_ethernet_module_exit(void) 2642 { 2643 platform_driver_unregister(&gemini_ethernet_driver); 2644 platform_driver_unregister(&gemini_ethernet_port_driver); 2645 } 2646 module_exit(gemini_ethernet_module_exit); 2647 2648 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>"); 2649 MODULE_DESCRIPTION("StorLink SL351x (Gemini) ethernet driver"); 2650 MODULE_LICENSE("GPL"); 2651 MODULE_ALIAS("platform:" DRV_NAME); 2652