1*e6550b3eSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2a6a5580cSJeff Kirsher /* 3a6a5580cSJeff Kirsher * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved. 4a6a5580cSJeff Kirsher * Copyright 2007 Nuova Systems, Inc. All rights reserved. 5a6a5580cSJeff Kirsher */ 6a6a5580cSJeff Kirsher 7a6a5580cSJeff Kirsher #ifndef _VNIC_RESOURCE_H_ 8a6a5580cSJeff Kirsher #define _VNIC_RESOURCE_H_ 9a6a5580cSJeff Kirsher 10a6a5580cSJeff Kirsher #define VNIC_RES_MAGIC 0x766E6963L /* 'vnic' */ 11a6a5580cSJeff Kirsher #define VNIC_RES_VERSION 0x00000000L 12a6a5580cSJeff Kirsher #define MGMTVNIC_MAGIC 0x544d474dL /* 'MGMT' */ 13a6a5580cSJeff Kirsher #define MGMTVNIC_VERSION 0x00000000L 14a6a5580cSJeff Kirsher 15a6a5580cSJeff Kirsher /* The MAC address assigned to the CFG vNIC is fixed. */ 16a6a5580cSJeff Kirsher #define MGMTVNIC_MAC { 0x02, 0x00, 0x54, 0x4d, 0x47, 0x4d } 17a6a5580cSJeff Kirsher 18a6a5580cSJeff Kirsher /* vNIC resource types */ 19a6a5580cSJeff Kirsher enum vnic_res_type { 20a6a5580cSJeff Kirsher RES_TYPE_EOL, /* End-of-list */ 21a6a5580cSJeff Kirsher RES_TYPE_WQ, /* Work queues */ 22a6a5580cSJeff Kirsher RES_TYPE_RQ, /* Receive queues */ 23a6a5580cSJeff Kirsher RES_TYPE_CQ, /* Completion queues */ 24a6a5580cSJeff Kirsher RES_TYPE_RSVD1, 25a6a5580cSJeff Kirsher RES_TYPE_NIC_CFG, /* Enet NIC config registers */ 26a6a5580cSJeff Kirsher RES_TYPE_RSVD2, 27a6a5580cSJeff Kirsher RES_TYPE_RSVD3, 28a6a5580cSJeff Kirsher RES_TYPE_RSVD4, 29a6a5580cSJeff Kirsher RES_TYPE_RSVD5, 30a6a5580cSJeff Kirsher RES_TYPE_INTR_CTRL, /* Interrupt ctrl table */ 31a6a5580cSJeff Kirsher RES_TYPE_INTR_TABLE, /* MSI/MSI-X Interrupt table */ 32a6a5580cSJeff Kirsher RES_TYPE_INTR_PBA, /* MSI/MSI-X PBA table */ 33a6a5580cSJeff Kirsher RES_TYPE_INTR_PBA_LEGACY, /* Legacy intr status */ 34a6a5580cSJeff Kirsher RES_TYPE_RSVD6, 35a6a5580cSJeff Kirsher RES_TYPE_RSVD7, 36a6a5580cSJeff Kirsher RES_TYPE_DEVCMD, /* Device command region */ 37a6a5580cSJeff Kirsher RES_TYPE_PASS_THRU_PAGE, /* Pass-thru page */ 38fda3f52bSGovindarajulu Varadarajan RES_TYPE_SUBVNIC, /* subvnic resource type */ 39fda3f52bSGovindarajulu Varadarajan RES_TYPE_MQ_WQ, /* MQ Work queues */ 40fda3f52bSGovindarajulu Varadarajan RES_TYPE_MQ_RQ, /* MQ Receive queues */ 41fda3f52bSGovindarajulu Varadarajan RES_TYPE_MQ_CQ, /* MQ Completion queues */ 42fda3f52bSGovindarajulu Varadarajan RES_TYPE_DEPRECATED1, /* Old version of devcmd 2 */ 43fda3f52bSGovindarajulu Varadarajan RES_TYPE_DEPRECATED2, /* Old version of devcmd 2 */ 44fda3f52bSGovindarajulu Varadarajan RES_TYPE_DEVCMD2, /* Device control region */ 45a6a5580cSJeff Kirsher 46a6a5580cSJeff Kirsher RES_TYPE_MAX, /* Count of resource types */ 47a6a5580cSJeff Kirsher }; 48a6a5580cSJeff Kirsher 49a6a5580cSJeff Kirsher struct vnic_resource_header { 50a6a5580cSJeff Kirsher u32 magic; 51a6a5580cSJeff Kirsher u32 version; 52a6a5580cSJeff Kirsher }; 53a6a5580cSJeff Kirsher 54a6a5580cSJeff Kirsher struct mgmt_barmap_hdr { 55a6a5580cSJeff Kirsher u32 magic; /* magic number */ 56a6a5580cSJeff Kirsher u32 version; /* header format version */ 57a6a5580cSJeff Kirsher u16 lif; /* loopback lif for mgmt frames */ 58a6a5580cSJeff Kirsher u16 pci_slot; /* installed pci slot */ 59a6a5580cSJeff Kirsher char serial[16]; /* card serial number */ 60a6a5580cSJeff Kirsher }; 61a6a5580cSJeff Kirsher 62a6a5580cSJeff Kirsher struct vnic_resource { 63a6a5580cSJeff Kirsher u8 type; 64a6a5580cSJeff Kirsher u8 bar; 65a6a5580cSJeff Kirsher u8 pad[2]; 66a6a5580cSJeff Kirsher u32 bar_offset; 67a6a5580cSJeff Kirsher u32 count; 68a6a5580cSJeff Kirsher }; 69a6a5580cSJeff Kirsher 70a6a5580cSJeff Kirsher #endif /* _VNIC_RESOURCE_H_ */ 71