1 /* 2 * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved. 3 * Copyright 2007 Nuova Systems, Inc. All rights reserved. 4 * 5 * This program is free software; you may redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; version 2 of the License. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 10 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 11 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 12 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 13 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 14 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 15 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 16 * SOFTWARE. 17 * 18 */ 19 20 #include <linux/module.h> 21 #include <linux/kernel.h> 22 #include <linux/string.h> 23 #include <linux/errno.h> 24 #include <linux/types.h> 25 #include <linux/init.h> 26 #include <linux/interrupt.h> 27 #include <linux/workqueue.h> 28 #include <linux/pci.h> 29 #include <linux/netdevice.h> 30 #include <linux/etherdevice.h> 31 #include <linux/if.h> 32 #include <linux/if_ether.h> 33 #include <linux/if_vlan.h> 34 #include <linux/in.h> 35 #include <linux/ip.h> 36 #include <linux/ipv6.h> 37 #include <linux/tcp.h> 38 #include <linux/rtnetlink.h> 39 #include <linux/prefetch.h> 40 #include <net/ip6_checksum.h> 41 #include <linux/ktime.h> 42 #ifdef CONFIG_RFS_ACCEL 43 #include <linux/cpu_rmap.h> 44 #endif 45 #ifdef CONFIG_NET_RX_BUSY_POLL 46 #include <net/busy_poll.h> 47 #endif 48 49 #include "cq_enet_desc.h" 50 #include "vnic_dev.h" 51 #include "vnic_intr.h" 52 #include "vnic_stats.h" 53 #include "vnic_vic.h" 54 #include "enic_res.h" 55 #include "enic.h" 56 #include "enic_dev.h" 57 #include "enic_pp.h" 58 #include "enic_clsf.h" 59 60 #define ENIC_NOTIFY_TIMER_PERIOD (2 * HZ) 61 #define WQ_ENET_MAX_DESC_LEN (1 << WQ_ENET_LEN_BITS) 62 #define MAX_TSO (1 << 16) 63 #define ENIC_DESC_MAX_SPLITS (MAX_TSO / WQ_ENET_MAX_DESC_LEN + 1) 64 65 #define PCI_DEVICE_ID_CISCO_VIC_ENET 0x0043 /* ethernet vnic */ 66 #define PCI_DEVICE_ID_CISCO_VIC_ENET_DYN 0x0044 /* enet dynamic vnic */ 67 #define PCI_DEVICE_ID_CISCO_VIC_ENET_VF 0x0071 /* enet SRIOV VF */ 68 69 #define RX_COPYBREAK_DEFAULT 256 70 71 /* Supported devices */ 72 static const struct pci_device_id enic_id_table[] = { 73 { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET) }, 74 { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET_DYN) }, 75 { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET_VF) }, 76 { 0, } /* end of table */ 77 }; 78 79 MODULE_DESCRIPTION(DRV_DESCRIPTION); 80 MODULE_AUTHOR("Scott Feldman <scofeldm@cisco.com>"); 81 MODULE_LICENSE("GPL"); 82 MODULE_VERSION(DRV_VERSION); 83 MODULE_DEVICE_TABLE(pci, enic_id_table); 84 85 #define ENIC_LARGE_PKT_THRESHOLD 1000 86 #define ENIC_MAX_COALESCE_TIMERS 10 87 /* Interrupt moderation table, which will be used to decide the 88 * coalescing timer values 89 * {rx_rate in Mbps, mapping percentage of the range} 90 */ 91 struct enic_intr_mod_table mod_table[ENIC_MAX_COALESCE_TIMERS + 1] = { 92 {4000, 0}, 93 {4400, 10}, 94 {5060, 20}, 95 {5230, 30}, 96 {5540, 40}, 97 {5820, 50}, 98 {6120, 60}, 99 {6435, 70}, 100 {6745, 80}, 101 {7000, 90}, 102 {0xFFFFFFFF, 100} 103 }; 104 105 /* This table helps the driver to pick different ranges for rx coalescing 106 * timer depending on the link speed. 107 */ 108 struct enic_intr_mod_range mod_range[ENIC_MAX_LINK_SPEEDS] = { 109 {0, 0}, /* 0 - 4 Gbps */ 110 {0, 3}, /* 4 - 10 Gbps */ 111 {3, 6}, /* 10 - 40 Gbps */ 112 }; 113 114 int enic_is_dynamic(struct enic *enic) 115 { 116 return enic->pdev->device == PCI_DEVICE_ID_CISCO_VIC_ENET_DYN; 117 } 118 119 int enic_sriov_enabled(struct enic *enic) 120 { 121 return (enic->priv_flags & ENIC_SRIOV_ENABLED) ? 1 : 0; 122 } 123 124 static int enic_is_sriov_vf(struct enic *enic) 125 { 126 return enic->pdev->device == PCI_DEVICE_ID_CISCO_VIC_ENET_VF; 127 } 128 129 int enic_is_valid_vf(struct enic *enic, int vf) 130 { 131 #ifdef CONFIG_PCI_IOV 132 return vf >= 0 && vf < enic->num_vfs; 133 #else 134 return 0; 135 #endif 136 } 137 138 static void enic_free_wq_buf(struct vnic_wq *wq, struct vnic_wq_buf *buf) 139 { 140 struct enic *enic = vnic_dev_priv(wq->vdev); 141 142 if (buf->sop) 143 pci_unmap_single(enic->pdev, buf->dma_addr, 144 buf->len, PCI_DMA_TODEVICE); 145 else 146 pci_unmap_page(enic->pdev, buf->dma_addr, 147 buf->len, PCI_DMA_TODEVICE); 148 149 if (buf->os_buf) 150 dev_kfree_skb_any(buf->os_buf); 151 } 152 153 static void enic_wq_free_buf(struct vnic_wq *wq, 154 struct cq_desc *cq_desc, struct vnic_wq_buf *buf, void *opaque) 155 { 156 enic_free_wq_buf(wq, buf); 157 } 158 159 static int enic_wq_service(struct vnic_dev *vdev, struct cq_desc *cq_desc, 160 u8 type, u16 q_number, u16 completed_index, void *opaque) 161 { 162 struct enic *enic = vnic_dev_priv(vdev); 163 164 spin_lock(&enic->wq_lock[q_number]); 165 166 vnic_wq_service(&enic->wq[q_number], cq_desc, 167 completed_index, enic_wq_free_buf, 168 opaque); 169 170 if (netif_tx_queue_stopped(netdev_get_tx_queue(enic->netdev, q_number)) && 171 vnic_wq_desc_avail(&enic->wq[q_number]) >= 172 (MAX_SKB_FRAGS + ENIC_DESC_MAX_SPLITS)) 173 netif_wake_subqueue(enic->netdev, q_number); 174 175 spin_unlock(&enic->wq_lock[q_number]); 176 177 return 0; 178 } 179 180 static void enic_log_q_error(struct enic *enic) 181 { 182 unsigned int i; 183 u32 error_status; 184 185 for (i = 0; i < enic->wq_count; i++) { 186 error_status = vnic_wq_error_status(&enic->wq[i]); 187 if (error_status) 188 netdev_err(enic->netdev, "WQ[%d] error_status %d\n", 189 i, error_status); 190 } 191 192 for (i = 0; i < enic->rq_count; i++) { 193 error_status = vnic_rq_error_status(&enic->rq[i]); 194 if (error_status) 195 netdev_err(enic->netdev, "RQ[%d] error_status %d\n", 196 i, error_status); 197 } 198 } 199 200 static void enic_msglvl_check(struct enic *enic) 201 { 202 u32 msg_enable = vnic_dev_msg_lvl(enic->vdev); 203 204 if (msg_enable != enic->msg_enable) { 205 netdev_info(enic->netdev, "msg lvl changed from 0x%x to 0x%x\n", 206 enic->msg_enable, msg_enable); 207 enic->msg_enable = msg_enable; 208 } 209 } 210 211 static void enic_mtu_check(struct enic *enic) 212 { 213 u32 mtu = vnic_dev_mtu(enic->vdev); 214 struct net_device *netdev = enic->netdev; 215 216 if (mtu && mtu != enic->port_mtu) { 217 enic->port_mtu = mtu; 218 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) { 219 mtu = max_t(int, ENIC_MIN_MTU, 220 min_t(int, ENIC_MAX_MTU, mtu)); 221 if (mtu != netdev->mtu) 222 schedule_work(&enic->change_mtu_work); 223 } else { 224 if (mtu < netdev->mtu) 225 netdev_warn(netdev, 226 "interface MTU (%d) set higher " 227 "than switch port MTU (%d)\n", 228 netdev->mtu, mtu); 229 } 230 } 231 } 232 233 static void enic_link_check(struct enic *enic) 234 { 235 int link_status = vnic_dev_link_status(enic->vdev); 236 int carrier_ok = netif_carrier_ok(enic->netdev); 237 238 if (link_status && !carrier_ok) { 239 netdev_info(enic->netdev, "Link UP\n"); 240 netif_carrier_on(enic->netdev); 241 } else if (!link_status && carrier_ok) { 242 netdev_info(enic->netdev, "Link DOWN\n"); 243 netif_carrier_off(enic->netdev); 244 } 245 } 246 247 static void enic_notify_check(struct enic *enic) 248 { 249 enic_msglvl_check(enic); 250 enic_mtu_check(enic); 251 enic_link_check(enic); 252 } 253 254 #define ENIC_TEST_INTR(pba, i) (pba & (1 << i)) 255 256 static irqreturn_t enic_isr_legacy(int irq, void *data) 257 { 258 struct net_device *netdev = data; 259 struct enic *enic = netdev_priv(netdev); 260 unsigned int io_intr = enic_legacy_io_intr(); 261 unsigned int err_intr = enic_legacy_err_intr(); 262 unsigned int notify_intr = enic_legacy_notify_intr(); 263 u32 pba; 264 265 vnic_intr_mask(&enic->intr[io_intr]); 266 267 pba = vnic_intr_legacy_pba(enic->legacy_pba); 268 if (!pba) { 269 vnic_intr_unmask(&enic->intr[io_intr]); 270 return IRQ_NONE; /* not our interrupt */ 271 } 272 273 if (ENIC_TEST_INTR(pba, notify_intr)) { 274 vnic_intr_return_all_credits(&enic->intr[notify_intr]); 275 enic_notify_check(enic); 276 } 277 278 if (ENIC_TEST_INTR(pba, err_intr)) { 279 vnic_intr_return_all_credits(&enic->intr[err_intr]); 280 enic_log_q_error(enic); 281 /* schedule recovery from WQ/RQ error */ 282 schedule_work(&enic->reset); 283 return IRQ_HANDLED; 284 } 285 286 if (ENIC_TEST_INTR(pba, io_intr)) { 287 if (napi_schedule_prep(&enic->napi[0])) 288 __napi_schedule(&enic->napi[0]); 289 } else { 290 vnic_intr_unmask(&enic->intr[io_intr]); 291 } 292 293 return IRQ_HANDLED; 294 } 295 296 static irqreturn_t enic_isr_msi(int irq, void *data) 297 { 298 struct enic *enic = data; 299 300 /* With MSI, there is no sharing of interrupts, so this is 301 * our interrupt and there is no need to ack it. The device 302 * is not providing per-vector masking, so the OS will not 303 * write to PCI config space to mask/unmask the interrupt. 304 * We're using mask_on_assertion for MSI, so the device 305 * automatically masks the interrupt when the interrupt is 306 * generated. Later, when exiting polling, the interrupt 307 * will be unmasked (see enic_poll). 308 * 309 * Also, the device uses the same PCIe Traffic Class (TC) 310 * for Memory Write data and MSI, so there are no ordering 311 * issues; the MSI will always arrive at the Root Complex 312 * _after_ corresponding Memory Writes (i.e. descriptor 313 * writes). 314 */ 315 316 napi_schedule(&enic->napi[0]); 317 318 return IRQ_HANDLED; 319 } 320 321 static irqreturn_t enic_isr_msix(int irq, void *data) 322 { 323 struct napi_struct *napi = data; 324 325 napi_schedule(napi); 326 327 return IRQ_HANDLED; 328 } 329 330 static irqreturn_t enic_isr_msix_err(int irq, void *data) 331 { 332 struct enic *enic = data; 333 unsigned int intr = enic_msix_err_intr(enic); 334 335 vnic_intr_return_all_credits(&enic->intr[intr]); 336 337 enic_log_q_error(enic); 338 339 /* schedule recovery from WQ/RQ error */ 340 schedule_work(&enic->reset); 341 342 return IRQ_HANDLED; 343 } 344 345 static irqreturn_t enic_isr_msix_notify(int irq, void *data) 346 { 347 struct enic *enic = data; 348 unsigned int intr = enic_msix_notify_intr(enic); 349 350 vnic_intr_return_all_credits(&enic->intr[intr]); 351 enic_notify_check(enic); 352 353 return IRQ_HANDLED; 354 } 355 356 static inline void enic_queue_wq_skb_cont(struct enic *enic, 357 struct vnic_wq *wq, struct sk_buff *skb, 358 unsigned int len_left, int loopback) 359 { 360 const skb_frag_t *frag; 361 362 /* Queue additional data fragments */ 363 for (frag = skb_shinfo(skb)->frags; len_left; frag++) { 364 len_left -= skb_frag_size(frag); 365 enic_queue_wq_desc_cont(wq, skb, 366 skb_frag_dma_map(&enic->pdev->dev, 367 frag, 0, skb_frag_size(frag), 368 DMA_TO_DEVICE), 369 skb_frag_size(frag), 370 (len_left == 0), /* EOP? */ 371 loopback); 372 } 373 } 374 375 static inline void enic_queue_wq_skb_vlan(struct enic *enic, 376 struct vnic_wq *wq, struct sk_buff *skb, 377 int vlan_tag_insert, unsigned int vlan_tag, int loopback) 378 { 379 unsigned int head_len = skb_headlen(skb); 380 unsigned int len_left = skb->len - head_len; 381 int eop = (len_left == 0); 382 383 /* Queue the main skb fragment. The fragments are no larger 384 * than max MTU(9000)+ETH_HDR_LEN(14) bytes, which is less 385 * than WQ_ENET_MAX_DESC_LEN length. So only one descriptor 386 * per fragment is queued. 387 */ 388 enic_queue_wq_desc(wq, skb, 389 pci_map_single(enic->pdev, skb->data, 390 head_len, PCI_DMA_TODEVICE), 391 head_len, 392 vlan_tag_insert, vlan_tag, 393 eop, loopback); 394 395 if (!eop) 396 enic_queue_wq_skb_cont(enic, wq, skb, len_left, loopback); 397 } 398 399 static inline void enic_queue_wq_skb_csum_l4(struct enic *enic, 400 struct vnic_wq *wq, struct sk_buff *skb, 401 int vlan_tag_insert, unsigned int vlan_tag, int loopback) 402 { 403 unsigned int head_len = skb_headlen(skb); 404 unsigned int len_left = skb->len - head_len; 405 unsigned int hdr_len = skb_checksum_start_offset(skb); 406 unsigned int csum_offset = hdr_len + skb->csum_offset; 407 int eop = (len_left == 0); 408 409 /* Queue the main skb fragment. The fragments are no larger 410 * than max MTU(9000)+ETH_HDR_LEN(14) bytes, which is less 411 * than WQ_ENET_MAX_DESC_LEN length. So only one descriptor 412 * per fragment is queued. 413 */ 414 enic_queue_wq_desc_csum_l4(wq, skb, 415 pci_map_single(enic->pdev, skb->data, 416 head_len, PCI_DMA_TODEVICE), 417 head_len, 418 csum_offset, 419 hdr_len, 420 vlan_tag_insert, vlan_tag, 421 eop, loopback); 422 423 if (!eop) 424 enic_queue_wq_skb_cont(enic, wq, skb, len_left, loopback); 425 } 426 427 static inline void enic_queue_wq_skb_tso(struct enic *enic, 428 struct vnic_wq *wq, struct sk_buff *skb, unsigned int mss, 429 int vlan_tag_insert, unsigned int vlan_tag, int loopback) 430 { 431 unsigned int frag_len_left = skb_headlen(skb); 432 unsigned int len_left = skb->len - frag_len_left; 433 unsigned int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 434 int eop = (len_left == 0); 435 unsigned int len; 436 dma_addr_t dma_addr; 437 unsigned int offset = 0; 438 skb_frag_t *frag; 439 440 /* Preload TCP csum field with IP pseudo hdr calculated 441 * with IP length set to zero. HW will later add in length 442 * to each TCP segment resulting from the TSO. 443 */ 444 445 if (skb->protocol == cpu_to_be16(ETH_P_IP)) { 446 ip_hdr(skb)->check = 0; 447 tcp_hdr(skb)->check = ~csum_tcpudp_magic(ip_hdr(skb)->saddr, 448 ip_hdr(skb)->daddr, 0, IPPROTO_TCP, 0); 449 } else if (skb->protocol == cpu_to_be16(ETH_P_IPV6)) { 450 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 451 &ipv6_hdr(skb)->daddr, 0, IPPROTO_TCP, 0); 452 } 453 454 /* Queue WQ_ENET_MAX_DESC_LEN length descriptors 455 * for the main skb fragment 456 */ 457 while (frag_len_left) { 458 len = min(frag_len_left, (unsigned int)WQ_ENET_MAX_DESC_LEN); 459 dma_addr = pci_map_single(enic->pdev, skb->data + offset, 460 len, PCI_DMA_TODEVICE); 461 enic_queue_wq_desc_tso(wq, skb, 462 dma_addr, 463 len, 464 mss, hdr_len, 465 vlan_tag_insert, vlan_tag, 466 eop && (len == frag_len_left), loopback); 467 frag_len_left -= len; 468 offset += len; 469 } 470 471 if (eop) 472 return; 473 474 /* Queue WQ_ENET_MAX_DESC_LEN length descriptors 475 * for additional data fragments 476 */ 477 for (frag = skb_shinfo(skb)->frags; len_left; frag++) { 478 len_left -= skb_frag_size(frag); 479 frag_len_left = skb_frag_size(frag); 480 offset = 0; 481 482 while (frag_len_left) { 483 len = min(frag_len_left, 484 (unsigned int)WQ_ENET_MAX_DESC_LEN); 485 dma_addr = skb_frag_dma_map(&enic->pdev->dev, frag, 486 offset, len, 487 DMA_TO_DEVICE); 488 enic_queue_wq_desc_cont(wq, skb, 489 dma_addr, 490 len, 491 (len_left == 0) && 492 (len == frag_len_left), /* EOP? */ 493 loopback); 494 frag_len_left -= len; 495 offset += len; 496 } 497 } 498 } 499 500 static inline void enic_queue_wq_skb(struct enic *enic, 501 struct vnic_wq *wq, struct sk_buff *skb) 502 { 503 unsigned int mss = skb_shinfo(skb)->gso_size; 504 unsigned int vlan_tag = 0; 505 int vlan_tag_insert = 0; 506 int loopback = 0; 507 508 if (vlan_tx_tag_present(skb)) { 509 /* VLAN tag from trunking driver */ 510 vlan_tag_insert = 1; 511 vlan_tag = vlan_tx_tag_get(skb); 512 } else if (enic->loop_enable) { 513 vlan_tag = enic->loop_tag; 514 loopback = 1; 515 } 516 517 if (mss) 518 enic_queue_wq_skb_tso(enic, wq, skb, mss, 519 vlan_tag_insert, vlan_tag, loopback); 520 else if (skb->ip_summed == CHECKSUM_PARTIAL) 521 enic_queue_wq_skb_csum_l4(enic, wq, skb, 522 vlan_tag_insert, vlan_tag, loopback); 523 else 524 enic_queue_wq_skb_vlan(enic, wq, skb, 525 vlan_tag_insert, vlan_tag, loopback); 526 } 527 528 /* netif_tx_lock held, process context with BHs disabled, or BH */ 529 static netdev_tx_t enic_hard_start_xmit(struct sk_buff *skb, 530 struct net_device *netdev) 531 { 532 struct enic *enic = netdev_priv(netdev); 533 struct vnic_wq *wq; 534 unsigned long flags; 535 unsigned int txq_map; 536 537 if (skb->len <= 0) { 538 dev_kfree_skb_any(skb); 539 return NETDEV_TX_OK; 540 } 541 542 txq_map = skb_get_queue_mapping(skb) % enic->wq_count; 543 wq = &enic->wq[txq_map]; 544 545 /* Non-TSO sends must fit within ENIC_NON_TSO_MAX_DESC descs, 546 * which is very likely. In the off chance it's going to take 547 * more than * ENIC_NON_TSO_MAX_DESC, linearize the skb. 548 */ 549 550 if (skb_shinfo(skb)->gso_size == 0 && 551 skb_shinfo(skb)->nr_frags + 1 > ENIC_NON_TSO_MAX_DESC && 552 skb_linearize(skb)) { 553 dev_kfree_skb_any(skb); 554 return NETDEV_TX_OK; 555 } 556 557 spin_lock_irqsave(&enic->wq_lock[txq_map], flags); 558 559 if (vnic_wq_desc_avail(wq) < 560 skb_shinfo(skb)->nr_frags + ENIC_DESC_MAX_SPLITS) { 561 netif_tx_stop_queue(netdev_get_tx_queue(netdev, txq_map)); 562 /* This is a hard error, log it */ 563 netdev_err(netdev, "BUG! Tx ring full when queue awake!\n"); 564 spin_unlock_irqrestore(&enic->wq_lock[txq_map], flags); 565 return NETDEV_TX_BUSY; 566 } 567 568 enic_queue_wq_skb(enic, wq, skb); 569 570 if (vnic_wq_desc_avail(wq) < MAX_SKB_FRAGS + ENIC_DESC_MAX_SPLITS) 571 netif_tx_stop_queue(netdev_get_tx_queue(netdev, txq_map)); 572 573 spin_unlock_irqrestore(&enic->wq_lock[txq_map], flags); 574 575 return NETDEV_TX_OK; 576 } 577 578 /* dev_base_lock rwlock held, nominally process context */ 579 static struct rtnl_link_stats64 *enic_get_stats(struct net_device *netdev, 580 struct rtnl_link_stats64 *net_stats) 581 { 582 struct enic *enic = netdev_priv(netdev); 583 struct vnic_stats *stats; 584 585 enic_dev_stats_dump(enic, &stats); 586 587 net_stats->tx_packets = stats->tx.tx_frames_ok; 588 net_stats->tx_bytes = stats->tx.tx_bytes_ok; 589 net_stats->tx_errors = stats->tx.tx_errors; 590 net_stats->tx_dropped = stats->tx.tx_drops; 591 592 net_stats->rx_packets = stats->rx.rx_frames_ok; 593 net_stats->rx_bytes = stats->rx.rx_bytes_ok; 594 net_stats->rx_errors = stats->rx.rx_errors; 595 net_stats->multicast = stats->rx.rx_multicast_frames_ok; 596 net_stats->rx_over_errors = enic->rq_truncated_pkts; 597 net_stats->rx_crc_errors = enic->rq_bad_fcs; 598 net_stats->rx_dropped = stats->rx.rx_no_bufs + stats->rx.rx_drop; 599 600 return net_stats; 601 } 602 603 static int enic_mc_sync(struct net_device *netdev, const u8 *mc_addr) 604 { 605 struct enic *enic = netdev_priv(netdev); 606 607 if (enic->mc_count == ENIC_MULTICAST_PERFECT_FILTERS) { 608 unsigned int mc_count = netdev_mc_count(netdev); 609 610 netdev_warn(netdev, "Registering only %d out of %d multicast addresses\n", 611 ENIC_MULTICAST_PERFECT_FILTERS, mc_count); 612 613 return -ENOSPC; 614 } 615 616 enic_dev_add_addr(enic, mc_addr); 617 enic->mc_count++; 618 619 return 0; 620 } 621 622 static int enic_mc_unsync(struct net_device *netdev, const u8 *mc_addr) 623 { 624 struct enic *enic = netdev_priv(netdev); 625 626 enic_dev_del_addr(enic, mc_addr); 627 enic->mc_count--; 628 629 return 0; 630 } 631 632 static int enic_uc_sync(struct net_device *netdev, const u8 *uc_addr) 633 { 634 struct enic *enic = netdev_priv(netdev); 635 636 if (enic->uc_count == ENIC_UNICAST_PERFECT_FILTERS) { 637 unsigned int uc_count = netdev_uc_count(netdev); 638 639 netdev_warn(netdev, "Registering only %d out of %d unicast addresses\n", 640 ENIC_UNICAST_PERFECT_FILTERS, uc_count); 641 642 return -ENOSPC; 643 } 644 645 enic_dev_add_addr(enic, uc_addr); 646 enic->uc_count++; 647 648 return 0; 649 } 650 651 static int enic_uc_unsync(struct net_device *netdev, const u8 *uc_addr) 652 { 653 struct enic *enic = netdev_priv(netdev); 654 655 enic_dev_del_addr(enic, uc_addr); 656 enic->uc_count--; 657 658 return 0; 659 } 660 661 void enic_reset_addr_lists(struct enic *enic) 662 { 663 struct net_device *netdev = enic->netdev; 664 665 __dev_uc_unsync(netdev, NULL); 666 __dev_mc_unsync(netdev, NULL); 667 668 enic->mc_count = 0; 669 enic->uc_count = 0; 670 enic->flags = 0; 671 } 672 673 static int enic_set_mac_addr(struct net_device *netdev, char *addr) 674 { 675 struct enic *enic = netdev_priv(netdev); 676 677 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) { 678 if (!is_valid_ether_addr(addr) && !is_zero_ether_addr(addr)) 679 return -EADDRNOTAVAIL; 680 } else { 681 if (!is_valid_ether_addr(addr)) 682 return -EADDRNOTAVAIL; 683 } 684 685 memcpy(netdev->dev_addr, addr, netdev->addr_len); 686 687 return 0; 688 } 689 690 static int enic_set_mac_address_dynamic(struct net_device *netdev, void *p) 691 { 692 struct enic *enic = netdev_priv(netdev); 693 struct sockaddr *saddr = p; 694 char *addr = saddr->sa_data; 695 int err; 696 697 if (netif_running(enic->netdev)) { 698 err = enic_dev_del_station_addr(enic); 699 if (err) 700 return err; 701 } 702 703 err = enic_set_mac_addr(netdev, addr); 704 if (err) 705 return err; 706 707 if (netif_running(enic->netdev)) { 708 err = enic_dev_add_station_addr(enic); 709 if (err) 710 return err; 711 } 712 713 return err; 714 } 715 716 static int enic_set_mac_address(struct net_device *netdev, void *p) 717 { 718 struct sockaddr *saddr = p; 719 char *addr = saddr->sa_data; 720 struct enic *enic = netdev_priv(netdev); 721 int err; 722 723 err = enic_dev_del_station_addr(enic); 724 if (err) 725 return err; 726 727 err = enic_set_mac_addr(netdev, addr); 728 if (err) 729 return err; 730 731 return enic_dev_add_station_addr(enic); 732 } 733 734 /* netif_tx_lock held, BHs disabled */ 735 static void enic_set_rx_mode(struct net_device *netdev) 736 { 737 struct enic *enic = netdev_priv(netdev); 738 int directed = 1; 739 int multicast = (netdev->flags & IFF_MULTICAST) ? 1 : 0; 740 int broadcast = (netdev->flags & IFF_BROADCAST) ? 1 : 0; 741 int promisc = (netdev->flags & IFF_PROMISC) || 742 netdev_uc_count(netdev) > ENIC_UNICAST_PERFECT_FILTERS; 743 int allmulti = (netdev->flags & IFF_ALLMULTI) || 744 netdev_mc_count(netdev) > ENIC_MULTICAST_PERFECT_FILTERS; 745 unsigned int flags = netdev->flags | 746 (allmulti ? IFF_ALLMULTI : 0) | 747 (promisc ? IFF_PROMISC : 0); 748 749 if (enic->flags != flags) { 750 enic->flags = flags; 751 enic_dev_packet_filter(enic, directed, 752 multicast, broadcast, promisc, allmulti); 753 } 754 755 if (!promisc) { 756 __dev_uc_sync(netdev, enic_uc_sync, enic_uc_unsync); 757 if (!allmulti) 758 __dev_mc_sync(netdev, enic_mc_sync, enic_mc_unsync); 759 } 760 } 761 762 /* netif_tx_lock held, BHs disabled */ 763 static void enic_tx_timeout(struct net_device *netdev) 764 { 765 struct enic *enic = netdev_priv(netdev); 766 schedule_work(&enic->reset); 767 } 768 769 static int enic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 770 { 771 struct enic *enic = netdev_priv(netdev); 772 struct enic_port_profile *pp; 773 int err; 774 775 ENIC_PP_BY_INDEX(enic, vf, pp, &err); 776 if (err) 777 return err; 778 779 if (is_valid_ether_addr(mac) || is_zero_ether_addr(mac)) { 780 if (vf == PORT_SELF_VF) { 781 memcpy(pp->vf_mac, mac, ETH_ALEN); 782 return 0; 783 } else { 784 /* 785 * For sriov vf's set the mac in hw 786 */ 787 ENIC_DEVCMD_PROXY_BY_INDEX(vf, err, enic, 788 vnic_dev_set_mac_addr, mac); 789 return enic_dev_status_to_errno(err); 790 } 791 } else 792 return -EINVAL; 793 } 794 795 static int enic_set_vf_port(struct net_device *netdev, int vf, 796 struct nlattr *port[]) 797 { 798 struct enic *enic = netdev_priv(netdev); 799 struct enic_port_profile prev_pp; 800 struct enic_port_profile *pp; 801 int err = 0, restore_pp = 1; 802 803 ENIC_PP_BY_INDEX(enic, vf, pp, &err); 804 if (err) 805 return err; 806 807 if (!port[IFLA_PORT_REQUEST]) 808 return -EOPNOTSUPP; 809 810 memcpy(&prev_pp, pp, sizeof(*enic->pp)); 811 memset(pp, 0, sizeof(*enic->pp)); 812 813 pp->set |= ENIC_SET_REQUEST; 814 pp->request = nla_get_u8(port[IFLA_PORT_REQUEST]); 815 816 if (port[IFLA_PORT_PROFILE]) { 817 pp->set |= ENIC_SET_NAME; 818 memcpy(pp->name, nla_data(port[IFLA_PORT_PROFILE]), 819 PORT_PROFILE_MAX); 820 } 821 822 if (port[IFLA_PORT_INSTANCE_UUID]) { 823 pp->set |= ENIC_SET_INSTANCE; 824 memcpy(pp->instance_uuid, 825 nla_data(port[IFLA_PORT_INSTANCE_UUID]), PORT_UUID_MAX); 826 } 827 828 if (port[IFLA_PORT_HOST_UUID]) { 829 pp->set |= ENIC_SET_HOST; 830 memcpy(pp->host_uuid, 831 nla_data(port[IFLA_PORT_HOST_UUID]), PORT_UUID_MAX); 832 } 833 834 if (vf == PORT_SELF_VF) { 835 /* Special case handling: mac came from IFLA_VF_MAC */ 836 if (!is_zero_ether_addr(prev_pp.vf_mac)) 837 memcpy(pp->mac_addr, prev_pp.vf_mac, ETH_ALEN); 838 839 if (is_zero_ether_addr(netdev->dev_addr)) 840 eth_hw_addr_random(netdev); 841 } else { 842 /* SR-IOV VF: get mac from adapter */ 843 ENIC_DEVCMD_PROXY_BY_INDEX(vf, err, enic, 844 vnic_dev_get_mac_addr, pp->mac_addr); 845 if (err) { 846 netdev_err(netdev, "Error getting mac for vf %d\n", vf); 847 memcpy(pp, &prev_pp, sizeof(*pp)); 848 return enic_dev_status_to_errno(err); 849 } 850 } 851 852 err = enic_process_set_pp_request(enic, vf, &prev_pp, &restore_pp); 853 if (err) { 854 if (restore_pp) { 855 /* Things are still the way they were: Implicit 856 * DISASSOCIATE failed 857 */ 858 memcpy(pp, &prev_pp, sizeof(*pp)); 859 } else { 860 memset(pp, 0, sizeof(*pp)); 861 if (vf == PORT_SELF_VF) 862 memset(netdev->dev_addr, 0, ETH_ALEN); 863 } 864 } else { 865 /* Set flag to indicate that the port assoc/disassoc 866 * request has been sent out to fw 867 */ 868 pp->set |= ENIC_PORT_REQUEST_APPLIED; 869 870 /* If DISASSOCIATE, clean up all assigned/saved macaddresses */ 871 if (pp->request == PORT_REQUEST_DISASSOCIATE) { 872 memset(pp->mac_addr, 0, ETH_ALEN); 873 if (vf == PORT_SELF_VF) 874 memset(netdev->dev_addr, 0, ETH_ALEN); 875 } 876 } 877 878 if (vf == PORT_SELF_VF) 879 memset(pp->vf_mac, 0, ETH_ALEN); 880 881 return err; 882 } 883 884 static int enic_get_vf_port(struct net_device *netdev, int vf, 885 struct sk_buff *skb) 886 { 887 struct enic *enic = netdev_priv(netdev); 888 u16 response = PORT_PROFILE_RESPONSE_SUCCESS; 889 struct enic_port_profile *pp; 890 int err; 891 892 ENIC_PP_BY_INDEX(enic, vf, pp, &err); 893 if (err) 894 return err; 895 896 if (!(pp->set & ENIC_PORT_REQUEST_APPLIED)) 897 return -ENODATA; 898 899 err = enic_process_get_pp_request(enic, vf, pp->request, &response); 900 if (err) 901 return err; 902 903 if (nla_put_u16(skb, IFLA_PORT_REQUEST, pp->request) || 904 nla_put_u16(skb, IFLA_PORT_RESPONSE, response) || 905 ((pp->set & ENIC_SET_NAME) && 906 nla_put(skb, IFLA_PORT_PROFILE, PORT_PROFILE_MAX, pp->name)) || 907 ((pp->set & ENIC_SET_INSTANCE) && 908 nla_put(skb, IFLA_PORT_INSTANCE_UUID, PORT_UUID_MAX, 909 pp->instance_uuid)) || 910 ((pp->set & ENIC_SET_HOST) && 911 nla_put(skb, IFLA_PORT_HOST_UUID, PORT_UUID_MAX, pp->host_uuid))) 912 goto nla_put_failure; 913 return 0; 914 915 nla_put_failure: 916 return -EMSGSIZE; 917 } 918 919 static void enic_free_rq_buf(struct vnic_rq *rq, struct vnic_rq_buf *buf) 920 { 921 struct enic *enic = vnic_dev_priv(rq->vdev); 922 923 if (!buf->os_buf) 924 return; 925 926 pci_unmap_single(enic->pdev, buf->dma_addr, 927 buf->len, PCI_DMA_FROMDEVICE); 928 dev_kfree_skb_any(buf->os_buf); 929 buf->os_buf = NULL; 930 } 931 932 static int enic_rq_alloc_buf(struct vnic_rq *rq) 933 { 934 struct enic *enic = vnic_dev_priv(rq->vdev); 935 struct net_device *netdev = enic->netdev; 936 struct sk_buff *skb; 937 unsigned int len = netdev->mtu + VLAN_ETH_HLEN; 938 unsigned int os_buf_index = 0; 939 dma_addr_t dma_addr; 940 struct vnic_rq_buf *buf = rq->to_use; 941 942 if (buf->os_buf) { 943 enic_queue_rq_desc(rq, buf->os_buf, os_buf_index, buf->dma_addr, 944 buf->len); 945 946 return 0; 947 } 948 skb = netdev_alloc_skb_ip_align(netdev, len); 949 if (!skb) 950 return -ENOMEM; 951 952 dma_addr = pci_map_single(enic->pdev, skb->data, 953 len, PCI_DMA_FROMDEVICE); 954 955 enic_queue_rq_desc(rq, skb, os_buf_index, 956 dma_addr, len); 957 958 return 0; 959 } 960 961 static void enic_intr_update_pkt_size(struct vnic_rx_bytes_counter *pkt_size, 962 u32 pkt_len) 963 { 964 if (ENIC_LARGE_PKT_THRESHOLD <= pkt_len) 965 pkt_size->large_pkt_bytes_cnt += pkt_len; 966 else 967 pkt_size->small_pkt_bytes_cnt += pkt_len; 968 } 969 970 static bool enic_rxcopybreak(struct net_device *netdev, struct sk_buff **skb, 971 struct vnic_rq_buf *buf, u16 len) 972 { 973 struct enic *enic = netdev_priv(netdev); 974 struct sk_buff *new_skb; 975 976 if (len > enic->rx_copybreak) 977 return false; 978 new_skb = netdev_alloc_skb_ip_align(netdev, len); 979 if (!new_skb) 980 return false; 981 pci_dma_sync_single_for_cpu(enic->pdev, buf->dma_addr, len, 982 DMA_FROM_DEVICE); 983 memcpy(new_skb->data, (*skb)->data, len); 984 *skb = new_skb; 985 986 return true; 987 } 988 989 static void enic_rq_indicate_buf(struct vnic_rq *rq, 990 struct cq_desc *cq_desc, struct vnic_rq_buf *buf, 991 int skipped, void *opaque) 992 { 993 struct enic *enic = vnic_dev_priv(rq->vdev); 994 struct net_device *netdev = enic->netdev; 995 struct sk_buff *skb; 996 struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)]; 997 998 u8 type, color, eop, sop, ingress_port, vlan_stripped; 999 u8 fcoe, fcoe_sof, fcoe_fc_crc_ok, fcoe_enc_error, fcoe_eof; 1000 u8 tcp_udp_csum_ok, udp, tcp, ipv4_csum_ok; 1001 u8 ipv6, ipv4, ipv4_fragment, fcs_ok, rss_type, csum_not_calc; 1002 u8 packet_error; 1003 u16 q_number, completed_index, bytes_written, vlan_tci, checksum; 1004 u32 rss_hash; 1005 1006 if (skipped) 1007 return; 1008 1009 skb = buf->os_buf; 1010 1011 cq_enet_rq_desc_dec((struct cq_enet_rq_desc *)cq_desc, 1012 &type, &color, &q_number, &completed_index, 1013 &ingress_port, &fcoe, &eop, &sop, &rss_type, 1014 &csum_not_calc, &rss_hash, &bytes_written, 1015 &packet_error, &vlan_stripped, &vlan_tci, &checksum, 1016 &fcoe_sof, &fcoe_fc_crc_ok, &fcoe_enc_error, 1017 &fcoe_eof, &tcp_udp_csum_ok, &udp, &tcp, 1018 &ipv4_csum_ok, &ipv6, &ipv4, &ipv4_fragment, 1019 &fcs_ok); 1020 1021 if (packet_error) { 1022 1023 if (!fcs_ok) { 1024 if (bytes_written > 0) 1025 enic->rq_bad_fcs++; 1026 else if (bytes_written == 0) 1027 enic->rq_truncated_pkts++; 1028 } 1029 1030 pci_unmap_single(enic->pdev, buf->dma_addr, buf->len, 1031 PCI_DMA_FROMDEVICE); 1032 dev_kfree_skb_any(skb); 1033 buf->os_buf = NULL; 1034 1035 return; 1036 } 1037 1038 if (eop && bytes_written > 0) { 1039 1040 /* Good receive 1041 */ 1042 1043 if (!enic_rxcopybreak(netdev, &skb, buf, bytes_written)) { 1044 buf->os_buf = NULL; 1045 pci_unmap_single(enic->pdev, buf->dma_addr, buf->len, 1046 PCI_DMA_FROMDEVICE); 1047 } 1048 prefetch(skb->data - NET_IP_ALIGN); 1049 1050 skb_put(skb, bytes_written); 1051 skb->protocol = eth_type_trans(skb, netdev); 1052 skb_record_rx_queue(skb, q_number); 1053 if (netdev->features & NETIF_F_RXHASH) { 1054 skb_set_hash(skb, rss_hash, 1055 (rss_type & 1056 (NIC_CFG_RSS_HASH_TYPE_TCP_IPV6_EX | 1057 NIC_CFG_RSS_HASH_TYPE_TCP_IPV6 | 1058 NIC_CFG_RSS_HASH_TYPE_TCP_IPV4)) ? 1059 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); 1060 } 1061 1062 if ((netdev->features & NETIF_F_RXCSUM) && !csum_not_calc) { 1063 skb->csum = htons(checksum); 1064 skb->ip_summed = CHECKSUM_COMPLETE; 1065 } 1066 1067 if (vlan_stripped) 1068 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tci); 1069 1070 skb_mark_napi_id(skb, &enic->napi[rq->index]); 1071 if (enic_poll_busy_polling(rq) || 1072 !(netdev->features & NETIF_F_GRO)) 1073 netif_receive_skb(skb); 1074 else 1075 napi_gro_receive(&enic->napi[q_number], skb); 1076 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce) 1077 enic_intr_update_pkt_size(&cq->pkt_size_counter, 1078 bytes_written); 1079 } else { 1080 1081 /* Buffer overflow 1082 */ 1083 1084 pci_unmap_single(enic->pdev, buf->dma_addr, buf->len, 1085 PCI_DMA_FROMDEVICE); 1086 dev_kfree_skb_any(skb); 1087 buf->os_buf = NULL; 1088 } 1089 } 1090 1091 static int enic_rq_service(struct vnic_dev *vdev, struct cq_desc *cq_desc, 1092 u8 type, u16 q_number, u16 completed_index, void *opaque) 1093 { 1094 struct enic *enic = vnic_dev_priv(vdev); 1095 1096 vnic_rq_service(&enic->rq[q_number], cq_desc, 1097 completed_index, VNIC_RQ_RETURN_DESC, 1098 enic_rq_indicate_buf, opaque); 1099 1100 return 0; 1101 } 1102 1103 static int enic_poll(struct napi_struct *napi, int budget) 1104 { 1105 struct net_device *netdev = napi->dev; 1106 struct enic *enic = netdev_priv(netdev); 1107 unsigned int cq_rq = enic_cq_rq(enic, 0); 1108 unsigned int cq_wq = enic_cq_wq(enic, 0); 1109 unsigned int intr = enic_legacy_io_intr(); 1110 unsigned int rq_work_to_do = budget; 1111 unsigned int wq_work_to_do = -1; /* no limit */ 1112 unsigned int work_done, rq_work_done = 0, wq_work_done; 1113 int err; 1114 1115 wq_work_done = vnic_cq_service(&enic->cq[cq_wq], wq_work_to_do, 1116 enic_wq_service, NULL); 1117 1118 if (!enic_poll_lock_napi(&enic->rq[cq_rq])) { 1119 if (wq_work_done > 0) 1120 vnic_intr_return_credits(&enic->intr[intr], 1121 wq_work_done, 1122 0 /* dont unmask intr */, 1123 0 /* dont reset intr timer */); 1124 return rq_work_done; 1125 } 1126 1127 if (budget > 0) 1128 rq_work_done = vnic_cq_service(&enic->cq[cq_rq], 1129 rq_work_to_do, enic_rq_service, NULL); 1130 1131 /* Accumulate intr event credits for this polling 1132 * cycle. An intr event is the completion of a 1133 * a WQ or RQ packet. 1134 */ 1135 1136 work_done = rq_work_done + wq_work_done; 1137 1138 if (work_done > 0) 1139 vnic_intr_return_credits(&enic->intr[intr], 1140 work_done, 1141 0 /* don't unmask intr */, 1142 0 /* don't reset intr timer */); 1143 1144 err = vnic_rq_fill(&enic->rq[0], enic_rq_alloc_buf); 1145 1146 /* Buffer allocation failed. Stay in polling 1147 * mode so we can try to fill the ring again. 1148 */ 1149 1150 if (err) 1151 rq_work_done = rq_work_to_do; 1152 1153 if (rq_work_done < rq_work_to_do) { 1154 1155 /* Some work done, but not enough to stay in polling, 1156 * exit polling 1157 */ 1158 1159 napi_complete(napi); 1160 vnic_intr_unmask(&enic->intr[intr]); 1161 } 1162 enic_poll_unlock_napi(&enic->rq[cq_rq]); 1163 1164 return rq_work_done; 1165 } 1166 1167 static void enic_set_int_moderation(struct enic *enic, struct vnic_rq *rq) 1168 { 1169 unsigned int intr = enic_msix_rq_intr(enic, rq->index); 1170 struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)]; 1171 u32 timer = cq->tobe_rx_coal_timeval; 1172 1173 if (cq->tobe_rx_coal_timeval != cq->cur_rx_coal_timeval) { 1174 vnic_intr_coalescing_timer_set(&enic->intr[intr], timer); 1175 cq->cur_rx_coal_timeval = cq->tobe_rx_coal_timeval; 1176 } 1177 } 1178 1179 static void enic_calc_int_moderation(struct enic *enic, struct vnic_rq *rq) 1180 { 1181 struct enic_rx_coal *rx_coal = &enic->rx_coalesce_setting; 1182 struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)]; 1183 struct vnic_rx_bytes_counter *pkt_size_counter = &cq->pkt_size_counter; 1184 int index; 1185 u32 timer; 1186 u32 range_start; 1187 u32 traffic; 1188 u64 delta; 1189 ktime_t now = ktime_get(); 1190 1191 delta = ktime_us_delta(now, cq->prev_ts); 1192 if (delta < ENIC_AIC_TS_BREAK) 1193 return; 1194 cq->prev_ts = now; 1195 1196 traffic = pkt_size_counter->large_pkt_bytes_cnt + 1197 pkt_size_counter->small_pkt_bytes_cnt; 1198 /* The table takes Mbps 1199 * traffic *= 8 => bits 1200 * traffic *= (10^6 / delta) => bps 1201 * traffic /= 10^6 => Mbps 1202 * 1203 * Combining, traffic *= (8 / delta) 1204 */ 1205 1206 traffic <<= 3; 1207 traffic = delta > UINT_MAX ? 0 : traffic / (u32)delta; 1208 1209 for (index = 0; index < ENIC_MAX_COALESCE_TIMERS; index++) 1210 if (traffic < mod_table[index].rx_rate) 1211 break; 1212 range_start = (pkt_size_counter->small_pkt_bytes_cnt > 1213 pkt_size_counter->large_pkt_bytes_cnt << 1) ? 1214 rx_coal->small_pkt_range_start : 1215 rx_coal->large_pkt_range_start; 1216 timer = range_start + ((rx_coal->range_end - range_start) * 1217 mod_table[index].range_percent / 100); 1218 /* Damping */ 1219 cq->tobe_rx_coal_timeval = (timer + cq->tobe_rx_coal_timeval) >> 1; 1220 1221 pkt_size_counter->large_pkt_bytes_cnt = 0; 1222 pkt_size_counter->small_pkt_bytes_cnt = 0; 1223 } 1224 1225 #ifdef CONFIG_RFS_ACCEL 1226 static void enic_free_rx_cpu_rmap(struct enic *enic) 1227 { 1228 free_irq_cpu_rmap(enic->netdev->rx_cpu_rmap); 1229 enic->netdev->rx_cpu_rmap = NULL; 1230 } 1231 1232 static void enic_set_rx_cpu_rmap(struct enic *enic) 1233 { 1234 int i, res; 1235 1236 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX) { 1237 enic->netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(enic->rq_count); 1238 if (unlikely(!enic->netdev->rx_cpu_rmap)) 1239 return; 1240 for (i = 0; i < enic->rq_count; i++) { 1241 res = irq_cpu_rmap_add(enic->netdev->rx_cpu_rmap, 1242 enic->msix_entry[i].vector); 1243 if (unlikely(res)) { 1244 enic_free_rx_cpu_rmap(enic); 1245 return; 1246 } 1247 } 1248 } 1249 } 1250 1251 #else 1252 1253 static void enic_free_rx_cpu_rmap(struct enic *enic) 1254 { 1255 } 1256 1257 static void enic_set_rx_cpu_rmap(struct enic *enic) 1258 { 1259 } 1260 1261 #endif /* CONFIG_RFS_ACCEL */ 1262 1263 #ifdef CONFIG_NET_RX_BUSY_POLL 1264 int enic_busy_poll(struct napi_struct *napi) 1265 { 1266 struct net_device *netdev = napi->dev; 1267 struct enic *enic = netdev_priv(netdev); 1268 unsigned int rq = (napi - &enic->napi[0]); 1269 unsigned int cq = enic_cq_rq(enic, rq); 1270 unsigned int intr = enic_msix_rq_intr(enic, rq); 1271 unsigned int work_to_do = -1; /* clean all pkts possible */ 1272 unsigned int work_done; 1273 1274 if (!enic_poll_lock_poll(&enic->rq[rq])) 1275 return LL_FLUSH_BUSY; 1276 work_done = vnic_cq_service(&enic->cq[cq], work_to_do, 1277 enic_rq_service, NULL); 1278 1279 if (work_done > 0) 1280 vnic_intr_return_credits(&enic->intr[intr], 1281 work_done, 0, 0); 1282 vnic_rq_fill(&enic->rq[rq], enic_rq_alloc_buf); 1283 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce) 1284 enic_calc_int_moderation(enic, &enic->rq[rq]); 1285 enic_poll_unlock_poll(&enic->rq[rq]); 1286 1287 return work_done; 1288 } 1289 #endif /* CONFIG_NET_RX_BUSY_POLL */ 1290 1291 static int enic_poll_msix_wq(struct napi_struct *napi, int budget) 1292 { 1293 struct net_device *netdev = napi->dev; 1294 struct enic *enic = netdev_priv(netdev); 1295 unsigned int wq_index = (napi - &enic->napi[0]) - enic->rq_count; 1296 struct vnic_wq *wq = &enic->wq[wq_index]; 1297 unsigned int cq; 1298 unsigned int intr; 1299 unsigned int wq_work_to_do = -1; /* clean all desc possible */ 1300 unsigned int wq_work_done; 1301 unsigned int wq_irq; 1302 1303 wq_irq = wq->index; 1304 cq = enic_cq_wq(enic, wq_irq); 1305 intr = enic_msix_wq_intr(enic, wq_irq); 1306 wq_work_done = vnic_cq_service(&enic->cq[cq], wq_work_to_do, 1307 enic_wq_service, NULL); 1308 1309 vnic_intr_return_credits(&enic->intr[intr], wq_work_done, 1310 0 /* don't unmask intr */, 1311 1 /* reset intr timer */); 1312 if (!wq_work_done) { 1313 napi_complete(napi); 1314 vnic_intr_unmask(&enic->intr[intr]); 1315 } 1316 1317 return 0; 1318 } 1319 1320 static int enic_poll_msix_rq(struct napi_struct *napi, int budget) 1321 { 1322 struct net_device *netdev = napi->dev; 1323 struct enic *enic = netdev_priv(netdev); 1324 unsigned int rq = (napi - &enic->napi[0]); 1325 unsigned int cq = enic_cq_rq(enic, rq); 1326 unsigned int intr = enic_msix_rq_intr(enic, rq); 1327 unsigned int work_to_do = budget; 1328 unsigned int work_done = 0; 1329 int err; 1330 1331 if (!enic_poll_lock_napi(&enic->rq[rq])) 1332 return work_done; 1333 /* Service RQ 1334 */ 1335 1336 if (budget > 0) 1337 work_done = vnic_cq_service(&enic->cq[cq], 1338 work_to_do, enic_rq_service, NULL); 1339 1340 /* Return intr event credits for this polling 1341 * cycle. An intr event is the completion of a 1342 * RQ packet. 1343 */ 1344 1345 if (work_done > 0) 1346 vnic_intr_return_credits(&enic->intr[intr], 1347 work_done, 1348 0 /* don't unmask intr */, 1349 0 /* don't reset intr timer */); 1350 1351 err = vnic_rq_fill(&enic->rq[rq], enic_rq_alloc_buf); 1352 1353 /* Buffer allocation failed. Stay in polling mode 1354 * so we can try to fill the ring again. 1355 */ 1356 1357 if (err) 1358 work_done = work_to_do; 1359 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce) 1360 /* Call the function which refreshes 1361 * the intr coalescing timer value based on 1362 * the traffic. This is supported only in 1363 * the case of MSI-x mode 1364 */ 1365 enic_calc_int_moderation(enic, &enic->rq[rq]); 1366 1367 if (work_done < work_to_do) { 1368 1369 /* Some work done, but not enough to stay in polling, 1370 * exit polling 1371 */ 1372 1373 napi_complete(napi); 1374 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce) 1375 enic_set_int_moderation(enic, &enic->rq[rq]); 1376 vnic_intr_unmask(&enic->intr[intr]); 1377 } 1378 enic_poll_unlock_napi(&enic->rq[rq]); 1379 1380 return work_done; 1381 } 1382 1383 static void enic_notify_timer(unsigned long data) 1384 { 1385 struct enic *enic = (struct enic *)data; 1386 1387 enic_notify_check(enic); 1388 1389 mod_timer(&enic->notify_timer, 1390 round_jiffies(jiffies + ENIC_NOTIFY_TIMER_PERIOD)); 1391 } 1392 1393 static void enic_free_intr(struct enic *enic) 1394 { 1395 struct net_device *netdev = enic->netdev; 1396 unsigned int i; 1397 1398 enic_free_rx_cpu_rmap(enic); 1399 switch (vnic_dev_get_intr_mode(enic->vdev)) { 1400 case VNIC_DEV_INTR_MODE_INTX: 1401 free_irq(enic->pdev->irq, netdev); 1402 break; 1403 case VNIC_DEV_INTR_MODE_MSI: 1404 free_irq(enic->pdev->irq, enic); 1405 break; 1406 case VNIC_DEV_INTR_MODE_MSIX: 1407 for (i = 0; i < ARRAY_SIZE(enic->msix); i++) 1408 if (enic->msix[i].requested) 1409 free_irq(enic->msix_entry[i].vector, 1410 enic->msix[i].devid); 1411 break; 1412 default: 1413 break; 1414 } 1415 } 1416 1417 static int enic_request_intr(struct enic *enic) 1418 { 1419 struct net_device *netdev = enic->netdev; 1420 unsigned int i, intr; 1421 int err = 0; 1422 1423 enic_set_rx_cpu_rmap(enic); 1424 switch (vnic_dev_get_intr_mode(enic->vdev)) { 1425 1426 case VNIC_DEV_INTR_MODE_INTX: 1427 1428 err = request_irq(enic->pdev->irq, enic_isr_legacy, 1429 IRQF_SHARED, netdev->name, netdev); 1430 break; 1431 1432 case VNIC_DEV_INTR_MODE_MSI: 1433 1434 err = request_irq(enic->pdev->irq, enic_isr_msi, 1435 0, netdev->name, enic); 1436 break; 1437 1438 case VNIC_DEV_INTR_MODE_MSIX: 1439 1440 for (i = 0; i < enic->rq_count; i++) { 1441 intr = enic_msix_rq_intr(enic, i); 1442 snprintf(enic->msix[intr].devname, 1443 sizeof(enic->msix[intr].devname), 1444 "%.11s-rx-%d", netdev->name, i); 1445 enic->msix[intr].isr = enic_isr_msix; 1446 enic->msix[intr].devid = &enic->napi[i]; 1447 } 1448 1449 for (i = 0; i < enic->wq_count; i++) { 1450 int wq = enic_cq_wq(enic, i); 1451 1452 intr = enic_msix_wq_intr(enic, i); 1453 snprintf(enic->msix[intr].devname, 1454 sizeof(enic->msix[intr].devname), 1455 "%.11s-tx-%d", netdev->name, i); 1456 enic->msix[intr].isr = enic_isr_msix; 1457 enic->msix[intr].devid = &enic->napi[wq]; 1458 } 1459 1460 intr = enic_msix_err_intr(enic); 1461 snprintf(enic->msix[intr].devname, 1462 sizeof(enic->msix[intr].devname), 1463 "%.11s-err", netdev->name); 1464 enic->msix[intr].isr = enic_isr_msix_err; 1465 enic->msix[intr].devid = enic; 1466 1467 intr = enic_msix_notify_intr(enic); 1468 snprintf(enic->msix[intr].devname, 1469 sizeof(enic->msix[intr].devname), 1470 "%.11s-notify", netdev->name); 1471 enic->msix[intr].isr = enic_isr_msix_notify; 1472 enic->msix[intr].devid = enic; 1473 1474 for (i = 0; i < ARRAY_SIZE(enic->msix); i++) 1475 enic->msix[i].requested = 0; 1476 1477 for (i = 0; i < enic->intr_count; i++) { 1478 err = request_irq(enic->msix_entry[i].vector, 1479 enic->msix[i].isr, 0, 1480 enic->msix[i].devname, 1481 enic->msix[i].devid); 1482 if (err) { 1483 enic_free_intr(enic); 1484 break; 1485 } 1486 enic->msix[i].requested = 1; 1487 } 1488 1489 break; 1490 1491 default: 1492 break; 1493 } 1494 1495 return err; 1496 } 1497 1498 static void enic_synchronize_irqs(struct enic *enic) 1499 { 1500 unsigned int i; 1501 1502 switch (vnic_dev_get_intr_mode(enic->vdev)) { 1503 case VNIC_DEV_INTR_MODE_INTX: 1504 case VNIC_DEV_INTR_MODE_MSI: 1505 synchronize_irq(enic->pdev->irq); 1506 break; 1507 case VNIC_DEV_INTR_MODE_MSIX: 1508 for (i = 0; i < enic->intr_count; i++) 1509 synchronize_irq(enic->msix_entry[i].vector); 1510 break; 1511 default: 1512 break; 1513 } 1514 } 1515 1516 static void enic_set_rx_coal_setting(struct enic *enic) 1517 { 1518 unsigned int speed; 1519 int index = -1; 1520 struct enic_rx_coal *rx_coal = &enic->rx_coalesce_setting; 1521 1522 /* If intr mode is not MSIX, do not do adaptive coalescing */ 1523 if (VNIC_DEV_INTR_MODE_MSIX != vnic_dev_get_intr_mode(enic->vdev)) { 1524 netdev_info(enic->netdev, "INTR mode is not MSIX, Not initializing adaptive coalescing"); 1525 return; 1526 } 1527 1528 /* 1. Read the link speed from fw 1529 * 2. Pick the default range for the speed 1530 * 3. Update it in enic->rx_coalesce_setting 1531 */ 1532 speed = vnic_dev_port_speed(enic->vdev); 1533 if (ENIC_LINK_SPEED_10G < speed) 1534 index = ENIC_LINK_40G_INDEX; 1535 else if (ENIC_LINK_SPEED_4G < speed) 1536 index = ENIC_LINK_10G_INDEX; 1537 else 1538 index = ENIC_LINK_4G_INDEX; 1539 1540 rx_coal->small_pkt_range_start = mod_range[index].small_pkt_range_start; 1541 rx_coal->large_pkt_range_start = mod_range[index].large_pkt_range_start; 1542 rx_coal->range_end = ENIC_RX_COALESCE_RANGE_END; 1543 1544 /* Start with the value provided by UCSM */ 1545 for (index = 0; index < enic->rq_count; index++) 1546 enic->cq[index].cur_rx_coal_timeval = 1547 enic->config.intr_timer_usec; 1548 1549 rx_coal->use_adaptive_rx_coalesce = 1; 1550 } 1551 1552 static int enic_dev_notify_set(struct enic *enic) 1553 { 1554 int err; 1555 1556 spin_lock_bh(&enic->devcmd_lock); 1557 switch (vnic_dev_get_intr_mode(enic->vdev)) { 1558 case VNIC_DEV_INTR_MODE_INTX: 1559 err = vnic_dev_notify_set(enic->vdev, 1560 enic_legacy_notify_intr()); 1561 break; 1562 case VNIC_DEV_INTR_MODE_MSIX: 1563 err = vnic_dev_notify_set(enic->vdev, 1564 enic_msix_notify_intr(enic)); 1565 break; 1566 default: 1567 err = vnic_dev_notify_set(enic->vdev, -1 /* no intr */); 1568 break; 1569 } 1570 spin_unlock_bh(&enic->devcmd_lock); 1571 1572 return err; 1573 } 1574 1575 static void enic_notify_timer_start(struct enic *enic) 1576 { 1577 switch (vnic_dev_get_intr_mode(enic->vdev)) { 1578 case VNIC_DEV_INTR_MODE_MSI: 1579 mod_timer(&enic->notify_timer, jiffies); 1580 break; 1581 default: 1582 /* Using intr for notification for INTx/MSI-X */ 1583 break; 1584 } 1585 } 1586 1587 /* rtnl lock is held, process context */ 1588 static int enic_open(struct net_device *netdev) 1589 { 1590 struct enic *enic = netdev_priv(netdev); 1591 unsigned int i; 1592 int err; 1593 1594 err = enic_request_intr(enic); 1595 if (err) { 1596 netdev_err(netdev, "Unable to request irq.\n"); 1597 return err; 1598 } 1599 1600 err = enic_dev_notify_set(enic); 1601 if (err) { 1602 netdev_err(netdev, 1603 "Failed to alloc notify buffer, aborting.\n"); 1604 goto err_out_free_intr; 1605 } 1606 1607 for (i = 0; i < enic->rq_count; i++) { 1608 vnic_rq_fill(&enic->rq[i], enic_rq_alloc_buf); 1609 /* Need at least one buffer on ring to get going */ 1610 if (vnic_rq_desc_used(&enic->rq[i]) == 0) { 1611 netdev_err(netdev, "Unable to alloc receive buffers\n"); 1612 err = -ENOMEM; 1613 goto err_out_notify_unset; 1614 } 1615 } 1616 1617 for (i = 0; i < enic->wq_count; i++) 1618 vnic_wq_enable(&enic->wq[i]); 1619 for (i = 0; i < enic->rq_count; i++) 1620 vnic_rq_enable(&enic->rq[i]); 1621 1622 if (!enic_is_dynamic(enic) && !enic_is_sriov_vf(enic)) 1623 enic_dev_add_station_addr(enic); 1624 1625 enic_set_rx_mode(netdev); 1626 1627 netif_tx_wake_all_queues(netdev); 1628 1629 for (i = 0; i < enic->rq_count; i++) { 1630 enic_busy_poll_init_lock(&enic->rq[i]); 1631 napi_enable(&enic->napi[i]); 1632 } 1633 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX) 1634 for (i = 0; i < enic->wq_count; i++) 1635 napi_enable(&enic->napi[enic_cq_wq(enic, i)]); 1636 enic_dev_enable(enic); 1637 1638 for (i = 0; i < enic->intr_count; i++) 1639 vnic_intr_unmask(&enic->intr[i]); 1640 1641 enic_notify_timer_start(enic); 1642 enic_rfs_flw_tbl_init(enic); 1643 1644 return 0; 1645 1646 err_out_notify_unset: 1647 enic_dev_notify_unset(enic); 1648 err_out_free_intr: 1649 enic_free_intr(enic); 1650 1651 return err; 1652 } 1653 1654 /* rtnl lock is held, process context */ 1655 static int enic_stop(struct net_device *netdev) 1656 { 1657 struct enic *enic = netdev_priv(netdev); 1658 unsigned int i; 1659 int err; 1660 1661 for (i = 0; i < enic->intr_count; i++) { 1662 vnic_intr_mask(&enic->intr[i]); 1663 (void)vnic_intr_masked(&enic->intr[i]); /* flush write */ 1664 } 1665 1666 enic_synchronize_irqs(enic); 1667 1668 del_timer_sync(&enic->notify_timer); 1669 enic_rfs_flw_tbl_free(enic); 1670 1671 enic_dev_disable(enic); 1672 1673 for (i = 0; i < enic->rq_count; i++) { 1674 napi_disable(&enic->napi[i]); 1675 local_bh_disable(); 1676 while (!enic_poll_lock_napi(&enic->rq[i])) 1677 mdelay(1); 1678 local_bh_enable(); 1679 } 1680 1681 netif_carrier_off(netdev); 1682 netif_tx_disable(netdev); 1683 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX) 1684 for (i = 0; i < enic->wq_count; i++) 1685 napi_disable(&enic->napi[enic_cq_wq(enic, i)]); 1686 1687 if (!enic_is_dynamic(enic) && !enic_is_sriov_vf(enic)) 1688 enic_dev_del_station_addr(enic); 1689 1690 for (i = 0; i < enic->wq_count; i++) { 1691 err = vnic_wq_disable(&enic->wq[i]); 1692 if (err) 1693 return err; 1694 } 1695 for (i = 0; i < enic->rq_count; i++) { 1696 err = vnic_rq_disable(&enic->rq[i]); 1697 if (err) 1698 return err; 1699 } 1700 1701 enic_dev_notify_unset(enic); 1702 enic_free_intr(enic); 1703 1704 for (i = 0; i < enic->wq_count; i++) 1705 vnic_wq_clean(&enic->wq[i], enic_free_wq_buf); 1706 for (i = 0; i < enic->rq_count; i++) 1707 vnic_rq_clean(&enic->rq[i], enic_free_rq_buf); 1708 for (i = 0; i < enic->cq_count; i++) 1709 vnic_cq_clean(&enic->cq[i]); 1710 for (i = 0; i < enic->intr_count; i++) 1711 vnic_intr_clean(&enic->intr[i]); 1712 1713 return 0; 1714 } 1715 1716 static int enic_change_mtu(struct net_device *netdev, int new_mtu) 1717 { 1718 struct enic *enic = netdev_priv(netdev); 1719 int running = netif_running(netdev); 1720 1721 if (new_mtu < ENIC_MIN_MTU || new_mtu > ENIC_MAX_MTU) 1722 return -EINVAL; 1723 1724 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) 1725 return -EOPNOTSUPP; 1726 1727 if (running) 1728 enic_stop(netdev); 1729 1730 netdev->mtu = new_mtu; 1731 1732 if (netdev->mtu > enic->port_mtu) 1733 netdev_warn(netdev, 1734 "interface MTU (%d) set higher than port MTU (%d)\n", 1735 netdev->mtu, enic->port_mtu); 1736 1737 if (running) 1738 enic_open(netdev); 1739 1740 return 0; 1741 } 1742 1743 static void enic_change_mtu_work(struct work_struct *work) 1744 { 1745 struct enic *enic = container_of(work, struct enic, change_mtu_work); 1746 struct net_device *netdev = enic->netdev; 1747 int new_mtu = vnic_dev_mtu(enic->vdev); 1748 int err; 1749 unsigned int i; 1750 1751 new_mtu = max_t(int, ENIC_MIN_MTU, min_t(int, ENIC_MAX_MTU, new_mtu)); 1752 1753 rtnl_lock(); 1754 1755 /* Stop RQ */ 1756 del_timer_sync(&enic->notify_timer); 1757 1758 for (i = 0; i < enic->rq_count; i++) 1759 napi_disable(&enic->napi[i]); 1760 1761 vnic_intr_mask(&enic->intr[0]); 1762 enic_synchronize_irqs(enic); 1763 err = vnic_rq_disable(&enic->rq[0]); 1764 if (err) { 1765 rtnl_unlock(); 1766 netdev_err(netdev, "Unable to disable RQ.\n"); 1767 return; 1768 } 1769 vnic_rq_clean(&enic->rq[0], enic_free_rq_buf); 1770 vnic_cq_clean(&enic->cq[0]); 1771 vnic_intr_clean(&enic->intr[0]); 1772 1773 /* Fill RQ with new_mtu-sized buffers */ 1774 netdev->mtu = new_mtu; 1775 vnic_rq_fill(&enic->rq[0], enic_rq_alloc_buf); 1776 /* Need at least one buffer on ring to get going */ 1777 if (vnic_rq_desc_used(&enic->rq[0]) == 0) { 1778 rtnl_unlock(); 1779 netdev_err(netdev, "Unable to alloc receive buffers.\n"); 1780 return; 1781 } 1782 1783 /* Start RQ */ 1784 vnic_rq_enable(&enic->rq[0]); 1785 napi_enable(&enic->napi[0]); 1786 vnic_intr_unmask(&enic->intr[0]); 1787 enic_notify_timer_start(enic); 1788 1789 rtnl_unlock(); 1790 1791 netdev_info(netdev, "interface MTU set as %d\n", netdev->mtu); 1792 } 1793 1794 #ifdef CONFIG_NET_POLL_CONTROLLER 1795 static void enic_poll_controller(struct net_device *netdev) 1796 { 1797 struct enic *enic = netdev_priv(netdev); 1798 struct vnic_dev *vdev = enic->vdev; 1799 unsigned int i, intr; 1800 1801 switch (vnic_dev_get_intr_mode(vdev)) { 1802 case VNIC_DEV_INTR_MODE_MSIX: 1803 for (i = 0; i < enic->rq_count; i++) { 1804 intr = enic_msix_rq_intr(enic, i); 1805 enic_isr_msix(enic->msix_entry[intr].vector, 1806 &enic->napi[i]); 1807 } 1808 1809 for (i = 0; i < enic->wq_count; i++) { 1810 intr = enic_msix_wq_intr(enic, i); 1811 enic_isr_msix(enic->msix_entry[intr].vector, 1812 &enic->napi[enic_cq_wq(enic, i)]); 1813 } 1814 1815 break; 1816 case VNIC_DEV_INTR_MODE_MSI: 1817 enic_isr_msi(enic->pdev->irq, enic); 1818 break; 1819 case VNIC_DEV_INTR_MODE_INTX: 1820 enic_isr_legacy(enic->pdev->irq, netdev); 1821 break; 1822 default: 1823 break; 1824 } 1825 } 1826 #endif 1827 1828 static int enic_dev_wait(struct vnic_dev *vdev, 1829 int (*start)(struct vnic_dev *, int), 1830 int (*finished)(struct vnic_dev *, int *), 1831 int arg) 1832 { 1833 unsigned long time; 1834 int done; 1835 int err; 1836 1837 BUG_ON(in_interrupt()); 1838 1839 err = start(vdev, arg); 1840 if (err) 1841 return err; 1842 1843 /* Wait for func to complete...2 seconds max 1844 */ 1845 1846 time = jiffies + (HZ * 2); 1847 do { 1848 1849 err = finished(vdev, &done); 1850 if (err) 1851 return err; 1852 1853 if (done) 1854 return 0; 1855 1856 schedule_timeout_uninterruptible(HZ / 10); 1857 1858 } while (time_after(time, jiffies)); 1859 1860 return -ETIMEDOUT; 1861 } 1862 1863 static int enic_dev_open(struct enic *enic) 1864 { 1865 int err; 1866 1867 err = enic_dev_wait(enic->vdev, vnic_dev_open, 1868 vnic_dev_open_done, 0); 1869 if (err) 1870 dev_err(enic_get_dev(enic), "vNIC device open failed, err %d\n", 1871 err); 1872 1873 return err; 1874 } 1875 1876 static int enic_dev_hang_reset(struct enic *enic) 1877 { 1878 int err; 1879 1880 err = enic_dev_wait(enic->vdev, vnic_dev_hang_reset, 1881 vnic_dev_hang_reset_done, 0); 1882 if (err) 1883 netdev_err(enic->netdev, "vNIC hang reset failed, err %d\n", 1884 err); 1885 1886 return err; 1887 } 1888 1889 static int enic_set_rsskey(struct enic *enic) 1890 { 1891 dma_addr_t rss_key_buf_pa; 1892 union vnic_rss_key *rss_key_buf_va = NULL; 1893 union vnic_rss_key rss_key = { 1894 .key[0].b = {85, 67, 83, 97, 119, 101, 115, 111, 109, 101}, 1895 .key[1].b = {80, 65, 76, 79, 117, 110, 105, 113, 117, 101}, 1896 .key[2].b = {76, 73, 78, 85, 88, 114, 111, 99, 107, 115}, 1897 .key[3].b = {69, 78, 73, 67, 105, 115, 99, 111, 111, 108}, 1898 }; 1899 int err; 1900 1901 rss_key_buf_va = pci_alloc_consistent(enic->pdev, 1902 sizeof(union vnic_rss_key), &rss_key_buf_pa); 1903 if (!rss_key_buf_va) 1904 return -ENOMEM; 1905 1906 memcpy(rss_key_buf_va, &rss_key, sizeof(union vnic_rss_key)); 1907 1908 spin_lock_bh(&enic->devcmd_lock); 1909 err = enic_set_rss_key(enic, 1910 rss_key_buf_pa, 1911 sizeof(union vnic_rss_key)); 1912 spin_unlock_bh(&enic->devcmd_lock); 1913 1914 pci_free_consistent(enic->pdev, sizeof(union vnic_rss_key), 1915 rss_key_buf_va, rss_key_buf_pa); 1916 1917 return err; 1918 } 1919 1920 static int enic_set_rsscpu(struct enic *enic, u8 rss_hash_bits) 1921 { 1922 dma_addr_t rss_cpu_buf_pa; 1923 union vnic_rss_cpu *rss_cpu_buf_va = NULL; 1924 unsigned int i; 1925 int err; 1926 1927 rss_cpu_buf_va = pci_alloc_consistent(enic->pdev, 1928 sizeof(union vnic_rss_cpu), &rss_cpu_buf_pa); 1929 if (!rss_cpu_buf_va) 1930 return -ENOMEM; 1931 1932 for (i = 0; i < (1 << rss_hash_bits); i++) 1933 (*rss_cpu_buf_va).cpu[i/4].b[i%4] = i % enic->rq_count; 1934 1935 spin_lock_bh(&enic->devcmd_lock); 1936 err = enic_set_rss_cpu(enic, 1937 rss_cpu_buf_pa, 1938 sizeof(union vnic_rss_cpu)); 1939 spin_unlock_bh(&enic->devcmd_lock); 1940 1941 pci_free_consistent(enic->pdev, sizeof(union vnic_rss_cpu), 1942 rss_cpu_buf_va, rss_cpu_buf_pa); 1943 1944 return err; 1945 } 1946 1947 static int enic_set_niccfg(struct enic *enic, u8 rss_default_cpu, 1948 u8 rss_hash_type, u8 rss_hash_bits, u8 rss_base_cpu, u8 rss_enable) 1949 { 1950 const u8 tso_ipid_split_en = 0; 1951 const u8 ig_vlan_strip_en = 1; 1952 int err; 1953 1954 /* Enable VLAN tag stripping. 1955 */ 1956 1957 spin_lock_bh(&enic->devcmd_lock); 1958 err = enic_set_nic_cfg(enic, 1959 rss_default_cpu, rss_hash_type, 1960 rss_hash_bits, rss_base_cpu, 1961 rss_enable, tso_ipid_split_en, 1962 ig_vlan_strip_en); 1963 spin_unlock_bh(&enic->devcmd_lock); 1964 1965 return err; 1966 } 1967 1968 static int enic_set_rss_nic_cfg(struct enic *enic) 1969 { 1970 struct device *dev = enic_get_dev(enic); 1971 const u8 rss_default_cpu = 0; 1972 const u8 rss_hash_type = NIC_CFG_RSS_HASH_TYPE_IPV4 | 1973 NIC_CFG_RSS_HASH_TYPE_TCP_IPV4 | 1974 NIC_CFG_RSS_HASH_TYPE_IPV6 | 1975 NIC_CFG_RSS_HASH_TYPE_TCP_IPV6; 1976 const u8 rss_hash_bits = 7; 1977 const u8 rss_base_cpu = 0; 1978 u8 rss_enable = ENIC_SETTING(enic, RSS) && (enic->rq_count > 1); 1979 1980 if (rss_enable) { 1981 if (!enic_set_rsskey(enic)) { 1982 if (enic_set_rsscpu(enic, rss_hash_bits)) { 1983 rss_enable = 0; 1984 dev_warn(dev, "RSS disabled, " 1985 "Failed to set RSS cpu indirection table."); 1986 } 1987 } else { 1988 rss_enable = 0; 1989 dev_warn(dev, "RSS disabled, Failed to set RSS key.\n"); 1990 } 1991 } 1992 1993 return enic_set_niccfg(enic, rss_default_cpu, rss_hash_type, 1994 rss_hash_bits, rss_base_cpu, rss_enable); 1995 } 1996 1997 static void enic_reset(struct work_struct *work) 1998 { 1999 struct enic *enic = container_of(work, struct enic, reset); 2000 2001 if (!netif_running(enic->netdev)) 2002 return; 2003 2004 rtnl_lock(); 2005 2006 spin_lock(&enic->enic_api_lock); 2007 enic_dev_hang_notify(enic); 2008 enic_stop(enic->netdev); 2009 enic_dev_hang_reset(enic); 2010 enic_reset_addr_lists(enic); 2011 enic_init_vnic_resources(enic); 2012 enic_set_rss_nic_cfg(enic); 2013 enic_dev_set_ig_vlan_rewrite_mode(enic); 2014 enic_open(enic->netdev); 2015 spin_unlock(&enic->enic_api_lock); 2016 call_netdevice_notifiers(NETDEV_REBOOT, enic->netdev); 2017 2018 rtnl_unlock(); 2019 } 2020 2021 static int enic_set_intr_mode(struct enic *enic) 2022 { 2023 unsigned int n = min_t(unsigned int, enic->rq_count, ENIC_RQ_MAX); 2024 unsigned int m = min_t(unsigned int, enic->wq_count, ENIC_WQ_MAX); 2025 unsigned int i; 2026 2027 /* Set interrupt mode (INTx, MSI, MSI-X) depending 2028 * on system capabilities. 2029 * 2030 * Try MSI-X first 2031 * 2032 * We need n RQs, m WQs, n+m CQs, and n+m+2 INTRs 2033 * (the second to last INTR is used for WQ/RQ errors) 2034 * (the last INTR is used for notifications) 2035 */ 2036 2037 BUG_ON(ARRAY_SIZE(enic->msix_entry) < n + m + 2); 2038 for (i = 0; i < n + m + 2; i++) 2039 enic->msix_entry[i].entry = i; 2040 2041 /* Use multiple RQs if RSS is enabled 2042 */ 2043 2044 if (ENIC_SETTING(enic, RSS) && 2045 enic->config.intr_mode < 1 && 2046 enic->rq_count >= n && 2047 enic->wq_count >= m && 2048 enic->cq_count >= n + m && 2049 enic->intr_count >= n + m + 2) { 2050 2051 if (pci_enable_msix_range(enic->pdev, enic->msix_entry, 2052 n + m + 2, n + m + 2) > 0) { 2053 2054 enic->rq_count = n; 2055 enic->wq_count = m; 2056 enic->cq_count = n + m; 2057 enic->intr_count = n + m + 2; 2058 2059 vnic_dev_set_intr_mode(enic->vdev, 2060 VNIC_DEV_INTR_MODE_MSIX); 2061 2062 return 0; 2063 } 2064 } 2065 2066 if (enic->config.intr_mode < 1 && 2067 enic->rq_count >= 1 && 2068 enic->wq_count >= m && 2069 enic->cq_count >= 1 + m && 2070 enic->intr_count >= 1 + m + 2) { 2071 if (pci_enable_msix_range(enic->pdev, enic->msix_entry, 2072 1 + m + 2, 1 + m + 2) > 0) { 2073 2074 enic->rq_count = 1; 2075 enic->wq_count = m; 2076 enic->cq_count = 1 + m; 2077 enic->intr_count = 1 + m + 2; 2078 2079 vnic_dev_set_intr_mode(enic->vdev, 2080 VNIC_DEV_INTR_MODE_MSIX); 2081 2082 return 0; 2083 } 2084 } 2085 2086 /* Next try MSI 2087 * 2088 * We need 1 RQ, 1 WQ, 2 CQs, and 1 INTR 2089 */ 2090 2091 if (enic->config.intr_mode < 2 && 2092 enic->rq_count >= 1 && 2093 enic->wq_count >= 1 && 2094 enic->cq_count >= 2 && 2095 enic->intr_count >= 1 && 2096 !pci_enable_msi(enic->pdev)) { 2097 2098 enic->rq_count = 1; 2099 enic->wq_count = 1; 2100 enic->cq_count = 2; 2101 enic->intr_count = 1; 2102 2103 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_MSI); 2104 2105 return 0; 2106 } 2107 2108 /* Next try INTx 2109 * 2110 * We need 1 RQ, 1 WQ, 2 CQs, and 3 INTRs 2111 * (the first INTR is used for WQ/RQ) 2112 * (the second INTR is used for WQ/RQ errors) 2113 * (the last INTR is used for notifications) 2114 */ 2115 2116 if (enic->config.intr_mode < 3 && 2117 enic->rq_count >= 1 && 2118 enic->wq_count >= 1 && 2119 enic->cq_count >= 2 && 2120 enic->intr_count >= 3) { 2121 2122 enic->rq_count = 1; 2123 enic->wq_count = 1; 2124 enic->cq_count = 2; 2125 enic->intr_count = 3; 2126 2127 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_INTX); 2128 2129 return 0; 2130 } 2131 2132 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_UNKNOWN); 2133 2134 return -EINVAL; 2135 } 2136 2137 static void enic_clear_intr_mode(struct enic *enic) 2138 { 2139 switch (vnic_dev_get_intr_mode(enic->vdev)) { 2140 case VNIC_DEV_INTR_MODE_MSIX: 2141 pci_disable_msix(enic->pdev); 2142 break; 2143 case VNIC_DEV_INTR_MODE_MSI: 2144 pci_disable_msi(enic->pdev); 2145 break; 2146 default: 2147 break; 2148 } 2149 2150 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_UNKNOWN); 2151 } 2152 2153 static const struct net_device_ops enic_netdev_dynamic_ops = { 2154 .ndo_open = enic_open, 2155 .ndo_stop = enic_stop, 2156 .ndo_start_xmit = enic_hard_start_xmit, 2157 .ndo_get_stats64 = enic_get_stats, 2158 .ndo_validate_addr = eth_validate_addr, 2159 .ndo_set_rx_mode = enic_set_rx_mode, 2160 .ndo_set_mac_address = enic_set_mac_address_dynamic, 2161 .ndo_change_mtu = enic_change_mtu, 2162 .ndo_vlan_rx_add_vid = enic_vlan_rx_add_vid, 2163 .ndo_vlan_rx_kill_vid = enic_vlan_rx_kill_vid, 2164 .ndo_tx_timeout = enic_tx_timeout, 2165 .ndo_set_vf_port = enic_set_vf_port, 2166 .ndo_get_vf_port = enic_get_vf_port, 2167 .ndo_set_vf_mac = enic_set_vf_mac, 2168 #ifdef CONFIG_NET_POLL_CONTROLLER 2169 .ndo_poll_controller = enic_poll_controller, 2170 #endif 2171 #ifdef CONFIG_RFS_ACCEL 2172 .ndo_rx_flow_steer = enic_rx_flow_steer, 2173 #endif 2174 #ifdef CONFIG_NET_RX_BUSY_POLL 2175 .ndo_busy_poll = enic_busy_poll, 2176 #endif 2177 }; 2178 2179 static const struct net_device_ops enic_netdev_ops = { 2180 .ndo_open = enic_open, 2181 .ndo_stop = enic_stop, 2182 .ndo_start_xmit = enic_hard_start_xmit, 2183 .ndo_get_stats64 = enic_get_stats, 2184 .ndo_validate_addr = eth_validate_addr, 2185 .ndo_set_mac_address = enic_set_mac_address, 2186 .ndo_set_rx_mode = enic_set_rx_mode, 2187 .ndo_change_mtu = enic_change_mtu, 2188 .ndo_vlan_rx_add_vid = enic_vlan_rx_add_vid, 2189 .ndo_vlan_rx_kill_vid = enic_vlan_rx_kill_vid, 2190 .ndo_tx_timeout = enic_tx_timeout, 2191 .ndo_set_vf_port = enic_set_vf_port, 2192 .ndo_get_vf_port = enic_get_vf_port, 2193 .ndo_set_vf_mac = enic_set_vf_mac, 2194 #ifdef CONFIG_NET_POLL_CONTROLLER 2195 .ndo_poll_controller = enic_poll_controller, 2196 #endif 2197 #ifdef CONFIG_RFS_ACCEL 2198 .ndo_rx_flow_steer = enic_rx_flow_steer, 2199 #endif 2200 #ifdef CONFIG_NET_RX_BUSY_POLL 2201 .ndo_busy_poll = enic_busy_poll, 2202 #endif 2203 }; 2204 2205 static void enic_dev_deinit(struct enic *enic) 2206 { 2207 unsigned int i; 2208 2209 for (i = 0; i < enic->rq_count; i++) { 2210 napi_hash_del(&enic->napi[i]); 2211 netif_napi_del(&enic->napi[i]); 2212 } 2213 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX) 2214 for (i = 0; i < enic->wq_count; i++) 2215 netif_napi_del(&enic->napi[enic_cq_wq(enic, i)]); 2216 2217 enic_free_vnic_resources(enic); 2218 enic_clear_intr_mode(enic); 2219 } 2220 2221 static int enic_dev_init(struct enic *enic) 2222 { 2223 struct device *dev = enic_get_dev(enic); 2224 struct net_device *netdev = enic->netdev; 2225 unsigned int i; 2226 int err; 2227 2228 /* Get interrupt coalesce timer info */ 2229 err = enic_dev_intr_coal_timer_info(enic); 2230 if (err) { 2231 dev_warn(dev, "Using default conversion factor for " 2232 "interrupt coalesce timer\n"); 2233 vnic_dev_intr_coal_timer_info_default(enic->vdev); 2234 } 2235 2236 /* Get vNIC configuration 2237 */ 2238 2239 err = enic_get_vnic_config(enic); 2240 if (err) { 2241 dev_err(dev, "Get vNIC configuration failed, aborting\n"); 2242 return err; 2243 } 2244 2245 /* Get available resource counts 2246 */ 2247 2248 enic_get_res_counts(enic); 2249 2250 /* Set interrupt mode based on resource counts and system 2251 * capabilities 2252 */ 2253 2254 err = enic_set_intr_mode(enic); 2255 if (err) { 2256 dev_err(dev, "Failed to set intr mode based on resource " 2257 "counts and system capabilities, aborting\n"); 2258 return err; 2259 } 2260 2261 /* Allocate and configure vNIC resources 2262 */ 2263 2264 err = enic_alloc_vnic_resources(enic); 2265 if (err) { 2266 dev_err(dev, "Failed to alloc vNIC resources, aborting\n"); 2267 goto err_out_free_vnic_resources; 2268 } 2269 2270 enic_init_vnic_resources(enic); 2271 2272 err = enic_set_rss_nic_cfg(enic); 2273 if (err) { 2274 dev_err(dev, "Failed to config nic, aborting\n"); 2275 goto err_out_free_vnic_resources; 2276 } 2277 2278 switch (vnic_dev_get_intr_mode(enic->vdev)) { 2279 default: 2280 netif_napi_add(netdev, &enic->napi[0], enic_poll, 64); 2281 napi_hash_add(&enic->napi[0]); 2282 break; 2283 case VNIC_DEV_INTR_MODE_MSIX: 2284 for (i = 0; i < enic->rq_count; i++) { 2285 netif_napi_add(netdev, &enic->napi[i], 2286 enic_poll_msix_rq, NAPI_POLL_WEIGHT); 2287 napi_hash_add(&enic->napi[i]); 2288 } 2289 for (i = 0; i < enic->wq_count; i++) 2290 netif_napi_add(netdev, &enic->napi[enic_cq_wq(enic, i)], 2291 enic_poll_msix_wq, NAPI_POLL_WEIGHT); 2292 break; 2293 } 2294 2295 return 0; 2296 2297 err_out_free_vnic_resources: 2298 enic_clear_intr_mode(enic); 2299 enic_free_vnic_resources(enic); 2300 2301 return err; 2302 } 2303 2304 static void enic_iounmap(struct enic *enic) 2305 { 2306 unsigned int i; 2307 2308 for (i = 0; i < ARRAY_SIZE(enic->bar); i++) 2309 if (enic->bar[i].vaddr) 2310 iounmap(enic->bar[i].vaddr); 2311 } 2312 2313 static int enic_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2314 { 2315 struct device *dev = &pdev->dev; 2316 struct net_device *netdev; 2317 struct enic *enic; 2318 int using_dac = 0; 2319 unsigned int i; 2320 int err; 2321 #ifdef CONFIG_PCI_IOV 2322 int pos = 0; 2323 #endif 2324 int num_pps = 1; 2325 2326 /* Allocate net device structure and initialize. Private 2327 * instance data is initialized to zero. 2328 */ 2329 2330 netdev = alloc_etherdev_mqs(sizeof(struct enic), 2331 ENIC_RQ_MAX, ENIC_WQ_MAX); 2332 if (!netdev) 2333 return -ENOMEM; 2334 2335 pci_set_drvdata(pdev, netdev); 2336 2337 SET_NETDEV_DEV(netdev, &pdev->dev); 2338 2339 enic = netdev_priv(netdev); 2340 enic->netdev = netdev; 2341 enic->pdev = pdev; 2342 2343 /* Setup PCI resources 2344 */ 2345 2346 err = pci_enable_device_mem(pdev); 2347 if (err) { 2348 dev_err(dev, "Cannot enable PCI device, aborting\n"); 2349 goto err_out_free_netdev; 2350 } 2351 2352 err = pci_request_regions(pdev, DRV_NAME); 2353 if (err) { 2354 dev_err(dev, "Cannot request PCI regions, aborting\n"); 2355 goto err_out_disable_device; 2356 } 2357 2358 pci_set_master(pdev); 2359 2360 /* Query PCI controller on system for DMA addressing 2361 * limitation for the device. Try 64-bit first, and 2362 * fail to 32-bit. 2363 */ 2364 2365 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 2366 if (err) { 2367 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 2368 if (err) { 2369 dev_err(dev, "No usable DMA configuration, aborting\n"); 2370 goto err_out_release_regions; 2371 } 2372 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 2373 if (err) { 2374 dev_err(dev, "Unable to obtain %u-bit DMA " 2375 "for consistent allocations, aborting\n", 32); 2376 goto err_out_release_regions; 2377 } 2378 } else { 2379 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 2380 if (err) { 2381 dev_err(dev, "Unable to obtain %u-bit DMA " 2382 "for consistent allocations, aborting\n", 64); 2383 goto err_out_release_regions; 2384 } 2385 using_dac = 1; 2386 } 2387 2388 /* Map vNIC resources from BAR0-5 2389 */ 2390 2391 for (i = 0; i < ARRAY_SIZE(enic->bar); i++) { 2392 if (!(pci_resource_flags(pdev, i) & IORESOURCE_MEM)) 2393 continue; 2394 enic->bar[i].len = pci_resource_len(pdev, i); 2395 enic->bar[i].vaddr = pci_iomap(pdev, i, enic->bar[i].len); 2396 if (!enic->bar[i].vaddr) { 2397 dev_err(dev, "Cannot memory-map BAR %d, aborting\n", i); 2398 err = -ENODEV; 2399 goto err_out_iounmap; 2400 } 2401 enic->bar[i].bus_addr = pci_resource_start(pdev, i); 2402 } 2403 2404 /* Register vNIC device 2405 */ 2406 2407 enic->vdev = vnic_dev_register(NULL, enic, pdev, enic->bar, 2408 ARRAY_SIZE(enic->bar)); 2409 if (!enic->vdev) { 2410 dev_err(dev, "vNIC registration failed, aborting\n"); 2411 err = -ENODEV; 2412 goto err_out_iounmap; 2413 } 2414 2415 #ifdef CONFIG_PCI_IOV 2416 /* Get number of subvnics */ 2417 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV); 2418 if (pos) { 2419 pci_read_config_word(pdev, pos + PCI_SRIOV_TOTAL_VF, 2420 &enic->num_vfs); 2421 if (enic->num_vfs) { 2422 err = pci_enable_sriov(pdev, enic->num_vfs); 2423 if (err) { 2424 dev_err(dev, "SRIOV enable failed, aborting." 2425 " pci_enable_sriov() returned %d\n", 2426 err); 2427 goto err_out_vnic_unregister; 2428 } 2429 enic->priv_flags |= ENIC_SRIOV_ENABLED; 2430 num_pps = enic->num_vfs; 2431 } 2432 } 2433 #endif 2434 2435 /* Allocate structure for port profiles */ 2436 enic->pp = kcalloc(num_pps, sizeof(*enic->pp), GFP_KERNEL); 2437 if (!enic->pp) { 2438 err = -ENOMEM; 2439 goto err_out_disable_sriov_pp; 2440 } 2441 2442 /* Issue device open to get device in known state 2443 */ 2444 2445 err = enic_dev_open(enic); 2446 if (err) { 2447 dev_err(dev, "vNIC dev open failed, aborting\n"); 2448 goto err_out_disable_sriov; 2449 } 2450 2451 /* Setup devcmd lock 2452 */ 2453 2454 spin_lock_init(&enic->devcmd_lock); 2455 spin_lock_init(&enic->enic_api_lock); 2456 2457 /* 2458 * Set ingress vlan rewrite mode before vnic initialization 2459 */ 2460 2461 err = enic_dev_set_ig_vlan_rewrite_mode(enic); 2462 if (err) { 2463 dev_err(dev, 2464 "Failed to set ingress vlan rewrite mode, aborting.\n"); 2465 goto err_out_dev_close; 2466 } 2467 2468 /* Issue device init to initialize the vnic-to-switch link. 2469 * We'll start with carrier off and wait for link UP 2470 * notification later to turn on carrier. We don't need 2471 * to wait here for the vnic-to-switch link initialization 2472 * to complete; link UP notification is the indication that 2473 * the process is complete. 2474 */ 2475 2476 netif_carrier_off(netdev); 2477 2478 /* Do not call dev_init for a dynamic vnic. 2479 * For a dynamic vnic, init_prov_info will be 2480 * called later by an upper layer. 2481 */ 2482 2483 if (!enic_is_dynamic(enic)) { 2484 err = vnic_dev_init(enic->vdev, 0); 2485 if (err) { 2486 dev_err(dev, "vNIC dev init failed, aborting\n"); 2487 goto err_out_dev_close; 2488 } 2489 } 2490 2491 err = enic_dev_init(enic); 2492 if (err) { 2493 dev_err(dev, "Device initialization failed, aborting\n"); 2494 goto err_out_dev_close; 2495 } 2496 2497 netif_set_real_num_tx_queues(netdev, enic->wq_count); 2498 netif_set_real_num_rx_queues(netdev, enic->rq_count); 2499 2500 /* Setup notification timer, HW reset task, and wq locks 2501 */ 2502 2503 init_timer(&enic->notify_timer); 2504 enic->notify_timer.function = enic_notify_timer; 2505 enic->notify_timer.data = (unsigned long)enic; 2506 2507 enic_set_rx_coal_setting(enic); 2508 INIT_WORK(&enic->reset, enic_reset); 2509 INIT_WORK(&enic->change_mtu_work, enic_change_mtu_work); 2510 2511 for (i = 0; i < enic->wq_count; i++) 2512 spin_lock_init(&enic->wq_lock[i]); 2513 2514 /* Register net device 2515 */ 2516 2517 enic->port_mtu = enic->config.mtu; 2518 (void)enic_change_mtu(netdev, enic->port_mtu); 2519 2520 err = enic_set_mac_addr(netdev, enic->mac_addr); 2521 if (err) { 2522 dev_err(dev, "Invalid MAC address, aborting\n"); 2523 goto err_out_dev_deinit; 2524 } 2525 2526 enic->tx_coalesce_usecs = enic->config.intr_timer_usec; 2527 /* rx coalesce time already got initialized. This gets used 2528 * if adaptive coal is turned off 2529 */ 2530 enic->rx_coalesce_usecs = enic->tx_coalesce_usecs; 2531 2532 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) 2533 netdev->netdev_ops = &enic_netdev_dynamic_ops; 2534 else 2535 netdev->netdev_ops = &enic_netdev_ops; 2536 2537 netdev->watchdog_timeo = 2 * HZ; 2538 enic_set_ethtool_ops(netdev); 2539 2540 netdev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 2541 if (ENIC_SETTING(enic, LOOP)) { 2542 netdev->features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2543 enic->loop_enable = 1; 2544 enic->loop_tag = enic->config.loop_tag; 2545 dev_info(dev, "loopback tag=0x%04x\n", enic->loop_tag); 2546 } 2547 if (ENIC_SETTING(enic, TXCSUM)) 2548 netdev->hw_features |= NETIF_F_SG | NETIF_F_HW_CSUM; 2549 if (ENIC_SETTING(enic, TSO)) 2550 netdev->hw_features |= NETIF_F_TSO | 2551 NETIF_F_TSO6 | NETIF_F_TSO_ECN; 2552 if (ENIC_SETTING(enic, RSS)) 2553 netdev->hw_features |= NETIF_F_RXHASH; 2554 if (ENIC_SETTING(enic, RXCSUM)) 2555 netdev->hw_features |= NETIF_F_RXCSUM; 2556 2557 netdev->features |= netdev->hw_features; 2558 2559 #ifdef CONFIG_RFS_ACCEL 2560 netdev->hw_features |= NETIF_F_NTUPLE; 2561 #endif 2562 2563 if (using_dac) 2564 netdev->features |= NETIF_F_HIGHDMA; 2565 2566 netdev->priv_flags |= IFF_UNICAST_FLT; 2567 2568 err = register_netdev(netdev); 2569 if (err) { 2570 dev_err(dev, "Cannot register net device, aborting\n"); 2571 goto err_out_dev_deinit; 2572 } 2573 enic->rx_copybreak = RX_COPYBREAK_DEFAULT; 2574 2575 return 0; 2576 2577 err_out_dev_deinit: 2578 enic_dev_deinit(enic); 2579 err_out_dev_close: 2580 vnic_dev_close(enic->vdev); 2581 err_out_disable_sriov: 2582 kfree(enic->pp); 2583 err_out_disable_sriov_pp: 2584 #ifdef CONFIG_PCI_IOV 2585 if (enic_sriov_enabled(enic)) { 2586 pci_disable_sriov(pdev); 2587 enic->priv_flags &= ~ENIC_SRIOV_ENABLED; 2588 } 2589 err_out_vnic_unregister: 2590 #endif 2591 vnic_dev_unregister(enic->vdev); 2592 err_out_iounmap: 2593 enic_iounmap(enic); 2594 err_out_release_regions: 2595 pci_release_regions(pdev); 2596 err_out_disable_device: 2597 pci_disable_device(pdev); 2598 err_out_free_netdev: 2599 free_netdev(netdev); 2600 2601 return err; 2602 } 2603 2604 static void enic_remove(struct pci_dev *pdev) 2605 { 2606 struct net_device *netdev = pci_get_drvdata(pdev); 2607 2608 if (netdev) { 2609 struct enic *enic = netdev_priv(netdev); 2610 2611 cancel_work_sync(&enic->reset); 2612 cancel_work_sync(&enic->change_mtu_work); 2613 unregister_netdev(netdev); 2614 enic_dev_deinit(enic); 2615 vnic_dev_close(enic->vdev); 2616 #ifdef CONFIG_PCI_IOV 2617 if (enic_sriov_enabled(enic)) { 2618 pci_disable_sriov(pdev); 2619 enic->priv_flags &= ~ENIC_SRIOV_ENABLED; 2620 } 2621 #endif 2622 kfree(enic->pp); 2623 vnic_dev_unregister(enic->vdev); 2624 enic_iounmap(enic); 2625 pci_release_regions(pdev); 2626 pci_disable_device(pdev); 2627 free_netdev(netdev); 2628 } 2629 } 2630 2631 static struct pci_driver enic_driver = { 2632 .name = DRV_NAME, 2633 .id_table = enic_id_table, 2634 .probe = enic_probe, 2635 .remove = enic_remove, 2636 }; 2637 2638 static int __init enic_init_module(void) 2639 { 2640 pr_info("%s, ver %s\n", DRV_DESCRIPTION, DRV_VERSION); 2641 2642 return pci_register_driver(&enic_driver); 2643 } 2644 2645 static void __exit enic_cleanup_module(void) 2646 { 2647 pci_unregister_driver(&enic_driver); 2648 } 2649 2650 module_init(enic_init_module); 2651 module_exit(enic_cleanup_module); 2652