1 /* 2 * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved. 3 * Copyright 2007 Nuova Systems, Inc. All rights reserved. 4 * 5 * This program is free software; you may redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; version 2 of the License. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 10 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 11 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 12 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 13 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 14 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 15 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 16 * SOFTWARE. 17 * 18 */ 19 20 #include <linux/module.h> 21 #include <linux/kernel.h> 22 #include <linux/string.h> 23 #include <linux/errno.h> 24 #include <linux/types.h> 25 #include <linux/init.h> 26 #include <linux/interrupt.h> 27 #include <linux/workqueue.h> 28 #include <linux/pci.h> 29 #include <linux/netdevice.h> 30 #include <linux/etherdevice.h> 31 #include <linux/if.h> 32 #include <linux/if_ether.h> 33 #include <linux/if_vlan.h> 34 #include <linux/in.h> 35 #include <linux/ip.h> 36 #include <linux/ipv6.h> 37 #include <linux/tcp.h> 38 #include <linux/rtnetlink.h> 39 #include <linux/prefetch.h> 40 #include <net/ip6_checksum.h> 41 #include <linux/ktime.h> 42 #ifdef CONFIG_RFS_ACCEL 43 #include <linux/cpu_rmap.h> 44 #endif 45 #ifdef CONFIG_NET_RX_BUSY_POLL 46 #include <net/busy_poll.h> 47 #endif 48 49 #include "cq_enet_desc.h" 50 #include "vnic_dev.h" 51 #include "vnic_intr.h" 52 #include "vnic_stats.h" 53 #include "vnic_vic.h" 54 #include "enic_res.h" 55 #include "enic.h" 56 #include "enic_dev.h" 57 #include "enic_pp.h" 58 #include "enic_clsf.h" 59 60 #define ENIC_NOTIFY_TIMER_PERIOD (2 * HZ) 61 #define WQ_ENET_MAX_DESC_LEN (1 << WQ_ENET_LEN_BITS) 62 #define MAX_TSO (1 << 16) 63 #define ENIC_DESC_MAX_SPLITS (MAX_TSO / WQ_ENET_MAX_DESC_LEN + 1) 64 65 #define PCI_DEVICE_ID_CISCO_VIC_ENET 0x0043 /* ethernet vnic */ 66 #define PCI_DEVICE_ID_CISCO_VIC_ENET_DYN 0x0044 /* enet dynamic vnic */ 67 #define PCI_DEVICE_ID_CISCO_VIC_ENET_VF 0x0071 /* enet SRIOV VF */ 68 69 #define RX_COPYBREAK_DEFAULT 256 70 71 /* Supported devices */ 72 static const struct pci_device_id enic_id_table[] = { 73 { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET) }, 74 { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET_DYN) }, 75 { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET_VF) }, 76 { 0, } /* end of table */ 77 }; 78 79 MODULE_DESCRIPTION(DRV_DESCRIPTION); 80 MODULE_AUTHOR("Scott Feldman <scofeldm@cisco.com>"); 81 MODULE_LICENSE("GPL"); 82 MODULE_VERSION(DRV_VERSION); 83 MODULE_DEVICE_TABLE(pci, enic_id_table); 84 85 #define ENIC_LARGE_PKT_THRESHOLD 1000 86 #define ENIC_MAX_COALESCE_TIMERS 10 87 /* Interrupt moderation table, which will be used to decide the 88 * coalescing timer values 89 * {rx_rate in Mbps, mapping percentage of the range} 90 */ 91 struct enic_intr_mod_table mod_table[ENIC_MAX_COALESCE_TIMERS + 1] = { 92 {4000, 0}, 93 {4400, 10}, 94 {5060, 20}, 95 {5230, 30}, 96 {5540, 40}, 97 {5820, 50}, 98 {6120, 60}, 99 {6435, 70}, 100 {6745, 80}, 101 {7000, 90}, 102 {0xFFFFFFFF, 100} 103 }; 104 105 /* This table helps the driver to pick different ranges for rx coalescing 106 * timer depending on the link speed. 107 */ 108 struct enic_intr_mod_range mod_range[ENIC_MAX_LINK_SPEEDS] = { 109 {0, 0}, /* 0 - 4 Gbps */ 110 {0, 3}, /* 4 - 10 Gbps */ 111 {3, 6}, /* 10 - 40 Gbps */ 112 }; 113 114 int enic_is_dynamic(struct enic *enic) 115 { 116 return enic->pdev->device == PCI_DEVICE_ID_CISCO_VIC_ENET_DYN; 117 } 118 119 int enic_sriov_enabled(struct enic *enic) 120 { 121 return (enic->priv_flags & ENIC_SRIOV_ENABLED) ? 1 : 0; 122 } 123 124 static int enic_is_sriov_vf(struct enic *enic) 125 { 126 return enic->pdev->device == PCI_DEVICE_ID_CISCO_VIC_ENET_VF; 127 } 128 129 int enic_is_valid_vf(struct enic *enic, int vf) 130 { 131 #ifdef CONFIG_PCI_IOV 132 return vf >= 0 && vf < enic->num_vfs; 133 #else 134 return 0; 135 #endif 136 } 137 138 static void enic_free_wq_buf(struct vnic_wq *wq, struct vnic_wq_buf *buf) 139 { 140 struct enic *enic = vnic_dev_priv(wq->vdev); 141 142 if (buf->sop) 143 pci_unmap_single(enic->pdev, buf->dma_addr, 144 buf->len, PCI_DMA_TODEVICE); 145 else 146 pci_unmap_page(enic->pdev, buf->dma_addr, 147 buf->len, PCI_DMA_TODEVICE); 148 149 if (buf->os_buf) 150 dev_kfree_skb_any(buf->os_buf); 151 } 152 153 static void enic_wq_free_buf(struct vnic_wq *wq, 154 struct cq_desc *cq_desc, struct vnic_wq_buf *buf, void *opaque) 155 { 156 enic_free_wq_buf(wq, buf); 157 } 158 159 static int enic_wq_service(struct vnic_dev *vdev, struct cq_desc *cq_desc, 160 u8 type, u16 q_number, u16 completed_index, void *opaque) 161 { 162 struct enic *enic = vnic_dev_priv(vdev); 163 164 spin_lock(&enic->wq_lock[q_number]); 165 166 vnic_wq_service(&enic->wq[q_number], cq_desc, 167 completed_index, enic_wq_free_buf, 168 opaque); 169 170 if (netif_tx_queue_stopped(netdev_get_tx_queue(enic->netdev, q_number)) && 171 vnic_wq_desc_avail(&enic->wq[q_number]) >= 172 (MAX_SKB_FRAGS + ENIC_DESC_MAX_SPLITS)) 173 netif_wake_subqueue(enic->netdev, q_number); 174 175 spin_unlock(&enic->wq_lock[q_number]); 176 177 return 0; 178 } 179 180 static void enic_log_q_error(struct enic *enic) 181 { 182 unsigned int i; 183 u32 error_status; 184 185 for (i = 0; i < enic->wq_count; i++) { 186 error_status = vnic_wq_error_status(&enic->wq[i]); 187 if (error_status) 188 netdev_err(enic->netdev, "WQ[%d] error_status %d\n", 189 i, error_status); 190 } 191 192 for (i = 0; i < enic->rq_count; i++) { 193 error_status = vnic_rq_error_status(&enic->rq[i]); 194 if (error_status) 195 netdev_err(enic->netdev, "RQ[%d] error_status %d\n", 196 i, error_status); 197 } 198 } 199 200 static void enic_msglvl_check(struct enic *enic) 201 { 202 u32 msg_enable = vnic_dev_msg_lvl(enic->vdev); 203 204 if (msg_enable != enic->msg_enable) { 205 netdev_info(enic->netdev, "msg lvl changed from 0x%x to 0x%x\n", 206 enic->msg_enable, msg_enable); 207 enic->msg_enable = msg_enable; 208 } 209 } 210 211 static void enic_mtu_check(struct enic *enic) 212 { 213 u32 mtu = vnic_dev_mtu(enic->vdev); 214 struct net_device *netdev = enic->netdev; 215 216 if (mtu && mtu != enic->port_mtu) { 217 enic->port_mtu = mtu; 218 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) { 219 mtu = max_t(int, ENIC_MIN_MTU, 220 min_t(int, ENIC_MAX_MTU, mtu)); 221 if (mtu != netdev->mtu) 222 schedule_work(&enic->change_mtu_work); 223 } else { 224 if (mtu < netdev->mtu) 225 netdev_warn(netdev, 226 "interface MTU (%d) set higher " 227 "than switch port MTU (%d)\n", 228 netdev->mtu, mtu); 229 } 230 } 231 } 232 233 static void enic_link_check(struct enic *enic) 234 { 235 int link_status = vnic_dev_link_status(enic->vdev); 236 int carrier_ok = netif_carrier_ok(enic->netdev); 237 238 if (link_status && !carrier_ok) { 239 netdev_info(enic->netdev, "Link UP\n"); 240 netif_carrier_on(enic->netdev); 241 } else if (!link_status && carrier_ok) { 242 netdev_info(enic->netdev, "Link DOWN\n"); 243 netif_carrier_off(enic->netdev); 244 } 245 } 246 247 static void enic_notify_check(struct enic *enic) 248 { 249 enic_msglvl_check(enic); 250 enic_mtu_check(enic); 251 enic_link_check(enic); 252 } 253 254 #define ENIC_TEST_INTR(pba, i) (pba & (1 << i)) 255 256 static irqreturn_t enic_isr_legacy(int irq, void *data) 257 { 258 struct net_device *netdev = data; 259 struct enic *enic = netdev_priv(netdev); 260 unsigned int io_intr = enic_legacy_io_intr(); 261 unsigned int err_intr = enic_legacy_err_intr(); 262 unsigned int notify_intr = enic_legacy_notify_intr(); 263 u32 pba; 264 265 vnic_intr_mask(&enic->intr[io_intr]); 266 267 pba = vnic_intr_legacy_pba(enic->legacy_pba); 268 if (!pba) { 269 vnic_intr_unmask(&enic->intr[io_intr]); 270 return IRQ_NONE; /* not our interrupt */ 271 } 272 273 if (ENIC_TEST_INTR(pba, notify_intr)) { 274 vnic_intr_return_all_credits(&enic->intr[notify_intr]); 275 enic_notify_check(enic); 276 } 277 278 if (ENIC_TEST_INTR(pba, err_intr)) { 279 vnic_intr_return_all_credits(&enic->intr[err_intr]); 280 enic_log_q_error(enic); 281 /* schedule recovery from WQ/RQ error */ 282 schedule_work(&enic->reset); 283 return IRQ_HANDLED; 284 } 285 286 if (ENIC_TEST_INTR(pba, io_intr)) { 287 if (napi_schedule_prep(&enic->napi[0])) 288 __napi_schedule(&enic->napi[0]); 289 } else { 290 vnic_intr_unmask(&enic->intr[io_intr]); 291 } 292 293 return IRQ_HANDLED; 294 } 295 296 static irqreturn_t enic_isr_msi(int irq, void *data) 297 { 298 struct enic *enic = data; 299 300 /* With MSI, there is no sharing of interrupts, so this is 301 * our interrupt and there is no need to ack it. The device 302 * is not providing per-vector masking, so the OS will not 303 * write to PCI config space to mask/unmask the interrupt. 304 * We're using mask_on_assertion for MSI, so the device 305 * automatically masks the interrupt when the interrupt is 306 * generated. Later, when exiting polling, the interrupt 307 * will be unmasked (see enic_poll). 308 * 309 * Also, the device uses the same PCIe Traffic Class (TC) 310 * for Memory Write data and MSI, so there are no ordering 311 * issues; the MSI will always arrive at the Root Complex 312 * _after_ corresponding Memory Writes (i.e. descriptor 313 * writes). 314 */ 315 316 napi_schedule(&enic->napi[0]); 317 318 return IRQ_HANDLED; 319 } 320 321 static irqreturn_t enic_isr_msix(int irq, void *data) 322 { 323 struct napi_struct *napi = data; 324 325 napi_schedule(napi); 326 327 return IRQ_HANDLED; 328 } 329 330 static irqreturn_t enic_isr_msix_err(int irq, void *data) 331 { 332 struct enic *enic = data; 333 unsigned int intr = enic_msix_err_intr(enic); 334 335 vnic_intr_return_all_credits(&enic->intr[intr]); 336 337 enic_log_q_error(enic); 338 339 /* schedule recovery from WQ/RQ error */ 340 schedule_work(&enic->reset); 341 342 return IRQ_HANDLED; 343 } 344 345 static irqreturn_t enic_isr_msix_notify(int irq, void *data) 346 { 347 struct enic *enic = data; 348 unsigned int intr = enic_msix_notify_intr(enic); 349 350 vnic_intr_return_all_credits(&enic->intr[intr]); 351 enic_notify_check(enic); 352 353 return IRQ_HANDLED; 354 } 355 356 static inline void enic_queue_wq_skb_cont(struct enic *enic, 357 struct vnic_wq *wq, struct sk_buff *skb, 358 unsigned int len_left, int loopback) 359 { 360 const skb_frag_t *frag; 361 362 /* Queue additional data fragments */ 363 for (frag = skb_shinfo(skb)->frags; len_left; frag++) { 364 len_left -= skb_frag_size(frag); 365 enic_queue_wq_desc_cont(wq, skb, 366 skb_frag_dma_map(&enic->pdev->dev, 367 frag, 0, skb_frag_size(frag), 368 DMA_TO_DEVICE), 369 skb_frag_size(frag), 370 (len_left == 0), /* EOP? */ 371 loopback); 372 } 373 } 374 375 static inline void enic_queue_wq_skb_vlan(struct enic *enic, 376 struct vnic_wq *wq, struct sk_buff *skb, 377 int vlan_tag_insert, unsigned int vlan_tag, int loopback) 378 { 379 unsigned int head_len = skb_headlen(skb); 380 unsigned int len_left = skb->len - head_len; 381 int eop = (len_left == 0); 382 383 /* Queue the main skb fragment. The fragments are no larger 384 * than max MTU(9000)+ETH_HDR_LEN(14) bytes, which is less 385 * than WQ_ENET_MAX_DESC_LEN length. So only one descriptor 386 * per fragment is queued. 387 */ 388 enic_queue_wq_desc(wq, skb, 389 pci_map_single(enic->pdev, skb->data, 390 head_len, PCI_DMA_TODEVICE), 391 head_len, 392 vlan_tag_insert, vlan_tag, 393 eop, loopback); 394 395 if (!eop) 396 enic_queue_wq_skb_cont(enic, wq, skb, len_left, loopback); 397 } 398 399 static inline void enic_queue_wq_skb_csum_l4(struct enic *enic, 400 struct vnic_wq *wq, struct sk_buff *skb, 401 int vlan_tag_insert, unsigned int vlan_tag, int loopback) 402 { 403 unsigned int head_len = skb_headlen(skb); 404 unsigned int len_left = skb->len - head_len; 405 unsigned int hdr_len = skb_checksum_start_offset(skb); 406 unsigned int csum_offset = hdr_len + skb->csum_offset; 407 int eop = (len_left == 0); 408 409 /* Queue the main skb fragment. The fragments are no larger 410 * than max MTU(9000)+ETH_HDR_LEN(14) bytes, which is less 411 * than WQ_ENET_MAX_DESC_LEN length. So only one descriptor 412 * per fragment is queued. 413 */ 414 enic_queue_wq_desc_csum_l4(wq, skb, 415 pci_map_single(enic->pdev, skb->data, 416 head_len, PCI_DMA_TODEVICE), 417 head_len, 418 csum_offset, 419 hdr_len, 420 vlan_tag_insert, vlan_tag, 421 eop, loopback); 422 423 if (!eop) 424 enic_queue_wq_skb_cont(enic, wq, skb, len_left, loopback); 425 } 426 427 static inline void enic_queue_wq_skb_tso(struct enic *enic, 428 struct vnic_wq *wq, struct sk_buff *skb, unsigned int mss, 429 int vlan_tag_insert, unsigned int vlan_tag, int loopback) 430 { 431 unsigned int frag_len_left = skb_headlen(skb); 432 unsigned int len_left = skb->len - frag_len_left; 433 unsigned int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 434 int eop = (len_left == 0); 435 unsigned int len; 436 dma_addr_t dma_addr; 437 unsigned int offset = 0; 438 skb_frag_t *frag; 439 440 /* Preload TCP csum field with IP pseudo hdr calculated 441 * with IP length set to zero. HW will later add in length 442 * to each TCP segment resulting from the TSO. 443 */ 444 445 if (skb->protocol == cpu_to_be16(ETH_P_IP)) { 446 ip_hdr(skb)->check = 0; 447 tcp_hdr(skb)->check = ~csum_tcpudp_magic(ip_hdr(skb)->saddr, 448 ip_hdr(skb)->daddr, 0, IPPROTO_TCP, 0); 449 } else if (skb->protocol == cpu_to_be16(ETH_P_IPV6)) { 450 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 451 &ipv6_hdr(skb)->daddr, 0, IPPROTO_TCP, 0); 452 } 453 454 /* Queue WQ_ENET_MAX_DESC_LEN length descriptors 455 * for the main skb fragment 456 */ 457 while (frag_len_left) { 458 len = min(frag_len_left, (unsigned int)WQ_ENET_MAX_DESC_LEN); 459 dma_addr = pci_map_single(enic->pdev, skb->data + offset, 460 len, PCI_DMA_TODEVICE); 461 enic_queue_wq_desc_tso(wq, skb, 462 dma_addr, 463 len, 464 mss, hdr_len, 465 vlan_tag_insert, vlan_tag, 466 eop && (len == frag_len_left), loopback); 467 frag_len_left -= len; 468 offset += len; 469 } 470 471 if (eop) 472 return; 473 474 /* Queue WQ_ENET_MAX_DESC_LEN length descriptors 475 * for additional data fragments 476 */ 477 for (frag = skb_shinfo(skb)->frags; len_left; frag++) { 478 len_left -= skb_frag_size(frag); 479 frag_len_left = skb_frag_size(frag); 480 offset = 0; 481 482 while (frag_len_left) { 483 len = min(frag_len_left, 484 (unsigned int)WQ_ENET_MAX_DESC_LEN); 485 dma_addr = skb_frag_dma_map(&enic->pdev->dev, frag, 486 offset, len, 487 DMA_TO_DEVICE); 488 enic_queue_wq_desc_cont(wq, skb, 489 dma_addr, 490 len, 491 (len_left == 0) && 492 (len == frag_len_left), /* EOP? */ 493 loopback); 494 frag_len_left -= len; 495 offset += len; 496 } 497 } 498 } 499 500 static inline void enic_queue_wq_skb(struct enic *enic, 501 struct vnic_wq *wq, struct sk_buff *skb) 502 { 503 unsigned int mss = skb_shinfo(skb)->gso_size; 504 unsigned int vlan_tag = 0; 505 int vlan_tag_insert = 0; 506 int loopback = 0; 507 508 if (vlan_tx_tag_present(skb)) { 509 /* VLAN tag from trunking driver */ 510 vlan_tag_insert = 1; 511 vlan_tag = vlan_tx_tag_get(skb); 512 } else if (enic->loop_enable) { 513 vlan_tag = enic->loop_tag; 514 loopback = 1; 515 } 516 517 if (mss) 518 enic_queue_wq_skb_tso(enic, wq, skb, mss, 519 vlan_tag_insert, vlan_tag, loopback); 520 else if (skb->ip_summed == CHECKSUM_PARTIAL) 521 enic_queue_wq_skb_csum_l4(enic, wq, skb, 522 vlan_tag_insert, vlan_tag, loopback); 523 else 524 enic_queue_wq_skb_vlan(enic, wq, skb, 525 vlan_tag_insert, vlan_tag, loopback); 526 } 527 528 /* netif_tx_lock held, process context with BHs disabled, or BH */ 529 static netdev_tx_t enic_hard_start_xmit(struct sk_buff *skb, 530 struct net_device *netdev) 531 { 532 struct enic *enic = netdev_priv(netdev); 533 struct vnic_wq *wq; 534 unsigned long flags; 535 unsigned int txq_map; 536 537 if (skb->len <= 0) { 538 dev_kfree_skb_any(skb); 539 return NETDEV_TX_OK; 540 } 541 542 txq_map = skb_get_queue_mapping(skb) % enic->wq_count; 543 wq = &enic->wq[txq_map]; 544 545 /* Non-TSO sends must fit within ENIC_NON_TSO_MAX_DESC descs, 546 * which is very likely. In the off chance it's going to take 547 * more than * ENIC_NON_TSO_MAX_DESC, linearize the skb. 548 */ 549 550 if (skb_shinfo(skb)->gso_size == 0 && 551 skb_shinfo(skb)->nr_frags + 1 > ENIC_NON_TSO_MAX_DESC && 552 skb_linearize(skb)) { 553 dev_kfree_skb_any(skb); 554 return NETDEV_TX_OK; 555 } 556 557 spin_lock_irqsave(&enic->wq_lock[txq_map], flags); 558 559 if (vnic_wq_desc_avail(wq) < 560 skb_shinfo(skb)->nr_frags + ENIC_DESC_MAX_SPLITS) { 561 netif_tx_stop_queue(netdev_get_tx_queue(netdev, txq_map)); 562 /* This is a hard error, log it */ 563 netdev_err(netdev, "BUG! Tx ring full when queue awake!\n"); 564 spin_unlock_irqrestore(&enic->wq_lock[txq_map], flags); 565 return NETDEV_TX_BUSY; 566 } 567 568 enic_queue_wq_skb(enic, wq, skb); 569 570 if (vnic_wq_desc_avail(wq) < MAX_SKB_FRAGS + ENIC_DESC_MAX_SPLITS) 571 netif_tx_stop_queue(netdev_get_tx_queue(netdev, txq_map)); 572 573 spin_unlock_irqrestore(&enic->wq_lock[txq_map], flags); 574 575 return NETDEV_TX_OK; 576 } 577 578 /* dev_base_lock rwlock held, nominally process context */ 579 static struct rtnl_link_stats64 *enic_get_stats(struct net_device *netdev, 580 struct rtnl_link_stats64 *net_stats) 581 { 582 struct enic *enic = netdev_priv(netdev); 583 struct vnic_stats *stats; 584 585 enic_dev_stats_dump(enic, &stats); 586 587 net_stats->tx_packets = stats->tx.tx_frames_ok; 588 net_stats->tx_bytes = stats->tx.tx_bytes_ok; 589 net_stats->tx_errors = stats->tx.tx_errors; 590 net_stats->tx_dropped = stats->tx.tx_drops; 591 592 net_stats->rx_packets = stats->rx.rx_frames_ok; 593 net_stats->rx_bytes = stats->rx.rx_bytes_ok; 594 net_stats->rx_errors = stats->rx.rx_errors; 595 net_stats->multicast = stats->rx.rx_multicast_frames_ok; 596 net_stats->rx_over_errors = enic->rq_truncated_pkts; 597 net_stats->rx_crc_errors = enic->rq_bad_fcs; 598 net_stats->rx_dropped = stats->rx.rx_no_bufs + stats->rx.rx_drop; 599 600 return net_stats; 601 } 602 603 static int enic_mc_sync(struct net_device *netdev, const u8 *mc_addr) 604 { 605 struct enic *enic = netdev_priv(netdev); 606 607 if (enic->mc_count == ENIC_MULTICAST_PERFECT_FILTERS) { 608 unsigned int mc_count = netdev_mc_count(netdev); 609 610 netdev_warn(netdev, "Registering only %d out of %d multicast addresses\n", 611 ENIC_MULTICAST_PERFECT_FILTERS, mc_count); 612 613 return -ENOSPC; 614 } 615 616 enic_dev_add_addr(enic, mc_addr); 617 enic->mc_count++; 618 619 return 0; 620 } 621 622 static int enic_mc_unsync(struct net_device *netdev, const u8 *mc_addr) 623 { 624 struct enic *enic = netdev_priv(netdev); 625 626 enic_dev_del_addr(enic, mc_addr); 627 enic->mc_count--; 628 629 return 0; 630 } 631 632 static int enic_uc_sync(struct net_device *netdev, const u8 *uc_addr) 633 { 634 struct enic *enic = netdev_priv(netdev); 635 636 if (enic->uc_count == ENIC_UNICAST_PERFECT_FILTERS) { 637 unsigned int uc_count = netdev_uc_count(netdev); 638 639 netdev_warn(netdev, "Registering only %d out of %d unicast addresses\n", 640 ENIC_UNICAST_PERFECT_FILTERS, uc_count); 641 642 return -ENOSPC; 643 } 644 645 enic_dev_add_addr(enic, uc_addr); 646 enic->uc_count++; 647 648 return 0; 649 } 650 651 static int enic_uc_unsync(struct net_device *netdev, const u8 *uc_addr) 652 { 653 struct enic *enic = netdev_priv(netdev); 654 655 enic_dev_del_addr(enic, uc_addr); 656 enic->uc_count--; 657 658 return 0; 659 } 660 661 void enic_reset_addr_lists(struct enic *enic) 662 { 663 struct net_device *netdev = enic->netdev; 664 665 __dev_uc_unsync(netdev, NULL); 666 __dev_mc_unsync(netdev, NULL); 667 668 enic->mc_count = 0; 669 enic->uc_count = 0; 670 enic->flags = 0; 671 } 672 673 static int enic_set_mac_addr(struct net_device *netdev, char *addr) 674 { 675 struct enic *enic = netdev_priv(netdev); 676 677 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) { 678 if (!is_valid_ether_addr(addr) && !is_zero_ether_addr(addr)) 679 return -EADDRNOTAVAIL; 680 } else { 681 if (!is_valid_ether_addr(addr)) 682 return -EADDRNOTAVAIL; 683 } 684 685 memcpy(netdev->dev_addr, addr, netdev->addr_len); 686 687 return 0; 688 } 689 690 static int enic_set_mac_address_dynamic(struct net_device *netdev, void *p) 691 { 692 struct enic *enic = netdev_priv(netdev); 693 struct sockaddr *saddr = p; 694 char *addr = saddr->sa_data; 695 int err; 696 697 if (netif_running(enic->netdev)) { 698 err = enic_dev_del_station_addr(enic); 699 if (err) 700 return err; 701 } 702 703 err = enic_set_mac_addr(netdev, addr); 704 if (err) 705 return err; 706 707 if (netif_running(enic->netdev)) { 708 err = enic_dev_add_station_addr(enic); 709 if (err) 710 return err; 711 } 712 713 return err; 714 } 715 716 static int enic_set_mac_address(struct net_device *netdev, void *p) 717 { 718 struct sockaddr *saddr = p; 719 char *addr = saddr->sa_data; 720 struct enic *enic = netdev_priv(netdev); 721 int err; 722 723 err = enic_dev_del_station_addr(enic); 724 if (err) 725 return err; 726 727 err = enic_set_mac_addr(netdev, addr); 728 if (err) 729 return err; 730 731 return enic_dev_add_station_addr(enic); 732 } 733 734 /* netif_tx_lock held, BHs disabled */ 735 static void enic_set_rx_mode(struct net_device *netdev) 736 { 737 struct enic *enic = netdev_priv(netdev); 738 int directed = 1; 739 int multicast = (netdev->flags & IFF_MULTICAST) ? 1 : 0; 740 int broadcast = (netdev->flags & IFF_BROADCAST) ? 1 : 0; 741 int promisc = (netdev->flags & IFF_PROMISC) || 742 netdev_uc_count(netdev) > ENIC_UNICAST_PERFECT_FILTERS; 743 int allmulti = (netdev->flags & IFF_ALLMULTI) || 744 netdev_mc_count(netdev) > ENIC_MULTICAST_PERFECT_FILTERS; 745 unsigned int flags = netdev->flags | 746 (allmulti ? IFF_ALLMULTI : 0) | 747 (promisc ? IFF_PROMISC : 0); 748 749 if (enic->flags != flags) { 750 enic->flags = flags; 751 enic_dev_packet_filter(enic, directed, 752 multicast, broadcast, promisc, allmulti); 753 } 754 755 if (!promisc) { 756 __dev_uc_sync(netdev, enic_uc_sync, enic_uc_unsync); 757 if (!allmulti) 758 __dev_mc_sync(netdev, enic_mc_sync, enic_mc_unsync); 759 } 760 } 761 762 /* netif_tx_lock held, BHs disabled */ 763 static void enic_tx_timeout(struct net_device *netdev) 764 { 765 struct enic *enic = netdev_priv(netdev); 766 schedule_work(&enic->reset); 767 } 768 769 static int enic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 770 { 771 struct enic *enic = netdev_priv(netdev); 772 struct enic_port_profile *pp; 773 int err; 774 775 ENIC_PP_BY_INDEX(enic, vf, pp, &err); 776 if (err) 777 return err; 778 779 if (is_valid_ether_addr(mac) || is_zero_ether_addr(mac)) { 780 if (vf == PORT_SELF_VF) { 781 memcpy(pp->vf_mac, mac, ETH_ALEN); 782 return 0; 783 } else { 784 /* 785 * For sriov vf's set the mac in hw 786 */ 787 ENIC_DEVCMD_PROXY_BY_INDEX(vf, err, enic, 788 vnic_dev_set_mac_addr, mac); 789 return enic_dev_status_to_errno(err); 790 } 791 } else 792 return -EINVAL; 793 } 794 795 static int enic_set_vf_port(struct net_device *netdev, int vf, 796 struct nlattr *port[]) 797 { 798 struct enic *enic = netdev_priv(netdev); 799 struct enic_port_profile prev_pp; 800 struct enic_port_profile *pp; 801 int err = 0, restore_pp = 1; 802 803 ENIC_PP_BY_INDEX(enic, vf, pp, &err); 804 if (err) 805 return err; 806 807 if (!port[IFLA_PORT_REQUEST]) 808 return -EOPNOTSUPP; 809 810 memcpy(&prev_pp, pp, sizeof(*enic->pp)); 811 memset(pp, 0, sizeof(*enic->pp)); 812 813 pp->set |= ENIC_SET_REQUEST; 814 pp->request = nla_get_u8(port[IFLA_PORT_REQUEST]); 815 816 if (port[IFLA_PORT_PROFILE]) { 817 pp->set |= ENIC_SET_NAME; 818 memcpy(pp->name, nla_data(port[IFLA_PORT_PROFILE]), 819 PORT_PROFILE_MAX); 820 } 821 822 if (port[IFLA_PORT_INSTANCE_UUID]) { 823 pp->set |= ENIC_SET_INSTANCE; 824 memcpy(pp->instance_uuid, 825 nla_data(port[IFLA_PORT_INSTANCE_UUID]), PORT_UUID_MAX); 826 } 827 828 if (port[IFLA_PORT_HOST_UUID]) { 829 pp->set |= ENIC_SET_HOST; 830 memcpy(pp->host_uuid, 831 nla_data(port[IFLA_PORT_HOST_UUID]), PORT_UUID_MAX); 832 } 833 834 if (vf == PORT_SELF_VF) { 835 /* Special case handling: mac came from IFLA_VF_MAC */ 836 if (!is_zero_ether_addr(prev_pp.vf_mac)) 837 memcpy(pp->mac_addr, prev_pp.vf_mac, ETH_ALEN); 838 839 if (is_zero_ether_addr(netdev->dev_addr)) 840 eth_hw_addr_random(netdev); 841 } else { 842 /* SR-IOV VF: get mac from adapter */ 843 ENIC_DEVCMD_PROXY_BY_INDEX(vf, err, enic, 844 vnic_dev_get_mac_addr, pp->mac_addr); 845 if (err) { 846 netdev_err(netdev, "Error getting mac for vf %d\n", vf); 847 memcpy(pp, &prev_pp, sizeof(*pp)); 848 return enic_dev_status_to_errno(err); 849 } 850 } 851 852 err = enic_process_set_pp_request(enic, vf, &prev_pp, &restore_pp); 853 if (err) { 854 if (restore_pp) { 855 /* Things are still the way they were: Implicit 856 * DISASSOCIATE failed 857 */ 858 memcpy(pp, &prev_pp, sizeof(*pp)); 859 } else { 860 memset(pp, 0, sizeof(*pp)); 861 if (vf == PORT_SELF_VF) 862 memset(netdev->dev_addr, 0, ETH_ALEN); 863 } 864 } else { 865 /* Set flag to indicate that the port assoc/disassoc 866 * request has been sent out to fw 867 */ 868 pp->set |= ENIC_PORT_REQUEST_APPLIED; 869 870 /* If DISASSOCIATE, clean up all assigned/saved macaddresses */ 871 if (pp->request == PORT_REQUEST_DISASSOCIATE) { 872 memset(pp->mac_addr, 0, ETH_ALEN); 873 if (vf == PORT_SELF_VF) 874 memset(netdev->dev_addr, 0, ETH_ALEN); 875 } 876 } 877 878 if (vf == PORT_SELF_VF) 879 memset(pp->vf_mac, 0, ETH_ALEN); 880 881 return err; 882 } 883 884 static int enic_get_vf_port(struct net_device *netdev, int vf, 885 struct sk_buff *skb) 886 { 887 struct enic *enic = netdev_priv(netdev); 888 u16 response = PORT_PROFILE_RESPONSE_SUCCESS; 889 struct enic_port_profile *pp; 890 int err; 891 892 ENIC_PP_BY_INDEX(enic, vf, pp, &err); 893 if (err) 894 return err; 895 896 if (!(pp->set & ENIC_PORT_REQUEST_APPLIED)) 897 return -ENODATA; 898 899 err = enic_process_get_pp_request(enic, vf, pp->request, &response); 900 if (err) 901 return err; 902 903 if (nla_put_u16(skb, IFLA_PORT_REQUEST, pp->request) || 904 nla_put_u16(skb, IFLA_PORT_RESPONSE, response) || 905 ((pp->set & ENIC_SET_NAME) && 906 nla_put(skb, IFLA_PORT_PROFILE, PORT_PROFILE_MAX, pp->name)) || 907 ((pp->set & ENIC_SET_INSTANCE) && 908 nla_put(skb, IFLA_PORT_INSTANCE_UUID, PORT_UUID_MAX, 909 pp->instance_uuid)) || 910 ((pp->set & ENIC_SET_HOST) && 911 nla_put(skb, IFLA_PORT_HOST_UUID, PORT_UUID_MAX, pp->host_uuid))) 912 goto nla_put_failure; 913 return 0; 914 915 nla_put_failure: 916 return -EMSGSIZE; 917 } 918 919 static void enic_free_rq_buf(struct vnic_rq *rq, struct vnic_rq_buf *buf) 920 { 921 struct enic *enic = vnic_dev_priv(rq->vdev); 922 923 if (!buf->os_buf) 924 return; 925 926 pci_unmap_single(enic->pdev, buf->dma_addr, 927 buf->len, PCI_DMA_FROMDEVICE); 928 dev_kfree_skb_any(buf->os_buf); 929 buf->os_buf = NULL; 930 } 931 932 static int enic_rq_alloc_buf(struct vnic_rq *rq) 933 { 934 struct enic *enic = vnic_dev_priv(rq->vdev); 935 struct net_device *netdev = enic->netdev; 936 struct sk_buff *skb; 937 unsigned int len = netdev->mtu + VLAN_ETH_HLEN; 938 unsigned int os_buf_index = 0; 939 dma_addr_t dma_addr; 940 struct vnic_rq_buf *buf = rq->to_use; 941 942 if (buf->os_buf) { 943 buf = buf->next; 944 rq->to_use = buf; 945 rq->ring.desc_avail--; 946 if ((buf->index & VNIC_RQ_RETURN_RATE) == 0) { 947 /* Adding write memory barrier prevents compiler and/or 948 * CPU reordering, thus avoiding descriptor posting 949 * before descriptor is initialized. Otherwise, hardware 950 * can read stale descriptor fields. 951 */ 952 wmb(); 953 iowrite32(buf->index, &rq->ctrl->posted_index); 954 } 955 956 return 0; 957 } 958 skb = netdev_alloc_skb_ip_align(netdev, len); 959 if (!skb) 960 return -ENOMEM; 961 962 dma_addr = pci_map_single(enic->pdev, skb->data, 963 len, PCI_DMA_FROMDEVICE); 964 965 enic_queue_rq_desc(rq, skb, os_buf_index, 966 dma_addr, len); 967 968 return 0; 969 } 970 971 static void enic_intr_update_pkt_size(struct vnic_rx_bytes_counter *pkt_size, 972 u32 pkt_len) 973 { 974 if (ENIC_LARGE_PKT_THRESHOLD <= pkt_len) 975 pkt_size->large_pkt_bytes_cnt += pkt_len; 976 else 977 pkt_size->small_pkt_bytes_cnt += pkt_len; 978 } 979 980 static bool enic_rxcopybreak(struct net_device *netdev, struct sk_buff **skb, 981 struct vnic_rq_buf *buf, u16 len) 982 { 983 struct enic *enic = netdev_priv(netdev); 984 struct sk_buff *new_skb; 985 986 if (len > enic->rx_copybreak) 987 return false; 988 new_skb = netdev_alloc_skb_ip_align(netdev, len); 989 if (!new_skb) 990 return false; 991 pci_dma_sync_single_for_cpu(enic->pdev, buf->dma_addr, len, 992 DMA_FROM_DEVICE); 993 memcpy(new_skb->data, (*skb)->data, len); 994 *skb = new_skb; 995 996 return true; 997 } 998 999 static void enic_rq_indicate_buf(struct vnic_rq *rq, 1000 struct cq_desc *cq_desc, struct vnic_rq_buf *buf, 1001 int skipped, void *opaque) 1002 { 1003 struct enic *enic = vnic_dev_priv(rq->vdev); 1004 struct net_device *netdev = enic->netdev; 1005 struct sk_buff *skb; 1006 struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)]; 1007 1008 u8 type, color, eop, sop, ingress_port, vlan_stripped; 1009 u8 fcoe, fcoe_sof, fcoe_fc_crc_ok, fcoe_enc_error, fcoe_eof; 1010 u8 tcp_udp_csum_ok, udp, tcp, ipv4_csum_ok; 1011 u8 ipv6, ipv4, ipv4_fragment, fcs_ok, rss_type, csum_not_calc; 1012 u8 packet_error; 1013 u16 q_number, completed_index, bytes_written, vlan_tci, checksum; 1014 u32 rss_hash; 1015 1016 if (skipped) 1017 return; 1018 1019 skb = buf->os_buf; 1020 1021 cq_enet_rq_desc_dec((struct cq_enet_rq_desc *)cq_desc, 1022 &type, &color, &q_number, &completed_index, 1023 &ingress_port, &fcoe, &eop, &sop, &rss_type, 1024 &csum_not_calc, &rss_hash, &bytes_written, 1025 &packet_error, &vlan_stripped, &vlan_tci, &checksum, 1026 &fcoe_sof, &fcoe_fc_crc_ok, &fcoe_enc_error, 1027 &fcoe_eof, &tcp_udp_csum_ok, &udp, &tcp, 1028 &ipv4_csum_ok, &ipv6, &ipv4, &ipv4_fragment, 1029 &fcs_ok); 1030 1031 if (packet_error) { 1032 1033 if (!fcs_ok) { 1034 if (bytes_written > 0) 1035 enic->rq_bad_fcs++; 1036 else if (bytes_written == 0) 1037 enic->rq_truncated_pkts++; 1038 } 1039 1040 dev_kfree_skb_any(skb); 1041 1042 return; 1043 } 1044 1045 if (eop && bytes_written > 0) { 1046 1047 /* Good receive 1048 */ 1049 1050 if (!enic_rxcopybreak(netdev, &skb, buf, bytes_written)) { 1051 buf->os_buf = NULL; 1052 pci_unmap_single(enic->pdev, buf->dma_addr, buf->len, 1053 PCI_DMA_FROMDEVICE); 1054 } 1055 prefetch(skb->data - NET_IP_ALIGN); 1056 1057 skb_put(skb, bytes_written); 1058 skb->protocol = eth_type_trans(skb, netdev); 1059 skb_record_rx_queue(skb, q_number); 1060 if (netdev->features & NETIF_F_RXHASH) { 1061 skb_set_hash(skb, rss_hash, 1062 (rss_type & 1063 (NIC_CFG_RSS_HASH_TYPE_TCP_IPV6_EX | 1064 NIC_CFG_RSS_HASH_TYPE_TCP_IPV6 | 1065 NIC_CFG_RSS_HASH_TYPE_TCP_IPV4)) ? 1066 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); 1067 } 1068 1069 if ((netdev->features & NETIF_F_RXCSUM) && !csum_not_calc) { 1070 skb->csum = htons(checksum); 1071 skb->ip_summed = CHECKSUM_COMPLETE; 1072 } 1073 1074 if (vlan_stripped) 1075 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tci); 1076 1077 skb_mark_napi_id(skb, &enic->napi[rq->index]); 1078 if (enic_poll_busy_polling(rq) || 1079 !(netdev->features & NETIF_F_GRO)) 1080 netif_receive_skb(skb); 1081 else 1082 napi_gro_receive(&enic->napi[q_number], skb); 1083 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce) 1084 enic_intr_update_pkt_size(&cq->pkt_size_counter, 1085 bytes_written); 1086 } else { 1087 1088 /* Buffer overflow 1089 */ 1090 1091 dev_kfree_skb_any(skb); 1092 } 1093 } 1094 1095 static int enic_rq_service(struct vnic_dev *vdev, struct cq_desc *cq_desc, 1096 u8 type, u16 q_number, u16 completed_index, void *opaque) 1097 { 1098 struct enic *enic = vnic_dev_priv(vdev); 1099 1100 vnic_rq_service(&enic->rq[q_number], cq_desc, 1101 completed_index, VNIC_RQ_RETURN_DESC, 1102 enic_rq_indicate_buf, opaque); 1103 1104 return 0; 1105 } 1106 1107 static int enic_poll(struct napi_struct *napi, int budget) 1108 { 1109 struct net_device *netdev = napi->dev; 1110 struct enic *enic = netdev_priv(netdev); 1111 unsigned int cq_rq = enic_cq_rq(enic, 0); 1112 unsigned int cq_wq = enic_cq_wq(enic, 0); 1113 unsigned int intr = enic_legacy_io_intr(); 1114 unsigned int rq_work_to_do = budget; 1115 unsigned int wq_work_to_do = -1; /* no limit */ 1116 unsigned int work_done, rq_work_done = 0, wq_work_done; 1117 int err; 1118 1119 wq_work_done = vnic_cq_service(&enic->cq[cq_wq], wq_work_to_do, 1120 enic_wq_service, NULL); 1121 1122 if (!enic_poll_lock_napi(&enic->rq[cq_rq])) { 1123 if (wq_work_done > 0) 1124 vnic_intr_return_credits(&enic->intr[intr], 1125 wq_work_done, 1126 0 /* dont unmask intr */, 1127 0 /* dont reset intr timer */); 1128 return rq_work_done; 1129 } 1130 1131 if (budget > 0) 1132 rq_work_done = vnic_cq_service(&enic->cq[cq_rq], 1133 rq_work_to_do, enic_rq_service, NULL); 1134 1135 /* Accumulate intr event credits for this polling 1136 * cycle. An intr event is the completion of a 1137 * a WQ or RQ packet. 1138 */ 1139 1140 work_done = rq_work_done + wq_work_done; 1141 1142 if (work_done > 0) 1143 vnic_intr_return_credits(&enic->intr[intr], 1144 work_done, 1145 0 /* don't unmask intr */, 1146 0 /* don't reset intr timer */); 1147 1148 err = vnic_rq_fill(&enic->rq[0], enic_rq_alloc_buf); 1149 1150 /* Buffer allocation failed. Stay in polling 1151 * mode so we can try to fill the ring again. 1152 */ 1153 1154 if (err) 1155 rq_work_done = rq_work_to_do; 1156 1157 if (rq_work_done < rq_work_to_do) { 1158 1159 /* Some work done, but not enough to stay in polling, 1160 * exit polling 1161 */ 1162 1163 napi_complete(napi); 1164 vnic_intr_unmask(&enic->intr[intr]); 1165 } 1166 enic_poll_unlock_napi(&enic->rq[cq_rq]); 1167 1168 return rq_work_done; 1169 } 1170 1171 static void enic_set_int_moderation(struct enic *enic, struct vnic_rq *rq) 1172 { 1173 unsigned int intr = enic_msix_rq_intr(enic, rq->index); 1174 struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)]; 1175 u32 timer = cq->tobe_rx_coal_timeval; 1176 1177 if (cq->tobe_rx_coal_timeval != cq->cur_rx_coal_timeval) { 1178 vnic_intr_coalescing_timer_set(&enic->intr[intr], timer); 1179 cq->cur_rx_coal_timeval = cq->tobe_rx_coal_timeval; 1180 } 1181 } 1182 1183 static void enic_calc_int_moderation(struct enic *enic, struct vnic_rq *rq) 1184 { 1185 struct enic_rx_coal *rx_coal = &enic->rx_coalesce_setting; 1186 struct vnic_cq *cq = &enic->cq[enic_cq_rq(enic, rq->index)]; 1187 struct vnic_rx_bytes_counter *pkt_size_counter = &cq->pkt_size_counter; 1188 int index; 1189 u32 timer; 1190 u32 range_start; 1191 u32 traffic; 1192 u64 delta; 1193 ktime_t now = ktime_get(); 1194 1195 delta = ktime_us_delta(now, cq->prev_ts); 1196 if (delta < ENIC_AIC_TS_BREAK) 1197 return; 1198 cq->prev_ts = now; 1199 1200 traffic = pkt_size_counter->large_pkt_bytes_cnt + 1201 pkt_size_counter->small_pkt_bytes_cnt; 1202 /* The table takes Mbps 1203 * traffic *= 8 => bits 1204 * traffic *= (10^6 / delta) => bps 1205 * traffic /= 10^6 => Mbps 1206 * 1207 * Combining, traffic *= (8 / delta) 1208 */ 1209 1210 traffic <<= 3; 1211 traffic = delta > UINT_MAX ? 0 : traffic / (u32)delta; 1212 1213 for (index = 0; index < ENIC_MAX_COALESCE_TIMERS; index++) 1214 if (traffic < mod_table[index].rx_rate) 1215 break; 1216 range_start = (pkt_size_counter->small_pkt_bytes_cnt > 1217 pkt_size_counter->large_pkt_bytes_cnt << 1) ? 1218 rx_coal->small_pkt_range_start : 1219 rx_coal->large_pkt_range_start; 1220 timer = range_start + ((rx_coal->range_end - range_start) * 1221 mod_table[index].range_percent / 100); 1222 /* Damping */ 1223 cq->tobe_rx_coal_timeval = (timer + cq->tobe_rx_coal_timeval) >> 1; 1224 1225 pkt_size_counter->large_pkt_bytes_cnt = 0; 1226 pkt_size_counter->small_pkt_bytes_cnt = 0; 1227 } 1228 1229 #ifdef CONFIG_RFS_ACCEL 1230 static void enic_free_rx_cpu_rmap(struct enic *enic) 1231 { 1232 free_irq_cpu_rmap(enic->netdev->rx_cpu_rmap); 1233 enic->netdev->rx_cpu_rmap = NULL; 1234 } 1235 1236 static void enic_set_rx_cpu_rmap(struct enic *enic) 1237 { 1238 int i, res; 1239 1240 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX) { 1241 enic->netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(enic->rq_count); 1242 if (unlikely(!enic->netdev->rx_cpu_rmap)) 1243 return; 1244 for (i = 0; i < enic->rq_count; i++) { 1245 res = irq_cpu_rmap_add(enic->netdev->rx_cpu_rmap, 1246 enic->msix_entry[i].vector); 1247 if (unlikely(res)) { 1248 enic_free_rx_cpu_rmap(enic); 1249 return; 1250 } 1251 } 1252 } 1253 } 1254 1255 #else 1256 1257 static void enic_free_rx_cpu_rmap(struct enic *enic) 1258 { 1259 } 1260 1261 static void enic_set_rx_cpu_rmap(struct enic *enic) 1262 { 1263 } 1264 1265 #endif /* CONFIG_RFS_ACCEL */ 1266 1267 #ifdef CONFIG_NET_RX_BUSY_POLL 1268 int enic_busy_poll(struct napi_struct *napi) 1269 { 1270 struct net_device *netdev = napi->dev; 1271 struct enic *enic = netdev_priv(netdev); 1272 unsigned int rq = (napi - &enic->napi[0]); 1273 unsigned int cq = enic_cq_rq(enic, rq); 1274 unsigned int intr = enic_msix_rq_intr(enic, rq); 1275 unsigned int work_to_do = -1; /* clean all pkts possible */ 1276 unsigned int work_done; 1277 1278 if (!enic_poll_lock_poll(&enic->rq[rq])) 1279 return LL_FLUSH_BUSY; 1280 work_done = vnic_cq_service(&enic->cq[cq], work_to_do, 1281 enic_rq_service, NULL); 1282 1283 if (work_done > 0) 1284 vnic_intr_return_credits(&enic->intr[intr], 1285 work_done, 0, 0); 1286 vnic_rq_fill(&enic->rq[rq], enic_rq_alloc_buf); 1287 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce) 1288 enic_calc_int_moderation(enic, &enic->rq[rq]); 1289 enic_poll_unlock_poll(&enic->rq[rq]); 1290 1291 return work_done; 1292 } 1293 #endif /* CONFIG_NET_RX_BUSY_POLL */ 1294 1295 static int enic_poll_msix_wq(struct napi_struct *napi, int budget) 1296 { 1297 struct net_device *netdev = napi->dev; 1298 struct enic *enic = netdev_priv(netdev); 1299 unsigned int wq_index = (napi - &enic->napi[0]) - enic->rq_count; 1300 struct vnic_wq *wq = &enic->wq[wq_index]; 1301 unsigned int cq; 1302 unsigned int intr; 1303 unsigned int wq_work_to_do = -1; /* clean all desc possible */ 1304 unsigned int wq_work_done; 1305 unsigned int wq_irq; 1306 1307 wq_irq = wq->index; 1308 cq = enic_cq_wq(enic, wq_irq); 1309 intr = enic_msix_wq_intr(enic, wq_irq); 1310 wq_work_done = vnic_cq_service(&enic->cq[cq], wq_work_to_do, 1311 enic_wq_service, NULL); 1312 1313 vnic_intr_return_credits(&enic->intr[intr], wq_work_done, 1314 0 /* don't unmask intr */, 1315 1 /* reset intr timer */); 1316 if (!wq_work_done) { 1317 napi_complete(napi); 1318 vnic_intr_unmask(&enic->intr[intr]); 1319 } 1320 1321 return 0; 1322 } 1323 1324 static int enic_poll_msix_rq(struct napi_struct *napi, int budget) 1325 { 1326 struct net_device *netdev = napi->dev; 1327 struct enic *enic = netdev_priv(netdev); 1328 unsigned int rq = (napi - &enic->napi[0]); 1329 unsigned int cq = enic_cq_rq(enic, rq); 1330 unsigned int intr = enic_msix_rq_intr(enic, rq); 1331 unsigned int work_to_do = budget; 1332 unsigned int work_done = 0; 1333 int err; 1334 1335 if (!enic_poll_lock_napi(&enic->rq[rq])) 1336 return work_done; 1337 /* Service RQ 1338 */ 1339 1340 if (budget > 0) 1341 work_done = vnic_cq_service(&enic->cq[cq], 1342 work_to_do, enic_rq_service, NULL); 1343 1344 /* Return intr event credits for this polling 1345 * cycle. An intr event is the completion of a 1346 * RQ packet. 1347 */ 1348 1349 if (work_done > 0) 1350 vnic_intr_return_credits(&enic->intr[intr], 1351 work_done, 1352 0 /* don't unmask intr */, 1353 0 /* don't reset intr timer */); 1354 1355 err = vnic_rq_fill(&enic->rq[rq], enic_rq_alloc_buf); 1356 1357 /* Buffer allocation failed. Stay in polling mode 1358 * so we can try to fill the ring again. 1359 */ 1360 1361 if (err) 1362 work_done = work_to_do; 1363 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce) 1364 /* Call the function which refreshes 1365 * the intr coalescing timer value based on 1366 * the traffic. This is supported only in 1367 * the case of MSI-x mode 1368 */ 1369 enic_calc_int_moderation(enic, &enic->rq[rq]); 1370 1371 if (work_done < work_to_do) { 1372 1373 /* Some work done, but not enough to stay in polling, 1374 * exit polling 1375 */ 1376 1377 napi_complete(napi); 1378 if (enic->rx_coalesce_setting.use_adaptive_rx_coalesce) 1379 enic_set_int_moderation(enic, &enic->rq[rq]); 1380 vnic_intr_unmask(&enic->intr[intr]); 1381 } 1382 enic_poll_unlock_napi(&enic->rq[rq]); 1383 1384 return work_done; 1385 } 1386 1387 static void enic_notify_timer(unsigned long data) 1388 { 1389 struct enic *enic = (struct enic *)data; 1390 1391 enic_notify_check(enic); 1392 1393 mod_timer(&enic->notify_timer, 1394 round_jiffies(jiffies + ENIC_NOTIFY_TIMER_PERIOD)); 1395 } 1396 1397 static void enic_free_intr(struct enic *enic) 1398 { 1399 struct net_device *netdev = enic->netdev; 1400 unsigned int i; 1401 1402 enic_free_rx_cpu_rmap(enic); 1403 switch (vnic_dev_get_intr_mode(enic->vdev)) { 1404 case VNIC_DEV_INTR_MODE_INTX: 1405 free_irq(enic->pdev->irq, netdev); 1406 break; 1407 case VNIC_DEV_INTR_MODE_MSI: 1408 free_irq(enic->pdev->irq, enic); 1409 break; 1410 case VNIC_DEV_INTR_MODE_MSIX: 1411 for (i = 0; i < ARRAY_SIZE(enic->msix); i++) 1412 if (enic->msix[i].requested) 1413 free_irq(enic->msix_entry[i].vector, 1414 enic->msix[i].devid); 1415 break; 1416 default: 1417 break; 1418 } 1419 } 1420 1421 static int enic_request_intr(struct enic *enic) 1422 { 1423 struct net_device *netdev = enic->netdev; 1424 unsigned int i, intr; 1425 int err = 0; 1426 1427 enic_set_rx_cpu_rmap(enic); 1428 switch (vnic_dev_get_intr_mode(enic->vdev)) { 1429 1430 case VNIC_DEV_INTR_MODE_INTX: 1431 1432 err = request_irq(enic->pdev->irq, enic_isr_legacy, 1433 IRQF_SHARED, netdev->name, netdev); 1434 break; 1435 1436 case VNIC_DEV_INTR_MODE_MSI: 1437 1438 err = request_irq(enic->pdev->irq, enic_isr_msi, 1439 0, netdev->name, enic); 1440 break; 1441 1442 case VNIC_DEV_INTR_MODE_MSIX: 1443 1444 for (i = 0; i < enic->rq_count; i++) { 1445 intr = enic_msix_rq_intr(enic, i); 1446 snprintf(enic->msix[intr].devname, 1447 sizeof(enic->msix[intr].devname), 1448 "%.11s-rx-%d", netdev->name, i); 1449 enic->msix[intr].isr = enic_isr_msix; 1450 enic->msix[intr].devid = &enic->napi[i]; 1451 } 1452 1453 for (i = 0; i < enic->wq_count; i++) { 1454 int wq = enic_cq_wq(enic, i); 1455 1456 intr = enic_msix_wq_intr(enic, i); 1457 snprintf(enic->msix[intr].devname, 1458 sizeof(enic->msix[intr].devname), 1459 "%.11s-tx-%d", netdev->name, i); 1460 enic->msix[intr].isr = enic_isr_msix; 1461 enic->msix[intr].devid = &enic->napi[wq]; 1462 } 1463 1464 intr = enic_msix_err_intr(enic); 1465 snprintf(enic->msix[intr].devname, 1466 sizeof(enic->msix[intr].devname), 1467 "%.11s-err", netdev->name); 1468 enic->msix[intr].isr = enic_isr_msix_err; 1469 enic->msix[intr].devid = enic; 1470 1471 intr = enic_msix_notify_intr(enic); 1472 snprintf(enic->msix[intr].devname, 1473 sizeof(enic->msix[intr].devname), 1474 "%.11s-notify", netdev->name); 1475 enic->msix[intr].isr = enic_isr_msix_notify; 1476 enic->msix[intr].devid = enic; 1477 1478 for (i = 0; i < ARRAY_SIZE(enic->msix); i++) 1479 enic->msix[i].requested = 0; 1480 1481 for (i = 0; i < enic->intr_count; i++) { 1482 err = request_irq(enic->msix_entry[i].vector, 1483 enic->msix[i].isr, 0, 1484 enic->msix[i].devname, 1485 enic->msix[i].devid); 1486 if (err) { 1487 enic_free_intr(enic); 1488 break; 1489 } 1490 enic->msix[i].requested = 1; 1491 } 1492 1493 break; 1494 1495 default: 1496 break; 1497 } 1498 1499 return err; 1500 } 1501 1502 static void enic_synchronize_irqs(struct enic *enic) 1503 { 1504 unsigned int i; 1505 1506 switch (vnic_dev_get_intr_mode(enic->vdev)) { 1507 case VNIC_DEV_INTR_MODE_INTX: 1508 case VNIC_DEV_INTR_MODE_MSI: 1509 synchronize_irq(enic->pdev->irq); 1510 break; 1511 case VNIC_DEV_INTR_MODE_MSIX: 1512 for (i = 0; i < enic->intr_count; i++) 1513 synchronize_irq(enic->msix_entry[i].vector); 1514 break; 1515 default: 1516 break; 1517 } 1518 } 1519 1520 static void enic_set_rx_coal_setting(struct enic *enic) 1521 { 1522 unsigned int speed; 1523 int index = -1; 1524 struct enic_rx_coal *rx_coal = &enic->rx_coalesce_setting; 1525 1526 /* If intr mode is not MSIX, do not do adaptive coalescing */ 1527 if (VNIC_DEV_INTR_MODE_MSIX != vnic_dev_get_intr_mode(enic->vdev)) { 1528 netdev_info(enic->netdev, "INTR mode is not MSIX, Not initializing adaptive coalescing"); 1529 return; 1530 } 1531 1532 /* 1. Read the link speed from fw 1533 * 2. Pick the default range for the speed 1534 * 3. Update it in enic->rx_coalesce_setting 1535 */ 1536 speed = vnic_dev_port_speed(enic->vdev); 1537 if (ENIC_LINK_SPEED_10G < speed) 1538 index = ENIC_LINK_40G_INDEX; 1539 else if (ENIC_LINK_SPEED_4G < speed) 1540 index = ENIC_LINK_10G_INDEX; 1541 else 1542 index = ENIC_LINK_4G_INDEX; 1543 1544 rx_coal->small_pkt_range_start = mod_range[index].small_pkt_range_start; 1545 rx_coal->large_pkt_range_start = mod_range[index].large_pkt_range_start; 1546 rx_coal->range_end = ENIC_RX_COALESCE_RANGE_END; 1547 1548 /* Start with the value provided by UCSM */ 1549 for (index = 0; index < enic->rq_count; index++) 1550 enic->cq[index].cur_rx_coal_timeval = 1551 enic->config.intr_timer_usec; 1552 1553 rx_coal->use_adaptive_rx_coalesce = 1; 1554 } 1555 1556 static int enic_dev_notify_set(struct enic *enic) 1557 { 1558 int err; 1559 1560 spin_lock_bh(&enic->devcmd_lock); 1561 switch (vnic_dev_get_intr_mode(enic->vdev)) { 1562 case VNIC_DEV_INTR_MODE_INTX: 1563 err = vnic_dev_notify_set(enic->vdev, 1564 enic_legacy_notify_intr()); 1565 break; 1566 case VNIC_DEV_INTR_MODE_MSIX: 1567 err = vnic_dev_notify_set(enic->vdev, 1568 enic_msix_notify_intr(enic)); 1569 break; 1570 default: 1571 err = vnic_dev_notify_set(enic->vdev, -1 /* no intr */); 1572 break; 1573 } 1574 spin_unlock_bh(&enic->devcmd_lock); 1575 1576 return err; 1577 } 1578 1579 static void enic_notify_timer_start(struct enic *enic) 1580 { 1581 switch (vnic_dev_get_intr_mode(enic->vdev)) { 1582 case VNIC_DEV_INTR_MODE_MSI: 1583 mod_timer(&enic->notify_timer, jiffies); 1584 break; 1585 default: 1586 /* Using intr for notification for INTx/MSI-X */ 1587 break; 1588 } 1589 } 1590 1591 /* rtnl lock is held, process context */ 1592 static int enic_open(struct net_device *netdev) 1593 { 1594 struct enic *enic = netdev_priv(netdev); 1595 unsigned int i; 1596 int err; 1597 1598 err = enic_request_intr(enic); 1599 if (err) { 1600 netdev_err(netdev, "Unable to request irq.\n"); 1601 return err; 1602 } 1603 1604 err = enic_dev_notify_set(enic); 1605 if (err) { 1606 netdev_err(netdev, 1607 "Failed to alloc notify buffer, aborting.\n"); 1608 goto err_out_free_intr; 1609 } 1610 1611 for (i = 0; i < enic->rq_count; i++) { 1612 vnic_rq_fill(&enic->rq[i], enic_rq_alloc_buf); 1613 /* Need at least one buffer on ring to get going */ 1614 if (vnic_rq_desc_used(&enic->rq[i]) == 0) { 1615 netdev_err(netdev, "Unable to alloc receive buffers\n"); 1616 err = -ENOMEM; 1617 goto err_out_notify_unset; 1618 } 1619 } 1620 1621 for (i = 0; i < enic->wq_count; i++) 1622 vnic_wq_enable(&enic->wq[i]); 1623 for (i = 0; i < enic->rq_count; i++) 1624 vnic_rq_enable(&enic->rq[i]); 1625 1626 if (!enic_is_dynamic(enic) && !enic_is_sriov_vf(enic)) 1627 enic_dev_add_station_addr(enic); 1628 1629 enic_set_rx_mode(netdev); 1630 1631 netif_tx_wake_all_queues(netdev); 1632 1633 for (i = 0; i < enic->rq_count; i++) { 1634 enic_busy_poll_init_lock(&enic->rq[i]); 1635 napi_enable(&enic->napi[i]); 1636 } 1637 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX) 1638 for (i = 0; i < enic->wq_count; i++) 1639 napi_enable(&enic->napi[enic_cq_wq(enic, i)]); 1640 enic_dev_enable(enic); 1641 1642 for (i = 0; i < enic->intr_count; i++) 1643 vnic_intr_unmask(&enic->intr[i]); 1644 1645 enic_notify_timer_start(enic); 1646 enic_rfs_flw_tbl_init(enic); 1647 1648 return 0; 1649 1650 err_out_notify_unset: 1651 enic_dev_notify_unset(enic); 1652 err_out_free_intr: 1653 enic_free_intr(enic); 1654 1655 return err; 1656 } 1657 1658 /* rtnl lock is held, process context */ 1659 static int enic_stop(struct net_device *netdev) 1660 { 1661 struct enic *enic = netdev_priv(netdev); 1662 unsigned int i; 1663 int err; 1664 1665 for (i = 0; i < enic->intr_count; i++) { 1666 vnic_intr_mask(&enic->intr[i]); 1667 (void)vnic_intr_masked(&enic->intr[i]); /* flush write */ 1668 } 1669 1670 enic_synchronize_irqs(enic); 1671 1672 del_timer_sync(&enic->notify_timer); 1673 enic_rfs_flw_tbl_free(enic); 1674 1675 enic_dev_disable(enic); 1676 1677 local_bh_disable(); 1678 for (i = 0; i < enic->rq_count; i++) { 1679 napi_disable(&enic->napi[i]); 1680 while (!enic_poll_lock_napi(&enic->rq[i])) 1681 mdelay(1); 1682 } 1683 local_bh_enable(); 1684 1685 netif_carrier_off(netdev); 1686 netif_tx_disable(netdev); 1687 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX) 1688 for (i = 0; i < enic->wq_count; i++) 1689 napi_disable(&enic->napi[enic_cq_wq(enic, i)]); 1690 1691 if (!enic_is_dynamic(enic) && !enic_is_sriov_vf(enic)) 1692 enic_dev_del_station_addr(enic); 1693 1694 for (i = 0; i < enic->wq_count; i++) { 1695 err = vnic_wq_disable(&enic->wq[i]); 1696 if (err) 1697 return err; 1698 } 1699 for (i = 0; i < enic->rq_count; i++) { 1700 err = vnic_rq_disable(&enic->rq[i]); 1701 if (err) 1702 return err; 1703 } 1704 1705 enic_dev_notify_unset(enic); 1706 enic_free_intr(enic); 1707 1708 for (i = 0; i < enic->wq_count; i++) 1709 vnic_wq_clean(&enic->wq[i], enic_free_wq_buf); 1710 for (i = 0; i < enic->rq_count; i++) 1711 vnic_rq_clean(&enic->rq[i], enic_free_rq_buf); 1712 for (i = 0; i < enic->cq_count; i++) 1713 vnic_cq_clean(&enic->cq[i]); 1714 for (i = 0; i < enic->intr_count; i++) 1715 vnic_intr_clean(&enic->intr[i]); 1716 1717 return 0; 1718 } 1719 1720 static int enic_change_mtu(struct net_device *netdev, int new_mtu) 1721 { 1722 struct enic *enic = netdev_priv(netdev); 1723 int running = netif_running(netdev); 1724 1725 if (new_mtu < ENIC_MIN_MTU || new_mtu > ENIC_MAX_MTU) 1726 return -EINVAL; 1727 1728 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) 1729 return -EOPNOTSUPP; 1730 1731 if (running) 1732 enic_stop(netdev); 1733 1734 netdev->mtu = new_mtu; 1735 1736 if (netdev->mtu > enic->port_mtu) 1737 netdev_warn(netdev, 1738 "interface MTU (%d) set higher than port MTU (%d)\n", 1739 netdev->mtu, enic->port_mtu); 1740 1741 if (running) 1742 enic_open(netdev); 1743 1744 return 0; 1745 } 1746 1747 static void enic_change_mtu_work(struct work_struct *work) 1748 { 1749 struct enic *enic = container_of(work, struct enic, change_mtu_work); 1750 struct net_device *netdev = enic->netdev; 1751 int new_mtu = vnic_dev_mtu(enic->vdev); 1752 int err; 1753 unsigned int i; 1754 1755 new_mtu = max_t(int, ENIC_MIN_MTU, min_t(int, ENIC_MAX_MTU, new_mtu)); 1756 1757 rtnl_lock(); 1758 1759 /* Stop RQ */ 1760 del_timer_sync(&enic->notify_timer); 1761 1762 for (i = 0; i < enic->rq_count; i++) 1763 napi_disable(&enic->napi[i]); 1764 1765 vnic_intr_mask(&enic->intr[0]); 1766 enic_synchronize_irqs(enic); 1767 err = vnic_rq_disable(&enic->rq[0]); 1768 if (err) { 1769 rtnl_unlock(); 1770 netdev_err(netdev, "Unable to disable RQ.\n"); 1771 return; 1772 } 1773 vnic_rq_clean(&enic->rq[0], enic_free_rq_buf); 1774 vnic_cq_clean(&enic->cq[0]); 1775 vnic_intr_clean(&enic->intr[0]); 1776 1777 /* Fill RQ with new_mtu-sized buffers */ 1778 netdev->mtu = new_mtu; 1779 vnic_rq_fill(&enic->rq[0], enic_rq_alloc_buf); 1780 /* Need at least one buffer on ring to get going */ 1781 if (vnic_rq_desc_used(&enic->rq[0]) == 0) { 1782 rtnl_unlock(); 1783 netdev_err(netdev, "Unable to alloc receive buffers.\n"); 1784 return; 1785 } 1786 1787 /* Start RQ */ 1788 vnic_rq_enable(&enic->rq[0]); 1789 napi_enable(&enic->napi[0]); 1790 vnic_intr_unmask(&enic->intr[0]); 1791 enic_notify_timer_start(enic); 1792 1793 rtnl_unlock(); 1794 1795 netdev_info(netdev, "interface MTU set as %d\n", netdev->mtu); 1796 } 1797 1798 #ifdef CONFIG_NET_POLL_CONTROLLER 1799 static void enic_poll_controller(struct net_device *netdev) 1800 { 1801 struct enic *enic = netdev_priv(netdev); 1802 struct vnic_dev *vdev = enic->vdev; 1803 unsigned int i, intr; 1804 1805 switch (vnic_dev_get_intr_mode(vdev)) { 1806 case VNIC_DEV_INTR_MODE_MSIX: 1807 for (i = 0; i < enic->rq_count; i++) { 1808 intr = enic_msix_rq_intr(enic, i); 1809 enic_isr_msix(enic->msix_entry[intr].vector, 1810 &enic->napi[i]); 1811 } 1812 1813 for (i = 0; i < enic->wq_count; i++) { 1814 intr = enic_msix_wq_intr(enic, i); 1815 enic_isr_msix(enic->msix_entry[intr].vector, 1816 &enic->napi[enic_cq_wq(enic, i)]); 1817 } 1818 1819 break; 1820 case VNIC_DEV_INTR_MODE_MSI: 1821 enic_isr_msi(enic->pdev->irq, enic); 1822 break; 1823 case VNIC_DEV_INTR_MODE_INTX: 1824 enic_isr_legacy(enic->pdev->irq, netdev); 1825 break; 1826 default: 1827 break; 1828 } 1829 } 1830 #endif 1831 1832 static int enic_dev_wait(struct vnic_dev *vdev, 1833 int (*start)(struct vnic_dev *, int), 1834 int (*finished)(struct vnic_dev *, int *), 1835 int arg) 1836 { 1837 unsigned long time; 1838 int done; 1839 int err; 1840 1841 BUG_ON(in_interrupt()); 1842 1843 err = start(vdev, arg); 1844 if (err) 1845 return err; 1846 1847 /* Wait for func to complete...2 seconds max 1848 */ 1849 1850 time = jiffies + (HZ * 2); 1851 do { 1852 1853 err = finished(vdev, &done); 1854 if (err) 1855 return err; 1856 1857 if (done) 1858 return 0; 1859 1860 schedule_timeout_uninterruptible(HZ / 10); 1861 1862 } while (time_after(time, jiffies)); 1863 1864 return -ETIMEDOUT; 1865 } 1866 1867 static int enic_dev_open(struct enic *enic) 1868 { 1869 int err; 1870 1871 err = enic_dev_wait(enic->vdev, vnic_dev_open, 1872 vnic_dev_open_done, 0); 1873 if (err) 1874 dev_err(enic_get_dev(enic), "vNIC device open failed, err %d\n", 1875 err); 1876 1877 return err; 1878 } 1879 1880 static int enic_dev_hang_reset(struct enic *enic) 1881 { 1882 int err; 1883 1884 err = enic_dev_wait(enic->vdev, vnic_dev_hang_reset, 1885 vnic_dev_hang_reset_done, 0); 1886 if (err) 1887 netdev_err(enic->netdev, "vNIC hang reset failed, err %d\n", 1888 err); 1889 1890 return err; 1891 } 1892 1893 static int enic_set_rsskey(struct enic *enic) 1894 { 1895 dma_addr_t rss_key_buf_pa; 1896 union vnic_rss_key *rss_key_buf_va = NULL; 1897 union vnic_rss_key rss_key = { 1898 .key[0].b = {85, 67, 83, 97, 119, 101, 115, 111, 109, 101}, 1899 .key[1].b = {80, 65, 76, 79, 117, 110, 105, 113, 117, 101}, 1900 .key[2].b = {76, 73, 78, 85, 88, 114, 111, 99, 107, 115}, 1901 .key[3].b = {69, 78, 73, 67, 105, 115, 99, 111, 111, 108}, 1902 }; 1903 int err; 1904 1905 rss_key_buf_va = pci_alloc_consistent(enic->pdev, 1906 sizeof(union vnic_rss_key), &rss_key_buf_pa); 1907 if (!rss_key_buf_va) 1908 return -ENOMEM; 1909 1910 memcpy(rss_key_buf_va, &rss_key, sizeof(union vnic_rss_key)); 1911 1912 spin_lock_bh(&enic->devcmd_lock); 1913 err = enic_set_rss_key(enic, 1914 rss_key_buf_pa, 1915 sizeof(union vnic_rss_key)); 1916 spin_unlock_bh(&enic->devcmd_lock); 1917 1918 pci_free_consistent(enic->pdev, sizeof(union vnic_rss_key), 1919 rss_key_buf_va, rss_key_buf_pa); 1920 1921 return err; 1922 } 1923 1924 static int enic_set_rsscpu(struct enic *enic, u8 rss_hash_bits) 1925 { 1926 dma_addr_t rss_cpu_buf_pa; 1927 union vnic_rss_cpu *rss_cpu_buf_va = NULL; 1928 unsigned int i; 1929 int err; 1930 1931 rss_cpu_buf_va = pci_alloc_consistent(enic->pdev, 1932 sizeof(union vnic_rss_cpu), &rss_cpu_buf_pa); 1933 if (!rss_cpu_buf_va) 1934 return -ENOMEM; 1935 1936 for (i = 0; i < (1 << rss_hash_bits); i++) 1937 (*rss_cpu_buf_va).cpu[i/4].b[i%4] = i % enic->rq_count; 1938 1939 spin_lock_bh(&enic->devcmd_lock); 1940 err = enic_set_rss_cpu(enic, 1941 rss_cpu_buf_pa, 1942 sizeof(union vnic_rss_cpu)); 1943 spin_unlock_bh(&enic->devcmd_lock); 1944 1945 pci_free_consistent(enic->pdev, sizeof(union vnic_rss_cpu), 1946 rss_cpu_buf_va, rss_cpu_buf_pa); 1947 1948 return err; 1949 } 1950 1951 static int enic_set_niccfg(struct enic *enic, u8 rss_default_cpu, 1952 u8 rss_hash_type, u8 rss_hash_bits, u8 rss_base_cpu, u8 rss_enable) 1953 { 1954 const u8 tso_ipid_split_en = 0; 1955 const u8 ig_vlan_strip_en = 1; 1956 int err; 1957 1958 /* Enable VLAN tag stripping. 1959 */ 1960 1961 spin_lock_bh(&enic->devcmd_lock); 1962 err = enic_set_nic_cfg(enic, 1963 rss_default_cpu, rss_hash_type, 1964 rss_hash_bits, rss_base_cpu, 1965 rss_enable, tso_ipid_split_en, 1966 ig_vlan_strip_en); 1967 spin_unlock_bh(&enic->devcmd_lock); 1968 1969 return err; 1970 } 1971 1972 static int enic_set_rss_nic_cfg(struct enic *enic) 1973 { 1974 struct device *dev = enic_get_dev(enic); 1975 const u8 rss_default_cpu = 0; 1976 const u8 rss_hash_type = NIC_CFG_RSS_HASH_TYPE_IPV4 | 1977 NIC_CFG_RSS_HASH_TYPE_TCP_IPV4 | 1978 NIC_CFG_RSS_HASH_TYPE_IPV6 | 1979 NIC_CFG_RSS_HASH_TYPE_TCP_IPV6; 1980 const u8 rss_hash_bits = 7; 1981 const u8 rss_base_cpu = 0; 1982 u8 rss_enable = ENIC_SETTING(enic, RSS) && (enic->rq_count > 1); 1983 1984 if (rss_enable) { 1985 if (!enic_set_rsskey(enic)) { 1986 if (enic_set_rsscpu(enic, rss_hash_bits)) { 1987 rss_enable = 0; 1988 dev_warn(dev, "RSS disabled, " 1989 "Failed to set RSS cpu indirection table."); 1990 } 1991 } else { 1992 rss_enable = 0; 1993 dev_warn(dev, "RSS disabled, Failed to set RSS key.\n"); 1994 } 1995 } 1996 1997 return enic_set_niccfg(enic, rss_default_cpu, rss_hash_type, 1998 rss_hash_bits, rss_base_cpu, rss_enable); 1999 } 2000 2001 static void enic_reset(struct work_struct *work) 2002 { 2003 struct enic *enic = container_of(work, struct enic, reset); 2004 2005 if (!netif_running(enic->netdev)) 2006 return; 2007 2008 rtnl_lock(); 2009 2010 spin_lock(&enic->enic_api_lock); 2011 enic_dev_hang_notify(enic); 2012 enic_stop(enic->netdev); 2013 enic_dev_hang_reset(enic); 2014 enic_reset_addr_lists(enic); 2015 enic_init_vnic_resources(enic); 2016 enic_set_rss_nic_cfg(enic); 2017 enic_dev_set_ig_vlan_rewrite_mode(enic); 2018 enic_open(enic->netdev); 2019 spin_unlock(&enic->enic_api_lock); 2020 call_netdevice_notifiers(NETDEV_REBOOT, enic->netdev); 2021 2022 rtnl_unlock(); 2023 } 2024 2025 static int enic_set_intr_mode(struct enic *enic) 2026 { 2027 unsigned int n = min_t(unsigned int, enic->rq_count, ENIC_RQ_MAX); 2028 unsigned int m = min_t(unsigned int, enic->wq_count, ENIC_WQ_MAX); 2029 unsigned int i; 2030 2031 /* Set interrupt mode (INTx, MSI, MSI-X) depending 2032 * on system capabilities. 2033 * 2034 * Try MSI-X first 2035 * 2036 * We need n RQs, m WQs, n+m CQs, and n+m+2 INTRs 2037 * (the second to last INTR is used for WQ/RQ errors) 2038 * (the last INTR is used for notifications) 2039 */ 2040 2041 BUG_ON(ARRAY_SIZE(enic->msix_entry) < n + m + 2); 2042 for (i = 0; i < n + m + 2; i++) 2043 enic->msix_entry[i].entry = i; 2044 2045 /* Use multiple RQs if RSS is enabled 2046 */ 2047 2048 if (ENIC_SETTING(enic, RSS) && 2049 enic->config.intr_mode < 1 && 2050 enic->rq_count >= n && 2051 enic->wq_count >= m && 2052 enic->cq_count >= n + m && 2053 enic->intr_count >= n + m + 2) { 2054 2055 if (pci_enable_msix_range(enic->pdev, enic->msix_entry, 2056 n + m + 2, n + m + 2) > 0) { 2057 2058 enic->rq_count = n; 2059 enic->wq_count = m; 2060 enic->cq_count = n + m; 2061 enic->intr_count = n + m + 2; 2062 2063 vnic_dev_set_intr_mode(enic->vdev, 2064 VNIC_DEV_INTR_MODE_MSIX); 2065 2066 return 0; 2067 } 2068 } 2069 2070 if (enic->config.intr_mode < 1 && 2071 enic->rq_count >= 1 && 2072 enic->wq_count >= m && 2073 enic->cq_count >= 1 + m && 2074 enic->intr_count >= 1 + m + 2) { 2075 if (pci_enable_msix_range(enic->pdev, enic->msix_entry, 2076 1 + m + 2, 1 + m + 2) > 0) { 2077 2078 enic->rq_count = 1; 2079 enic->wq_count = m; 2080 enic->cq_count = 1 + m; 2081 enic->intr_count = 1 + m + 2; 2082 2083 vnic_dev_set_intr_mode(enic->vdev, 2084 VNIC_DEV_INTR_MODE_MSIX); 2085 2086 return 0; 2087 } 2088 } 2089 2090 /* Next try MSI 2091 * 2092 * We need 1 RQ, 1 WQ, 2 CQs, and 1 INTR 2093 */ 2094 2095 if (enic->config.intr_mode < 2 && 2096 enic->rq_count >= 1 && 2097 enic->wq_count >= 1 && 2098 enic->cq_count >= 2 && 2099 enic->intr_count >= 1 && 2100 !pci_enable_msi(enic->pdev)) { 2101 2102 enic->rq_count = 1; 2103 enic->wq_count = 1; 2104 enic->cq_count = 2; 2105 enic->intr_count = 1; 2106 2107 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_MSI); 2108 2109 return 0; 2110 } 2111 2112 /* Next try INTx 2113 * 2114 * We need 1 RQ, 1 WQ, 2 CQs, and 3 INTRs 2115 * (the first INTR is used for WQ/RQ) 2116 * (the second INTR is used for WQ/RQ errors) 2117 * (the last INTR is used for notifications) 2118 */ 2119 2120 if (enic->config.intr_mode < 3 && 2121 enic->rq_count >= 1 && 2122 enic->wq_count >= 1 && 2123 enic->cq_count >= 2 && 2124 enic->intr_count >= 3) { 2125 2126 enic->rq_count = 1; 2127 enic->wq_count = 1; 2128 enic->cq_count = 2; 2129 enic->intr_count = 3; 2130 2131 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_INTX); 2132 2133 return 0; 2134 } 2135 2136 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_UNKNOWN); 2137 2138 return -EINVAL; 2139 } 2140 2141 static void enic_clear_intr_mode(struct enic *enic) 2142 { 2143 switch (vnic_dev_get_intr_mode(enic->vdev)) { 2144 case VNIC_DEV_INTR_MODE_MSIX: 2145 pci_disable_msix(enic->pdev); 2146 break; 2147 case VNIC_DEV_INTR_MODE_MSI: 2148 pci_disable_msi(enic->pdev); 2149 break; 2150 default: 2151 break; 2152 } 2153 2154 vnic_dev_set_intr_mode(enic->vdev, VNIC_DEV_INTR_MODE_UNKNOWN); 2155 } 2156 2157 static const struct net_device_ops enic_netdev_dynamic_ops = { 2158 .ndo_open = enic_open, 2159 .ndo_stop = enic_stop, 2160 .ndo_start_xmit = enic_hard_start_xmit, 2161 .ndo_get_stats64 = enic_get_stats, 2162 .ndo_validate_addr = eth_validate_addr, 2163 .ndo_set_rx_mode = enic_set_rx_mode, 2164 .ndo_set_mac_address = enic_set_mac_address_dynamic, 2165 .ndo_change_mtu = enic_change_mtu, 2166 .ndo_vlan_rx_add_vid = enic_vlan_rx_add_vid, 2167 .ndo_vlan_rx_kill_vid = enic_vlan_rx_kill_vid, 2168 .ndo_tx_timeout = enic_tx_timeout, 2169 .ndo_set_vf_port = enic_set_vf_port, 2170 .ndo_get_vf_port = enic_get_vf_port, 2171 .ndo_set_vf_mac = enic_set_vf_mac, 2172 #ifdef CONFIG_NET_POLL_CONTROLLER 2173 .ndo_poll_controller = enic_poll_controller, 2174 #endif 2175 #ifdef CONFIG_RFS_ACCEL 2176 .ndo_rx_flow_steer = enic_rx_flow_steer, 2177 #endif 2178 #ifdef CONFIG_NET_RX_BUSY_POLL 2179 .ndo_busy_poll = enic_busy_poll, 2180 #endif 2181 }; 2182 2183 static const struct net_device_ops enic_netdev_ops = { 2184 .ndo_open = enic_open, 2185 .ndo_stop = enic_stop, 2186 .ndo_start_xmit = enic_hard_start_xmit, 2187 .ndo_get_stats64 = enic_get_stats, 2188 .ndo_validate_addr = eth_validate_addr, 2189 .ndo_set_mac_address = enic_set_mac_address, 2190 .ndo_set_rx_mode = enic_set_rx_mode, 2191 .ndo_change_mtu = enic_change_mtu, 2192 .ndo_vlan_rx_add_vid = enic_vlan_rx_add_vid, 2193 .ndo_vlan_rx_kill_vid = enic_vlan_rx_kill_vid, 2194 .ndo_tx_timeout = enic_tx_timeout, 2195 .ndo_set_vf_port = enic_set_vf_port, 2196 .ndo_get_vf_port = enic_get_vf_port, 2197 .ndo_set_vf_mac = enic_set_vf_mac, 2198 #ifdef CONFIG_NET_POLL_CONTROLLER 2199 .ndo_poll_controller = enic_poll_controller, 2200 #endif 2201 #ifdef CONFIG_RFS_ACCEL 2202 .ndo_rx_flow_steer = enic_rx_flow_steer, 2203 #endif 2204 #ifdef CONFIG_NET_RX_BUSY_POLL 2205 .ndo_busy_poll = enic_busy_poll, 2206 #endif 2207 }; 2208 2209 static void enic_dev_deinit(struct enic *enic) 2210 { 2211 unsigned int i; 2212 2213 for (i = 0; i < enic->rq_count; i++) { 2214 napi_hash_del(&enic->napi[i]); 2215 netif_napi_del(&enic->napi[i]); 2216 } 2217 if (vnic_dev_get_intr_mode(enic->vdev) == VNIC_DEV_INTR_MODE_MSIX) 2218 for (i = 0; i < enic->wq_count; i++) 2219 netif_napi_del(&enic->napi[enic_cq_wq(enic, i)]); 2220 2221 enic_free_vnic_resources(enic); 2222 enic_clear_intr_mode(enic); 2223 } 2224 2225 static int enic_dev_init(struct enic *enic) 2226 { 2227 struct device *dev = enic_get_dev(enic); 2228 struct net_device *netdev = enic->netdev; 2229 unsigned int i; 2230 int err; 2231 2232 /* Get interrupt coalesce timer info */ 2233 err = enic_dev_intr_coal_timer_info(enic); 2234 if (err) { 2235 dev_warn(dev, "Using default conversion factor for " 2236 "interrupt coalesce timer\n"); 2237 vnic_dev_intr_coal_timer_info_default(enic->vdev); 2238 } 2239 2240 /* Get vNIC configuration 2241 */ 2242 2243 err = enic_get_vnic_config(enic); 2244 if (err) { 2245 dev_err(dev, "Get vNIC configuration failed, aborting\n"); 2246 return err; 2247 } 2248 2249 /* Get available resource counts 2250 */ 2251 2252 enic_get_res_counts(enic); 2253 2254 /* Set interrupt mode based on resource counts and system 2255 * capabilities 2256 */ 2257 2258 err = enic_set_intr_mode(enic); 2259 if (err) { 2260 dev_err(dev, "Failed to set intr mode based on resource " 2261 "counts and system capabilities, aborting\n"); 2262 return err; 2263 } 2264 2265 /* Allocate and configure vNIC resources 2266 */ 2267 2268 err = enic_alloc_vnic_resources(enic); 2269 if (err) { 2270 dev_err(dev, "Failed to alloc vNIC resources, aborting\n"); 2271 goto err_out_free_vnic_resources; 2272 } 2273 2274 enic_init_vnic_resources(enic); 2275 2276 err = enic_set_rss_nic_cfg(enic); 2277 if (err) { 2278 dev_err(dev, "Failed to config nic, aborting\n"); 2279 goto err_out_free_vnic_resources; 2280 } 2281 2282 switch (vnic_dev_get_intr_mode(enic->vdev)) { 2283 default: 2284 netif_napi_add(netdev, &enic->napi[0], enic_poll, 64); 2285 napi_hash_add(&enic->napi[0]); 2286 break; 2287 case VNIC_DEV_INTR_MODE_MSIX: 2288 for (i = 0; i < enic->rq_count; i++) { 2289 netif_napi_add(netdev, &enic->napi[i], 2290 enic_poll_msix_rq, NAPI_POLL_WEIGHT); 2291 napi_hash_add(&enic->napi[i]); 2292 } 2293 for (i = 0; i < enic->wq_count; i++) 2294 netif_napi_add(netdev, &enic->napi[enic_cq_wq(enic, i)], 2295 enic_poll_msix_wq, NAPI_POLL_WEIGHT); 2296 break; 2297 } 2298 2299 return 0; 2300 2301 err_out_free_vnic_resources: 2302 enic_clear_intr_mode(enic); 2303 enic_free_vnic_resources(enic); 2304 2305 return err; 2306 } 2307 2308 static void enic_iounmap(struct enic *enic) 2309 { 2310 unsigned int i; 2311 2312 for (i = 0; i < ARRAY_SIZE(enic->bar); i++) 2313 if (enic->bar[i].vaddr) 2314 iounmap(enic->bar[i].vaddr); 2315 } 2316 2317 static int enic_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2318 { 2319 struct device *dev = &pdev->dev; 2320 struct net_device *netdev; 2321 struct enic *enic; 2322 int using_dac = 0; 2323 unsigned int i; 2324 int err; 2325 #ifdef CONFIG_PCI_IOV 2326 int pos = 0; 2327 #endif 2328 int num_pps = 1; 2329 2330 /* Allocate net device structure and initialize. Private 2331 * instance data is initialized to zero. 2332 */ 2333 2334 netdev = alloc_etherdev_mqs(sizeof(struct enic), 2335 ENIC_RQ_MAX, ENIC_WQ_MAX); 2336 if (!netdev) 2337 return -ENOMEM; 2338 2339 pci_set_drvdata(pdev, netdev); 2340 2341 SET_NETDEV_DEV(netdev, &pdev->dev); 2342 2343 enic = netdev_priv(netdev); 2344 enic->netdev = netdev; 2345 enic->pdev = pdev; 2346 2347 /* Setup PCI resources 2348 */ 2349 2350 err = pci_enable_device_mem(pdev); 2351 if (err) { 2352 dev_err(dev, "Cannot enable PCI device, aborting\n"); 2353 goto err_out_free_netdev; 2354 } 2355 2356 err = pci_request_regions(pdev, DRV_NAME); 2357 if (err) { 2358 dev_err(dev, "Cannot request PCI regions, aborting\n"); 2359 goto err_out_disable_device; 2360 } 2361 2362 pci_set_master(pdev); 2363 2364 /* Query PCI controller on system for DMA addressing 2365 * limitation for the device. Try 64-bit first, and 2366 * fail to 32-bit. 2367 */ 2368 2369 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 2370 if (err) { 2371 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 2372 if (err) { 2373 dev_err(dev, "No usable DMA configuration, aborting\n"); 2374 goto err_out_release_regions; 2375 } 2376 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 2377 if (err) { 2378 dev_err(dev, "Unable to obtain %u-bit DMA " 2379 "for consistent allocations, aborting\n", 32); 2380 goto err_out_release_regions; 2381 } 2382 } else { 2383 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 2384 if (err) { 2385 dev_err(dev, "Unable to obtain %u-bit DMA " 2386 "for consistent allocations, aborting\n", 64); 2387 goto err_out_release_regions; 2388 } 2389 using_dac = 1; 2390 } 2391 2392 /* Map vNIC resources from BAR0-5 2393 */ 2394 2395 for (i = 0; i < ARRAY_SIZE(enic->bar); i++) { 2396 if (!(pci_resource_flags(pdev, i) & IORESOURCE_MEM)) 2397 continue; 2398 enic->bar[i].len = pci_resource_len(pdev, i); 2399 enic->bar[i].vaddr = pci_iomap(pdev, i, enic->bar[i].len); 2400 if (!enic->bar[i].vaddr) { 2401 dev_err(dev, "Cannot memory-map BAR %d, aborting\n", i); 2402 err = -ENODEV; 2403 goto err_out_iounmap; 2404 } 2405 enic->bar[i].bus_addr = pci_resource_start(pdev, i); 2406 } 2407 2408 /* Register vNIC device 2409 */ 2410 2411 enic->vdev = vnic_dev_register(NULL, enic, pdev, enic->bar, 2412 ARRAY_SIZE(enic->bar)); 2413 if (!enic->vdev) { 2414 dev_err(dev, "vNIC registration failed, aborting\n"); 2415 err = -ENODEV; 2416 goto err_out_iounmap; 2417 } 2418 2419 #ifdef CONFIG_PCI_IOV 2420 /* Get number of subvnics */ 2421 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV); 2422 if (pos) { 2423 pci_read_config_word(pdev, pos + PCI_SRIOV_TOTAL_VF, 2424 &enic->num_vfs); 2425 if (enic->num_vfs) { 2426 err = pci_enable_sriov(pdev, enic->num_vfs); 2427 if (err) { 2428 dev_err(dev, "SRIOV enable failed, aborting." 2429 " pci_enable_sriov() returned %d\n", 2430 err); 2431 goto err_out_vnic_unregister; 2432 } 2433 enic->priv_flags |= ENIC_SRIOV_ENABLED; 2434 num_pps = enic->num_vfs; 2435 } 2436 } 2437 #endif 2438 2439 /* Allocate structure for port profiles */ 2440 enic->pp = kcalloc(num_pps, sizeof(*enic->pp), GFP_KERNEL); 2441 if (!enic->pp) { 2442 err = -ENOMEM; 2443 goto err_out_disable_sriov_pp; 2444 } 2445 2446 /* Issue device open to get device in known state 2447 */ 2448 2449 err = enic_dev_open(enic); 2450 if (err) { 2451 dev_err(dev, "vNIC dev open failed, aborting\n"); 2452 goto err_out_disable_sriov; 2453 } 2454 2455 /* Setup devcmd lock 2456 */ 2457 2458 spin_lock_init(&enic->devcmd_lock); 2459 spin_lock_init(&enic->enic_api_lock); 2460 2461 /* 2462 * Set ingress vlan rewrite mode before vnic initialization 2463 */ 2464 2465 err = enic_dev_set_ig_vlan_rewrite_mode(enic); 2466 if (err) { 2467 dev_err(dev, 2468 "Failed to set ingress vlan rewrite mode, aborting.\n"); 2469 goto err_out_dev_close; 2470 } 2471 2472 /* Issue device init to initialize the vnic-to-switch link. 2473 * We'll start with carrier off and wait for link UP 2474 * notification later to turn on carrier. We don't need 2475 * to wait here for the vnic-to-switch link initialization 2476 * to complete; link UP notification is the indication that 2477 * the process is complete. 2478 */ 2479 2480 netif_carrier_off(netdev); 2481 2482 /* Do not call dev_init for a dynamic vnic. 2483 * For a dynamic vnic, init_prov_info will be 2484 * called later by an upper layer. 2485 */ 2486 2487 if (!enic_is_dynamic(enic)) { 2488 err = vnic_dev_init(enic->vdev, 0); 2489 if (err) { 2490 dev_err(dev, "vNIC dev init failed, aborting\n"); 2491 goto err_out_dev_close; 2492 } 2493 } 2494 2495 err = enic_dev_init(enic); 2496 if (err) { 2497 dev_err(dev, "Device initialization failed, aborting\n"); 2498 goto err_out_dev_close; 2499 } 2500 2501 netif_set_real_num_tx_queues(netdev, enic->wq_count); 2502 netif_set_real_num_rx_queues(netdev, enic->rq_count); 2503 2504 /* Setup notification timer, HW reset task, and wq locks 2505 */ 2506 2507 init_timer(&enic->notify_timer); 2508 enic->notify_timer.function = enic_notify_timer; 2509 enic->notify_timer.data = (unsigned long)enic; 2510 2511 enic_set_rx_coal_setting(enic); 2512 INIT_WORK(&enic->reset, enic_reset); 2513 INIT_WORK(&enic->change_mtu_work, enic_change_mtu_work); 2514 2515 for (i = 0; i < enic->wq_count; i++) 2516 spin_lock_init(&enic->wq_lock[i]); 2517 2518 /* Register net device 2519 */ 2520 2521 enic->port_mtu = enic->config.mtu; 2522 (void)enic_change_mtu(netdev, enic->port_mtu); 2523 2524 err = enic_set_mac_addr(netdev, enic->mac_addr); 2525 if (err) { 2526 dev_err(dev, "Invalid MAC address, aborting\n"); 2527 goto err_out_dev_deinit; 2528 } 2529 2530 enic->tx_coalesce_usecs = enic->config.intr_timer_usec; 2531 /* rx coalesce time already got initialized. This gets used 2532 * if adaptive coal is turned off 2533 */ 2534 enic->rx_coalesce_usecs = enic->tx_coalesce_usecs; 2535 2536 if (enic_is_dynamic(enic) || enic_is_sriov_vf(enic)) 2537 netdev->netdev_ops = &enic_netdev_dynamic_ops; 2538 else 2539 netdev->netdev_ops = &enic_netdev_ops; 2540 2541 netdev->watchdog_timeo = 2 * HZ; 2542 enic_set_ethtool_ops(netdev); 2543 2544 netdev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 2545 if (ENIC_SETTING(enic, LOOP)) { 2546 netdev->features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2547 enic->loop_enable = 1; 2548 enic->loop_tag = enic->config.loop_tag; 2549 dev_info(dev, "loopback tag=0x%04x\n", enic->loop_tag); 2550 } 2551 if (ENIC_SETTING(enic, TXCSUM)) 2552 netdev->hw_features |= NETIF_F_SG | NETIF_F_HW_CSUM; 2553 if (ENIC_SETTING(enic, TSO)) 2554 netdev->hw_features |= NETIF_F_TSO | 2555 NETIF_F_TSO6 | NETIF_F_TSO_ECN; 2556 if (ENIC_SETTING(enic, RSS)) 2557 netdev->hw_features |= NETIF_F_RXHASH; 2558 if (ENIC_SETTING(enic, RXCSUM)) 2559 netdev->hw_features |= NETIF_F_RXCSUM; 2560 2561 netdev->features |= netdev->hw_features; 2562 2563 #ifdef CONFIG_RFS_ACCEL 2564 netdev->hw_features |= NETIF_F_NTUPLE; 2565 #endif 2566 2567 if (using_dac) 2568 netdev->features |= NETIF_F_HIGHDMA; 2569 2570 netdev->priv_flags |= IFF_UNICAST_FLT; 2571 2572 err = register_netdev(netdev); 2573 if (err) { 2574 dev_err(dev, "Cannot register net device, aborting\n"); 2575 goto err_out_dev_deinit; 2576 } 2577 enic->rx_copybreak = RX_COPYBREAK_DEFAULT; 2578 2579 return 0; 2580 2581 err_out_dev_deinit: 2582 enic_dev_deinit(enic); 2583 err_out_dev_close: 2584 vnic_dev_close(enic->vdev); 2585 err_out_disable_sriov: 2586 kfree(enic->pp); 2587 err_out_disable_sriov_pp: 2588 #ifdef CONFIG_PCI_IOV 2589 if (enic_sriov_enabled(enic)) { 2590 pci_disable_sriov(pdev); 2591 enic->priv_flags &= ~ENIC_SRIOV_ENABLED; 2592 } 2593 err_out_vnic_unregister: 2594 #endif 2595 vnic_dev_unregister(enic->vdev); 2596 err_out_iounmap: 2597 enic_iounmap(enic); 2598 err_out_release_regions: 2599 pci_release_regions(pdev); 2600 err_out_disable_device: 2601 pci_disable_device(pdev); 2602 err_out_free_netdev: 2603 free_netdev(netdev); 2604 2605 return err; 2606 } 2607 2608 static void enic_remove(struct pci_dev *pdev) 2609 { 2610 struct net_device *netdev = pci_get_drvdata(pdev); 2611 2612 if (netdev) { 2613 struct enic *enic = netdev_priv(netdev); 2614 2615 cancel_work_sync(&enic->reset); 2616 cancel_work_sync(&enic->change_mtu_work); 2617 unregister_netdev(netdev); 2618 enic_dev_deinit(enic); 2619 vnic_dev_close(enic->vdev); 2620 #ifdef CONFIG_PCI_IOV 2621 if (enic_sriov_enabled(enic)) { 2622 pci_disable_sriov(pdev); 2623 enic->priv_flags &= ~ENIC_SRIOV_ENABLED; 2624 } 2625 #endif 2626 kfree(enic->pp); 2627 vnic_dev_unregister(enic->vdev); 2628 enic_iounmap(enic); 2629 pci_release_regions(pdev); 2630 pci_disable_device(pdev); 2631 free_netdev(netdev); 2632 } 2633 } 2634 2635 static struct pci_driver enic_driver = { 2636 .name = DRV_NAME, 2637 .id_table = enic_id_table, 2638 .probe = enic_probe, 2639 .remove = enic_remove, 2640 }; 2641 2642 static int __init enic_init_module(void) 2643 { 2644 pr_info("%s, ver %s\n", DRV_DESCRIPTION, DRV_VERSION); 2645 2646 return pci_register_driver(&enic_driver); 2647 } 2648 2649 static void __exit enic_cleanup_module(void) 2650 { 2651 pci_unregister_driver(&enic_driver); 2652 } 2653 2654 module_init(enic_init_module); 2655 module_exit(enic_cleanup_module); 2656