1 /* 2 * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved. 3 * Copyright 2007 Nuova Systems, Inc. All rights reserved. 4 * 5 * This program is free software; you may redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; version 2 of the License. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 10 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 11 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 12 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 13 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 14 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 15 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 16 * SOFTWARE. 17 * 18 */ 19 20 #ifndef _ENIC_H_ 21 #define _ENIC_H_ 22 23 #include "vnic_enet.h" 24 #include "vnic_dev.h" 25 #include "vnic_wq.h" 26 #include "vnic_rq.h" 27 #include "vnic_cq.h" 28 #include "vnic_intr.h" 29 #include "vnic_stats.h" 30 #include "vnic_nic.h" 31 #include "vnic_rss.h" 32 #include <linux/irq.h> 33 34 #define DRV_NAME "enic" 35 #define DRV_DESCRIPTION "Cisco VIC Ethernet NIC Driver" 36 #define DRV_VERSION "2.1.1.67" 37 #define DRV_COPYRIGHT "Copyright 2008-2013 Cisco Systems, Inc" 38 39 #define ENIC_BARS_MAX 6 40 41 #define ENIC_WQ_MAX 8 42 #define ENIC_RQ_MAX 8 43 #define ENIC_CQ_MAX (ENIC_WQ_MAX + ENIC_RQ_MAX) 44 #define ENIC_INTR_MAX (ENIC_CQ_MAX + 2) 45 46 #define ENIC_AIC_LARGE_PKT_DIFF 3 47 48 struct enic_msix_entry { 49 int requested; 50 char devname[IFNAMSIZ]; 51 irqreturn_t (*isr)(int, void *); 52 void *devid; 53 }; 54 55 /* Store only the lower range. Higher range is given by fw. */ 56 struct enic_intr_mod_range { 57 u32 small_pkt_range_start; 58 u32 large_pkt_range_start; 59 }; 60 61 struct enic_intr_mod_table { 62 u32 rx_rate; 63 u32 range_percent; 64 }; 65 66 #define ENIC_MAX_LINK_SPEEDS 3 67 #define ENIC_LINK_SPEED_10G 10000 68 #define ENIC_LINK_SPEED_4G 4000 69 #define ENIC_LINK_40G_INDEX 2 70 #define ENIC_LINK_10G_INDEX 1 71 #define ENIC_LINK_4G_INDEX 0 72 #define ENIC_RX_COALESCE_RANGE_END 125 73 #define ENIC_AIC_TS_BREAK 100 74 75 struct enic_rx_coal { 76 u32 small_pkt_range_start; 77 u32 large_pkt_range_start; 78 u32 range_end; 79 u32 use_adaptive_rx_coalesce; 80 }; 81 82 /* priv_flags */ 83 #define ENIC_SRIOV_ENABLED (1 << 0) 84 85 /* enic port profile set flags */ 86 #define ENIC_PORT_REQUEST_APPLIED (1 << 0) 87 #define ENIC_SET_REQUEST (1 << 1) 88 #define ENIC_SET_NAME (1 << 2) 89 #define ENIC_SET_INSTANCE (1 << 3) 90 #define ENIC_SET_HOST (1 << 4) 91 92 struct enic_port_profile { 93 u32 set; 94 u8 request; 95 char name[PORT_PROFILE_MAX]; 96 u8 instance_uuid[PORT_UUID_MAX]; 97 u8 host_uuid[PORT_UUID_MAX]; 98 u8 vf_mac[ETH_ALEN]; 99 u8 mac_addr[ETH_ALEN]; 100 }; 101 102 #ifdef CONFIG_RFS_ACCEL 103 /* enic_rfs_fltr_node - rfs filter node in hash table 104 * @@keys: IPv4 5 tuple 105 * @flow_id: flow_id of clsf filter provided by kernel 106 * @fltr_id: filter id of clsf filter returned by adaptor 107 * @rq_id: desired rq index 108 * @node: hlist_node 109 */ 110 struct enic_rfs_fltr_node { 111 struct flow_keys keys; 112 u32 flow_id; 113 u16 fltr_id; 114 u16 rq_id; 115 struct hlist_node node; 116 }; 117 118 /* enic_rfs_flw_tbl - rfs flow table 119 * @max: Maximum number of filters vNIC supports 120 * @free: Number of free filters available 121 * @toclean: hash table index to clean next 122 * @ht_head: hash table list head 123 * @lock: spin lock 124 * @rfs_may_expire: timer function for enic_rps_may_expire_flow 125 */ 126 struct enic_rfs_flw_tbl { 127 u16 max; 128 int free; 129 130 #define ENIC_RFS_FLW_BITSHIFT (10) 131 #define ENIC_RFS_FLW_MASK ((1 << ENIC_RFS_FLW_BITSHIFT) - 1) 132 u16 toclean:ENIC_RFS_FLW_BITSHIFT; 133 struct hlist_head ht_head[1 << ENIC_RFS_FLW_BITSHIFT]; 134 spinlock_t lock; 135 struct timer_list rfs_may_expire; 136 }; 137 138 #endif /* CONFIG_RFS_ACCEL */ 139 140 /* Per-instance private data structure */ 141 struct enic { 142 struct net_device *netdev; 143 struct pci_dev *pdev; 144 struct vnic_enet_config config; 145 struct vnic_dev_bar bar[ENIC_BARS_MAX]; 146 struct vnic_dev *vdev; 147 struct timer_list notify_timer; 148 struct work_struct reset; 149 struct work_struct change_mtu_work; 150 struct msix_entry msix_entry[ENIC_INTR_MAX]; 151 struct enic_msix_entry msix[ENIC_INTR_MAX]; 152 u32 msg_enable; 153 spinlock_t devcmd_lock; 154 u8 mac_addr[ETH_ALEN]; 155 unsigned int flags; 156 unsigned int priv_flags; 157 unsigned int mc_count; 158 unsigned int uc_count; 159 u32 port_mtu; 160 struct enic_rx_coal rx_coalesce_setting; 161 u32 rx_coalesce_usecs; 162 u32 tx_coalesce_usecs; 163 #ifdef CONFIG_PCI_IOV 164 u16 num_vfs; 165 #endif 166 spinlock_t enic_api_lock; 167 struct enic_port_profile *pp; 168 169 /* work queue cache line section */ 170 ____cacheline_aligned struct vnic_wq wq[ENIC_WQ_MAX]; 171 spinlock_t wq_lock[ENIC_WQ_MAX]; 172 unsigned int wq_count; 173 u16 loop_enable; 174 u16 loop_tag; 175 176 /* receive queue cache line section */ 177 ____cacheline_aligned struct vnic_rq rq[ENIC_RQ_MAX]; 178 unsigned int rq_count; 179 u64 rq_truncated_pkts; 180 u64 rq_bad_fcs; 181 struct napi_struct napi[ENIC_RQ_MAX + ENIC_WQ_MAX]; 182 183 /* interrupt resource cache line section */ 184 ____cacheline_aligned struct vnic_intr intr[ENIC_INTR_MAX]; 185 unsigned int intr_count; 186 u32 __iomem *legacy_pba; /* memory-mapped */ 187 188 /* completion queue cache line section */ 189 ____cacheline_aligned struct vnic_cq cq[ENIC_CQ_MAX]; 190 unsigned int cq_count; 191 #ifdef CONFIG_RFS_ACCEL 192 struct enic_rfs_flw_tbl rfs_h; 193 #endif 194 }; 195 196 static inline struct device *enic_get_dev(struct enic *enic) 197 { 198 return &(enic->pdev->dev); 199 } 200 201 static inline unsigned int enic_cq_rq(struct enic *enic, unsigned int rq) 202 { 203 return rq; 204 } 205 206 static inline unsigned int enic_cq_wq(struct enic *enic, unsigned int wq) 207 { 208 return enic->rq_count + wq; 209 } 210 211 static inline unsigned int enic_legacy_io_intr(void) 212 { 213 return 0; 214 } 215 216 static inline unsigned int enic_legacy_err_intr(void) 217 { 218 return 1; 219 } 220 221 static inline unsigned int enic_legacy_notify_intr(void) 222 { 223 return 2; 224 } 225 226 static inline unsigned int enic_msix_rq_intr(struct enic *enic, 227 unsigned int rq) 228 { 229 return enic->cq[enic_cq_rq(enic, rq)].interrupt_offset; 230 } 231 232 static inline unsigned int enic_msix_wq_intr(struct enic *enic, 233 unsigned int wq) 234 { 235 return enic->cq[enic_cq_wq(enic, wq)].interrupt_offset; 236 } 237 238 static inline unsigned int enic_msix_err_intr(struct enic *enic) 239 { 240 return enic->rq_count + enic->wq_count; 241 } 242 243 static inline unsigned int enic_msix_notify_intr(struct enic *enic) 244 { 245 return enic->rq_count + enic->wq_count + 1; 246 } 247 248 void enic_reset_addr_lists(struct enic *enic); 249 int enic_sriov_enabled(struct enic *enic); 250 int enic_is_valid_vf(struct enic *enic, int vf); 251 int enic_is_dynamic(struct enic *enic); 252 void enic_set_ethtool_ops(struct net_device *netdev); 253 254 #endif /* _ENIC_H_ */ 255