1 /* 2 * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved. 3 * Copyright 2007 Nuova Systems, Inc. All rights reserved. 4 * 5 * This program is free software; you may redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; version 2 of the License. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 10 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 11 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 12 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 13 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 14 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 15 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 16 * SOFTWARE. 17 * 18 */ 19 20 #ifndef _ENIC_H_ 21 #define _ENIC_H_ 22 23 #include "vnic_enet.h" 24 #include "vnic_dev.h" 25 #include "vnic_wq.h" 26 #include "vnic_rq.h" 27 #include "vnic_cq.h" 28 #include "vnic_intr.h" 29 #include "vnic_stats.h" 30 #include "vnic_nic.h" 31 #include "vnic_rss.h" 32 #include <linux/irq.h> 33 34 #define DRV_NAME "enic" 35 #define DRV_DESCRIPTION "Cisco VIC Ethernet NIC Driver" 36 #define DRV_VERSION "2.1.1.50" 37 #define DRV_COPYRIGHT "Copyright 2008-2013 Cisco Systems, Inc" 38 39 #define ENIC_BARS_MAX 6 40 41 #define ENIC_WQ_MAX 8 42 #define ENIC_RQ_MAX 8 43 #define ENIC_CQ_MAX (ENIC_WQ_MAX + ENIC_RQ_MAX) 44 #define ENIC_INTR_MAX (ENIC_CQ_MAX + 2) 45 46 #define ENIC_AIC_LARGE_PKT_DIFF 3 47 48 struct enic_msix_entry { 49 int requested; 50 char devname[IFNAMSIZ]; 51 irqreturn_t (*isr)(int, void *); 52 void *devid; 53 }; 54 55 /* Store only the lower range. Higher range is given by fw. */ 56 struct enic_intr_mod_range { 57 u32 small_pkt_range_start; 58 u32 large_pkt_range_start; 59 }; 60 61 struct enic_intr_mod_table { 62 u32 rx_rate; 63 u32 range_percent; 64 }; 65 66 #define ENIC_MAX_LINK_SPEEDS 3 67 #define ENIC_LINK_SPEED_10G 10000 68 #define ENIC_LINK_SPEED_4G 4000 69 #define ENIC_LINK_40G_INDEX 2 70 #define ENIC_LINK_10G_INDEX 1 71 #define ENIC_LINK_4G_INDEX 0 72 #define ENIC_RX_COALESCE_RANGE_END 125 73 #define ENIC_AIC_TS_BREAK 100 74 75 struct enic_rx_coal { 76 u32 small_pkt_range_start; 77 u32 large_pkt_range_start; 78 u32 range_end; 79 u32 use_adaptive_rx_coalesce; 80 }; 81 82 /* priv_flags */ 83 #define ENIC_SRIOV_ENABLED (1 << 0) 84 85 /* enic port profile set flags */ 86 #define ENIC_PORT_REQUEST_APPLIED (1 << 0) 87 #define ENIC_SET_REQUEST (1 << 1) 88 #define ENIC_SET_NAME (1 << 2) 89 #define ENIC_SET_INSTANCE (1 << 3) 90 #define ENIC_SET_HOST (1 << 4) 91 92 struct enic_port_profile { 93 u32 set; 94 u8 request; 95 char name[PORT_PROFILE_MAX]; 96 u8 instance_uuid[PORT_UUID_MAX]; 97 u8 host_uuid[PORT_UUID_MAX]; 98 u8 vf_mac[ETH_ALEN]; 99 u8 mac_addr[ETH_ALEN]; 100 }; 101 102 /* Per-instance private data structure */ 103 struct enic { 104 struct net_device *netdev; 105 struct pci_dev *pdev; 106 struct vnic_enet_config config; 107 struct vnic_dev_bar bar[ENIC_BARS_MAX]; 108 struct vnic_dev *vdev; 109 struct timer_list notify_timer; 110 struct work_struct reset; 111 struct work_struct change_mtu_work; 112 struct msix_entry msix_entry[ENIC_INTR_MAX]; 113 struct enic_msix_entry msix[ENIC_INTR_MAX]; 114 u32 msg_enable; 115 spinlock_t devcmd_lock; 116 u8 mac_addr[ETH_ALEN]; 117 u8 mc_addr[ENIC_MULTICAST_PERFECT_FILTERS][ETH_ALEN]; 118 u8 uc_addr[ENIC_UNICAST_PERFECT_FILTERS][ETH_ALEN]; 119 unsigned int flags; 120 unsigned int priv_flags; 121 unsigned int mc_count; 122 unsigned int uc_count; 123 u32 port_mtu; 124 struct enic_rx_coal rx_coalesce_setting; 125 u32 rx_coalesce_usecs; 126 u32 tx_coalesce_usecs; 127 #ifdef CONFIG_PCI_IOV 128 u16 num_vfs; 129 #endif 130 spinlock_t enic_api_lock; 131 struct enic_port_profile *pp; 132 133 /* work queue cache line section */ 134 ____cacheline_aligned struct vnic_wq wq[ENIC_WQ_MAX]; 135 spinlock_t wq_lock[ENIC_WQ_MAX]; 136 unsigned int wq_count; 137 u16 loop_enable; 138 u16 loop_tag; 139 140 /* receive queue cache line section */ 141 ____cacheline_aligned struct vnic_rq rq[ENIC_RQ_MAX]; 142 unsigned int rq_count; 143 u64 rq_truncated_pkts; 144 u64 rq_bad_fcs; 145 struct napi_struct napi[ENIC_RQ_MAX]; 146 147 /* interrupt resource cache line section */ 148 ____cacheline_aligned struct vnic_intr intr[ENIC_INTR_MAX]; 149 unsigned int intr_count; 150 u32 __iomem *legacy_pba; /* memory-mapped */ 151 152 /* completion queue cache line section */ 153 ____cacheline_aligned struct vnic_cq cq[ENIC_CQ_MAX]; 154 unsigned int cq_count; 155 }; 156 157 static inline struct device *enic_get_dev(struct enic *enic) 158 { 159 return &(enic->pdev->dev); 160 } 161 162 static inline unsigned int enic_cq_rq(struct enic *enic, unsigned int rq) 163 { 164 return rq; 165 } 166 167 static inline unsigned int enic_cq_wq(struct enic *enic, unsigned int wq) 168 { 169 return enic->rq_count + wq; 170 } 171 172 static inline unsigned int enic_legacy_io_intr(void) 173 { 174 return 0; 175 } 176 177 static inline unsigned int enic_legacy_err_intr(void) 178 { 179 return 1; 180 } 181 182 static inline unsigned int enic_legacy_notify_intr(void) 183 { 184 return 2; 185 } 186 187 static inline unsigned int enic_msix_rq_intr(struct enic *enic, 188 unsigned int rq) 189 { 190 return enic->cq[enic_cq_rq(enic, rq)].interrupt_offset; 191 } 192 193 static inline unsigned int enic_msix_wq_intr(struct enic *enic, 194 unsigned int wq) 195 { 196 return enic->cq[enic_cq_wq(enic, wq)].interrupt_offset; 197 } 198 199 static inline unsigned int enic_msix_err_intr(struct enic *enic) 200 { 201 return enic->rq_count + enic->wq_count; 202 } 203 204 static inline unsigned int enic_msix_notify_intr(struct enic *enic) 205 { 206 return enic->rq_count + enic->wq_count + 1; 207 } 208 209 void enic_reset_addr_lists(struct enic *enic); 210 int enic_sriov_enabled(struct enic *enic); 211 int enic_is_valid_vf(struct enic *enic, int vf); 212 int enic_is_dynamic(struct enic *enic); 213 void enic_set_ethtool_ops(struct net_device *netdev); 214 215 #endif /* _ENIC_H_ */ 216