1 /* 2 * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved. 3 * Copyright 2007 Nuova Systems, Inc. All rights reserved. 4 * 5 * This program is free software; you may redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; version 2 of the License. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 10 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 11 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 12 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 13 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 14 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 15 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 16 * SOFTWARE. 17 * 18 */ 19 20 #ifndef _ENIC_H_ 21 #define _ENIC_H_ 22 23 #include "vnic_enet.h" 24 #include "vnic_dev.h" 25 #include "vnic_wq.h" 26 #include "vnic_rq.h" 27 #include "vnic_cq.h" 28 #include "vnic_intr.h" 29 #include "vnic_stats.h" 30 #include "vnic_nic.h" 31 #include "vnic_rss.h" 32 #include <linux/irq.h> 33 34 #define DRV_NAME "enic" 35 #define DRV_DESCRIPTION "Cisco VIC Ethernet NIC Driver" 36 #define DRV_VERSION "2.3.0.45" 37 #define DRV_COPYRIGHT "Copyright 2008-2013 Cisco Systems, Inc" 38 39 #define ENIC_BARS_MAX 6 40 41 #define ENIC_WQ_MAX 8 42 #define ENIC_RQ_MAX 8 43 #define ENIC_CQ_MAX (ENIC_WQ_MAX + ENIC_RQ_MAX) 44 #define ENIC_INTR_MAX (ENIC_CQ_MAX + 2) 45 46 #define ENIC_WQ_NAPI_BUDGET 256 47 48 #define ENIC_AIC_LARGE_PKT_DIFF 3 49 50 struct enic_msix_entry { 51 int requested; 52 char devname[IFNAMSIZ + 8]; 53 irqreturn_t (*isr)(int, void *); 54 void *devid; 55 cpumask_var_t affinity_mask; 56 }; 57 58 /* Store only the lower range. Higher range is given by fw. */ 59 struct enic_intr_mod_range { 60 u32 small_pkt_range_start; 61 u32 large_pkt_range_start; 62 }; 63 64 struct enic_intr_mod_table { 65 u32 rx_rate; 66 u32 range_percent; 67 }; 68 69 #define ENIC_MAX_LINK_SPEEDS 3 70 #define ENIC_LINK_SPEED_10G 10000 71 #define ENIC_LINK_SPEED_4G 4000 72 #define ENIC_LINK_40G_INDEX 2 73 #define ENIC_LINK_10G_INDEX 1 74 #define ENIC_LINK_4G_INDEX 0 75 #define ENIC_RX_COALESCE_RANGE_END 125 76 #define ENIC_AIC_TS_BREAK 100 77 78 struct enic_rx_coal { 79 u32 small_pkt_range_start; 80 u32 large_pkt_range_start; 81 u32 range_end; 82 u32 use_adaptive_rx_coalesce; 83 }; 84 85 /* priv_flags */ 86 #define ENIC_SRIOV_ENABLED (1 << 0) 87 88 /* enic port profile set flags */ 89 #define ENIC_PORT_REQUEST_APPLIED (1 << 0) 90 #define ENIC_SET_REQUEST (1 << 1) 91 #define ENIC_SET_NAME (1 << 2) 92 #define ENIC_SET_INSTANCE (1 << 3) 93 #define ENIC_SET_HOST (1 << 4) 94 95 struct enic_port_profile { 96 u32 set; 97 u8 request; 98 char name[PORT_PROFILE_MAX]; 99 u8 instance_uuid[PORT_UUID_MAX]; 100 u8 host_uuid[PORT_UUID_MAX]; 101 u8 vf_mac[ETH_ALEN]; 102 u8 mac_addr[ETH_ALEN]; 103 }; 104 105 /* enic_rfs_fltr_node - rfs filter node in hash table 106 * @@keys: IPv4 5 tuple 107 * @flow_id: flow_id of clsf filter provided by kernel 108 * @fltr_id: filter id of clsf filter returned by adaptor 109 * @rq_id: desired rq index 110 * @node: hlist_node 111 */ 112 struct enic_rfs_fltr_node { 113 struct flow_keys keys; 114 u32 flow_id; 115 u16 fltr_id; 116 u16 rq_id; 117 struct hlist_node node; 118 }; 119 120 /* enic_rfs_flw_tbl - rfs flow table 121 * @max: Maximum number of filters vNIC supports 122 * @free: Number of free filters available 123 * @toclean: hash table index to clean next 124 * @ht_head: hash table list head 125 * @lock: spin lock 126 * @rfs_may_expire: timer function for enic_rps_may_expire_flow 127 */ 128 struct enic_rfs_flw_tbl { 129 u16 max; 130 int free; 131 132 #define ENIC_RFS_FLW_BITSHIFT (10) 133 #define ENIC_RFS_FLW_MASK ((1 << ENIC_RFS_FLW_BITSHIFT) - 1) 134 u16 toclean:ENIC_RFS_FLW_BITSHIFT; 135 struct hlist_head ht_head[1 << ENIC_RFS_FLW_BITSHIFT]; 136 spinlock_t lock; 137 struct timer_list rfs_may_expire; 138 }; 139 140 struct vxlan_offload { 141 u16 vxlan_udp_port_number; 142 u8 patch_level; 143 }; 144 145 /* Per-instance private data structure */ 146 struct enic { 147 struct net_device *netdev; 148 struct pci_dev *pdev; 149 struct vnic_enet_config config; 150 struct vnic_dev_bar bar[ENIC_BARS_MAX]; 151 struct vnic_dev *vdev; 152 struct timer_list notify_timer; 153 struct work_struct reset; 154 struct work_struct tx_hang_reset; 155 struct work_struct change_mtu_work; 156 struct msix_entry msix_entry[ENIC_INTR_MAX]; 157 struct enic_msix_entry msix[ENIC_INTR_MAX]; 158 u32 msg_enable; 159 spinlock_t devcmd_lock; 160 u8 mac_addr[ETH_ALEN]; 161 unsigned int flags; 162 unsigned int priv_flags; 163 unsigned int mc_count; 164 unsigned int uc_count; 165 u32 port_mtu; 166 struct enic_rx_coal rx_coalesce_setting; 167 u32 rx_coalesce_usecs; 168 u32 tx_coalesce_usecs; 169 #ifdef CONFIG_PCI_IOV 170 u16 num_vfs; 171 #endif 172 spinlock_t enic_api_lock; 173 struct enic_port_profile *pp; 174 175 /* work queue cache line section */ 176 ____cacheline_aligned struct vnic_wq wq[ENIC_WQ_MAX]; 177 spinlock_t wq_lock[ENIC_WQ_MAX]; 178 unsigned int wq_count; 179 u16 loop_enable; 180 u16 loop_tag; 181 182 /* receive queue cache line section */ 183 ____cacheline_aligned struct vnic_rq rq[ENIC_RQ_MAX]; 184 unsigned int rq_count; 185 struct vxlan_offload vxlan; 186 u64 rq_truncated_pkts; 187 u64 rq_bad_fcs; 188 struct napi_struct napi[ENIC_RQ_MAX + ENIC_WQ_MAX]; 189 190 /* interrupt resource cache line section */ 191 ____cacheline_aligned struct vnic_intr intr[ENIC_INTR_MAX]; 192 unsigned int intr_count; 193 u32 __iomem *legacy_pba; /* memory-mapped */ 194 195 /* completion queue cache line section */ 196 ____cacheline_aligned struct vnic_cq cq[ENIC_CQ_MAX]; 197 unsigned int cq_count; 198 struct enic_rfs_flw_tbl rfs_h; 199 u32 rx_copybreak; 200 u8 rss_key[ENIC_RSS_LEN]; 201 struct vnic_gen_stats gen_stats; 202 }; 203 204 static inline struct net_device *vnic_get_netdev(struct vnic_dev *vdev) 205 { 206 struct enic *enic = vdev->priv; 207 208 return enic->netdev; 209 } 210 211 /* wrappers function for kernel log 212 */ 213 #define vdev_err(vdev, fmt, ...) \ 214 dev_err(&(vdev)->pdev->dev, fmt, ##__VA_ARGS__) 215 #define vdev_warn(vdev, fmt, ...) \ 216 dev_warn(&(vdev)->pdev->dev, fmt, ##__VA_ARGS__) 217 #define vdev_info(vdev, fmt, ...) \ 218 dev_info(&(vdev)->pdev->dev, fmt, ##__VA_ARGS__) 219 220 #define vdev_neterr(vdev, fmt, ...) \ 221 netdev_err(vnic_get_netdev(vdev), fmt, ##__VA_ARGS__) 222 #define vdev_netwarn(vdev, fmt, ...) \ 223 netdev_warn(vnic_get_netdev(vdev), fmt, ##__VA_ARGS__) 224 #define vdev_netinfo(vdev, fmt, ...) \ 225 netdev_info(vnic_get_netdev(vdev), fmt, ##__VA_ARGS__) 226 227 static inline struct device *enic_get_dev(struct enic *enic) 228 { 229 return &(enic->pdev->dev); 230 } 231 232 static inline unsigned int enic_cq_rq(struct enic *enic, unsigned int rq) 233 { 234 return rq; 235 } 236 237 static inline unsigned int enic_cq_wq(struct enic *enic, unsigned int wq) 238 { 239 return enic->rq_count + wq; 240 } 241 242 static inline unsigned int enic_legacy_io_intr(void) 243 { 244 return 0; 245 } 246 247 static inline unsigned int enic_legacy_err_intr(void) 248 { 249 return 1; 250 } 251 252 static inline unsigned int enic_legacy_notify_intr(void) 253 { 254 return 2; 255 } 256 257 static inline unsigned int enic_msix_rq_intr(struct enic *enic, 258 unsigned int rq) 259 { 260 return enic->cq[enic_cq_rq(enic, rq)].interrupt_offset; 261 } 262 263 static inline unsigned int enic_msix_wq_intr(struct enic *enic, 264 unsigned int wq) 265 { 266 return enic->cq[enic_cq_wq(enic, wq)].interrupt_offset; 267 } 268 269 static inline unsigned int enic_msix_err_intr(struct enic *enic) 270 { 271 return enic->rq_count + enic->wq_count; 272 } 273 274 static inline unsigned int enic_msix_notify_intr(struct enic *enic) 275 { 276 return enic->rq_count + enic->wq_count + 1; 277 } 278 279 static inline bool enic_is_err_intr(struct enic *enic, int intr) 280 { 281 switch (vnic_dev_get_intr_mode(enic->vdev)) { 282 case VNIC_DEV_INTR_MODE_INTX: 283 return intr == enic_legacy_err_intr(); 284 case VNIC_DEV_INTR_MODE_MSIX: 285 return intr == enic_msix_err_intr(enic); 286 case VNIC_DEV_INTR_MODE_MSI: 287 default: 288 return false; 289 } 290 } 291 292 static inline bool enic_is_notify_intr(struct enic *enic, int intr) 293 { 294 switch (vnic_dev_get_intr_mode(enic->vdev)) { 295 case VNIC_DEV_INTR_MODE_INTX: 296 return intr == enic_legacy_notify_intr(); 297 case VNIC_DEV_INTR_MODE_MSIX: 298 return intr == enic_msix_notify_intr(enic); 299 case VNIC_DEV_INTR_MODE_MSI: 300 default: 301 return false; 302 } 303 } 304 305 static inline int enic_dma_map_check(struct enic *enic, dma_addr_t dma_addr) 306 { 307 if (unlikely(pci_dma_mapping_error(enic->pdev, dma_addr))) { 308 net_warn_ratelimited("%s: PCI dma mapping failed!\n", 309 enic->netdev->name); 310 enic->gen_stats.dma_map_error++; 311 312 return -ENOMEM; 313 } 314 315 return 0; 316 } 317 318 void enic_reset_addr_lists(struct enic *enic); 319 int enic_sriov_enabled(struct enic *enic); 320 int enic_is_valid_vf(struct enic *enic, int vf); 321 int enic_is_dynamic(struct enic *enic); 322 void enic_set_ethtool_ops(struct net_device *netdev); 323 int __enic_set_rsskey(struct enic *enic); 324 325 #endif /* _ENIC_H_ */ 326