1*e6550b3eSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2a6a5580cSJeff Kirsher /* 3a6a5580cSJeff Kirsher * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved. 4a6a5580cSJeff Kirsher * Copyright 2007 Nuova Systems, Inc. All rights reserved. 5a6a5580cSJeff Kirsher */ 6a6a5580cSJeff Kirsher 7a6a5580cSJeff Kirsher #ifndef _ENIC_H_ 8a6a5580cSJeff Kirsher #define _ENIC_H_ 9a6a5580cSJeff Kirsher 10a6a5580cSJeff Kirsher #include "vnic_enet.h" 11a6a5580cSJeff Kirsher #include "vnic_dev.h" 12a6a5580cSJeff Kirsher #include "vnic_wq.h" 13a6a5580cSJeff Kirsher #include "vnic_rq.h" 14a6a5580cSJeff Kirsher #include "vnic_cq.h" 15a6a5580cSJeff Kirsher #include "vnic_intr.h" 16a6a5580cSJeff Kirsher #include "vnic_stats.h" 17a6a5580cSJeff Kirsher #include "vnic_nic.h" 18a6a5580cSJeff Kirsher #include "vnic_rss.h" 19fef1f07cSJosh Boyer #include <linux/irq.h> 20a6a5580cSJeff Kirsher 21a6a5580cSJeff Kirsher #define DRV_NAME "enic" 22a6a5580cSJeff Kirsher #define DRV_DESCRIPTION "Cisco VIC Ethernet NIC Driver" 23a6a5580cSJeff Kirsher 24a6a5580cSJeff Kirsher #define ENIC_BARS_MAX 6 25a6a5580cSJeff Kirsher 26822473b6Sgovindarajulu.v #define ENIC_WQ_MAX 8 2763da93d9SNeel Patel #define ENIC_RQ_MAX 8 28a6a5580cSJeff Kirsher #define ENIC_CQ_MAX (ENIC_WQ_MAX + ENIC_RQ_MAX) 29a6a5580cSJeff Kirsher #define ENIC_INTR_MAX (ENIC_CQ_MAX + 2) 30a6a5580cSJeff Kirsher 3118feb871SGovindarajulu Varadarajan #define ENIC_WQ_NAPI_BUDGET 256 3218feb871SGovindarajulu Varadarajan 337c2ce6e6SSujith Sankar #define ENIC_AIC_LARGE_PKT_DIFF 3 347c2ce6e6SSujith Sankar 35a6a5580cSJeff Kirsher struct enic_msix_entry { 36a6a5580cSJeff Kirsher int requested; 377044f429SGovindarajulu Varadarajan char devname[IFNAMSIZ + 8]; 38a6a5580cSJeff Kirsher irqreturn_t (*isr)(int, void *); 39a6a5580cSJeff Kirsher void *devid; 40322cf7e3SGovindarajulu Varadarajan cpumask_var_t affinity_mask; 41a6a5580cSJeff Kirsher }; 42a6a5580cSJeff Kirsher 437c2ce6e6SSujith Sankar /* Store only the lower range. Higher range is given by fw. */ 447c2ce6e6SSujith Sankar struct enic_intr_mod_range { 457c2ce6e6SSujith Sankar u32 small_pkt_range_start; 467c2ce6e6SSujith Sankar u32 large_pkt_range_start; 477c2ce6e6SSujith Sankar }; 487c2ce6e6SSujith Sankar 497c2ce6e6SSujith Sankar struct enic_intr_mod_table { 507c2ce6e6SSujith Sankar u32 rx_rate; 517c2ce6e6SSujith Sankar u32 range_percent; 527c2ce6e6SSujith Sankar }; 537c2ce6e6SSujith Sankar 547c2ce6e6SSujith Sankar #define ENIC_MAX_LINK_SPEEDS 3 557c2ce6e6SSujith Sankar #define ENIC_LINK_SPEED_10G 10000 567c2ce6e6SSujith Sankar #define ENIC_LINK_SPEED_4G 4000 577c2ce6e6SSujith Sankar #define ENIC_LINK_40G_INDEX 2 587c2ce6e6SSujith Sankar #define ENIC_LINK_10G_INDEX 1 597c2ce6e6SSujith Sankar #define ENIC_LINK_4G_INDEX 0 607c2ce6e6SSujith Sankar #define ENIC_RX_COALESCE_RANGE_END 125 617c2ce6e6SSujith Sankar #define ENIC_AIC_TS_BREAK 100 627c2ce6e6SSujith Sankar 637c2ce6e6SSujith Sankar struct enic_rx_coal { 647c2ce6e6SSujith Sankar u32 small_pkt_range_start; 657c2ce6e6SSujith Sankar u32 large_pkt_range_start; 667c2ce6e6SSujith Sankar u32 range_end; 677c2ce6e6SSujith Sankar u32 use_adaptive_rx_coalesce; 687c2ce6e6SSujith Sankar }; 697c2ce6e6SSujith Sankar 708749b427SRoopa Prabhu /* priv_flags */ 718749b427SRoopa Prabhu #define ENIC_SRIOV_ENABLED (1 << 0) 728749b427SRoopa Prabhu 738749b427SRoopa Prabhu /* enic port profile set flags */ 74a6a5580cSJeff Kirsher #define ENIC_PORT_REQUEST_APPLIED (1 << 0) 75a6a5580cSJeff Kirsher #define ENIC_SET_REQUEST (1 << 1) 76a6a5580cSJeff Kirsher #define ENIC_SET_NAME (1 << 2) 77a6a5580cSJeff Kirsher #define ENIC_SET_INSTANCE (1 << 3) 78a6a5580cSJeff Kirsher #define ENIC_SET_HOST (1 << 4) 79a6a5580cSJeff Kirsher 80a6a5580cSJeff Kirsher struct enic_port_profile { 81a6a5580cSJeff Kirsher u32 set; 82a6a5580cSJeff Kirsher u8 request; 83a6a5580cSJeff Kirsher char name[PORT_PROFILE_MAX]; 84a6a5580cSJeff Kirsher u8 instance_uuid[PORT_UUID_MAX]; 85a6a5580cSJeff Kirsher u8 host_uuid[PORT_UUID_MAX]; 86a6a5580cSJeff Kirsher u8 vf_mac[ETH_ALEN]; 87a6a5580cSJeff Kirsher u8 mac_addr[ETH_ALEN]; 88a6a5580cSJeff Kirsher }; 89a6a5580cSJeff Kirsher 90a145df23SGovindarajulu Varadarajan /* enic_rfs_fltr_node - rfs filter node in hash table 91a145df23SGovindarajulu Varadarajan * @@keys: IPv4 5 tuple 92a145df23SGovindarajulu Varadarajan * @flow_id: flow_id of clsf filter provided by kernel 93a145df23SGovindarajulu Varadarajan * @fltr_id: filter id of clsf filter returned by adaptor 94a145df23SGovindarajulu Varadarajan * @rq_id: desired rq index 95a145df23SGovindarajulu Varadarajan * @node: hlist_node 96a145df23SGovindarajulu Varadarajan */ 97a145df23SGovindarajulu Varadarajan struct enic_rfs_fltr_node { 98a145df23SGovindarajulu Varadarajan struct flow_keys keys; 99a145df23SGovindarajulu Varadarajan u32 flow_id; 100a145df23SGovindarajulu Varadarajan u16 fltr_id; 101a145df23SGovindarajulu Varadarajan u16 rq_id; 102a145df23SGovindarajulu Varadarajan struct hlist_node node; 103a145df23SGovindarajulu Varadarajan }; 104a145df23SGovindarajulu Varadarajan 105a145df23SGovindarajulu Varadarajan /* enic_rfs_flw_tbl - rfs flow table 106a145df23SGovindarajulu Varadarajan * @max: Maximum number of filters vNIC supports 107a145df23SGovindarajulu Varadarajan * @free: Number of free filters available 108a145df23SGovindarajulu Varadarajan * @toclean: hash table index to clean next 109a145df23SGovindarajulu Varadarajan * @ht_head: hash table list head 110a145df23SGovindarajulu Varadarajan * @lock: spin lock 111a145df23SGovindarajulu Varadarajan * @rfs_may_expire: timer function for enic_rps_may_expire_flow 112a145df23SGovindarajulu Varadarajan */ 113a145df23SGovindarajulu Varadarajan struct enic_rfs_flw_tbl { 114a145df23SGovindarajulu Varadarajan u16 max; 115a145df23SGovindarajulu Varadarajan int free; 116a145df23SGovindarajulu Varadarajan 117a145df23SGovindarajulu Varadarajan #define ENIC_RFS_FLW_BITSHIFT (10) 118a145df23SGovindarajulu Varadarajan #define ENIC_RFS_FLW_MASK ((1 << ENIC_RFS_FLW_BITSHIFT) - 1) 119a145df23SGovindarajulu Varadarajan u16 toclean:ENIC_RFS_FLW_BITSHIFT; 120a145df23SGovindarajulu Varadarajan struct hlist_head ht_head[1 << ENIC_RFS_FLW_BITSHIFT]; 121a145df23SGovindarajulu Varadarajan spinlock_t lock; 122a145df23SGovindarajulu Varadarajan struct timer_list rfs_may_expire; 123a145df23SGovindarajulu Varadarajan }; 124a145df23SGovindarajulu Varadarajan 125257e7382SGovindarajulu Varadarajan struct vxlan_offload { 126257e7382SGovindarajulu Varadarajan u16 vxlan_udp_port_number; 127257e7382SGovindarajulu Varadarajan u8 patch_level; 128d1179094SGovindarajulu Varadarajan u8 flags; 129257e7382SGovindarajulu Varadarajan }; 130257e7382SGovindarajulu Varadarajan 131a6a5580cSJeff Kirsher /* Per-instance private data structure */ 132a6a5580cSJeff Kirsher struct enic { 133a6a5580cSJeff Kirsher struct net_device *netdev; 134a6a5580cSJeff Kirsher struct pci_dev *pdev; 135a6a5580cSJeff Kirsher struct vnic_enet_config config; 136a6a5580cSJeff Kirsher struct vnic_dev_bar bar[ENIC_BARS_MAX]; 137a6a5580cSJeff Kirsher struct vnic_dev *vdev; 138a6a5580cSJeff Kirsher struct timer_list notify_timer; 139a6a5580cSJeff Kirsher struct work_struct reset; 140937317c7SGovindarajulu Varadarajan struct work_struct tx_hang_reset; 141a6a5580cSJeff Kirsher struct work_struct change_mtu_work; 142a6a5580cSJeff Kirsher struct msix_entry msix_entry[ENIC_INTR_MAX]; 143a6a5580cSJeff Kirsher struct enic_msix_entry msix[ENIC_INTR_MAX]; 144a6a5580cSJeff Kirsher u32 msg_enable; 145a6a5580cSJeff Kirsher spinlock_t devcmd_lock; 146a6a5580cSJeff Kirsher u8 mac_addr[ETH_ALEN]; 147a6a5580cSJeff Kirsher unsigned int flags; 1488749b427SRoopa Prabhu unsigned int priv_flags; 149a6a5580cSJeff Kirsher unsigned int mc_count; 150a6a5580cSJeff Kirsher unsigned int uc_count; 151a6a5580cSJeff Kirsher u32 port_mtu; 1527c2ce6e6SSujith Sankar struct enic_rx_coal rx_coalesce_setting; 153a6a5580cSJeff Kirsher u32 rx_coalesce_usecs; 154a6a5580cSJeff Kirsher u32 tx_coalesce_usecs; 1558749b427SRoopa Prabhu #ifdef CONFIG_PCI_IOV 156413708bbSDan Carpenter u16 num_vfs; 1578749b427SRoopa Prabhu #endif 1580b038566SNeel Patel spinlock_t enic_api_lock; 159a53b59ecSThomas Gleixner bool enic_api_busy; 1603f192795SRoopa Prabhu struct enic_port_profile *pp; 161a6a5580cSJeff Kirsher 162a6a5580cSJeff Kirsher /* work queue cache line section */ 163a6a5580cSJeff Kirsher ____cacheline_aligned struct vnic_wq wq[ENIC_WQ_MAX]; 164a6a5580cSJeff Kirsher spinlock_t wq_lock[ENIC_WQ_MAX]; 165a6a5580cSJeff Kirsher unsigned int wq_count; 166a6a5580cSJeff Kirsher u16 loop_enable; 167a6a5580cSJeff Kirsher u16 loop_tag; 168a6a5580cSJeff Kirsher 169a6a5580cSJeff Kirsher /* receive queue cache line section */ 170a6a5580cSJeff Kirsher ____cacheline_aligned struct vnic_rq rq[ENIC_RQ_MAX]; 171a6a5580cSJeff Kirsher unsigned int rq_count; 172257e7382SGovindarajulu Varadarajan struct vxlan_offload vxlan; 173a6a5580cSJeff Kirsher u64 rq_truncated_pkts; 174a6a5580cSJeff Kirsher u64 rq_bad_fcs; 1754cfe8785SGovindarajulu Varadarajan struct napi_struct napi[ENIC_RQ_MAX + ENIC_WQ_MAX]; 176a6a5580cSJeff Kirsher 177a6a5580cSJeff Kirsher /* interrupt resource cache line section */ 178a6a5580cSJeff Kirsher ____cacheline_aligned struct vnic_intr intr[ENIC_INTR_MAX]; 179a6a5580cSJeff Kirsher unsigned int intr_count; 180a6a5580cSJeff Kirsher u32 __iomem *legacy_pba; /* memory-mapped */ 181a6a5580cSJeff Kirsher 182a6a5580cSJeff Kirsher /* completion queue cache line section */ 183a6a5580cSJeff Kirsher ____cacheline_aligned struct vnic_cq cq[ENIC_CQ_MAX]; 184a6a5580cSJeff Kirsher unsigned int cq_count; 185a145df23SGovindarajulu Varadarajan struct enic_rfs_flw_tbl rfs_h; 186a03bb56eSGovindarajulu Varadarajan u32 rx_copybreak; 1874f675eb2SGovindarajulu Varadarajan u8 rss_key[ENIC_RSS_LEN]; 18858feff07SGovindarajulu Varadarajan struct vnic_gen_stats gen_stats; 189a6a5580cSJeff Kirsher }; 190a6a5580cSJeff Kirsher 1916a3c2f83SGovindarajulu Varadarajan static inline struct net_device *vnic_get_netdev(struct vnic_dev *vdev) 1926a3c2f83SGovindarajulu Varadarajan { 1936a3c2f83SGovindarajulu Varadarajan struct enic *enic = vdev->priv; 1946a3c2f83SGovindarajulu Varadarajan 1956a3c2f83SGovindarajulu Varadarajan return enic->netdev; 1966a3c2f83SGovindarajulu Varadarajan } 1976a3c2f83SGovindarajulu Varadarajan 1986a3c2f83SGovindarajulu Varadarajan /* wrappers function for kernel log 1996a3c2f83SGovindarajulu Varadarajan */ 200e327f4e1SJoe Perches #define vdev_err(vdev, fmt, ...) \ 201e327f4e1SJoe Perches dev_err(&(vdev)->pdev->dev, fmt, ##__VA_ARGS__) 202e327f4e1SJoe Perches #define vdev_warn(vdev, fmt, ...) \ 203e327f4e1SJoe Perches dev_warn(&(vdev)->pdev->dev, fmt, ##__VA_ARGS__) 204e327f4e1SJoe Perches #define vdev_info(vdev, fmt, ...) \ 205e327f4e1SJoe Perches dev_info(&(vdev)->pdev->dev, fmt, ##__VA_ARGS__) 2066a3c2f83SGovindarajulu Varadarajan 207e327f4e1SJoe Perches #define vdev_neterr(vdev, fmt, ...) \ 208e327f4e1SJoe Perches netdev_err(vnic_get_netdev(vdev), fmt, ##__VA_ARGS__) 209e327f4e1SJoe Perches #define vdev_netwarn(vdev, fmt, ...) \ 210e327f4e1SJoe Perches netdev_warn(vnic_get_netdev(vdev), fmt, ##__VA_ARGS__) 211e327f4e1SJoe Perches #define vdev_netinfo(vdev, fmt, ...) \ 212e327f4e1SJoe Perches netdev_info(vnic_get_netdev(vdev), fmt, ##__VA_ARGS__) 2136a3c2f83SGovindarajulu Varadarajan 214a6a5580cSJeff Kirsher static inline struct device *enic_get_dev(struct enic *enic) 215a6a5580cSJeff Kirsher { 216a6a5580cSJeff Kirsher return &(enic->pdev->dev); 217a6a5580cSJeff Kirsher } 218a6a5580cSJeff Kirsher 219f13bbc2fSNeel Patel static inline unsigned int enic_cq_rq(struct enic *enic, unsigned int rq) 220f13bbc2fSNeel Patel { 221f13bbc2fSNeel Patel return rq; 222f13bbc2fSNeel Patel } 223f13bbc2fSNeel Patel 224f13bbc2fSNeel Patel static inline unsigned int enic_cq_wq(struct enic *enic, unsigned int wq) 225f13bbc2fSNeel Patel { 226f13bbc2fSNeel Patel return enic->rq_count + wq; 227f13bbc2fSNeel Patel } 228f13bbc2fSNeel Patel 229f13bbc2fSNeel Patel static inline unsigned int enic_legacy_io_intr(void) 230f13bbc2fSNeel Patel { 231f13bbc2fSNeel Patel return 0; 232f13bbc2fSNeel Patel } 233f13bbc2fSNeel Patel 234f13bbc2fSNeel Patel static inline unsigned int enic_legacy_err_intr(void) 235f13bbc2fSNeel Patel { 236f13bbc2fSNeel Patel return 1; 237f13bbc2fSNeel Patel } 238f13bbc2fSNeel Patel 239f13bbc2fSNeel Patel static inline unsigned int enic_legacy_notify_intr(void) 240f13bbc2fSNeel Patel { 241f13bbc2fSNeel Patel return 2; 242f13bbc2fSNeel Patel } 243f13bbc2fSNeel Patel 244f13bbc2fSNeel Patel static inline unsigned int enic_msix_rq_intr(struct enic *enic, 245f13bbc2fSNeel Patel unsigned int rq) 246f13bbc2fSNeel Patel { 247f13bbc2fSNeel Patel return enic->cq[enic_cq_rq(enic, rq)].interrupt_offset; 248f13bbc2fSNeel Patel } 249f13bbc2fSNeel Patel 250f13bbc2fSNeel Patel static inline unsigned int enic_msix_wq_intr(struct enic *enic, 251f13bbc2fSNeel Patel unsigned int wq) 252f13bbc2fSNeel Patel { 253f13bbc2fSNeel Patel return enic->cq[enic_cq_wq(enic, wq)].interrupt_offset; 254f13bbc2fSNeel Patel } 255f13bbc2fSNeel Patel 256f13bbc2fSNeel Patel static inline unsigned int enic_msix_err_intr(struct enic *enic) 257f13bbc2fSNeel Patel { 258f13bbc2fSNeel Patel return enic->rq_count + enic->wq_count; 259f13bbc2fSNeel Patel } 260f13bbc2fSNeel Patel 261f13bbc2fSNeel Patel static inline unsigned int enic_msix_notify_intr(struct enic *enic) 262f13bbc2fSNeel Patel { 263f13bbc2fSNeel Patel return enic->rq_count + enic->wq_count + 1; 264f13bbc2fSNeel Patel } 265f13bbc2fSNeel Patel 266322cf7e3SGovindarajulu Varadarajan static inline bool enic_is_err_intr(struct enic *enic, int intr) 267322cf7e3SGovindarajulu Varadarajan { 268322cf7e3SGovindarajulu Varadarajan switch (vnic_dev_get_intr_mode(enic->vdev)) { 269322cf7e3SGovindarajulu Varadarajan case VNIC_DEV_INTR_MODE_INTX: 270322cf7e3SGovindarajulu Varadarajan return intr == enic_legacy_err_intr(); 271322cf7e3SGovindarajulu Varadarajan case VNIC_DEV_INTR_MODE_MSIX: 272322cf7e3SGovindarajulu Varadarajan return intr == enic_msix_err_intr(enic); 273322cf7e3SGovindarajulu Varadarajan case VNIC_DEV_INTR_MODE_MSI: 274322cf7e3SGovindarajulu Varadarajan default: 275322cf7e3SGovindarajulu Varadarajan return false; 276322cf7e3SGovindarajulu Varadarajan } 277322cf7e3SGovindarajulu Varadarajan } 278322cf7e3SGovindarajulu Varadarajan 279322cf7e3SGovindarajulu Varadarajan static inline bool enic_is_notify_intr(struct enic *enic, int intr) 280322cf7e3SGovindarajulu Varadarajan { 281322cf7e3SGovindarajulu Varadarajan switch (vnic_dev_get_intr_mode(enic->vdev)) { 282322cf7e3SGovindarajulu Varadarajan case VNIC_DEV_INTR_MODE_INTX: 283322cf7e3SGovindarajulu Varadarajan return intr == enic_legacy_notify_intr(); 284322cf7e3SGovindarajulu Varadarajan case VNIC_DEV_INTR_MODE_MSIX: 285322cf7e3SGovindarajulu Varadarajan return intr == enic_msix_notify_intr(enic); 286322cf7e3SGovindarajulu Varadarajan case VNIC_DEV_INTR_MODE_MSI: 287322cf7e3SGovindarajulu Varadarajan default: 288322cf7e3SGovindarajulu Varadarajan return false; 289322cf7e3SGovindarajulu Varadarajan } 290322cf7e3SGovindarajulu Varadarajan } 291322cf7e3SGovindarajulu Varadarajan 292065df159SGovindarajulu Varadarajan static inline int enic_dma_map_check(struct enic *enic, dma_addr_t dma_addr) 293065df159SGovindarajulu Varadarajan { 29460c33202SChristophe JAILLET if (unlikely(dma_mapping_error(&enic->pdev->dev, dma_addr))) { 295065df159SGovindarajulu Varadarajan net_warn_ratelimited("%s: PCI dma mapping failed!\n", 296065df159SGovindarajulu Varadarajan enic->netdev->name); 29758feff07SGovindarajulu Varadarajan enic->gen_stats.dma_map_error++; 298065df159SGovindarajulu Varadarajan 299065df159SGovindarajulu Varadarajan return -ENOMEM; 300065df159SGovindarajulu Varadarajan } 301065df159SGovindarajulu Varadarajan 302065df159SGovindarajulu Varadarajan return 0; 303065df159SGovindarajulu Varadarajan } 304065df159SGovindarajulu Varadarajan 305a6a5580cSJeff Kirsher void enic_reset_addr_lists(struct enic *enic); 3068749b427SRoopa Prabhu int enic_sriov_enabled(struct enic *enic); 307889d13f5SRoopa Prabhu int enic_is_valid_vf(struct enic *enic, int vf); 3083f192795SRoopa Prabhu int enic_is_dynamic(struct enic *enic); 309f13bbc2fSNeel Patel void enic_set_ethtool_ops(struct net_device *netdev); 3104f675eb2SGovindarajulu Varadarajan int __enic_set_rsskey(struct enic *enic); 311a6a5580cSJeff Kirsher 312a6a5580cSJeff Kirsher #endif /* _ENIC_H_ */ 313