1a6a5580cSJeff Kirsher /* 2a6a5580cSJeff Kirsher * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved. 3a6a5580cSJeff Kirsher * Copyright 2007 Nuova Systems, Inc. All rights reserved. 4a6a5580cSJeff Kirsher * 5a6a5580cSJeff Kirsher * This program is free software; you may redistribute it and/or modify 6a6a5580cSJeff Kirsher * it under the terms of the GNU General Public License as published by 7a6a5580cSJeff Kirsher * the Free Software Foundation; version 2 of the License. 8a6a5580cSJeff Kirsher * 9a6a5580cSJeff Kirsher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 10a6a5580cSJeff Kirsher * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 11a6a5580cSJeff Kirsher * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 12a6a5580cSJeff Kirsher * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 13a6a5580cSJeff Kirsher * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 14a6a5580cSJeff Kirsher * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 15a6a5580cSJeff Kirsher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 16a6a5580cSJeff Kirsher * SOFTWARE. 17a6a5580cSJeff Kirsher * 18a6a5580cSJeff Kirsher */ 19a6a5580cSJeff Kirsher 20a6a5580cSJeff Kirsher #ifndef _ENIC_H_ 21a6a5580cSJeff Kirsher #define _ENIC_H_ 22a6a5580cSJeff Kirsher 23a6a5580cSJeff Kirsher #include "vnic_enet.h" 24a6a5580cSJeff Kirsher #include "vnic_dev.h" 25a6a5580cSJeff Kirsher #include "vnic_wq.h" 26a6a5580cSJeff Kirsher #include "vnic_rq.h" 27a6a5580cSJeff Kirsher #include "vnic_cq.h" 28a6a5580cSJeff Kirsher #include "vnic_intr.h" 29a6a5580cSJeff Kirsher #include "vnic_stats.h" 30a6a5580cSJeff Kirsher #include "vnic_nic.h" 31a6a5580cSJeff Kirsher #include "vnic_rss.h" 32fef1f07cSJosh Boyer #include <linux/irq.h> 33a6a5580cSJeff Kirsher 34a6a5580cSJeff Kirsher #define DRV_NAME "enic" 35a6a5580cSJeff Kirsher #define DRV_DESCRIPTION "Cisco VIC Ethernet NIC Driver" 36ed519b74SParvi Kaustubhi #define DRV_VERSION "2.3.0.45" 3792e2b469SNeel Patel #define DRV_COPYRIGHT "Copyright 2008-2013 Cisco Systems, Inc" 38a6a5580cSJeff Kirsher 39a6a5580cSJeff Kirsher #define ENIC_BARS_MAX 6 40a6a5580cSJeff Kirsher 41822473b6Sgovindarajulu.v #define ENIC_WQ_MAX 8 4263da93d9SNeel Patel #define ENIC_RQ_MAX 8 43a6a5580cSJeff Kirsher #define ENIC_CQ_MAX (ENIC_WQ_MAX + ENIC_RQ_MAX) 44a6a5580cSJeff Kirsher #define ENIC_INTR_MAX (ENIC_CQ_MAX + 2) 45a6a5580cSJeff Kirsher 4618feb871SGovindarajulu Varadarajan #define ENIC_WQ_NAPI_BUDGET 256 4718feb871SGovindarajulu Varadarajan 487c2ce6e6SSujith Sankar #define ENIC_AIC_LARGE_PKT_DIFF 3 497c2ce6e6SSujith Sankar 50a6a5580cSJeff Kirsher struct enic_msix_entry { 51a6a5580cSJeff Kirsher int requested; 527044f429SGovindarajulu Varadarajan char devname[IFNAMSIZ + 8]; 53a6a5580cSJeff Kirsher irqreturn_t (*isr)(int, void *); 54a6a5580cSJeff Kirsher void *devid; 55322cf7e3SGovindarajulu Varadarajan cpumask_var_t affinity_mask; 56a6a5580cSJeff Kirsher }; 57a6a5580cSJeff Kirsher 587c2ce6e6SSujith Sankar /* Store only the lower range. Higher range is given by fw. */ 597c2ce6e6SSujith Sankar struct enic_intr_mod_range { 607c2ce6e6SSujith Sankar u32 small_pkt_range_start; 617c2ce6e6SSujith Sankar u32 large_pkt_range_start; 627c2ce6e6SSujith Sankar }; 637c2ce6e6SSujith Sankar 647c2ce6e6SSujith Sankar struct enic_intr_mod_table { 657c2ce6e6SSujith Sankar u32 rx_rate; 667c2ce6e6SSujith Sankar u32 range_percent; 677c2ce6e6SSujith Sankar }; 687c2ce6e6SSujith Sankar 697c2ce6e6SSujith Sankar #define ENIC_MAX_LINK_SPEEDS 3 707c2ce6e6SSujith Sankar #define ENIC_LINK_SPEED_10G 10000 717c2ce6e6SSujith Sankar #define ENIC_LINK_SPEED_4G 4000 727c2ce6e6SSujith Sankar #define ENIC_LINK_40G_INDEX 2 737c2ce6e6SSujith Sankar #define ENIC_LINK_10G_INDEX 1 747c2ce6e6SSujith Sankar #define ENIC_LINK_4G_INDEX 0 757c2ce6e6SSujith Sankar #define ENIC_RX_COALESCE_RANGE_END 125 767c2ce6e6SSujith Sankar #define ENIC_AIC_TS_BREAK 100 777c2ce6e6SSujith Sankar 787c2ce6e6SSujith Sankar struct enic_rx_coal { 797c2ce6e6SSujith Sankar u32 small_pkt_range_start; 807c2ce6e6SSujith Sankar u32 large_pkt_range_start; 817c2ce6e6SSujith Sankar u32 range_end; 827c2ce6e6SSujith Sankar u32 use_adaptive_rx_coalesce; 837c2ce6e6SSujith Sankar }; 847c2ce6e6SSujith Sankar 858749b427SRoopa Prabhu /* priv_flags */ 868749b427SRoopa Prabhu #define ENIC_SRIOV_ENABLED (1 << 0) 878749b427SRoopa Prabhu 888749b427SRoopa Prabhu /* enic port profile set flags */ 89a6a5580cSJeff Kirsher #define ENIC_PORT_REQUEST_APPLIED (1 << 0) 90a6a5580cSJeff Kirsher #define ENIC_SET_REQUEST (1 << 1) 91a6a5580cSJeff Kirsher #define ENIC_SET_NAME (1 << 2) 92a6a5580cSJeff Kirsher #define ENIC_SET_INSTANCE (1 << 3) 93a6a5580cSJeff Kirsher #define ENIC_SET_HOST (1 << 4) 94a6a5580cSJeff Kirsher 95a6a5580cSJeff Kirsher struct enic_port_profile { 96a6a5580cSJeff Kirsher u32 set; 97a6a5580cSJeff Kirsher u8 request; 98a6a5580cSJeff Kirsher char name[PORT_PROFILE_MAX]; 99a6a5580cSJeff Kirsher u8 instance_uuid[PORT_UUID_MAX]; 100a6a5580cSJeff Kirsher u8 host_uuid[PORT_UUID_MAX]; 101a6a5580cSJeff Kirsher u8 vf_mac[ETH_ALEN]; 102a6a5580cSJeff Kirsher u8 mac_addr[ETH_ALEN]; 103a6a5580cSJeff Kirsher }; 104a6a5580cSJeff Kirsher 105a145df23SGovindarajulu Varadarajan /* enic_rfs_fltr_node - rfs filter node in hash table 106a145df23SGovindarajulu Varadarajan * @@keys: IPv4 5 tuple 107a145df23SGovindarajulu Varadarajan * @flow_id: flow_id of clsf filter provided by kernel 108a145df23SGovindarajulu Varadarajan * @fltr_id: filter id of clsf filter returned by adaptor 109a145df23SGovindarajulu Varadarajan * @rq_id: desired rq index 110a145df23SGovindarajulu Varadarajan * @node: hlist_node 111a145df23SGovindarajulu Varadarajan */ 112a145df23SGovindarajulu Varadarajan struct enic_rfs_fltr_node { 113a145df23SGovindarajulu Varadarajan struct flow_keys keys; 114a145df23SGovindarajulu Varadarajan u32 flow_id; 115a145df23SGovindarajulu Varadarajan u16 fltr_id; 116a145df23SGovindarajulu Varadarajan u16 rq_id; 117a145df23SGovindarajulu Varadarajan struct hlist_node node; 118a145df23SGovindarajulu Varadarajan }; 119a145df23SGovindarajulu Varadarajan 120a145df23SGovindarajulu Varadarajan /* enic_rfs_flw_tbl - rfs flow table 121a145df23SGovindarajulu Varadarajan * @max: Maximum number of filters vNIC supports 122a145df23SGovindarajulu Varadarajan * @free: Number of free filters available 123a145df23SGovindarajulu Varadarajan * @toclean: hash table index to clean next 124a145df23SGovindarajulu Varadarajan * @ht_head: hash table list head 125a145df23SGovindarajulu Varadarajan * @lock: spin lock 126a145df23SGovindarajulu Varadarajan * @rfs_may_expire: timer function for enic_rps_may_expire_flow 127a145df23SGovindarajulu Varadarajan */ 128a145df23SGovindarajulu Varadarajan struct enic_rfs_flw_tbl { 129a145df23SGovindarajulu Varadarajan u16 max; 130a145df23SGovindarajulu Varadarajan int free; 131a145df23SGovindarajulu Varadarajan 132a145df23SGovindarajulu Varadarajan #define ENIC_RFS_FLW_BITSHIFT (10) 133a145df23SGovindarajulu Varadarajan #define ENIC_RFS_FLW_MASK ((1 << ENIC_RFS_FLW_BITSHIFT) - 1) 134a145df23SGovindarajulu Varadarajan u16 toclean:ENIC_RFS_FLW_BITSHIFT; 135a145df23SGovindarajulu Varadarajan struct hlist_head ht_head[1 << ENIC_RFS_FLW_BITSHIFT]; 136a145df23SGovindarajulu Varadarajan spinlock_t lock; 137a145df23SGovindarajulu Varadarajan struct timer_list rfs_may_expire; 138a145df23SGovindarajulu Varadarajan }; 139a145df23SGovindarajulu Varadarajan 140257e7382SGovindarajulu Varadarajan struct vxlan_offload { 141257e7382SGovindarajulu Varadarajan u16 vxlan_udp_port_number; 142257e7382SGovindarajulu Varadarajan u8 patch_level; 143d1179094SGovindarajulu Varadarajan u8 flags; 144257e7382SGovindarajulu Varadarajan }; 145257e7382SGovindarajulu Varadarajan 146a6a5580cSJeff Kirsher /* Per-instance private data structure */ 147a6a5580cSJeff Kirsher struct enic { 148a6a5580cSJeff Kirsher struct net_device *netdev; 149a6a5580cSJeff Kirsher struct pci_dev *pdev; 150a6a5580cSJeff Kirsher struct vnic_enet_config config; 151a6a5580cSJeff Kirsher struct vnic_dev_bar bar[ENIC_BARS_MAX]; 152a6a5580cSJeff Kirsher struct vnic_dev *vdev; 153a6a5580cSJeff Kirsher struct timer_list notify_timer; 154a6a5580cSJeff Kirsher struct work_struct reset; 155937317c7SGovindarajulu Varadarajan struct work_struct tx_hang_reset; 156a6a5580cSJeff Kirsher struct work_struct change_mtu_work; 157a6a5580cSJeff Kirsher struct msix_entry msix_entry[ENIC_INTR_MAX]; 158a6a5580cSJeff Kirsher struct enic_msix_entry msix[ENIC_INTR_MAX]; 159a6a5580cSJeff Kirsher u32 msg_enable; 160a6a5580cSJeff Kirsher spinlock_t devcmd_lock; 161a6a5580cSJeff Kirsher u8 mac_addr[ETH_ALEN]; 162a6a5580cSJeff Kirsher unsigned int flags; 1638749b427SRoopa Prabhu unsigned int priv_flags; 164a6a5580cSJeff Kirsher unsigned int mc_count; 165a6a5580cSJeff Kirsher unsigned int uc_count; 166a6a5580cSJeff Kirsher u32 port_mtu; 1677c2ce6e6SSujith Sankar struct enic_rx_coal rx_coalesce_setting; 168a6a5580cSJeff Kirsher u32 rx_coalesce_usecs; 169a6a5580cSJeff Kirsher u32 tx_coalesce_usecs; 1708749b427SRoopa Prabhu #ifdef CONFIG_PCI_IOV 171413708bbSDan Carpenter u16 num_vfs; 1728749b427SRoopa Prabhu #endif 1730b038566SNeel Patel spinlock_t enic_api_lock; 1743f192795SRoopa Prabhu struct enic_port_profile *pp; 175a6a5580cSJeff Kirsher 176a6a5580cSJeff Kirsher /* work queue cache line section */ 177a6a5580cSJeff Kirsher ____cacheline_aligned struct vnic_wq wq[ENIC_WQ_MAX]; 178a6a5580cSJeff Kirsher spinlock_t wq_lock[ENIC_WQ_MAX]; 179a6a5580cSJeff Kirsher unsigned int wq_count; 180a6a5580cSJeff Kirsher u16 loop_enable; 181a6a5580cSJeff Kirsher u16 loop_tag; 182a6a5580cSJeff Kirsher 183a6a5580cSJeff Kirsher /* receive queue cache line section */ 184a6a5580cSJeff Kirsher ____cacheline_aligned struct vnic_rq rq[ENIC_RQ_MAX]; 185a6a5580cSJeff Kirsher unsigned int rq_count; 186257e7382SGovindarajulu Varadarajan struct vxlan_offload vxlan; 187a6a5580cSJeff Kirsher u64 rq_truncated_pkts; 188a6a5580cSJeff Kirsher u64 rq_bad_fcs; 1894cfe8785SGovindarajulu Varadarajan struct napi_struct napi[ENIC_RQ_MAX + ENIC_WQ_MAX]; 190a6a5580cSJeff Kirsher 191a6a5580cSJeff Kirsher /* interrupt resource cache line section */ 192a6a5580cSJeff Kirsher ____cacheline_aligned struct vnic_intr intr[ENIC_INTR_MAX]; 193a6a5580cSJeff Kirsher unsigned int intr_count; 194a6a5580cSJeff Kirsher u32 __iomem *legacy_pba; /* memory-mapped */ 195a6a5580cSJeff Kirsher 196a6a5580cSJeff Kirsher /* completion queue cache line section */ 197a6a5580cSJeff Kirsher ____cacheline_aligned struct vnic_cq cq[ENIC_CQ_MAX]; 198a6a5580cSJeff Kirsher unsigned int cq_count; 199a145df23SGovindarajulu Varadarajan struct enic_rfs_flw_tbl rfs_h; 200a03bb56eSGovindarajulu Varadarajan u32 rx_copybreak; 2014f675eb2SGovindarajulu Varadarajan u8 rss_key[ENIC_RSS_LEN]; 20258feff07SGovindarajulu Varadarajan struct vnic_gen_stats gen_stats; 203a6a5580cSJeff Kirsher }; 204a6a5580cSJeff Kirsher 2056a3c2f83SGovindarajulu Varadarajan static inline struct net_device *vnic_get_netdev(struct vnic_dev *vdev) 2066a3c2f83SGovindarajulu Varadarajan { 2076a3c2f83SGovindarajulu Varadarajan struct enic *enic = vdev->priv; 2086a3c2f83SGovindarajulu Varadarajan 2096a3c2f83SGovindarajulu Varadarajan return enic->netdev; 2106a3c2f83SGovindarajulu Varadarajan } 2116a3c2f83SGovindarajulu Varadarajan 2126a3c2f83SGovindarajulu Varadarajan /* wrappers function for kernel log 2136a3c2f83SGovindarajulu Varadarajan */ 214e327f4e1SJoe Perches #define vdev_err(vdev, fmt, ...) \ 215e327f4e1SJoe Perches dev_err(&(vdev)->pdev->dev, fmt, ##__VA_ARGS__) 216e327f4e1SJoe Perches #define vdev_warn(vdev, fmt, ...) \ 217e327f4e1SJoe Perches dev_warn(&(vdev)->pdev->dev, fmt, ##__VA_ARGS__) 218e327f4e1SJoe Perches #define vdev_info(vdev, fmt, ...) \ 219e327f4e1SJoe Perches dev_info(&(vdev)->pdev->dev, fmt, ##__VA_ARGS__) 2206a3c2f83SGovindarajulu Varadarajan 221e327f4e1SJoe Perches #define vdev_neterr(vdev, fmt, ...) \ 222e327f4e1SJoe Perches netdev_err(vnic_get_netdev(vdev), fmt, ##__VA_ARGS__) 223e327f4e1SJoe Perches #define vdev_netwarn(vdev, fmt, ...) \ 224e327f4e1SJoe Perches netdev_warn(vnic_get_netdev(vdev), fmt, ##__VA_ARGS__) 225e327f4e1SJoe Perches #define vdev_netinfo(vdev, fmt, ...) \ 226e327f4e1SJoe Perches netdev_info(vnic_get_netdev(vdev), fmt, ##__VA_ARGS__) 2276a3c2f83SGovindarajulu Varadarajan 228a6a5580cSJeff Kirsher static inline struct device *enic_get_dev(struct enic *enic) 229a6a5580cSJeff Kirsher { 230a6a5580cSJeff Kirsher return &(enic->pdev->dev); 231a6a5580cSJeff Kirsher } 232a6a5580cSJeff Kirsher 233f13bbc2fSNeel Patel static inline unsigned int enic_cq_rq(struct enic *enic, unsigned int rq) 234f13bbc2fSNeel Patel { 235f13bbc2fSNeel Patel return rq; 236f13bbc2fSNeel Patel } 237f13bbc2fSNeel Patel 238f13bbc2fSNeel Patel static inline unsigned int enic_cq_wq(struct enic *enic, unsigned int wq) 239f13bbc2fSNeel Patel { 240f13bbc2fSNeel Patel return enic->rq_count + wq; 241f13bbc2fSNeel Patel } 242f13bbc2fSNeel Patel 243f13bbc2fSNeel Patel static inline unsigned int enic_legacy_io_intr(void) 244f13bbc2fSNeel Patel { 245f13bbc2fSNeel Patel return 0; 246f13bbc2fSNeel Patel } 247f13bbc2fSNeel Patel 248f13bbc2fSNeel Patel static inline unsigned int enic_legacy_err_intr(void) 249f13bbc2fSNeel Patel { 250f13bbc2fSNeel Patel return 1; 251f13bbc2fSNeel Patel } 252f13bbc2fSNeel Patel 253f13bbc2fSNeel Patel static inline unsigned int enic_legacy_notify_intr(void) 254f13bbc2fSNeel Patel { 255f13bbc2fSNeel Patel return 2; 256f13bbc2fSNeel Patel } 257f13bbc2fSNeel Patel 258f13bbc2fSNeel Patel static inline unsigned int enic_msix_rq_intr(struct enic *enic, 259f13bbc2fSNeel Patel unsigned int rq) 260f13bbc2fSNeel Patel { 261f13bbc2fSNeel Patel return enic->cq[enic_cq_rq(enic, rq)].interrupt_offset; 262f13bbc2fSNeel Patel } 263f13bbc2fSNeel Patel 264f13bbc2fSNeel Patel static inline unsigned int enic_msix_wq_intr(struct enic *enic, 265f13bbc2fSNeel Patel unsigned int wq) 266f13bbc2fSNeel Patel { 267f13bbc2fSNeel Patel return enic->cq[enic_cq_wq(enic, wq)].interrupt_offset; 268f13bbc2fSNeel Patel } 269f13bbc2fSNeel Patel 270f13bbc2fSNeel Patel static inline unsigned int enic_msix_err_intr(struct enic *enic) 271f13bbc2fSNeel Patel { 272f13bbc2fSNeel Patel return enic->rq_count + enic->wq_count; 273f13bbc2fSNeel Patel } 274f13bbc2fSNeel Patel 275f13bbc2fSNeel Patel static inline unsigned int enic_msix_notify_intr(struct enic *enic) 276f13bbc2fSNeel Patel { 277f13bbc2fSNeel Patel return enic->rq_count + enic->wq_count + 1; 278f13bbc2fSNeel Patel } 279f13bbc2fSNeel Patel 280322cf7e3SGovindarajulu Varadarajan static inline bool enic_is_err_intr(struct enic *enic, int intr) 281322cf7e3SGovindarajulu Varadarajan { 282322cf7e3SGovindarajulu Varadarajan switch (vnic_dev_get_intr_mode(enic->vdev)) { 283322cf7e3SGovindarajulu Varadarajan case VNIC_DEV_INTR_MODE_INTX: 284322cf7e3SGovindarajulu Varadarajan return intr == enic_legacy_err_intr(); 285322cf7e3SGovindarajulu Varadarajan case VNIC_DEV_INTR_MODE_MSIX: 286322cf7e3SGovindarajulu Varadarajan return intr == enic_msix_err_intr(enic); 287322cf7e3SGovindarajulu Varadarajan case VNIC_DEV_INTR_MODE_MSI: 288322cf7e3SGovindarajulu Varadarajan default: 289322cf7e3SGovindarajulu Varadarajan return false; 290322cf7e3SGovindarajulu Varadarajan } 291322cf7e3SGovindarajulu Varadarajan } 292322cf7e3SGovindarajulu Varadarajan 293322cf7e3SGovindarajulu Varadarajan static inline bool enic_is_notify_intr(struct enic *enic, int intr) 294322cf7e3SGovindarajulu Varadarajan { 295322cf7e3SGovindarajulu Varadarajan switch (vnic_dev_get_intr_mode(enic->vdev)) { 296322cf7e3SGovindarajulu Varadarajan case VNIC_DEV_INTR_MODE_INTX: 297322cf7e3SGovindarajulu Varadarajan return intr == enic_legacy_notify_intr(); 298322cf7e3SGovindarajulu Varadarajan case VNIC_DEV_INTR_MODE_MSIX: 299322cf7e3SGovindarajulu Varadarajan return intr == enic_msix_notify_intr(enic); 300322cf7e3SGovindarajulu Varadarajan case VNIC_DEV_INTR_MODE_MSI: 301322cf7e3SGovindarajulu Varadarajan default: 302322cf7e3SGovindarajulu Varadarajan return false; 303322cf7e3SGovindarajulu Varadarajan } 304322cf7e3SGovindarajulu Varadarajan } 305322cf7e3SGovindarajulu Varadarajan 306065df159SGovindarajulu Varadarajan static inline int enic_dma_map_check(struct enic *enic, dma_addr_t dma_addr) 307065df159SGovindarajulu Varadarajan { 308065df159SGovindarajulu Varadarajan if (unlikely(pci_dma_mapping_error(enic->pdev, dma_addr))) { 309065df159SGovindarajulu Varadarajan net_warn_ratelimited("%s: PCI dma mapping failed!\n", 310065df159SGovindarajulu Varadarajan enic->netdev->name); 31158feff07SGovindarajulu Varadarajan enic->gen_stats.dma_map_error++; 312065df159SGovindarajulu Varadarajan 313065df159SGovindarajulu Varadarajan return -ENOMEM; 314065df159SGovindarajulu Varadarajan } 315065df159SGovindarajulu Varadarajan 316065df159SGovindarajulu Varadarajan return 0; 317065df159SGovindarajulu Varadarajan } 318065df159SGovindarajulu Varadarajan 319a6a5580cSJeff Kirsher void enic_reset_addr_lists(struct enic *enic); 3208749b427SRoopa Prabhu int enic_sriov_enabled(struct enic *enic); 321889d13f5SRoopa Prabhu int enic_is_valid_vf(struct enic *enic, int vf); 3223f192795SRoopa Prabhu int enic_is_dynamic(struct enic *enic); 323f13bbc2fSNeel Patel void enic_set_ethtool_ops(struct net_device *netdev); 3244f675eb2SGovindarajulu Varadarajan int __enic_set_rsskey(struct enic *enic); 325a6a5580cSJeff Kirsher 326a6a5580cSJeff Kirsher #endif /* _ENIC_H_ */ 327