1 /*
2  * EP93xx ethernet network device driver
3  * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
4  * Dedicated to Marija Kulikova.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  */
11 
12 #define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__
13 
14 #include <linux/dma-mapping.h>
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/netdevice.h>
18 #include <linux/mii.h>
19 #include <linux/etherdevice.h>
20 #include <linux/ethtool.h>
21 #include <linux/interrupt.h>
22 #include <linux/moduleparam.h>
23 #include <linux/platform_device.h>
24 #include <linux/delay.h>
25 #include <linux/io.h>
26 #include <linux/slab.h>
27 
28 #include <mach/hardware.h>
29 
30 #define DRV_MODULE_NAME		"ep93xx-eth"
31 #define DRV_MODULE_VERSION	"0.1"
32 
33 #define RX_QUEUE_ENTRIES	64
34 #define TX_QUEUE_ENTRIES	8
35 
36 #define MAX_PKT_SIZE		2044
37 #define PKT_BUF_SIZE		2048
38 
39 #define REG_RXCTL		0x0000
40 #define  REG_RXCTL_DEFAULT	0x00073800
41 #define REG_TXCTL		0x0004
42 #define  REG_TXCTL_ENABLE	0x00000001
43 #define REG_MIICMD		0x0010
44 #define  REG_MIICMD_READ	0x00008000
45 #define  REG_MIICMD_WRITE	0x00004000
46 #define REG_MIIDATA		0x0014
47 #define REG_MIISTS		0x0018
48 #define  REG_MIISTS_BUSY	0x00000001
49 #define REG_SELFCTL		0x0020
50 #define  REG_SELFCTL_RESET	0x00000001
51 #define REG_INTEN		0x0024
52 #define  REG_INTEN_TX		0x00000008
53 #define  REG_INTEN_RX		0x00000007
54 #define REG_INTSTSP		0x0028
55 #define  REG_INTSTS_TX		0x00000008
56 #define  REG_INTSTS_RX		0x00000004
57 #define REG_INTSTSC		0x002c
58 #define REG_AFP			0x004c
59 #define REG_INDAD0		0x0050
60 #define REG_INDAD1		0x0051
61 #define REG_INDAD2		0x0052
62 #define REG_INDAD3		0x0053
63 #define REG_INDAD4		0x0054
64 #define REG_INDAD5		0x0055
65 #define REG_GIINTMSK		0x0064
66 #define  REG_GIINTMSK_ENABLE	0x00008000
67 #define REG_BMCTL		0x0080
68 #define  REG_BMCTL_ENABLE_TX	0x00000100
69 #define  REG_BMCTL_ENABLE_RX	0x00000001
70 #define REG_BMSTS		0x0084
71 #define  REG_BMSTS_RX_ACTIVE	0x00000008
72 #define REG_RXDQBADD		0x0090
73 #define REG_RXDQBLEN		0x0094
74 #define REG_RXDCURADD		0x0098
75 #define REG_RXDENQ		0x009c
76 #define REG_RXSTSQBADD		0x00a0
77 #define REG_RXSTSQBLEN		0x00a4
78 #define REG_RXSTSQCURADD	0x00a8
79 #define REG_RXSTSENQ		0x00ac
80 #define REG_TXDQBADD		0x00b0
81 #define REG_TXDQBLEN		0x00b4
82 #define REG_TXDQCURADD		0x00b8
83 #define REG_TXDENQ		0x00bc
84 #define REG_TXSTSQBADD		0x00c0
85 #define REG_TXSTSQBLEN		0x00c4
86 #define REG_TXSTSQCURADD	0x00c8
87 #define REG_MAXFRMLEN		0x00e8
88 
89 struct ep93xx_rdesc
90 {
91 	u32	buf_addr;
92 	u32	rdesc1;
93 };
94 
95 #define RDESC1_NSOF		0x80000000
96 #define RDESC1_BUFFER_INDEX	0x7fff0000
97 #define RDESC1_BUFFER_LENGTH	0x0000ffff
98 
99 struct ep93xx_rstat
100 {
101 	u32	rstat0;
102 	u32	rstat1;
103 };
104 
105 #define RSTAT0_RFP		0x80000000
106 #define RSTAT0_RWE		0x40000000
107 #define RSTAT0_EOF		0x20000000
108 #define RSTAT0_EOB		0x10000000
109 #define RSTAT0_AM		0x00c00000
110 #define RSTAT0_RX_ERR		0x00200000
111 #define RSTAT0_OE		0x00100000
112 #define RSTAT0_FE		0x00080000
113 #define RSTAT0_RUNT		0x00040000
114 #define RSTAT0_EDATA		0x00020000
115 #define RSTAT0_CRCE		0x00010000
116 #define RSTAT0_CRCI		0x00008000
117 #define RSTAT0_HTI		0x00003f00
118 #define RSTAT1_RFP		0x80000000
119 #define RSTAT1_BUFFER_INDEX	0x7fff0000
120 #define RSTAT1_FRAME_LENGTH	0x0000ffff
121 
122 struct ep93xx_tdesc
123 {
124 	u32	buf_addr;
125 	u32	tdesc1;
126 };
127 
128 #define TDESC1_EOF		0x80000000
129 #define TDESC1_BUFFER_INDEX	0x7fff0000
130 #define TDESC1_BUFFER_ABORT	0x00008000
131 #define TDESC1_BUFFER_LENGTH	0x00000fff
132 
133 struct ep93xx_tstat
134 {
135 	u32	tstat0;
136 };
137 
138 #define TSTAT0_TXFP		0x80000000
139 #define TSTAT0_TXWE		0x40000000
140 #define TSTAT0_FA		0x20000000
141 #define TSTAT0_LCRS		0x10000000
142 #define TSTAT0_OW		0x04000000
143 #define TSTAT0_TXU		0x02000000
144 #define TSTAT0_ECOLL		0x01000000
145 #define TSTAT0_NCOLL		0x001f0000
146 #define TSTAT0_BUFFER_INDEX	0x00007fff
147 
148 struct ep93xx_descs
149 {
150 	struct ep93xx_rdesc	rdesc[RX_QUEUE_ENTRIES];
151 	struct ep93xx_tdesc	tdesc[TX_QUEUE_ENTRIES];
152 	struct ep93xx_rstat	rstat[RX_QUEUE_ENTRIES];
153 	struct ep93xx_tstat	tstat[TX_QUEUE_ENTRIES];
154 };
155 
156 struct ep93xx_priv
157 {
158 	struct resource		*res;
159 	void __iomem		*base_addr;
160 	int			irq;
161 
162 	struct ep93xx_descs	*descs;
163 	dma_addr_t		descs_dma_addr;
164 
165 	void			*rx_buf[RX_QUEUE_ENTRIES];
166 	void			*tx_buf[TX_QUEUE_ENTRIES];
167 
168 	spinlock_t		rx_lock;
169 	unsigned int		rx_pointer;
170 	unsigned int		tx_clean_pointer;
171 	unsigned int		tx_pointer;
172 	spinlock_t		tx_pending_lock;
173 	unsigned int		tx_pending;
174 
175 	struct net_device	*dev;
176 	struct napi_struct	napi;
177 
178 	struct mii_if_info	mii;
179 	u8			mdc_divisor;
180 };
181 
182 #define rdb(ep, off)		__raw_readb((ep)->base_addr + (off))
183 #define rdw(ep, off)		__raw_readw((ep)->base_addr + (off))
184 #define rdl(ep, off)		__raw_readl((ep)->base_addr + (off))
185 #define wrb(ep, off, val)	__raw_writeb((val), (ep)->base_addr + (off))
186 #define wrw(ep, off, val)	__raw_writew((val), (ep)->base_addr + (off))
187 #define wrl(ep, off, val)	__raw_writel((val), (ep)->base_addr + (off))
188 
189 static int ep93xx_mdio_read(struct net_device *dev, int phy_id, int reg)
190 {
191 	struct ep93xx_priv *ep = netdev_priv(dev);
192 	int data;
193 	int i;
194 
195 	wrl(ep, REG_MIICMD, REG_MIICMD_READ | (phy_id << 5) | reg);
196 
197 	for (i = 0; i < 10; i++) {
198 		if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0)
199 			break;
200 		msleep(1);
201 	}
202 
203 	if (i == 10) {
204 		pr_info("mdio read timed out\n");
205 		data = 0xffff;
206 	} else {
207 		data = rdl(ep, REG_MIIDATA);
208 	}
209 
210 	return data;
211 }
212 
213 static void ep93xx_mdio_write(struct net_device *dev, int phy_id, int reg, int data)
214 {
215 	struct ep93xx_priv *ep = netdev_priv(dev);
216 	int i;
217 
218 	wrl(ep, REG_MIIDATA, data);
219 	wrl(ep, REG_MIICMD, REG_MIICMD_WRITE | (phy_id << 5) | reg);
220 
221 	for (i = 0; i < 10; i++) {
222 		if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0)
223 			break;
224 		msleep(1);
225 	}
226 
227 	if (i == 10)
228 		pr_info("mdio write timed out\n");
229 }
230 
231 static int ep93xx_rx(struct net_device *dev, int budget)
232 {
233 	struct ep93xx_priv *ep = netdev_priv(dev);
234 	int processed = 0;
235 
236 	while (processed < budget) {
237 		int entry;
238 		struct ep93xx_rstat *rstat;
239 		u32 rstat0;
240 		u32 rstat1;
241 		int length;
242 		struct sk_buff *skb;
243 
244 		entry = ep->rx_pointer;
245 		rstat = ep->descs->rstat + entry;
246 
247 		rstat0 = rstat->rstat0;
248 		rstat1 = rstat->rstat1;
249 		if (!(rstat0 & RSTAT0_RFP) || !(rstat1 & RSTAT1_RFP))
250 			break;
251 
252 		rstat->rstat0 = 0;
253 		rstat->rstat1 = 0;
254 
255 		if (!(rstat0 & RSTAT0_EOF))
256 			pr_crit("not end-of-frame %.8x %.8x\n", rstat0, rstat1);
257 		if (!(rstat0 & RSTAT0_EOB))
258 			pr_crit("not end-of-buffer %.8x %.8x\n", rstat0, rstat1);
259 		if ((rstat1 & RSTAT1_BUFFER_INDEX) >> 16 != entry)
260 			pr_crit("entry mismatch %.8x %.8x\n", rstat0, rstat1);
261 
262 		if (!(rstat0 & RSTAT0_RWE)) {
263 			dev->stats.rx_errors++;
264 			if (rstat0 & RSTAT0_OE)
265 				dev->stats.rx_fifo_errors++;
266 			if (rstat0 & RSTAT0_FE)
267 				dev->stats.rx_frame_errors++;
268 			if (rstat0 & (RSTAT0_RUNT | RSTAT0_EDATA))
269 				dev->stats.rx_length_errors++;
270 			if (rstat0 & RSTAT0_CRCE)
271 				dev->stats.rx_crc_errors++;
272 			goto err;
273 		}
274 
275 		length = rstat1 & RSTAT1_FRAME_LENGTH;
276 		if (length > MAX_PKT_SIZE) {
277 			pr_notice("invalid length %.8x %.8x\n", rstat0, rstat1);
278 			goto err;
279 		}
280 
281 		/* Strip FCS.  */
282 		if (rstat0 & RSTAT0_CRCI)
283 			length -= 4;
284 
285 		skb = netdev_alloc_skb(dev, length + 2);
286 		if (likely(skb != NULL)) {
287 			struct ep93xx_rdesc *rxd = &ep->descs->rdesc[entry];
288 			skb_reserve(skb, 2);
289 			dma_sync_single_for_cpu(dev->dev.parent, rxd->buf_addr,
290 						length, DMA_FROM_DEVICE);
291 			skb_copy_to_linear_data(skb, ep->rx_buf[entry], length);
292 			dma_sync_single_for_device(dev->dev.parent,
293 						   rxd->buf_addr, length,
294 						   DMA_FROM_DEVICE);
295 			skb_put(skb, length);
296 			skb->protocol = eth_type_trans(skb, dev);
297 
298 			napi_gro_receive(&ep->napi, skb);
299 
300 			dev->stats.rx_packets++;
301 			dev->stats.rx_bytes += length;
302 		} else {
303 			dev->stats.rx_dropped++;
304 		}
305 
306 err:
307 		ep->rx_pointer = (entry + 1) & (RX_QUEUE_ENTRIES - 1);
308 		processed++;
309 	}
310 
311 	return processed;
312 }
313 
314 static int ep93xx_poll(struct napi_struct *napi, int budget)
315 {
316 	struct ep93xx_priv *ep = container_of(napi, struct ep93xx_priv, napi);
317 	struct net_device *dev = ep->dev;
318 	int rx;
319 
320 	rx = ep93xx_rx(dev, budget);
321 	if (rx < budget && napi_complete_done(napi, rx)) {
322 		spin_lock_irq(&ep->rx_lock);
323 		wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX);
324 		spin_unlock_irq(&ep->rx_lock);
325 	}
326 
327 	if (rx) {
328 		wrw(ep, REG_RXDENQ, rx);
329 		wrw(ep, REG_RXSTSENQ, rx);
330 	}
331 
332 	return rx;
333 }
334 
335 static int ep93xx_xmit(struct sk_buff *skb, struct net_device *dev)
336 {
337 	struct ep93xx_priv *ep = netdev_priv(dev);
338 	struct ep93xx_tdesc *txd;
339 	int entry;
340 
341 	if (unlikely(skb->len > MAX_PKT_SIZE)) {
342 		dev->stats.tx_dropped++;
343 		dev_kfree_skb(skb);
344 		return NETDEV_TX_OK;
345 	}
346 
347 	entry = ep->tx_pointer;
348 	ep->tx_pointer = (ep->tx_pointer + 1) & (TX_QUEUE_ENTRIES - 1);
349 
350 	txd = &ep->descs->tdesc[entry];
351 
352 	txd->tdesc1 = TDESC1_EOF | (entry << 16) | (skb->len & 0xfff);
353 	dma_sync_single_for_cpu(dev->dev.parent, txd->buf_addr, skb->len,
354 				DMA_TO_DEVICE);
355 	skb_copy_and_csum_dev(skb, ep->tx_buf[entry]);
356 	dma_sync_single_for_device(dev->dev.parent, txd->buf_addr, skb->len,
357 				   DMA_TO_DEVICE);
358 	dev_kfree_skb(skb);
359 
360 	spin_lock_irq(&ep->tx_pending_lock);
361 	ep->tx_pending++;
362 	if (ep->tx_pending == TX_QUEUE_ENTRIES)
363 		netif_stop_queue(dev);
364 	spin_unlock_irq(&ep->tx_pending_lock);
365 
366 	wrl(ep, REG_TXDENQ, 1);
367 
368 	return NETDEV_TX_OK;
369 }
370 
371 static void ep93xx_tx_complete(struct net_device *dev)
372 {
373 	struct ep93xx_priv *ep = netdev_priv(dev);
374 	int wake;
375 
376 	wake = 0;
377 
378 	spin_lock(&ep->tx_pending_lock);
379 	while (1) {
380 		int entry;
381 		struct ep93xx_tstat *tstat;
382 		u32 tstat0;
383 
384 		entry = ep->tx_clean_pointer;
385 		tstat = ep->descs->tstat + entry;
386 
387 		tstat0 = tstat->tstat0;
388 		if (!(tstat0 & TSTAT0_TXFP))
389 			break;
390 
391 		tstat->tstat0 = 0;
392 
393 		if (tstat0 & TSTAT0_FA)
394 			pr_crit("frame aborted %.8x\n", tstat0);
395 		if ((tstat0 & TSTAT0_BUFFER_INDEX) != entry)
396 			pr_crit("entry mismatch %.8x\n", tstat0);
397 
398 		if (tstat0 & TSTAT0_TXWE) {
399 			int length = ep->descs->tdesc[entry].tdesc1 & 0xfff;
400 
401 			dev->stats.tx_packets++;
402 			dev->stats.tx_bytes += length;
403 		} else {
404 			dev->stats.tx_errors++;
405 		}
406 
407 		if (tstat0 & TSTAT0_OW)
408 			dev->stats.tx_window_errors++;
409 		if (tstat0 & TSTAT0_TXU)
410 			dev->stats.tx_fifo_errors++;
411 		dev->stats.collisions += (tstat0 >> 16) & 0x1f;
412 
413 		ep->tx_clean_pointer = (entry + 1) & (TX_QUEUE_ENTRIES - 1);
414 		if (ep->tx_pending == TX_QUEUE_ENTRIES)
415 			wake = 1;
416 		ep->tx_pending--;
417 	}
418 	spin_unlock(&ep->tx_pending_lock);
419 
420 	if (wake)
421 		netif_wake_queue(dev);
422 }
423 
424 static irqreturn_t ep93xx_irq(int irq, void *dev_id)
425 {
426 	struct net_device *dev = dev_id;
427 	struct ep93xx_priv *ep = netdev_priv(dev);
428 	u32 status;
429 
430 	status = rdl(ep, REG_INTSTSC);
431 	if (status == 0)
432 		return IRQ_NONE;
433 
434 	if (status & REG_INTSTS_RX) {
435 		spin_lock(&ep->rx_lock);
436 		if (likely(napi_schedule_prep(&ep->napi))) {
437 			wrl(ep, REG_INTEN, REG_INTEN_TX);
438 			__napi_schedule(&ep->napi);
439 		}
440 		spin_unlock(&ep->rx_lock);
441 	}
442 
443 	if (status & REG_INTSTS_TX)
444 		ep93xx_tx_complete(dev);
445 
446 	return IRQ_HANDLED;
447 }
448 
449 static void ep93xx_free_buffers(struct ep93xx_priv *ep)
450 {
451 	struct device *dev = ep->dev->dev.parent;
452 	int i;
453 
454 	if (!ep->descs)
455 		return;
456 
457 	for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
458 		dma_addr_t d;
459 
460 		d = ep->descs->rdesc[i].buf_addr;
461 		if (d)
462 			dma_unmap_single(dev, d, PKT_BUF_SIZE, DMA_FROM_DEVICE);
463 
464 		kfree(ep->rx_buf[i]);
465 	}
466 
467 	for (i = 0; i < TX_QUEUE_ENTRIES; i++) {
468 		dma_addr_t d;
469 
470 		d = ep->descs->tdesc[i].buf_addr;
471 		if (d)
472 			dma_unmap_single(dev, d, PKT_BUF_SIZE, DMA_TO_DEVICE);
473 
474 		kfree(ep->tx_buf[i]);
475 	}
476 
477 	dma_free_coherent(dev, sizeof(struct ep93xx_descs), ep->descs,
478 							ep->descs_dma_addr);
479 	ep->descs = NULL;
480 }
481 
482 static int ep93xx_alloc_buffers(struct ep93xx_priv *ep)
483 {
484 	struct device *dev = ep->dev->dev.parent;
485 	int i;
486 
487 	ep->descs = dma_alloc_coherent(dev, sizeof(struct ep93xx_descs),
488 				&ep->descs_dma_addr, GFP_KERNEL);
489 	if (ep->descs == NULL)
490 		return 1;
491 
492 	for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
493 		void *buf;
494 		dma_addr_t d;
495 
496 		buf = kmalloc(PKT_BUF_SIZE, GFP_KERNEL);
497 		if (buf == NULL)
498 			goto err;
499 
500 		d = dma_map_single(dev, buf, PKT_BUF_SIZE, DMA_FROM_DEVICE);
501 		if (dma_mapping_error(dev, d)) {
502 			kfree(buf);
503 			goto err;
504 		}
505 
506 		ep->rx_buf[i] = buf;
507 		ep->descs->rdesc[i].buf_addr = d;
508 		ep->descs->rdesc[i].rdesc1 = (i << 16) | PKT_BUF_SIZE;
509 	}
510 
511 	for (i = 0; i < TX_QUEUE_ENTRIES; i++) {
512 		void *buf;
513 		dma_addr_t d;
514 
515 		buf = kmalloc(PKT_BUF_SIZE, GFP_KERNEL);
516 		if (buf == NULL)
517 			goto err;
518 
519 		d = dma_map_single(dev, buf, PKT_BUF_SIZE, DMA_TO_DEVICE);
520 		if (dma_mapping_error(dev, d)) {
521 			kfree(buf);
522 			goto err;
523 		}
524 
525 		ep->tx_buf[i] = buf;
526 		ep->descs->tdesc[i].buf_addr = d;
527 	}
528 
529 	return 0;
530 
531 err:
532 	ep93xx_free_buffers(ep);
533 	return 1;
534 }
535 
536 static int ep93xx_start_hw(struct net_device *dev)
537 {
538 	struct ep93xx_priv *ep = netdev_priv(dev);
539 	unsigned long addr;
540 	int i;
541 
542 	wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET);
543 	for (i = 0; i < 10; i++) {
544 		if ((rdl(ep, REG_SELFCTL) & REG_SELFCTL_RESET) == 0)
545 			break;
546 		msleep(1);
547 	}
548 
549 	if (i == 10) {
550 		pr_crit("hw failed to reset\n");
551 		return 1;
552 	}
553 
554 	wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9));
555 
556 	/* Does the PHY support preamble suppress?  */
557 	if ((ep93xx_mdio_read(dev, ep->mii.phy_id, MII_BMSR) & 0x0040) != 0)
558 		wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9) | (1 << 8));
559 
560 	/* Receive descriptor ring.  */
561 	addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, rdesc);
562 	wrl(ep, REG_RXDQBADD, addr);
563 	wrl(ep, REG_RXDCURADD, addr);
564 	wrw(ep, REG_RXDQBLEN, RX_QUEUE_ENTRIES * sizeof(struct ep93xx_rdesc));
565 
566 	/* Receive status ring.  */
567 	addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, rstat);
568 	wrl(ep, REG_RXSTSQBADD, addr);
569 	wrl(ep, REG_RXSTSQCURADD, addr);
570 	wrw(ep, REG_RXSTSQBLEN, RX_QUEUE_ENTRIES * sizeof(struct ep93xx_rstat));
571 
572 	/* Transmit descriptor ring.  */
573 	addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, tdesc);
574 	wrl(ep, REG_TXDQBADD, addr);
575 	wrl(ep, REG_TXDQCURADD, addr);
576 	wrw(ep, REG_TXDQBLEN, TX_QUEUE_ENTRIES * sizeof(struct ep93xx_tdesc));
577 
578 	/* Transmit status ring.  */
579 	addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, tstat);
580 	wrl(ep, REG_TXSTSQBADD, addr);
581 	wrl(ep, REG_TXSTSQCURADD, addr);
582 	wrw(ep, REG_TXSTSQBLEN, TX_QUEUE_ENTRIES * sizeof(struct ep93xx_tstat));
583 
584 	wrl(ep, REG_BMCTL, REG_BMCTL_ENABLE_TX | REG_BMCTL_ENABLE_RX);
585 	wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX);
586 	wrl(ep, REG_GIINTMSK, 0);
587 
588 	for (i = 0; i < 10; i++) {
589 		if ((rdl(ep, REG_BMSTS) & REG_BMSTS_RX_ACTIVE) != 0)
590 			break;
591 		msleep(1);
592 	}
593 
594 	if (i == 10) {
595 		pr_crit("hw failed to start\n");
596 		return 1;
597 	}
598 
599 	wrl(ep, REG_RXDENQ, RX_QUEUE_ENTRIES);
600 	wrl(ep, REG_RXSTSENQ, RX_QUEUE_ENTRIES);
601 
602 	wrb(ep, REG_INDAD0, dev->dev_addr[0]);
603 	wrb(ep, REG_INDAD1, dev->dev_addr[1]);
604 	wrb(ep, REG_INDAD2, dev->dev_addr[2]);
605 	wrb(ep, REG_INDAD3, dev->dev_addr[3]);
606 	wrb(ep, REG_INDAD4, dev->dev_addr[4]);
607 	wrb(ep, REG_INDAD5, dev->dev_addr[5]);
608 	wrl(ep, REG_AFP, 0);
609 
610 	wrl(ep, REG_MAXFRMLEN, (MAX_PKT_SIZE << 16) | MAX_PKT_SIZE);
611 
612 	wrl(ep, REG_RXCTL, REG_RXCTL_DEFAULT);
613 	wrl(ep, REG_TXCTL, REG_TXCTL_ENABLE);
614 
615 	return 0;
616 }
617 
618 static void ep93xx_stop_hw(struct net_device *dev)
619 {
620 	struct ep93xx_priv *ep = netdev_priv(dev);
621 	int i;
622 
623 	wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET);
624 	for (i = 0; i < 10; i++) {
625 		if ((rdl(ep, REG_SELFCTL) & REG_SELFCTL_RESET) == 0)
626 			break;
627 		msleep(1);
628 	}
629 
630 	if (i == 10)
631 		pr_crit("hw failed to reset\n");
632 }
633 
634 static int ep93xx_open(struct net_device *dev)
635 {
636 	struct ep93xx_priv *ep = netdev_priv(dev);
637 	int err;
638 
639 	if (ep93xx_alloc_buffers(ep))
640 		return -ENOMEM;
641 
642 	napi_enable(&ep->napi);
643 
644 	if (ep93xx_start_hw(dev)) {
645 		napi_disable(&ep->napi);
646 		ep93xx_free_buffers(ep);
647 		return -EIO;
648 	}
649 
650 	spin_lock_init(&ep->rx_lock);
651 	ep->rx_pointer = 0;
652 	ep->tx_clean_pointer = 0;
653 	ep->tx_pointer = 0;
654 	spin_lock_init(&ep->tx_pending_lock);
655 	ep->tx_pending = 0;
656 
657 	err = request_irq(ep->irq, ep93xx_irq, IRQF_SHARED, dev->name, dev);
658 	if (err) {
659 		napi_disable(&ep->napi);
660 		ep93xx_stop_hw(dev);
661 		ep93xx_free_buffers(ep);
662 		return err;
663 	}
664 
665 	wrl(ep, REG_GIINTMSK, REG_GIINTMSK_ENABLE);
666 
667 	netif_start_queue(dev);
668 
669 	return 0;
670 }
671 
672 static int ep93xx_close(struct net_device *dev)
673 {
674 	struct ep93xx_priv *ep = netdev_priv(dev);
675 
676 	napi_disable(&ep->napi);
677 	netif_stop_queue(dev);
678 
679 	wrl(ep, REG_GIINTMSK, 0);
680 	free_irq(ep->irq, dev);
681 	ep93xx_stop_hw(dev);
682 	ep93xx_free_buffers(ep);
683 
684 	return 0;
685 }
686 
687 static int ep93xx_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
688 {
689 	struct ep93xx_priv *ep = netdev_priv(dev);
690 	struct mii_ioctl_data *data = if_mii(ifr);
691 
692 	return generic_mii_ioctl(&ep->mii, data, cmd, NULL);
693 }
694 
695 static void ep93xx_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
696 {
697 	strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
698 	strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
699 }
700 
701 static int ep93xx_get_link_ksettings(struct net_device *dev,
702 				     struct ethtool_link_ksettings *cmd)
703 {
704 	struct ep93xx_priv *ep = netdev_priv(dev);
705 
706 	mii_ethtool_get_link_ksettings(&ep->mii, cmd);
707 
708 	return 0;
709 }
710 
711 static int ep93xx_set_link_ksettings(struct net_device *dev,
712 				     const struct ethtool_link_ksettings *cmd)
713 {
714 	struct ep93xx_priv *ep = netdev_priv(dev);
715 	return mii_ethtool_set_link_ksettings(&ep->mii, cmd);
716 }
717 
718 static int ep93xx_nway_reset(struct net_device *dev)
719 {
720 	struct ep93xx_priv *ep = netdev_priv(dev);
721 	return mii_nway_restart(&ep->mii);
722 }
723 
724 static u32 ep93xx_get_link(struct net_device *dev)
725 {
726 	struct ep93xx_priv *ep = netdev_priv(dev);
727 	return mii_link_ok(&ep->mii);
728 }
729 
730 static const struct ethtool_ops ep93xx_ethtool_ops = {
731 	.get_drvinfo		= ep93xx_get_drvinfo,
732 	.nway_reset		= ep93xx_nway_reset,
733 	.get_link		= ep93xx_get_link,
734 	.get_link_ksettings	= ep93xx_get_link_ksettings,
735 	.set_link_ksettings	= ep93xx_set_link_ksettings,
736 };
737 
738 static const struct net_device_ops ep93xx_netdev_ops = {
739 	.ndo_open		= ep93xx_open,
740 	.ndo_stop		= ep93xx_close,
741 	.ndo_start_xmit		= ep93xx_xmit,
742 	.ndo_do_ioctl		= ep93xx_ioctl,
743 	.ndo_validate_addr	= eth_validate_addr,
744 	.ndo_set_mac_address	= eth_mac_addr,
745 };
746 
747 static struct net_device *ep93xx_dev_alloc(struct ep93xx_eth_data *data)
748 {
749 	struct net_device *dev;
750 
751 	dev = alloc_etherdev(sizeof(struct ep93xx_priv));
752 	if (dev == NULL)
753 		return NULL;
754 
755 	memcpy(dev->dev_addr, data->dev_addr, ETH_ALEN);
756 
757 	dev->ethtool_ops = &ep93xx_ethtool_ops;
758 	dev->netdev_ops = &ep93xx_netdev_ops;
759 
760 	dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
761 
762 	return dev;
763 }
764 
765 
766 static int ep93xx_eth_remove(struct platform_device *pdev)
767 {
768 	struct net_device *dev;
769 	struct ep93xx_priv *ep;
770 
771 	dev = platform_get_drvdata(pdev);
772 	if (dev == NULL)
773 		return 0;
774 
775 	ep = netdev_priv(dev);
776 
777 	/* @@@ Force down.  */
778 	unregister_netdev(dev);
779 	ep93xx_free_buffers(ep);
780 
781 	if (ep->base_addr != NULL)
782 		iounmap(ep->base_addr);
783 
784 	if (ep->res != NULL) {
785 		release_resource(ep->res);
786 		kfree(ep->res);
787 	}
788 
789 	free_netdev(dev);
790 
791 	return 0;
792 }
793 
794 static int ep93xx_eth_probe(struct platform_device *pdev)
795 {
796 	struct ep93xx_eth_data *data;
797 	struct net_device *dev;
798 	struct ep93xx_priv *ep;
799 	struct resource *mem;
800 	int irq;
801 	int err;
802 
803 	if (pdev == NULL)
804 		return -ENODEV;
805 	data = dev_get_platdata(&pdev->dev);
806 
807 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
808 	irq = platform_get_irq(pdev, 0);
809 	if (!mem || irq < 0)
810 		return -ENXIO;
811 
812 	dev = ep93xx_dev_alloc(data);
813 	if (dev == NULL) {
814 		err = -ENOMEM;
815 		goto err_out;
816 	}
817 	ep = netdev_priv(dev);
818 	ep->dev = dev;
819 	SET_NETDEV_DEV(dev, &pdev->dev);
820 	netif_napi_add(dev, &ep->napi, ep93xx_poll, 64);
821 
822 	platform_set_drvdata(pdev, dev);
823 
824 	ep->res = request_mem_region(mem->start, resource_size(mem),
825 				     dev_name(&pdev->dev));
826 	if (ep->res == NULL) {
827 		dev_err(&pdev->dev, "Could not reserve memory region\n");
828 		err = -ENOMEM;
829 		goto err_out;
830 	}
831 
832 	ep->base_addr = ioremap(mem->start, resource_size(mem));
833 	if (ep->base_addr == NULL) {
834 		dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
835 		err = -EIO;
836 		goto err_out;
837 	}
838 	ep->irq = irq;
839 
840 	ep->mii.phy_id = data->phy_id;
841 	ep->mii.phy_id_mask = 0x1f;
842 	ep->mii.reg_num_mask = 0x1f;
843 	ep->mii.dev = dev;
844 	ep->mii.mdio_read = ep93xx_mdio_read;
845 	ep->mii.mdio_write = ep93xx_mdio_write;
846 	ep->mdc_divisor = 40;	/* Max HCLK 100 MHz, min MDIO clk 2.5 MHz.  */
847 
848 	if (is_zero_ether_addr(dev->dev_addr))
849 		eth_hw_addr_random(dev);
850 
851 	err = register_netdev(dev);
852 	if (err) {
853 		dev_err(&pdev->dev, "Failed to register netdev\n");
854 		goto err_out;
855 	}
856 
857 	printk(KERN_INFO "%s: ep93xx on-chip ethernet, IRQ %d, %pM\n",
858 			dev->name, ep->irq, dev->dev_addr);
859 
860 	return 0;
861 
862 err_out:
863 	ep93xx_eth_remove(pdev);
864 	return err;
865 }
866 
867 
868 static struct platform_driver ep93xx_eth_driver = {
869 	.probe		= ep93xx_eth_probe,
870 	.remove		= ep93xx_eth_remove,
871 	.driver		= {
872 		.name	= "ep93xx-eth",
873 	},
874 };
875 
876 module_platform_driver(ep93xx_eth_driver);
877 
878 MODULE_LICENSE("GPL");
879 MODULE_ALIAS("platform:ep93xx-eth");
880