1 /* 2 * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet 3 * driver for Linux. 4 * 5 * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * OpenIB.org BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or 14 * without modification, are permitted provided that the following 15 * conditions are met: 16 * 17 * - Redistributions of source code must retain the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer. 20 * 21 * - Redistributions in binary form must reproduce the above 22 * copyright notice, this list of conditions and the following 23 * disclaimer in the documentation and/or other materials 24 * provided with the distribution. 25 * 26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 33 * SOFTWARE. 34 */ 35 36 #ifndef __T4VF_COMMON_H__ 37 #define __T4VF_COMMON_H__ 38 39 #include "../cxgb4/t4_hw.h" 40 #include "../cxgb4/t4fw_api.h" 41 42 #define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision)) 43 #define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf) 44 #define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf) 45 46 /* All T4 and later chips have their PCI-E Device IDs encoded as 0xVFPP where: 47 * 48 * V = "4" for T4; "5" for T5, etc. or 49 * = "a" for T4 FPGA; "b" for T4 FPGA, etc. 50 * F = "0" for PF 0..3; "4".."7" for PF4..7; and "8" for VFs 51 * PP = adapter product designation 52 */ 53 #define CHELSIO_T4 0x4 54 #define CHELSIO_T5 0x5 55 #define CHELSIO_T6 0x6 56 57 enum chip_type { 58 T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1), 59 T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2), 60 T4_FIRST_REV = T4_A1, 61 T4_LAST_REV = T4_A2, 62 63 T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0), 64 T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1), 65 T5_FIRST_REV = T5_A0, 66 T5_LAST_REV = T5_A1, 67 }; 68 69 /* 70 * The "len16" field of a Firmware Command Structure ... 71 */ 72 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 73 74 /* 75 * Per-VF statistics. 76 */ 77 struct t4vf_port_stats { 78 /* 79 * TX statistics. 80 */ 81 u64 tx_bcast_bytes; /* broadcast */ 82 u64 tx_bcast_frames; 83 u64 tx_mcast_bytes; /* multicast */ 84 u64 tx_mcast_frames; 85 u64 tx_ucast_bytes; /* unicast */ 86 u64 tx_ucast_frames; 87 u64 tx_drop_frames; /* TX dropped frames */ 88 u64 tx_offload_bytes; /* offload */ 89 u64 tx_offload_frames; 90 91 /* 92 * RX statistics. 93 */ 94 u64 rx_bcast_bytes; /* broadcast */ 95 u64 rx_bcast_frames; 96 u64 rx_mcast_bytes; /* multicast */ 97 u64 rx_mcast_frames; 98 u64 rx_ucast_bytes; 99 u64 rx_ucast_frames; /* unicast */ 100 101 u64 rx_err_frames; /* RX error frames */ 102 }; 103 104 /* 105 * Per-"port" (Virtual Interface) link configuration ... 106 */ 107 typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */ 108 typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */ 109 110 enum fw_caps { 111 FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */ 112 FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */ 113 FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */ 114 }; 115 116 enum cc_pause { 117 PAUSE_RX = 1 << 0, 118 PAUSE_TX = 1 << 1, 119 PAUSE_AUTONEG = 1 << 2 120 }; 121 122 enum cc_fec { 123 FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */ 124 FEC_RS = 1 << 1, /* Reed-Solomon */ 125 FEC_BASER_RS = 1 << 2, /* BaseR/Reed-Solomon */ 126 }; 127 128 struct link_config { 129 fw_port_cap32_t pcaps; /* link capabilities */ 130 fw_port_cap32_t acaps; /* advertised capabilities */ 131 fw_port_cap32_t lpacaps; /* peer advertised capabilities */ 132 133 fw_port_cap32_t speed_caps; /* speed(s) user has requested */ 134 u32 speed; /* actual link speed */ 135 136 enum cc_pause requested_fc; /* flow control user has requested */ 137 enum cc_pause fc; /* actual link flow control */ 138 139 enum cc_fec auto_fec; /* Forward Error Correction: */ 140 enum cc_fec requested_fec; /* "automatic" (IEEE 802.3), */ 141 enum cc_fec fec; /* requested, and actual in use */ 142 143 unsigned char autoneg; /* autonegotiating? */ 144 145 unsigned char link_ok; /* link up? */ 146 unsigned char link_down_rc; /* link down reason */ 147 }; 148 149 /* Return true if the Link Configuration supports "High Speeds" (those greater 150 * than 1Gb/s). 151 */ 152 static inline bool is_x_10g_port(const struct link_config *lc) 153 { 154 fw_port_cap32_t speeds, high_speeds; 155 156 speeds = FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_G(lc->pcaps)); 157 high_speeds = 158 speeds & ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G); 159 160 return high_speeds != 0; 161 } 162 163 /* 164 * General device parameters ... 165 */ 166 struct dev_params { 167 u32 fwrev; /* firmware version */ 168 u32 tprev; /* TP Microcode Version */ 169 }; 170 171 /* 172 * Scatter Gather Engine parameters. These are almost all determined by the 173 * Physical Function Driver. We just need to grab them to see within which 174 * environment we're playing ... 175 */ 176 struct sge_params { 177 u32 sge_control; /* padding, boundaries, lengths, etc. */ 178 u32 sge_control2; /* T5: more of the same */ 179 u32 sge_host_page_size; /* PF0-7 page sizes */ 180 u32 sge_egress_queues_per_page; /* PF0-7 egress queues/page */ 181 u32 sge_ingress_queues_per_page;/* PF0-7 ingress queues/page */ 182 u32 sge_vf_hps; /* host page size for our vf */ 183 u32 sge_vf_eq_qpp; /* egress queues/page for our VF */ 184 u32 sge_vf_iq_qpp; /* ingress queues/page for our VF */ 185 u32 sge_fl_buffer_size[16]; /* free list buffer sizes */ 186 u32 sge_ingress_rx_threshold; /* RX counter interrupt threshold[4] */ 187 u32 sge_congestion_control; /* congestion thresholds, etc. */ 188 u32 sge_timer_value_0_and_1; /* interrupt coalescing timer values */ 189 u32 sge_timer_value_2_and_3; 190 u32 sge_timer_value_4_and_5; 191 }; 192 193 /* 194 * Vital Product Data parameters. 195 */ 196 struct vpd_params { 197 u32 cclk; /* Core Clock (KHz) */ 198 }; 199 200 /* Stores chip specific parameters */ 201 struct arch_specific_params { 202 u32 sge_fl_db; 203 u16 mps_tcam_size; 204 }; 205 206 /* 207 * Global Receive Side Scaling (RSS) parameters in host-native format. 208 */ 209 struct rss_params { 210 unsigned int mode; /* RSS mode */ 211 union { 212 struct { 213 unsigned int synmapen:1; /* SYN Map Enable */ 214 unsigned int syn4tupenipv6:1; /* enable hashing 4-tuple IPv6 SYNs */ 215 unsigned int syn2tupenipv6:1; /* enable hashing 2-tuple IPv6 SYNs */ 216 unsigned int syn4tupenipv4:1; /* enable hashing 4-tuple IPv4 SYNs */ 217 unsigned int syn2tupenipv4:1; /* enable hashing 2-tuple IPv4 SYNs */ 218 unsigned int ofdmapen:1; /* Offload Map Enable */ 219 unsigned int tnlmapen:1; /* Tunnel Map Enable */ 220 unsigned int tnlalllookup:1; /* Tunnel All Lookup */ 221 unsigned int hashtoeplitz:1; /* use Toeplitz hash */ 222 } basicvirtual; 223 } u; 224 }; 225 226 /* 227 * Virtual Interface RSS Configuration in host-native format. 228 */ 229 union rss_vi_config { 230 struct { 231 u16 defaultq; /* Ingress Queue ID for !tnlalllookup */ 232 unsigned int ip6fourtupen:1; /* hash 4-tuple IPv6 ingress packets */ 233 unsigned int ip6twotupen:1; /* hash 2-tuple IPv6 ingress packets */ 234 unsigned int ip4fourtupen:1; /* hash 4-tuple IPv4 ingress packets */ 235 unsigned int ip4twotupen:1; /* hash 2-tuple IPv4 ingress packets */ 236 int udpen; /* hash 4-tuple UDP ingress packets */ 237 } basicvirtual; 238 }; 239 240 /* 241 * Maximum resources provisioned for a PCI VF. 242 */ 243 struct vf_resources { 244 unsigned int nvi; /* N virtual interfaces */ 245 unsigned int neq; /* N egress Qs */ 246 unsigned int nethctrl; /* N egress ETH or CTRL Qs */ 247 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ 248 unsigned int niq; /* N ingress Qs */ 249 unsigned int tc; /* PCI-E traffic class */ 250 unsigned int pmask; /* port access rights mask */ 251 unsigned int nexactf; /* N exact MPS filters */ 252 unsigned int r_caps; /* read capabilities */ 253 unsigned int wx_caps; /* write/execute capabilities */ 254 }; 255 256 /* 257 * Per-"adapter" (Virtual Function) parameters. 258 */ 259 struct adapter_params { 260 struct dev_params dev; /* general device parameters */ 261 struct sge_params sge; /* Scatter Gather Engine */ 262 struct vpd_params vpd; /* Vital Product Data */ 263 struct rss_params rss; /* Receive Side Scaling */ 264 struct vf_resources vfres; /* Virtual Function Resource limits */ 265 struct arch_specific_params arch; /* chip specific params */ 266 enum chip_type chip; /* chip code */ 267 u8 nports; /* # of Ethernet "ports" */ 268 u8 fw_caps_support; /* 32-bit Port Capabilities */ 269 }; 270 271 /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format. 272 * The access and execute times are signed in order to accommodate negative 273 * error returns. 274 */ 275 struct mbox_cmd { 276 u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */ 277 u64 timestamp; /* OS-dependent timestamp */ 278 u32 seqno; /* sequence number */ 279 s16 access; /* time (ms) to access mailbox */ 280 s16 execute; /* time (ms) to execute */ 281 }; 282 283 struct mbox_cmd_log { 284 unsigned int size; /* number of entries in the log */ 285 unsigned int cursor; /* next position in the log to write */ 286 u32 seqno; /* next sequence number */ 287 /* variable length mailbox command log starts here */ 288 }; 289 290 /* Given a pointer to a Firmware Mailbox Command Log and a log entry index, 291 * return a pointer to the specified entry. 292 */ 293 static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log, 294 unsigned int entry_idx) 295 { 296 return &((struct mbox_cmd *)&(log)[1])[entry_idx]; 297 } 298 299 #include "adapter.h" 300 301 #ifndef PCI_VENDOR_ID_CHELSIO 302 # define PCI_VENDOR_ID_CHELSIO 0x1425 303 #endif 304 305 #define for_each_port(adapter, iter) \ 306 for (iter = 0; iter < (adapter)->params.nports; iter++) 307 308 static inline unsigned int core_ticks_per_usec(const struct adapter *adapter) 309 { 310 return adapter->params.vpd.cclk / 1000; 311 } 312 313 static inline unsigned int us_to_core_ticks(const struct adapter *adapter, 314 unsigned int us) 315 { 316 return (us * adapter->params.vpd.cclk) / 1000; 317 } 318 319 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 320 unsigned int ticks) 321 { 322 return (ticks * 1000) / adapter->params.vpd.cclk; 323 } 324 325 int t4vf_wr_mbox_core(struct adapter *, const void *, int, void *, bool); 326 327 static inline int t4vf_wr_mbox(struct adapter *adapter, const void *cmd, 328 int size, void *rpl) 329 { 330 return t4vf_wr_mbox_core(adapter, cmd, size, rpl, true); 331 } 332 333 static inline int t4vf_wr_mbox_ns(struct adapter *adapter, const void *cmd, 334 int size, void *rpl) 335 { 336 return t4vf_wr_mbox_core(adapter, cmd, size, rpl, false); 337 } 338 339 #define CHELSIO_PCI_ID_VER(dev_id) ((dev_id) >> 12) 340 341 static inline int is_t4(enum chip_type chip) 342 { 343 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4; 344 } 345 346 /** 347 * hash_mac_addr - return the hash value of a MAC address 348 * @addr: the 48-bit Ethernet MAC address 349 * 350 * Hashes a MAC address according to the hash function used by hardware 351 * inexact (hash) address matching. 352 */ 353 static inline int hash_mac_addr(const u8 *addr) 354 { 355 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 356 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 357 358 a ^= b; 359 a ^= (a >> 12); 360 a ^= (a >> 6); 361 return a & 0x3f; 362 } 363 364 int t4vf_wait_dev_ready(struct adapter *); 365 int t4vf_port_init(struct adapter *, int); 366 367 int t4vf_fw_reset(struct adapter *); 368 int t4vf_set_params(struct adapter *, unsigned int, const u32 *, const u32 *); 369 370 int t4vf_fl_pkt_align(struct adapter *adapter); 371 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 372 int t4vf_bar2_sge_qregs(struct adapter *adapter, 373 unsigned int qid, 374 enum t4_bar2_qtype qtype, 375 u64 *pbar2_qoffset, 376 unsigned int *pbar2_qid); 377 378 unsigned int t4vf_get_pf_from_vf(struct adapter *); 379 int t4vf_get_sge_params(struct adapter *); 380 int t4vf_get_vpd_params(struct adapter *); 381 int t4vf_get_dev_params(struct adapter *); 382 int t4vf_get_rss_glb_config(struct adapter *); 383 int t4vf_get_vfres(struct adapter *); 384 385 int t4vf_read_rss_vi_config(struct adapter *, unsigned int, 386 union rss_vi_config *); 387 int t4vf_write_rss_vi_config(struct adapter *, unsigned int, 388 union rss_vi_config *); 389 int t4vf_config_rss_range(struct adapter *, unsigned int, int, int, 390 const u16 *, int); 391 392 int t4vf_alloc_vi(struct adapter *, int); 393 int t4vf_free_vi(struct adapter *, int); 394 int t4vf_enable_vi(struct adapter *adapter, unsigned int viid, bool rx_en, 395 bool tx_en); 396 int t4vf_enable_pi(struct adapter *adapter, struct port_info *pi, bool rx_en, 397 bool tx_en); 398 int t4vf_identify_port(struct adapter *, unsigned int, unsigned int); 399 400 int t4vf_set_rxmode(struct adapter *, unsigned int, int, int, int, int, int, 401 bool); 402 int t4vf_alloc_mac_filt(struct adapter *, unsigned int, bool, unsigned int, 403 const u8 **, u16 *, u64 *, bool); 404 int t4vf_free_mac_filt(struct adapter *, unsigned int, unsigned int naddr, 405 const u8 **, bool); 406 int t4vf_change_mac(struct adapter *, unsigned int, int, const u8 *, bool); 407 int t4vf_set_addr_hash(struct adapter *, unsigned int, bool, u64, bool); 408 int t4vf_get_port_stats(struct adapter *, int, struct t4vf_port_stats *); 409 410 int t4vf_iq_free(struct adapter *, unsigned int, unsigned int, unsigned int, 411 unsigned int); 412 int t4vf_eth_eq_free(struct adapter *, unsigned int); 413 414 int t4vf_update_port_info(struct port_info *pi); 415 int t4vf_handle_fw_rpl(struct adapter *, const __be64 *); 416 int t4vf_prep_adapter(struct adapter *); 417 int t4vf_get_vf_mac_acl(struct adapter *adapter, unsigned int pf, 418 unsigned int *naddr, u8 *addr); 419 int t4vf_get_vf_vlan_acl(struct adapter *adapter); 420 421 #endif /* __T4VF_COMMON_H__ */ 422