1 /*
2  * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
3  * driver for Linux.
4  *
5  * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
6  *
7  * This software is available to you under a choice of one of two
8  * licenses.  You may choose to be licensed under the terms of the GNU
9  * General Public License (GPL) Version 2, available from the file
10  * COPYING in the main directory of this source tree, or the
11  * OpenIB.org BSD license below:
12  *
13  *     Redistribution and use in source and binary forms, with or
14  *     without modification, are permitted provided that the following
15  *     conditions are met:
16  *
17  *      - Redistributions of source code must retain the above
18  *        copyright notice, this list of conditions and the following
19  *        disclaimer.
20  *
21  *      - Redistributions in binary form must reproduce the above
22  *        copyright notice, this list of conditions and the following
23  *        disclaimer in the documentation and/or other materials
24  *        provided with the distribution.
25  *
26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33  * SOFTWARE.
34  */
35 
36 #ifndef __T4VF_COMMON_H__
37 #define __T4VF_COMMON_H__
38 
39 #include "../cxgb4/t4_hw.h"
40 #include "../cxgb4/t4fw_api.h"
41 
42 #define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
43 #define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf)
44 #define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
45 
46 /* All T4 and later chips have their PCI-E Device IDs encoded as 0xVFPP where:
47  *
48  *   V  = "4" for T4; "5" for T5, etc. or
49  *      = "a" for T4 FPGA; "b" for T4 FPGA, etc.
50  *   F  = "0" for PF 0..3; "4".."7" for PF4..7; and "8" for VFs
51  *   PP = adapter product designation
52  */
53 #define CHELSIO_T4		0x4
54 #define CHELSIO_T5		0x5
55 #define CHELSIO_T6		0x6
56 
57 enum chip_type {
58 	T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
59 	T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
60 	T4_FIRST_REV	= T4_A1,
61 	T4_LAST_REV	= T4_A2,
62 
63 	T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
64 	T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
65 	T5_FIRST_REV	= T5_A0,
66 	T5_LAST_REV	= T5_A1,
67 };
68 
69 /*
70  * The "len16" field of a Firmware Command Structure ...
71  */
72 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
73 
74 /*
75  * Per-VF statistics.
76  */
77 struct t4vf_port_stats {
78 	/*
79 	 * TX statistics.
80 	 */
81 	u64 tx_bcast_bytes;		/* broadcast */
82 	u64 tx_bcast_frames;
83 	u64 tx_mcast_bytes;		/* multicast */
84 	u64 tx_mcast_frames;
85 	u64 tx_ucast_bytes;		/* unicast */
86 	u64 tx_ucast_frames;
87 	u64 tx_drop_frames;		/* TX dropped frames */
88 	u64 tx_offload_bytes;		/* offload */
89 	u64 tx_offload_frames;
90 
91 	/*
92 	 * RX statistics.
93 	 */
94 	u64 rx_bcast_bytes;		/* broadcast */
95 	u64 rx_bcast_frames;
96 	u64 rx_mcast_bytes;		/* multicast */
97 	u64 rx_mcast_frames;
98 	u64 rx_ucast_bytes;
99 	u64 rx_ucast_frames;		/* unicast */
100 
101 	u64 rx_err_frames;		/* RX error frames */
102 };
103 
104 /*
105  * Per-"port" (Virtual Interface) link configuration ...
106  */
107 struct link_config {
108 	unsigned int   supported;        /* link capabilities */
109 	unsigned int   advertising;      /* advertised capabilities */
110 	unsigned short requested_speed;  /* speed user has requested */
111 	unsigned short speed;            /* actual link speed */
112 	unsigned char  requested_fc;     /* flow control user has requested */
113 	unsigned char  fc;               /* actual link flow control */
114 	unsigned char  autoneg;          /* autonegotiating? */
115 	unsigned char  link_ok;          /* link up? */
116 };
117 
118 enum {
119 	PAUSE_RX      = 1 << 0,
120 	PAUSE_TX      = 1 << 1,
121 	PAUSE_AUTONEG = 1 << 2
122 };
123 
124 /*
125  * General device parameters ...
126  */
127 struct dev_params {
128 	u32 fwrev;			/* firmware version */
129 	u32 tprev;			/* TP Microcode Version */
130 };
131 
132 /*
133  * Scatter Gather Engine parameters.  These are almost all determined by the
134  * Physical Function Driver.  We just need to grab them to see within which
135  * environment we're playing ...
136  */
137 struct sge_params {
138 	u32 sge_control;		/* padding, boundaries, lengths, etc. */
139 	u32 sge_control2;		/* T5: more of the same */
140 	u32 sge_host_page_size;		/* PF0-7 page sizes */
141 	u32 sge_egress_queues_per_page;	/* PF0-7 egress queues/page */
142 	u32 sge_ingress_queues_per_page;/* PF0-7 ingress queues/page */
143 	u32 sge_vf_hps;                 /* host page size for our vf */
144 	u32 sge_vf_eq_qpp;		/* egress queues/page for our VF */
145 	u32 sge_vf_iq_qpp;		/* ingress queues/page for our VF */
146 	u32 sge_fl_buffer_size[16];	/* free list buffer sizes */
147 	u32 sge_ingress_rx_threshold;	/* RX counter interrupt threshold[4] */
148 	u32 sge_congestion_control;     /* congestion thresholds, etc. */
149 	u32 sge_timer_value_0_and_1;	/* interrupt coalescing timer values */
150 	u32 sge_timer_value_2_and_3;
151 	u32 sge_timer_value_4_and_5;
152 };
153 
154 /*
155  * Vital Product Data parameters.
156  */
157 struct vpd_params {
158 	u32 cclk;			/* Core Clock (KHz) */
159 };
160 
161 /* Stores chip specific parameters */
162 struct arch_specific_params {
163 	u32 sge_fl_db;
164 	u16 mps_tcam_size;
165 };
166 
167 /*
168  * Global Receive Side Scaling (RSS) parameters in host-native format.
169  */
170 struct rss_params {
171 	unsigned int mode;		/* RSS mode */
172 	union {
173 	    struct {
174 		unsigned int synmapen:1;	/* SYN Map Enable */
175 		unsigned int syn4tupenipv6:1;	/* enable hashing 4-tuple IPv6 SYNs */
176 		unsigned int syn2tupenipv6:1;	/* enable hashing 2-tuple IPv6 SYNs */
177 		unsigned int syn4tupenipv4:1;	/* enable hashing 4-tuple IPv4 SYNs */
178 		unsigned int syn2tupenipv4:1;	/* enable hashing 2-tuple IPv4 SYNs */
179 		unsigned int ofdmapen:1;	/* Offload Map Enable */
180 		unsigned int tnlmapen:1;	/* Tunnel Map Enable */
181 		unsigned int tnlalllookup:1;	/* Tunnel All Lookup */
182 		unsigned int hashtoeplitz:1;	/* use Toeplitz hash */
183 	    } basicvirtual;
184 	} u;
185 };
186 
187 /*
188  * Virtual Interface RSS Configuration in host-native format.
189  */
190 union rss_vi_config {
191     struct {
192 	u16 defaultq;			/* Ingress Queue ID for !tnlalllookup */
193 	unsigned int ip6fourtupen:1;	/* hash 4-tuple IPv6 ingress packets */
194 	unsigned int ip6twotupen:1;	/* hash 2-tuple IPv6 ingress packets */
195 	unsigned int ip4fourtupen:1;	/* hash 4-tuple IPv4 ingress packets */
196 	unsigned int ip4twotupen:1;	/* hash 2-tuple IPv4 ingress packets */
197 	int udpen;			/* hash 4-tuple UDP ingress packets */
198     } basicvirtual;
199 };
200 
201 /*
202  * Maximum resources provisioned for a PCI VF.
203  */
204 struct vf_resources {
205 	unsigned int nvi;		/* N virtual interfaces */
206 	unsigned int neq;		/* N egress Qs */
207 	unsigned int nethctrl;		/* N egress ETH or CTRL Qs */
208 	unsigned int niqflint;		/* N ingress Qs/w free list(s) & intr */
209 	unsigned int niq;		/* N ingress Qs */
210 	unsigned int tc;		/* PCI-E traffic class */
211 	unsigned int pmask;		/* port access rights mask */
212 	unsigned int nexactf;		/* N exact MPS filters */
213 	unsigned int r_caps;		/* read capabilities */
214 	unsigned int wx_caps;		/* write/execute capabilities */
215 };
216 
217 /*
218  * Per-"adapter" (Virtual Function) parameters.
219  */
220 struct adapter_params {
221 	struct dev_params dev;		/* general device parameters */
222 	struct sge_params sge;		/* Scatter Gather Engine */
223 	struct vpd_params vpd;		/* Vital Product Data */
224 	struct rss_params rss;		/* Receive Side Scaling */
225 	struct vf_resources vfres;	/* Virtual Function Resource limits */
226 	struct arch_specific_params arch; /* chip specific params */
227 	enum chip_type chip;		/* chip code */
228 	u8 nports;			/* # of Ethernet "ports" */
229 };
230 
231 /* Firmware Mailbox Command/Reply log.  All values are in Host-Endian format.
232  * The access and execute times are signed in order to accommodate negative
233  * error returns.
234  */
235 struct mbox_cmd {
236 	u64 cmd[MBOX_LEN / 8];		/* a Firmware Mailbox Command/Reply */
237 	u64 timestamp;			/* OS-dependent timestamp */
238 	u32 seqno;			/* sequence number */
239 	s16 access;			/* time (ms) to access mailbox */
240 	s16 execute;			/* time (ms) to execute */
241 };
242 
243 struct mbox_cmd_log {
244 	unsigned int size;		/* number of entries in the log */
245 	unsigned int cursor;		/* next position in the log to write */
246 	u32 seqno;			/* next sequence number */
247 	/* variable length mailbox command log starts here */
248 };
249 
250 /* Given a pointer to a Firmware Mailbox Command Log and a log entry index,
251  * return a pointer to the specified entry.
252  */
253 static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log,
254 						  unsigned int entry_idx)
255 {
256 	return &((struct mbox_cmd *)&(log)[1])[entry_idx];
257 }
258 
259 #include "adapter.h"
260 
261 #ifndef PCI_VENDOR_ID_CHELSIO
262 # define PCI_VENDOR_ID_CHELSIO 0x1425
263 #endif
264 
265 #define for_each_port(adapter, iter) \
266 	for (iter = 0; iter < (adapter)->params.nports; iter++)
267 
268 static inline bool is_10g_port(const struct link_config *lc)
269 {
270 	return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0;
271 }
272 
273 static inline bool is_x_10g_port(const struct link_config *lc)
274 {
275 	return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0 ||
276 		(lc->supported & FW_PORT_CAP_SPEED_40G) != 0;
277 }
278 
279 static inline unsigned int core_ticks_per_usec(const struct adapter *adapter)
280 {
281 	return adapter->params.vpd.cclk / 1000;
282 }
283 
284 static inline unsigned int us_to_core_ticks(const struct adapter *adapter,
285 					    unsigned int us)
286 {
287 	return (us * adapter->params.vpd.cclk) / 1000;
288 }
289 
290 static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
291 					    unsigned int ticks)
292 {
293 	return (ticks * 1000) / adapter->params.vpd.cclk;
294 }
295 
296 int t4vf_wr_mbox_core(struct adapter *, const void *, int, void *, bool);
297 
298 static inline int t4vf_wr_mbox(struct adapter *adapter, const void *cmd,
299 			       int size, void *rpl)
300 {
301 	return t4vf_wr_mbox_core(adapter, cmd, size, rpl, true);
302 }
303 
304 static inline int t4vf_wr_mbox_ns(struct adapter *adapter, const void *cmd,
305 				  int size, void *rpl)
306 {
307 	return t4vf_wr_mbox_core(adapter, cmd, size, rpl, false);
308 }
309 
310 #define CHELSIO_PCI_ID_VER(dev_id)  ((dev_id) >> 12)
311 
312 static inline int is_t4(enum chip_type chip)
313 {
314 	return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4;
315 }
316 
317 /**
318  *	hash_mac_addr - return the hash value of a MAC address
319  *	@addr: the 48-bit Ethernet MAC address
320  *
321  *	Hashes a MAC address according to the hash function used by hardware
322  *	inexact (hash) address matching.
323  */
324 static inline int hash_mac_addr(const u8 *addr)
325 {
326 	u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
327 	u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
328 
329 	a ^= b;
330 	a ^= (a >> 12);
331 	a ^= (a >> 6);
332 	return a & 0x3f;
333 }
334 
335 int t4vf_wait_dev_ready(struct adapter *);
336 int t4vf_port_init(struct adapter *, int);
337 
338 int t4vf_fw_reset(struct adapter *);
339 int t4vf_set_params(struct adapter *, unsigned int, const u32 *, const u32 *);
340 
341 int t4vf_fl_pkt_align(struct adapter *adapter);
342 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
343 int t4vf_bar2_sge_qregs(struct adapter *adapter,
344 			unsigned int qid,
345 			enum t4_bar2_qtype qtype,
346 			u64 *pbar2_qoffset,
347 			unsigned int *pbar2_qid);
348 
349 int t4vf_get_sge_params(struct adapter *);
350 int t4vf_get_vpd_params(struct adapter *);
351 int t4vf_get_dev_params(struct adapter *);
352 int t4vf_get_rss_glb_config(struct adapter *);
353 int t4vf_get_vfres(struct adapter *);
354 
355 int t4vf_read_rss_vi_config(struct adapter *, unsigned int,
356 			    union rss_vi_config *);
357 int t4vf_write_rss_vi_config(struct adapter *, unsigned int,
358 			     union rss_vi_config *);
359 int t4vf_config_rss_range(struct adapter *, unsigned int, int, int,
360 			  const u16 *, int);
361 
362 int t4vf_alloc_vi(struct adapter *, int);
363 int t4vf_free_vi(struct adapter *, int);
364 int t4vf_enable_vi(struct adapter *, unsigned int, bool, bool);
365 int t4vf_identify_port(struct adapter *, unsigned int, unsigned int);
366 
367 int t4vf_set_rxmode(struct adapter *, unsigned int, int, int, int, int, int,
368 		    bool);
369 int t4vf_alloc_mac_filt(struct adapter *, unsigned int, bool, unsigned int,
370 			const u8 **, u16 *, u64 *, bool);
371 int t4vf_free_mac_filt(struct adapter *, unsigned int, unsigned int naddr,
372 		       const u8 **, bool);
373 int t4vf_change_mac(struct adapter *, unsigned int, int, const u8 *, bool);
374 int t4vf_set_addr_hash(struct adapter *, unsigned int, bool, u64, bool);
375 int t4vf_get_port_stats(struct adapter *, int, struct t4vf_port_stats *);
376 
377 int t4vf_iq_free(struct adapter *, unsigned int, unsigned int, unsigned int,
378 		 unsigned int);
379 int t4vf_eth_eq_free(struct adapter *, unsigned int);
380 
381 int t4vf_handle_fw_rpl(struct adapter *, const __be64 *);
382 int t4vf_prep_adapter(struct adapter *);
383 
384 #endif /* __T4VF_COMMON_H__ */
385