1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2009-2014 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef _T4FW_INTERFACE_H_ 36 #define _T4FW_INTERFACE_H_ 37 38 enum fw_retval { 39 FW_SUCCESS = 0, /* completed sucessfully */ 40 FW_EPERM = 1, /* operation not permitted */ 41 FW_ENOENT = 2, /* no such file or directory */ 42 FW_EIO = 5, /* input/output error; hw bad */ 43 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 44 FW_EAGAIN = 11, /* try again */ 45 FW_ENOMEM = 12, /* out of memory */ 46 FW_EFAULT = 14, /* bad address; fw bad */ 47 FW_EBUSY = 16, /* resource busy */ 48 FW_EEXIST = 17, /* file exists */ 49 FW_ENODEV = 19, /* no such device */ 50 FW_EINVAL = 22, /* invalid argument */ 51 FW_ENOSPC = 28, /* no space left on device */ 52 FW_ENOSYS = 38, /* functionality not implemented */ 53 FW_ENODATA = 61, /* no data available */ 54 FW_EPROTO = 71, /* protocol error */ 55 FW_EADDRINUSE = 98, /* address already in use */ 56 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 57 FW_ENETDOWN = 100, /* network is down */ 58 FW_ENETUNREACH = 101, /* network is unreachable */ 59 FW_ENOBUFS = 105, /* no buffer space available */ 60 FW_ETIMEDOUT = 110, /* timeout */ 61 FW_EINPROGRESS = 115, /* fw internal */ 62 FW_SCSI_ABORT_REQUESTED = 128, /* */ 63 FW_SCSI_ABORT_TIMEDOUT = 129, /* */ 64 FW_SCSI_ABORTED = 130, /* */ 65 FW_SCSI_CLOSE_REQUESTED = 131, /* */ 66 FW_ERR_LINK_DOWN = 132, /* */ 67 FW_RDEV_NOT_READY = 133, /* */ 68 FW_ERR_RDEV_LOST = 134, /* */ 69 FW_ERR_RDEV_LOGO = 135, /* */ 70 FW_FCOE_NO_XCHG = 136, /* */ 71 FW_SCSI_RSP_ERR = 137, /* */ 72 FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 73 FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 74 FW_SCSI_OVER_FLOW_ERR = 140, /* */ 75 FW_SCSI_DDP_ERR = 141, /* DDP error*/ 76 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 77 }; 78 79 #define FW_T4VF_SGE_BASE_ADDR 0x0000 80 #define FW_T4VF_MPS_BASE_ADDR 0x0100 81 #define FW_T4VF_PL_BASE_ADDR 0x0200 82 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240 83 #define FW_T4VF_CIM_BASE_ADDR 0x0300 84 85 enum fw_wr_opcodes { 86 FW_FILTER_WR = 0x02, 87 FW_ULPTX_WR = 0x04, 88 FW_TP_WR = 0x05, 89 FW_ETH_TX_PKT_WR = 0x08, 90 FW_OFLD_CONNECTION_WR = 0x2f, 91 FW_FLOWC_WR = 0x0a, 92 FW_OFLD_TX_DATA_WR = 0x0b, 93 FW_CMD_WR = 0x10, 94 FW_ETH_TX_PKT_VM_WR = 0x11, 95 FW_RI_RES_WR = 0x0c, 96 FW_RI_INIT_WR = 0x0d, 97 FW_RI_RDMA_WRITE_WR = 0x14, 98 FW_RI_SEND_WR = 0x15, 99 FW_RI_RDMA_READ_WR = 0x16, 100 FW_RI_RECV_WR = 0x17, 101 FW_RI_BIND_MW_WR = 0x18, 102 FW_RI_FR_NSMR_WR = 0x19, 103 FW_RI_INV_LSTAG_WR = 0x1a, 104 FW_LASTC2E_WR = 0x40 105 }; 106 107 struct fw_wr_hdr { 108 __be32 hi; 109 __be32 lo; 110 }; 111 112 /* work request opcode (hi) */ 113 #define FW_WR_OP_S 24 114 #define FW_WR_OP_M 0xff 115 #define FW_WR_OP_V(x) ((x) << FW_WR_OP_S) 116 #define FW_WR_OP_G(x) (((x) >> FW_WR_OP_S) & FW_WR_OP_M) 117 118 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */ 119 #define FW_WR_ATOMIC_S 23 120 #define FW_WR_ATOMIC_V(x) ((x) << FW_WR_ATOMIC_S) 121 122 /* flush flag (hi) - firmware flushes flushable work request buffered 123 * in the flow context. 124 */ 125 #define FW_WR_FLUSH_S 22 126 #define FW_WR_FLUSH_V(x) ((x) << FW_WR_FLUSH_S) 127 128 /* completion flag (hi) - firmware generates a cpl_fw6_ack */ 129 #define FW_WR_COMPL_S 21 130 #define FW_WR_COMPL_V(x) ((x) << FW_WR_COMPL_S) 131 #define FW_WR_COMPL_F FW_WR_COMPL_V(1U) 132 133 /* work request immediate data length (hi) */ 134 #define FW_WR_IMMDLEN_S 0 135 #define FW_WR_IMMDLEN_M 0xff 136 #define FW_WR_IMMDLEN_V(x) ((x) << FW_WR_IMMDLEN_S) 137 138 /* egress queue status update to associated ingress queue entry (lo) */ 139 #define FW_WR_EQUIQ_S 31 140 #define FW_WR_EQUIQ_V(x) ((x) << FW_WR_EQUIQ_S) 141 #define FW_WR_EQUIQ_F FW_WR_EQUIQ_V(1U) 142 143 /* egress queue status update to egress queue status entry (lo) */ 144 #define FW_WR_EQUEQ_S 30 145 #define FW_WR_EQUEQ_V(x) ((x) << FW_WR_EQUEQ_S) 146 #define FW_WR_EQUEQ_F FW_WR_EQUEQ_V(1U) 147 148 /* flow context identifier (lo) */ 149 #define FW_WR_FLOWID_S 8 150 #define FW_WR_FLOWID_V(x) ((x) << FW_WR_FLOWID_S) 151 152 /* length in units of 16-bytes (lo) */ 153 #define FW_WR_LEN16_S 0 154 #define FW_WR_LEN16_V(x) ((x) << FW_WR_LEN16_S) 155 156 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 157 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327 158 159 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 160 enum fw_filter_wr_cookie { 161 FW_FILTER_WR_SUCCESS, 162 FW_FILTER_WR_FLT_ADDED, 163 FW_FILTER_WR_FLT_DELETED, 164 FW_FILTER_WR_SMT_TBL_FULL, 165 FW_FILTER_WR_EINVAL, 166 }; 167 168 struct fw_filter_wr { 169 __be32 op_pkd; 170 __be32 len16_pkd; 171 __be64 r3; 172 __be32 tid_to_iq; 173 __be32 del_filter_to_l2tix; 174 __be16 ethtype; 175 __be16 ethtypem; 176 __u8 frag_to_ovlan_vldm; 177 __u8 smac_sel; 178 __be16 rx_chan_rx_rpl_iq; 179 __be32 maci_to_matchtypem; 180 __u8 ptcl; 181 __u8 ptclm; 182 __u8 ttyp; 183 __u8 ttypm; 184 __be16 ivlan; 185 __be16 ivlanm; 186 __be16 ovlan; 187 __be16 ovlanm; 188 __u8 lip[16]; 189 __u8 lipm[16]; 190 __u8 fip[16]; 191 __u8 fipm[16]; 192 __be16 lp; 193 __be16 lpm; 194 __be16 fp; 195 __be16 fpm; 196 __be16 r7; 197 __u8 sma[6]; 198 }; 199 200 #define S_FW_FILTER_WR_TID 12 201 #define M_FW_FILTER_WR_TID 0xfffff 202 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID) 203 #define G_FW_FILTER_WR_TID(x) \ 204 (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID) 205 206 #define S_FW_FILTER_WR_RQTYPE 11 207 #define M_FW_FILTER_WR_RQTYPE 0x1 208 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE) 209 #define G_FW_FILTER_WR_RQTYPE(x) \ 210 (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE) 211 #define F_FW_FILTER_WR_RQTYPE V_FW_FILTER_WR_RQTYPE(1U) 212 213 #define S_FW_FILTER_WR_NOREPLY 10 214 #define M_FW_FILTER_WR_NOREPLY 0x1 215 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY) 216 #define G_FW_FILTER_WR_NOREPLY(x) \ 217 (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY) 218 #define F_FW_FILTER_WR_NOREPLY V_FW_FILTER_WR_NOREPLY(1U) 219 220 #define S_FW_FILTER_WR_IQ 0 221 #define M_FW_FILTER_WR_IQ 0x3ff 222 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ) 223 #define G_FW_FILTER_WR_IQ(x) \ 224 (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ) 225 226 #define S_FW_FILTER_WR_DEL_FILTER 31 227 #define M_FW_FILTER_WR_DEL_FILTER 0x1 228 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER) 229 #define G_FW_FILTER_WR_DEL_FILTER(x) \ 230 (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER) 231 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U) 232 233 #define S_FW_FILTER_WR_RPTTID 25 234 #define M_FW_FILTER_WR_RPTTID 0x1 235 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID) 236 #define G_FW_FILTER_WR_RPTTID(x) \ 237 (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID) 238 #define F_FW_FILTER_WR_RPTTID V_FW_FILTER_WR_RPTTID(1U) 239 240 #define S_FW_FILTER_WR_DROP 24 241 #define M_FW_FILTER_WR_DROP 0x1 242 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP) 243 #define G_FW_FILTER_WR_DROP(x) \ 244 (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP) 245 #define F_FW_FILTER_WR_DROP V_FW_FILTER_WR_DROP(1U) 246 247 #define S_FW_FILTER_WR_DIRSTEER 23 248 #define M_FW_FILTER_WR_DIRSTEER 0x1 249 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER) 250 #define G_FW_FILTER_WR_DIRSTEER(x) \ 251 (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER) 252 #define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U) 253 254 #define S_FW_FILTER_WR_MASKHASH 22 255 #define M_FW_FILTER_WR_MASKHASH 0x1 256 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH) 257 #define G_FW_FILTER_WR_MASKHASH(x) \ 258 (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH) 259 #define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U) 260 261 #define S_FW_FILTER_WR_DIRSTEERHASH 21 262 #define M_FW_FILTER_WR_DIRSTEERHASH 0x1 263 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH) 264 #define G_FW_FILTER_WR_DIRSTEERHASH(x) \ 265 (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH) 266 #define F_FW_FILTER_WR_DIRSTEERHASH V_FW_FILTER_WR_DIRSTEERHASH(1U) 267 268 #define S_FW_FILTER_WR_LPBK 20 269 #define M_FW_FILTER_WR_LPBK 0x1 270 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK) 271 #define G_FW_FILTER_WR_LPBK(x) \ 272 (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK) 273 #define F_FW_FILTER_WR_LPBK V_FW_FILTER_WR_LPBK(1U) 274 275 #define S_FW_FILTER_WR_DMAC 19 276 #define M_FW_FILTER_WR_DMAC 0x1 277 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC) 278 #define G_FW_FILTER_WR_DMAC(x) \ 279 (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC) 280 #define F_FW_FILTER_WR_DMAC V_FW_FILTER_WR_DMAC(1U) 281 282 #define S_FW_FILTER_WR_SMAC 18 283 #define M_FW_FILTER_WR_SMAC 0x1 284 #define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC) 285 #define G_FW_FILTER_WR_SMAC(x) \ 286 (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC) 287 #define F_FW_FILTER_WR_SMAC V_FW_FILTER_WR_SMAC(1U) 288 289 #define S_FW_FILTER_WR_INSVLAN 17 290 #define M_FW_FILTER_WR_INSVLAN 0x1 291 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN) 292 #define G_FW_FILTER_WR_INSVLAN(x) \ 293 (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN) 294 #define F_FW_FILTER_WR_INSVLAN V_FW_FILTER_WR_INSVLAN(1U) 295 296 #define S_FW_FILTER_WR_RMVLAN 16 297 #define M_FW_FILTER_WR_RMVLAN 0x1 298 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN) 299 #define G_FW_FILTER_WR_RMVLAN(x) \ 300 (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN) 301 #define F_FW_FILTER_WR_RMVLAN V_FW_FILTER_WR_RMVLAN(1U) 302 303 #define S_FW_FILTER_WR_HITCNTS 15 304 #define M_FW_FILTER_WR_HITCNTS 0x1 305 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS) 306 #define G_FW_FILTER_WR_HITCNTS(x) \ 307 (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS) 308 #define F_FW_FILTER_WR_HITCNTS V_FW_FILTER_WR_HITCNTS(1U) 309 310 #define S_FW_FILTER_WR_TXCHAN 13 311 #define M_FW_FILTER_WR_TXCHAN 0x3 312 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN) 313 #define G_FW_FILTER_WR_TXCHAN(x) \ 314 (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN) 315 316 #define S_FW_FILTER_WR_PRIO 12 317 #define M_FW_FILTER_WR_PRIO 0x1 318 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO) 319 #define G_FW_FILTER_WR_PRIO(x) \ 320 (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO) 321 #define F_FW_FILTER_WR_PRIO V_FW_FILTER_WR_PRIO(1U) 322 323 #define S_FW_FILTER_WR_L2TIX 0 324 #define M_FW_FILTER_WR_L2TIX 0xfff 325 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX) 326 #define G_FW_FILTER_WR_L2TIX(x) \ 327 (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX) 328 329 #define S_FW_FILTER_WR_FRAG 7 330 #define M_FW_FILTER_WR_FRAG 0x1 331 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG) 332 #define G_FW_FILTER_WR_FRAG(x) \ 333 (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG) 334 #define F_FW_FILTER_WR_FRAG V_FW_FILTER_WR_FRAG(1U) 335 336 #define S_FW_FILTER_WR_FRAGM 6 337 #define M_FW_FILTER_WR_FRAGM 0x1 338 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM) 339 #define G_FW_FILTER_WR_FRAGM(x) \ 340 (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM) 341 #define F_FW_FILTER_WR_FRAGM V_FW_FILTER_WR_FRAGM(1U) 342 343 #define S_FW_FILTER_WR_IVLAN_VLD 5 344 #define M_FW_FILTER_WR_IVLAN_VLD 0x1 345 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD) 346 #define G_FW_FILTER_WR_IVLAN_VLD(x) \ 347 (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD) 348 #define F_FW_FILTER_WR_IVLAN_VLD V_FW_FILTER_WR_IVLAN_VLD(1U) 349 350 #define S_FW_FILTER_WR_OVLAN_VLD 4 351 #define M_FW_FILTER_WR_OVLAN_VLD 0x1 352 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD) 353 #define G_FW_FILTER_WR_OVLAN_VLD(x) \ 354 (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD) 355 #define F_FW_FILTER_WR_OVLAN_VLD V_FW_FILTER_WR_OVLAN_VLD(1U) 356 357 #define S_FW_FILTER_WR_IVLAN_VLDM 3 358 #define M_FW_FILTER_WR_IVLAN_VLDM 0x1 359 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM) 360 #define G_FW_FILTER_WR_IVLAN_VLDM(x) \ 361 (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM) 362 #define F_FW_FILTER_WR_IVLAN_VLDM V_FW_FILTER_WR_IVLAN_VLDM(1U) 363 364 #define S_FW_FILTER_WR_OVLAN_VLDM 2 365 #define M_FW_FILTER_WR_OVLAN_VLDM 0x1 366 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM) 367 #define G_FW_FILTER_WR_OVLAN_VLDM(x) \ 368 (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM) 369 #define F_FW_FILTER_WR_OVLAN_VLDM V_FW_FILTER_WR_OVLAN_VLDM(1U) 370 371 #define S_FW_FILTER_WR_RX_CHAN 15 372 #define M_FW_FILTER_WR_RX_CHAN 0x1 373 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN) 374 #define G_FW_FILTER_WR_RX_CHAN(x) \ 375 (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN) 376 #define F_FW_FILTER_WR_RX_CHAN V_FW_FILTER_WR_RX_CHAN(1U) 377 378 #define S_FW_FILTER_WR_RX_RPL_IQ 0 379 #define M_FW_FILTER_WR_RX_RPL_IQ 0x3ff 380 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ) 381 #define G_FW_FILTER_WR_RX_RPL_IQ(x) \ 382 (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ) 383 384 #define S_FW_FILTER_WR_MACI 23 385 #define M_FW_FILTER_WR_MACI 0x1ff 386 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI) 387 #define G_FW_FILTER_WR_MACI(x) \ 388 (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI) 389 390 #define S_FW_FILTER_WR_MACIM 14 391 #define M_FW_FILTER_WR_MACIM 0x1ff 392 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM) 393 #define G_FW_FILTER_WR_MACIM(x) \ 394 (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM) 395 396 #define S_FW_FILTER_WR_FCOE 13 397 #define M_FW_FILTER_WR_FCOE 0x1 398 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE) 399 #define G_FW_FILTER_WR_FCOE(x) \ 400 (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE) 401 #define F_FW_FILTER_WR_FCOE V_FW_FILTER_WR_FCOE(1U) 402 403 #define S_FW_FILTER_WR_FCOEM 12 404 #define M_FW_FILTER_WR_FCOEM 0x1 405 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM) 406 #define G_FW_FILTER_WR_FCOEM(x) \ 407 (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM) 408 #define F_FW_FILTER_WR_FCOEM V_FW_FILTER_WR_FCOEM(1U) 409 410 #define S_FW_FILTER_WR_PORT 9 411 #define M_FW_FILTER_WR_PORT 0x7 412 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT) 413 #define G_FW_FILTER_WR_PORT(x) \ 414 (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT) 415 416 #define S_FW_FILTER_WR_PORTM 6 417 #define M_FW_FILTER_WR_PORTM 0x7 418 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM) 419 #define G_FW_FILTER_WR_PORTM(x) \ 420 (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM) 421 422 #define S_FW_FILTER_WR_MATCHTYPE 3 423 #define M_FW_FILTER_WR_MATCHTYPE 0x7 424 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE) 425 #define G_FW_FILTER_WR_MATCHTYPE(x) \ 426 (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE) 427 428 #define S_FW_FILTER_WR_MATCHTYPEM 0 429 #define M_FW_FILTER_WR_MATCHTYPEM 0x7 430 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM) 431 #define G_FW_FILTER_WR_MATCHTYPEM(x) \ 432 (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM) 433 434 struct fw_ulptx_wr { 435 __be32 op_to_compl; 436 __be32 flowid_len16; 437 u64 cookie; 438 }; 439 440 struct fw_tp_wr { 441 __be32 op_to_immdlen; 442 __be32 flowid_len16; 443 u64 cookie; 444 }; 445 446 struct fw_eth_tx_pkt_wr { 447 __be32 op_immdlen; 448 __be32 equiq_to_len16; 449 __be64 r3; 450 }; 451 452 struct fw_ofld_connection_wr { 453 __be32 op_compl; 454 __be32 len16_pkd; 455 __u64 cookie; 456 __be64 r2; 457 __be64 r3; 458 struct fw_ofld_connection_le { 459 __be32 version_cpl; 460 __be32 filter; 461 __be32 r1; 462 __be16 lport; 463 __be16 pport; 464 union fw_ofld_connection_leip { 465 struct fw_ofld_connection_le_ipv4 { 466 __be32 pip; 467 __be32 lip; 468 __be64 r0; 469 __be64 r1; 470 __be64 r2; 471 } ipv4; 472 struct fw_ofld_connection_le_ipv6 { 473 __be64 pip_hi; 474 __be64 pip_lo; 475 __be64 lip_hi; 476 __be64 lip_lo; 477 } ipv6; 478 } u; 479 } le; 480 struct fw_ofld_connection_tcb { 481 __be32 t_state_to_astid; 482 __be16 cplrxdataack_cplpassacceptrpl; 483 __be16 rcv_adv; 484 __be32 rcv_nxt; 485 __be32 tx_max; 486 __be64 opt0; 487 __be32 opt2; 488 __be32 r1; 489 __be64 r2; 490 __be64 r3; 491 } tcb; 492 }; 493 494 #define S_FW_OFLD_CONNECTION_WR_VERSION 31 495 #define M_FW_OFLD_CONNECTION_WR_VERSION 0x1 496 #define V_FW_OFLD_CONNECTION_WR_VERSION(x) \ 497 ((x) << S_FW_OFLD_CONNECTION_WR_VERSION) 498 #define G_FW_OFLD_CONNECTION_WR_VERSION(x) \ 499 (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \ 500 M_FW_OFLD_CONNECTION_WR_VERSION) 501 #define F_FW_OFLD_CONNECTION_WR_VERSION \ 502 V_FW_OFLD_CONNECTION_WR_VERSION(1U) 503 504 #define S_FW_OFLD_CONNECTION_WR_CPL 30 505 #define M_FW_OFLD_CONNECTION_WR_CPL 0x1 506 #define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL) 507 #define G_FW_OFLD_CONNECTION_WR_CPL(x) \ 508 (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL) 509 #define F_FW_OFLD_CONNECTION_WR_CPL V_FW_OFLD_CONNECTION_WR_CPL(1U) 510 511 #define S_FW_OFLD_CONNECTION_WR_T_STATE 28 512 #define M_FW_OFLD_CONNECTION_WR_T_STATE 0xf 513 #define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 514 ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE) 515 #define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 516 (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \ 517 M_FW_OFLD_CONNECTION_WR_T_STATE) 518 519 #define S_FW_OFLD_CONNECTION_WR_RCV_SCALE 24 520 #define M_FW_OFLD_CONNECTION_WR_RCV_SCALE 0xf 521 #define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 522 ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE) 523 #define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 524 (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \ 525 M_FW_OFLD_CONNECTION_WR_RCV_SCALE) 526 527 #define S_FW_OFLD_CONNECTION_WR_ASTID 0 528 #define M_FW_OFLD_CONNECTION_WR_ASTID 0xffffff 529 #define V_FW_OFLD_CONNECTION_WR_ASTID(x) \ 530 ((x) << S_FW_OFLD_CONNECTION_WR_ASTID) 531 #define G_FW_OFLD_CONNECTION_WR_ASTID(x) \ 532 (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID) 533 534 #define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 15 535 #define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 0x1 536 #define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 537 ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 538 #define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 539 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \ 540 M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 541 #define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \ 542 V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U) 543 544 #define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 14 545 #define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 0x1 546 #define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 547 ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 548 #define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 549 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \ 550 M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 551 #define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \ 552 V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U) 553 554 enum fw_flowc_mnem { 555 FW_FLOWC_MNEM_PFNVFN, /* PFN [15:8] VFN [7:0] */ 556 FW_FLOWC_MNEM_CH, 557 FW_FLOWC_MNEM_PORT, 558 FW_FLOWC_MNEM_IQID, 559 FW_FLOWC_MNEM_SNDNXT, 560 FW_FLOWC_MNEM_RCVNXT, 561 FW_FLOWC_MNEM_SNDBUF, 562 FW_FLOWC_MNEM_MSS, 563 }; 564 565 struct fw_flowc_mnemval { 566 u8 mnemonic; 567 u8 r4[3]; 568 __be32 val; 569 }; 570 571 struct fw_flowc_wr { 572 __be32 op_to_nparams; 573 __be32 flowid_len16; 574 struct fw_flowc_mnemval mnemval[0]; 575 }; 576 577 #define FW_FLOWC_WR_NPARAMS_S 0 578 #define FW_FLOWC_WR_NPARAMS_V(x) ((x) << FW_FLOWC_WR_NPARAMS_S) 579 580 struct fw_ofld_tx_data_wr { 581 __be32 op_to_immdlen; 582 __be32 flowid_len16; 583 __be32 plen; 584 __be32 tunnel_to_proxy; 585 }; 586 587 #define FW_OFLD_TX_DATA_WR_TUNNEL_S 19 588 #define FW_OFLD_TX_DATA_WR_TUNNEL_V(x) ((x) << FW_OFLD_TX_DATA_WR_TUNNEL_S) 589 590 #define FW_OFLD_TX_DATA_WR_SAVE_S 18 591 #define FW_OFLD_TX_DATA_WR_SAVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SAVE_S) 592 593 #define FW_OFLD_TX_DATA_WR_FLUSH_S 17 594 #define FW_OFLD_TX_DATA_WR_FLUSH_V(x) ((x) << FW_OFLD_TX_DATA_WR_FLUSH_S) 595 #define FW_OFLD_TX_DATA_WR_FLUSH_F FW_OFLD_TX_DATA_WR_FLUSH_V(1U) 596 597 #define FW_OFLD_TX_DATA_WR_URGENT_S 16 598 #define FW_OFLD_TX_DATA_WR_URGENT_V(x) ((x) << FW_OFLD_TX_DATA_WR_URGENT_S) 599 600 #define FW_OFLD_TX_DATA_WR_MORE_S 15 601 #define FW_OFLD_TX_DATA_WR_MORE_V(x) ((x) << FW_OFLD_TX_DATA_WR_MORE_S) 602 603 #define FW_OFLD_TX_DATA_WR_SHOVE_S 14 604 #define FW_OFLD_TX_DATA_WR_SHOVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SHOVE_S) 605 #define FW_OFLD_TX_DATA_WR_SHOVE_F FW_OFLD_TX_DATA_WR_SHOVE_V(1U) 606 607 #define FW_OFLD_TX_DATA_WR_ULPMODE_S 10 608 #define FW_OFLD_TX_DATA_WR_ULPMODE_V(x) ((x) << FW_OFLD_TX_DATA_WR_ULPMODE_S) 609 610 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_S 6 611 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_V(x) \ 612 ((x) << FW_OFLD_TX_DATA_WR_ULPSUBMODE_S) 613 614 struct fw_cmd_wr { 615 __be32 op_dma; 616 #define FW_CMD_WR_DMA (1U << 17) 617 __be32 len16_pkd; 618 __be64 cookie_daddr; 619 }; 620 621 #define FW_CMD_WR_DMA_S 17 622 #define FW_CMD_WR_DMA_V(x) ((x) << FW_CMD_WR_DMA_S) 623 624 struct fw_eth_tx_pkt_vm_wr { 625 __be32 op_immdlen; 626 __be32 equiq_to_len16; 627 __be32 r3[2]; 628 u8 ethmacdst[6]; 629 u8 ethmacsrc[6]; 630 __be16 ethtype; 631 __be16 vlantci; 632 }; 633 634 #define FW_CMD_MAX_TIMEOUT 10000 635 636 /* 637 * If a host driver does a HELLO and discovers that there's already a MASTER 638 * selected, we may have to wait for that MASTER to finish issuing RESET, 639 * configuration and INITIALIZE commands. Also, there's a possibility that 640 * our own HELLO may get lost if it happens right as the MASTER is issuign a 641 * RESET command, so we need to be willing to make a few retries of our HELLO. 642 */ 643 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 644 #define FW_CMD_HELLO_RETRIES 3 645 646 647 enum fw_cmd_opcodes { 648 FW_LDST_CMD = 0x01, 649 FW_RESET_CMD = 0x03, 650 FW_HELLO_CMD = 0x04, 651 FW_BYE_CMD = 0x05, 652 FW_INITIALIZE_CMD = 0x06, 653 FW_CAPS_CONFIG_CMD = 0x07, 654 FW_PARAMS_CMD = 0x08, 655 FW_PFVF_CMD = 0x09, 656 FW_IQ_CMD = 0x10, 657 FW_EQ_MNGT_CMD = 0x11, 658 FW_EQ_ETH_CMD = 0x12, 659 FW_EQ_CTRL_CMD = 0x13, 660 FW_EQ_OFLD_CMD = 0x21, 661 FW_VI_CMD = 0x14, 662 FW_VI_MAC_CMD = 0x15, 663 FW_VI_RXMODE_CMD = 0x16, 664 FW_VI_ENABLE_CMD = 0x17, 665 FW_ACL_MAC_CMD = 0x18, 666 FW_ACL_VLAN_CMD = 0x19, 667 FW_VI_STATS_CMD = 0x1a, 668 FW_PORT_CMD = 0x1b, 669 FW_PORT_STATS_CMD = 0x1c, 670 FW_PORT_LB_STATS_CMD = 0x1d, 671 FW_PORT_TRACE_CMD = 0x1e, 672 FW_PORT_TRACE_MMAP_CMD = 0x1f, 673 FW_RSS_IND_TBL_CMD = 0x20, 674 FW_RSS_GLB_CONFIG_CMD = 0x22, 675 FW_RSS_VI_CONFIG_CMD = 0x23, 676 FW_CLIP_CMD = 0x28, 677 FW_LASTC2E_CMD = 0x40, 678 FW_ERROR_CMD = 0x80, 679 FW_DEBUG_CMD = 0x81, 680 }; 681 682 enum fw_cmd_cap { 683 FW_CMD_CAP_PF = 0x01, 684 FW_CMD_CAP_DMAQ = 0x02, 685 FW_CMD_CAP_PORT = 0x04, 686 FW_CMD_CAP_PORTPROMISC = 0x08, 687 FW_CMD_CAP_PORTSTATS = 0x10, 688 FW_CMD_CAP_VF = 0x80, 689 }; 690 691 /* 692 * Generic command header flit0 693 */ 694 struct fw_cmd_hdr { 695 __be32 hi; 696 __be32 lo; 697 }; 698 699 #define FW_CMD_OP_S 24 700 #define FW_CMD_OP_M 0xff 701 #define FW_CMD_OP_V(x) ((x) << FW_CMD_OP_S) 702 #define FW_CMD_OP_G(x) (((x) >> FW_CMD_OP_S) & FW_CMD_OP_M) 703 704 #define FW_CMD_REQUEST_S 23 705 #define FW_CMD_REQUEST_V(x) ((x) << FW_CMD_REQUEST_S) 706 #define FW_CMD_REQUEST_F FW_CMD_REQUEST_V(1U) 707 708 #define FW_CMD_READ_S 22 709 #define FW_CMD_READ_V(x) ((x) << FW_CMD_READ_S) 710 #define FW_CMD_READ_F FW_CMD_READ_V(1U) 711 712 #define FW_CMD_WRITE_S 21 713 #define FW_CMD_WRITE_V(x) ((x) << FW_CMD_WRITE_S) 714 #define FW_CMD_WRITE_F FW_CMD_WRITE_V(1U) 715 716 #define FW_CMD_EXEC_S 20 717 #define FW_CMD_EXEC_V(x) ((x) << FW_CMD_EXEC_S) 718 #define FW_CMD_EXEC_F FW_CMD_EXEC_V(1U) 719 720 #define FW_CMD_RAMASK_S 20 721 #define FW_CMD_RAMASK_V(x) ((x) << FW_CMD_RAMASK_S) 722 723 #define FW_CMD_RETVAL_S 8 724 #define FW_CMD_RETVAL_M 0xff 725 #define FW_CMD_RETVAL_V(x) ((x) << FW_CMD_RETVAL_S) 726 #define FW_CMD_RETVAL_G(x) (((x) >> FW_CMD_RETVAL_S) & FW_CMD_RETVAL_M) 727 728 #define FW_CMD_LEN16_S 0 729 #define FW_CMD_LEN16_V(x) ((x) << FW_CMD_LEN16_S) 730 731 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 732 733 enum fw_ldst_addrspc { 734 FW_LDST_ADDRSPC_FIRMWARE = 0x0001, 735 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, 736 FW_LDST_ADDRSPC_SGE_INGC = 0x0009, 737 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, 738 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 739 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 740 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 741 FW_LDST_ADDRSPC_TP_MIB = 0x0012, 742 FW_LDST_ADDRSPC_MDIO = 0x0018, 743 FW_LDST_ADDRSPC_MPS = 0x0020, 744 FW_LDST_ADDRSPC_FUNC = 0x0028, 745 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, 746 }; 747 748 enum fw_ldst_mps_fid { 749 FW_LDST_MPS_ATRB, 750 FW_LDST_MPS_RPLC 751 }; 752 753 enum fw_ldst_func_access_ctl { 754 FW_LDST_FUNC_ACC_CTL_VIID, 755 FW_LDST_FUNC_ACC_CTL_FID 756 }; 757 758 enum fw_ldst_func_mod_index { 759 FW_LDST_FUNC_MPS 760 }; 761 762 struct fw_ldst_cmd { 763 __be32 op_to_addrspace; 764 #define FW_LDST_CMD_ADDRSPACE(x) ((x) << 0) 765 __be32 cycles_to_len16; 766 union fw_ldst { 767 struct fw_ldst_addrval { 768 __be32 addr; 769 __be32 val; 770 } addrval; 771 struct fw_ldst_idctxt { 772 __be32 physid; 773 __be32 msg_pkd; 774 __be32 ctxt_data7; 775 __be32 ctxt_data6; 776 __be32 ctxt_data5; 777 __be32 ctxt_data4; 778 __be32 ctxt_data3; 779 __be32 ctxt_data2; 780 __be32 ctxt_data1; 781 __be32 ctxt_data0; 782 } idctxt; 783 struct fw_ldst_mdio { 784 __be16 paddr_mmd; 785 __be16 raddr; 786 __be16 vctl; 787 __be16 rval; 788 } mdio; 789 struct fw_ldst_mps { 790 __be16 fid_ctl; 791 __be16 rplcpf_pkd; 792 __be32 rplc127_96; 793 __be32 rplc95_64; 794 __be32 rplc63_32; 795 __be32 rplc31_0; 796 __be32 atrb; 797 __be16 vlan[16]; 798 } mps; 799 struct fw_ldst_func { 800 u8 access_ctl; 801 u8 mod_index; 802 __be16 ctl_id; 803 __be32 offset; 804 __be64 data0; 805 __be64 data1; 806 } func; 807 struct fw_ldst_pcie { 808 u8 ctrl_to_fn; 809 u8 bnum; 810 u8 r; 811 u8 ext_r; 812 u8 select_naccess; 813 u8 pcie_fn; 814 __be16 nset_pkd; 815 __be32 data[12]; 816 } pcie; 817 } u; 818 }; 819 820 #define FW_LDST_CMD_MSG(x) ((x) << 31) 821 #define FW_LDST_CMD_PADDR(x) ((x) << 8) 822 #define FW_LDST_CMD_MMD(x) ((x) << 0) 823 #define FW_LDST_CMD_FID(x) ((x) << 15) 824 #define FW_LDST_CMD_CTL(x) ((x) << 0) 825 #define FW_LDST_CMD_RPLCPF(x) ((x) << 0) 826 #define FW_LDST_CMD_LC (1U << 4) 827 #define FW_LDST_CMD_NACCESS(x) ((x) << 0) 828 #define FW_LDST_CMD_FN(x) ((x) << 0) 829 830 struct fw_reset_cmd { 831 __be32 op_to_write; 832 __be32 retval_len16; 833 __be32 val; 834 __be32 halt_pkd; 835 }; 836 837 #define FW_RESET_CMD_HALT_SHIFT 31 838 #define FW_RESET_CMD_HALT_MASK 0x1 839 #define FW_RESET_CMD_HALT(x) ((x) << FW_RESET_CMD_HALT_SHIFT) 840 #define FW_RESET_CMD_HALT_GET(x) \ 841 (((x) >> FW_RESET_CMD_HALT_SHIFT) & FW_RESET_CMD_HALT_MASK) 842 843 enum fw_hellow_cmd { 844 fw_hello_cmd_stage_os = 0x0 845 }; 846 847 struct fw_hello_cmd { 848 __be32 op_to_write; 849 __be32 retval_len16; 850 __be32 err_to_clearinit; 851 #define FW_HELLO_CMD_ERR (1U << 31) 852 #define FW_HELLO_CMD_INIT (1U << 30) 853 #define FW_HELLO_CMD_MASTERDIS(x) ((x) << 29) 854 #define FW_HELLO_CMD_MASTERFORCE(x) ((x) << 28) 855 #define FW_HELLO_CMD_MBMASTER_MASK 0xfU 856 #define FW_HELLO_CMD_MBMASTER_SHIFT 24 857 #define FW_HELLO_CMD_MBMASTER(x) ((x) << FW_HELLO_CMD_MBMASTER_SHIFT) 858 #define FW_HELLO_CMD_MBMASTER_GET(x) \ 859 (((x) >> FW_HELLO_CMD_MBMASTER_SHIFT) & FW_HELLO_CMD_MBMASTER_MASK) 860 #define FW_HELLO_CMD_MBASYNCNOTINT(x) ((x) << 23) 861 #define FW_HELLO_CMD_MBASYNCNOT(x) ((x) << 20) 862 #define FW_HELLO_CMD_STAGE(x) ((x) << 17) 863 #define FW_HELLO_CMD_CLEARINIT (1U << 16) 864 __be32 fwrev; 865 }; 866 867 struct fw_bye_cmd { 868 __be32 op_to_write; 869 __be32 retval_len16; 870 __be64 r3; 871 }; 872 873 struct fw_initialize_cmd { 874 __be32 op_to_write; 875 __be32 retval_len16; 876 __be64 r3; 877 }; 878 879 enum fw_caps_config_hm { 880 FW_CAPS_CONFIG_HM_PCIE = 0x00000001, 881 FW_CAPS_CONFIG_HM_PL = 0x00000002, 882 FW_CAPS_CONFIG_HM_SGE = 0x00000004, 883 FW_CAPS_CONFIG_HM_CIM = 0x00000008, 884 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, 885 FW_CAPS_CONFIG_HM_TP = 0x00000020, 886 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, 887 FW_CAPS_CONFIG_HM_PMRX = 0x00000080, 888 FW_CAPS_CONFIG_HM_PMTX = 0x00000100, 889 FW_CAPS_CONFIG_HM_MC = 0x00000200, 890 FW_CAPS_CONFIG_HM_LE = 0x00000400, 891 FW_CAPS_CONFIG_HM_MPS = 0x00000800, 892 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, 893 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, 894 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, 895 FW_CAPS_CONFIG_HM_MI = 0x00008000, 896 FW_CAPS_CONFIG_HM_I2CM = 0x00010000, 897 FW_CAPS_CONFIG_HM_NCSI = 0x00020000, 898 FW_CAPS_CONFIG_HM_SMB = 0x00040000, 899 FW_CAPS_CONFIG_HM_MA = 0x00080000, 900 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, 901 FW_CAPS_CONFIG_HM_PMU = 0x00200000, 902 FW_CAPS_CONFIG_HM_UART = 0x00400000, 903 FW_CAPS_CONFIG_HM_SF = 0x00800000, 904 }; 905 906 enum fw_caps_config_nbm { 907 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, 908 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, 909 }; 910 911 enum fw_caps_config_link { 912 FW_CAPS_CONFIG_LINK_PPP = 0x00000001, 913 FW_CAPS_CONFIG_LINK_QFC = 0x00000002, 914 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, 915 }; 916 917 enum fw_caps_config_switch { 918 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, 919 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, 920 }; 921 922 enum fw_caps_config_nic { 923 FW_CAPS_CONFIG_NIC = 0x00000001, 924 FW_CAPS_CONFIG_NIC_VM = 0x00000002, 925 }; 926 927 enum fw_caps_config_ofld { 928 FW_CAPS_CONFIG_OFLD = 0x00000001, 929 }; 930 931 enum fw_caps_config_rdma { 932 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, 933 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, 934 }; 935 936 enum fw_caps_config_iscsi { 937 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, 938 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, 939 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, 940 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, 941 }; 942 943 enum fw_caps_config_fcoe { 944 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 945 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 946 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 947 }; 948 949 enum fw_memtype_cf { 950 FW_MEMTYPE_CF_EDC0 = 0x0, 951 FW_MEMTYPE_CF_EDC1 = 0x1, 952 FW_MEMTYPE_CF_EXTMEM = 0x2, 953 FW_MEMTYPE_CF_FLASH = 0x4, 954 FW_MEMTYPE_CF_INTERNAL = 0x5, 955 }; 956 957 struct fw_caps_config_cmd { 958 __be32 op_to_write; 959 __be32 cfvalid_to_len16; 960 __be32 r2; 961 __be32 hwmbitmap; 962 __be16 nbmcaps; 963 __be16 linkcaps; 964 __be16 switchcaps; 965 __be16 r3; 966 __be16 niccaps; 967 __be16 ofldcaps; 968 __be16 rdmacaps; 969 __be16 r4; 970 __be16 iscsicaps; 971 __be16 fcoecaps; 972 __be32 cfcsum; 973 __be32 finiver; 974 __be32 finicsum; 975 }; 976 977 #define FW_CAPS_CONFIG_CMD_CFVALID (1U << 27) 978 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) ((x) << 24) 979 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) ((x) << 16) 980 981 /* 982 * params command mnemonics 983 */ 984 enum fw_params_mnem { 985 FW_PARAMS_MNEM_DEV = 1, /* device params */ 986 FW_PARAMS_MNEM_PFVF = 2, /* function params */ 987 FW_PARAMS_MNEM_REG = 3, /* limited register access */ 988 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 989 FW_PARAMS_MNEM_LAST 990 }; 991 992 /* 993 * device parameters 994 */ 995 enum fw_params_param_dev { 996 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 997 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 998 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs 999 * allocated by the device's 1000 * Lookup Engine 1001 */ 1002 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, 1003 FW_PARAMS_PARAM_DEV_INTVER_NIC = 0x04, 1004 FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05, 1005 FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06, 1006 FW_PARAMS_PARAM_DEV_INTVER_RI = 0x07, 1007 FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08, 1008 FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09, 1009 FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A, 1010 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, 1011 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, 1012 FW_PARAMS_PARAM_DEV_CF = 0x0D, 1013 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD */ 1014 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER = 0x14, /* max supported adap IRD */ 1015 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, 1016 }; 1017 1018 /* 1019 * physical and virtual function parameters 1020 */ 1021 enum fw_params_param_pfvf { 1022 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, 1023 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, 1024 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, 1025 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 1026 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 1027 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 1028 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 1029 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, 1030 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, 1031 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, 1032 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, 1033 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, 1034 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, 1035 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, 1036 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, 1037 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, 1038 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, 1039 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, 1040 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, 1041 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 1042 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 1043 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15, 1044 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16, 1045 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17, 1046 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18, 1047 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, 1048 FW_PARAMS_PARAM_PFVF_VIID = 0x24, 1049 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 1050 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 1051 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 1052 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 1053 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 1054 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 1055 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, 1056 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 1057 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 1058 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, 1059 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30, 1060 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31 1061 }; 1062 1063 /* 1064 * dma queue parameters 1065 */ 1066 enum fw_params_param_dmaq { 1067 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 1068 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 1069 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 1070 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 1071 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, 1072 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13, 1073 }; 1074 1075 #define FW_PARAMS_MNEM(x) ((x) << 24) 1076 #define FW_PARAMS_PARAM_X(x) ((x) << 16) 1077 #define FW_PARAMS_PARAM_Y_SHIFT 8 1078 #define FW_PARAMS_PARAM_Y_MASK 0xffU 1079 #define FW_PARAMS_PARAM_Y(x) ((x) << FW_PARAMS_PARAM_Y_SHIFT) 1080 #define FW_PARAMS_PARAM_Y_GET(x) (((x) >> FW_PARAMS_PARAM_Y_SHIFT) &\ 1081 FW_PARAMS_PARAM_Y_MASK) 1082 #define FW_PARAMS_PARAM_Z_SHIFT 0 1083 #define FW_PARAMS_PARAM_Z_MASK 0xffu 1084 #define FW_PARAMS_PARAM_Z(x) ((x) << FW_PARAMS_PARAM_Z_SHIFT) 1085 #define FW_PARAMS_PARAM_Z_GET(x) (((x) >> FW_PARAMS_PARAM_Z_SHIFT) &\ 1086 FW_PARAMS_PARAM_Z_MASK) 1087 #define FW_PARAMS_PARAM_XYZ(x) ((x) << 0) 1088 #define FW_PARAMS_PARAM_YZ(x) ((x) << 0) 1089 1090 struct fw_params_cmd { 1091 __be32 op_to_vfn; 1092 __be32 retval_len16; 1093 struct fw_params_param { 1094 __be32 mnem; 1095 __be32 val; 1096 } param[7]; 1097 }; 1098 1099 #define FW_PARAMS_CMD_PFN(x) ((x) << 8) 1100 #define FW_PARAMS_CMD_VFN(x) ((x) << 0) 1101 1102 struct fw_pfvf_cmd { 1103 __be32 op_to_vfn; 1104 __be32 retval_len16; 1105 __be32 niqflint_niq; 1106 __be32 type_to_neq; 1107 __be32 tc_to_nexactf; 1108 __be32 r_caps_to_nethctrl; 1109 __be16 nricq; 1110 __be16 nriqp; 1111 __be32 r4; 1112 }; 1113 1114 #define FW_PFVF_CMD_PFN(x) ((x) << 8) 1115 #define FW_PFVF_CMD_VFN(x) ((x) << 0) 1116 1117 #define FW_PFVF_CMD_NIQFLINT(x) ((x) << 20) 1118 #define FW_PFVF_CMD_NIQFLINT_GET(x) (((x) >> 20) & 0xfff) 1119 1120 #define FW_PFVF_CMD_NIQ(x) ((x) << 0) 1121 #define FW_PFVF_CMD_NIQ_GET(x) (((x) >> 0) & 0xfffff) 1122 1123 #define FW_PFVF_CMD_TYPE (1 << 31) 1124 #define FW_PFVF_CMD_TYPE_GET(x) (((x) >> 31) & 0x1) 1125 1126 #define FW_PFVF_CMD_CMASK(x) ((x) << 24) 1127 #define FW_PFVF_CMD_CMASK_MASK 0xf 1128 #define FW_PFVF_CMD_CMASK_GET(x) (((x) >> 24) & FW_PFVF_CMD_CMASK_MASK) 1129 1130 #define FW_PFVF_CMD_PMASK(x) ((x) << 20) 1131 #define FW_PFVF_CMD_PMASK_MASK 0xf 1132 #define FW_PFVF_CMD_PMASK_GET(x) (((x) >> 20) & FW_PFVF_CMD_PMASK_MASK) 1133 1134 #define FW_PFVF_CMD_NEQ(x) ((x) << 0) 1135 #define FW_PFVF_CMD_NEQ_GET(x) (((x) >> 0) & 0xfffff) 1136 1137 #define FW_PFVF_CMD_TC(x) ((x) << 24) 1138 #define FW_PFVF_CMD_TC_GET(x) (((x) >> 24) & 0xff) 1139 1140 #define FW_PFVF_CMD_NVI(x) ((x) << 16) 1141 #define FW_PFVF_CMD_NVI_GET(x) (((x) >> 16) & 0xff) 1142 1143 #define FW_PFVF_CMD_NEXACTF(x) ((x) << 0) 1144 #define FW_PFVF_CMD_NEXACTF_GET(x) (((x) >> 0) & 0xffff) 1145 1146 #define FW_PFVF_CMD_R_CAPS(x) ((x) << 24) 1147 #define FW_PFVF_CMD_R_CAPS_GET(x) (((x) >> 24) & 0xff) 1148 1149 #define FW_PFVF_CMD_WX_CAPS(x) ((x) << 16) 1150 #define FW_PFVF_CMD_WX_CAPS_GET(x) (((x) >> 16) & 0xff) 1151 1152 #define FW_PFVF_CMD_NETHCTRL(x) ((x) << 0) 1153 #define FW_PFVF_CMD_NETHCTRL_GET(x) (((x) >> 0) & 0xffff) 1154 1155 enum fw_iq_type { 1156 FW_IQ_TYPE_FL_INT_CAP, 1157 FW_IQ_TYPE_NO_FL_INT_CAP 1158 }; 1159 1160 struct fw_iq_cmd { 1161 __be32 op_to_vfn; 1162 __be32 alloc_to_len16; 1163 __be16 physiqid; 1164 __be16 iqid; 1165 __be16 fl0id; 1166 __be16 fl1id; 1167 __be32 type_to_iqandstindex; 1168 __be16 iqdroprss_to_iqesize; 1169 __be16 iqsize; 1170 __be64 iqaddr; 1171 __be32 iqns_to_fl0congen; 1172 __be16 fl0dcaen_to_fl0cidxfthresh; 1173 __be16 fl0size; 1174 __be64 fl0addr; 1175 __be32 fl1cngchmap_to_fl1congen; 1176 __be16 fl1dcaen_to_fl1cidxfthresh; 1177 __be16 fl1size; 1178 __be64 fl1addr; 1179 }; 1180 1181 #define FW_IQ_CMD_PFN(x) ((x) << 8) 1182 #define FW_IQ_CMD_VFN(x) ((x) << 0) 1183 1184 #define FW_IQ_CMD_ALLOC (1U << 31) 1185 #define FW_IQ_CMD_FREE (1U << 30) 1186 #define FW_IQ_CMD_MODIFY (1U << 29) 1187 #define FW_IQ_CMD_IQSTART(x) ((x) << 28) 1188 #define FW_IQ_CMD_IQSTOP(x) ((x) << 27) 1189 1190 #define FW_IQ_CMD_TYPE(x) ((x) << 29) 1191 #define FW_IQ_CMD_IQASYNCH(x) ((x) << 28) 1192 #define FW_IQ_CMD_VIID(x) ((x) << 16) 1193 #define FW_IQ_CMD_IQANDST(x) ((x) << 15) 1194 #define FW_IQ_CMD_IQANUS(x) ((x) << 14) 1195 #define FW_IQ_CMD_IQANUD(x) ((x) << 12) 1196 #define FW_IQ_CMD_IQANDSTINDEX(x) ((x) << 0) 1197 1198 #define FW_IQ_CMD_IQDROPRSS (1U << 15) 1199 #define FW_IQ_CMD_IQGTSMODE (1U << 14) 1200 #define FW_IQ_CMD_IQPCIECH(x) ((x) << 12) 1201 #define FW_IQ_CMD_IQDCAEN(x) ((x) << 11) 1202 #define FW_IQ_CMD_IQDCACPU(x) ((x) << 6) 1203 #define FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << 4) 1204 #define FW_IQ_CMD_IQO (1U << 3) 1205 #define FW_IQ_CMD_IQCPRIO(x) ((x) << 2) 1206 #define FW_IQ_CMD_IQESIZE(x) ((x) << 0) 1207 1208 #define FW_IQ_CMD_IQNS(x) ((x) << 31) 1209 #define FW_IQ_CMD_IQRO(x) ((x) << 30) 1210 #define FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << 28) 1211 #define FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << 27) 1212 #define FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << 26) 1213 #define FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << 20) 1214 #define FW_IQ_CMD_FL0CACHELOCK(x) ((x) << 15) 1215 #define FW_IQ_CMD_FL0DBP(x) ((x) << 14) 1216 #define FW_IQ_CMD_FL0DATANS(x) ((x) << 13) 1217 #define FW_IQ_CMD_FL0DATARO(x) ((x) << 12) 1218 #define FW_IQ_CMD_FL0CONGCIF(x) ((x) << 11) 1219 #define FW_IQ_CMD_FL0ONCHIP(x) ((x) << 10) 1220 #define FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << 9) 1221 #define FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << 8) 1222 #define FW_IQ_CMD_FL0FETCHNS(x) ((x) << 7) 1223 #define FW_IQ_CMD_FL0FETCHRO(x) ((x) << 6) 1224 #define FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << 4) 1225 #define FW_IQ_CMD_FL0CPRIO(x) ((x) << 3) 1226 #define FW_IQ_CMD_FL0PADEN(x) ((x) << 2) 1227 #define FW_IQ_CMD_FL0PACKEN(x) ((x) << 1) 1228 #define FW_IQ_CMD_FL0CONGEN (1U << 0) 1229 1230 #define FW_IQ_CMD_FL0DCAEN(x) ((x) << 15) 1231 #define FW_IQ_CMD_FL0DCACPU(x) ((x) << 10) 1232 #define FW_IQ_CMD_FL0FBMIN(x) ((x) << 7) 1233 #define FW_IQ_CMD_FL0FBMAX(x) ((x) << 4) 1234 #define FW_IQ_CMD_FL0CIDXFTHRESHO (1U << 3) 1235 #define FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << 0) 1236 1237 #define FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << 20) 1238 #define FW_IQ_CMD_FL1CACHELOCK(x) ((x) << 15) 1239 #define FW_IQ_CMD_FL1DBP(x) ((x) << 14) 1240 #define FW_IQ_CMD_FL1DATANS(x) ((x) << 13) 1241 #define FW_IQ_CMD_FL1DATARO(x) ((x) << 12) 1242 #define FW_IQ_CMD_FL1CONGCIF(x) ((x) << 11) 1243 #define FW_IQ_CMD_FL1ONCHIP(x) ((x) << 10) 1244 #define FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << 9) 1245 #define FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << 8) 1246 #define FW_IQ_CMD_FL1FETCHNS(x) ((x) << 7) 1247 #define FW_IQ_CMD_FL1FETCHRO(x) ((x) << 6) 1248 #define FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << 4) 1249 #define FW_IQ_CMD_FL1CPRIO(x) ((x) << 3) 1250 #define FW_IQ_CMD_FL1PADEN (1U << 2) 1251 #define FW_IQ_CMD_FL1PACKEN (1U << 1) 1252 #define FW_IQ_CMD_FL1CONGEN (1U << 0) 1253 1254 #define FW_IQ_CMD_FL1DCAEN(x) ((x) << 15) 1255 #define FW_IQ_CMD_FL1DCACPU(x) ((x) << 10) 1256 #define FW_IQ_CMD_FL1FBMIN(x) ((x) << 7) 1257 #define FW_IQ_CMD_FL1FBMAX(x) ((x) << 4) 1258 #define FW_IQ_CMD_FL1CIDXFTHRESHO (1U << 3) 1259 #define FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << 0) 1260 1261 struct fw_eq_eth_cmd { 1262 __be32 op_to_vfn; 1263 __be32 alloc_to_len16; 1264 __be32 eqid_pkd; 1265 __be32 physeqid_pkd; 1266 __be32 fetchszm_to_iqid; 1267 __be32 dcaen_to_eqsize; 1268 __be64 eqaddr; 1269 __be32 viid_pkd; 1270 __be32 r8_lo; 1271 __be64 r9; 1272 }; 1273 1274 #define FW_EQ_ETH_CMD_PFN(x) ((x) << 8) 1275 #define FW_EQ_ETH_CMD_VFN(x) ((x) << 0) 1276 #define FW_EQ_ETH_CMD_ALLOC (1U << 31) 1277 #define FW_EQ_ETH_CMD_FREE (1U << 30) 1278 #define FW_EQ_ETH_CMD_MODIFY (1U << 29) 1279 #define FW_EQ_ETH_CMD_EQSTART (1U << 28) 1280 #define FW_EQ_ETH_CMD_EQSTOP (1U << 27) 1281 1282 #define FW_EQ_ETH_CMD_EQID(x) ((x) << 0) 1283 #define FW_EQ_ETH_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff) 1284 #define FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << 0) 1285 #define FW_EQ_ETH_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff) 1286 1287 #define FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << 26) 1288 #define FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << 25) 1289 #define FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << 24) 1290 #define FW_EQ_ETH_CMD_FETCHNS(x) ((x) << 23) 1291 #define FW_EQ_ETH_CMD_FETCHRO(x) ((x) << 22) 1292 #define FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << 20) 1293 #define FW_EQ_ETH_CMD_CPRIO(x) ((x) << 19) 1294 #define FW_EQ_ETH_CMD_ONCHIP(x) ((x) << 18) 1295 #define FW_EQ_ETH_CMD_PCIECHN(x) ((x) << 16) 1296 #define FW_EQ_ETH_CMD_IQID(x) ((x) << 0) 1297 1298 #define FW_EQ_ETH_CMD_DCAEN(x) ((x) << 31) 1299 #define FW_EQ_ETH_CMD_DCACPU(x) ((x) << 26) 1300 #define FW_EQ_ETH_CMD_FBMIN(x) ((x) << 23) 1301 #define FW_EQ_ETH_CMD_FBMAX(x) ((x) << 20) 1302 #define FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << 19) 1303 #define FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << 16) 1304 #define FW_EQ_ETH_CMD_EQSIZE(x) ((x) << 0) 1305 1306 #define FW_EQ_ETH_CMD_AUTOEQUEQE (1U << 30) 1307 #define FW_EQ_ETH_CMD_VIID(x) ((x) << 16) 1308 1309 struct fw_eq_ctrl_cmd { 1310 __be32 op_to_vfn; 1311 __be32 alloc_to_len16; 1312 __be32 cmpliqid_eqid; 1313 __be32 physeqid_pkd; 1314 __be32 fetchszm_to_iqid; 1315 __be32 dcaen_to_eqsize; 1316 __be64 eqaddr; 1317 }; 1318 1319 #define FW_EQ_CTRL_CMD_PFN(x) ((x) << 8) 1320 #define FW_EQ_CTRL_CMD_VFN(x) ((x) << 0) 1321 1322 #define FW_EQ_CTRL_CMD_ALLOC (1U << 31) 1323 #define FW_EQ_CTRL_CMD_FREE (1U << 30) 1324 #define FW_EQ_CTRL_CMD_MODIFY (1U << 29) 1325 #define FW_EQ_CTRL_CMD_EQSTART (1U << 28) 1326 #define FW_EQ_CTRL_CMD_EQSTOP (1U << 27) 1327 1328 #define FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << 20) 1329 #define FW_EQ_CTRL_CMD_EQID(x) ((x) << 0) 1330 #define FW_EQ_CTRL_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff) 1331 #define FW_EQ_CTRL_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff) 1332 1333 #define FW_EQ_CTRL_CMD_FETCHSZM (1U << 26) 1334 #define FW_EQ_CTRL_CMD_STATUSPGNS (1U << 25) 1335 #define FW_EQ_CTRL_CMD_STATUSPGRO (1U << 24) 1336 #define FW_EQ_CTRL_CMD_FETCHNS (1U << 23) 1337 #define FW_EQ_CTRL_CMD_FETCHRO (1U << 22) 1338 #define FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << 20) 1339 #define FW_EQ_CTRL_CMD_CPRIO(x) ((x) << 19) 1340 #define FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << 18) 1341 #define FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << 16) 1342 #define FW_EQ_CTRL_CMD_IQID(x) ((x) << 0) 1343 1344 #define FW_EQ_CTRL_CMD_DCAEN(x) ((x) << 31) 1345 #define FW_EQ_CTRL_CMD_DCACPU(x) ((x) << 26) 1346 #define FW_EQ_CTRL_CMD_FBMIN(x) ((x) << 23) 1347 #define FW_EQ_CTRL_CMD_FBMAX(x) ((x) << 20) 1348 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) ((x) << 19) 1349 #define FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << 16) 1350 #define FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << 0) 1351 1352 struct fw_eq_ofld_cmd { 1353 __be32 op_to_vfn; 1354 __be32 alloc_to_len16; 1355 __be32 eqid_pkd; 1356 __be32 physeqid_pkd; 1357 __be32 fetchszm_to_iqid; 1358 __be32 dcaen_to_eqsize; 1359 __be64 eqaddr; 1360 }; 1361 1362 #define FW_EQ_OFLD_CMD_PFN(x) ((x) << 8) 1363 #define FW_EQ_OFLD_CMD_VFN(x) ((x) << 0) 1364 1365 #define FW_EQ_OFLD_CMD_ALLOC (1U << 31) 1366 #define FW_EQ_OFLD_CMD_FREE (1U << 30) 1367 #define FW_EQ_OFLD_CMD_MODIFY (1U << 29) 1368 #define FW_EQ_OFLD_CMD_EQSTART (1U << 28) 1369 #define FW_EQ_OFLD_CMD_EQSTOP (1U << 27) 1370 1371 #define FW_EQ_OFLD_CMD_EQID(x) ((x) << 0) 1372 #define FW_EQ_OFLD_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff) 1373 #define FW_EQ_OFLD_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff) 1374 1375 #define FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << 26) 1376 #define FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << 25) 1377 #define FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << 24) 1378 #define FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << 23) 1379 #define FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << 22) 1380 #define FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << 20) 1381 #define FW_EQ_OFLD_CMD_CPRIO(x) ((x) << 19) 1382 #define FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << 18) 1383 #define FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << 16) 1384 #define FW_EQ_OFLD_CMD_IQID(x) ((x) << 0) 1385 1386 #define FW_EQ_OFLD_CMD_DCAEN(x) ((x) << 31) 1387 #define FW_EQ_OFLD_CMD_DCACPU(x) ((x) << 26) 1388 #define FW_EQ_OFLD_CMD_FBMIN(x) ((x) << 23) 1389 #define FW_EQ_OFLD_CMD_FBMAX(x) ((x) << 20) 1390 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) ((x) << 19) 1391 #define FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << 16) 1392 #define FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << 0) 1393 1394 /* 1395 * Macros for VIID parsing: 1396 * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number 1397 */ 1398 #define FW_VIID_PFN_GET(x) (((x) >> 8) & 0x7) 1399 #define FW_VIID_VIVLD_GET(x) (((x) >> 7) & 0x1) 1400 #define FW_VIID_VIN_GET(x) (((x) >> 0) & 0x7F) 1401 1402 struct fw_vi_cmd { 1403 __be32 op_to_vfn; 1404 __be32 alloc_to_len16; 1405 __be16 type_viid; 1406 u8 mac[6]; 1407 u8 portid_pkd; 1408 u8 nmac; 1409 u8 nmac0[6]; 1410 __be16 rsssize_pkd; 1411 u8 nmac1[6]; 1412 __be16 idsiiq_pkd; 1413 u8 nmac2[6]; 1414 __be16 idseiq_pkd; 1415 u8 nmac3[6]; 1416 __be64 r9; 1417 __be64 r10; 1418 }; 1419 1420 #define FW_VI_CMD_PFN(x) ((x) << 8) 1421 #define FW_VI_CMD_VFN(x) ((x) << 0) 1422 #define FW_VI_CMD_ALLOC (1U << 31) 1423 #define FW_VI_CMD_FREE (1U << 30) 1424 #define FW_VI_CMD_VIID(x) ((x) << 0) 1425 #define FW_VI_CMD_VIID_GET(x) ((x) & 0xfff) 1426 #define FW_VI_CMD_PORTID(x) ((x) << 4) 1427 #define FW_VI_CMD_PORTID_GET(x) (((x) >> 4) & 0xf) 1428 #define FW_VI_CMD_RSSSIZE_GET(x) (((x) >> 0) & 0x7ff) 1429 1430 /* Special VI_MAC command index ids */ 1431 #define FW_VI_MAC_ADD_MAC 0x3FF 1432 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 1433 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD 1434 #define FW_CLS_TCAM_NUM_ENTRIES 336 1435 1436 enum fw_vi_mac_smac { 1437 FW_VI_MAC_MPS_TCAM_ENTRY, 1438 FW_VI_MAC_MPS_TCAM_ONLY, 1439 FW_VI_MAC_SMT_ONLY, 1440 FW_VI_MAC_SMT_AND_MPSTCAM 1441 }; 1442 1443 enum fw_vi_mac_result { 1444 FW_VI_MAC_R_SUCCESS, 1445 FW_VI_MAC_R_F_NONEXISTENT_NOMEM, 1446 FW_VI_MAC_R_SMAC_FAIL, 1447 FW_VI_MAC_R_F_ACL_CHECK 1448 }; 1449 1450 struct fw_vi_mac_cmd { 1451 __be32 op_to_viid; 1452 __be32 freemacs_to_len16; 1453 union fw_vi_mac { 1454 struct fw_vi_mac_exact { 1455 __be16 valid_to_idx; 1456 u8 macaddr[6]; 1457 } exact[7]; 1458 struct fw_vi_mac_hash { 1459 __be64 hashvec; 1460 } hash; 1461 } u; 1462 }; 1463 1464 #define FW_VI_MAC_CMD_VIID(x) ((x) << 0) 1465 #define FW_VI_MAC_CMD_FREEMACS(x) ((x) << 31) 1466 #define FW_VI_MAC_CMD_HASHVECEN (1U << 23) 1467 #define FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << 22) 1468 #define FW_VI_MAC_CMD_VALID (1U << 15) 1469 #define FW_VI_MAC_CMD_PRIO(x) ((x) << 12) 1470 #define FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << 10) 1471 #define FW_VI_MAC_CMD_SMAC_RESULT_GET(x) (((x) >> 10) & 0x3) 1472 #define FW_VI_MAC_CMD_IDX(x) ((x) << 0) 1473 #define FW_VI_MAC_CMD_IDX_GET(x) (((x) >> 0) & 0x3ff) 1474 1475 #define FW_RXMODE_MTU_NO_CHG 65535 1476 1477 struct fw_vi_rxmode_cmd { 1478 __be32 op_to_viid; 1479 __be32 retval_len16; 1480 __be32 mtu_to_vlanexen; 1481 __be32 r4_lo; 1482 }; 1483 1484 #define FW_VI_RXMODE_CMD_VIID(x) ((x) << 0) 1485 #define FW_VI_RXMODE_CMD_MTU_MASK 0xffff 1486 #define FW_VI_RXMODE_CMD_MTU(x) ((x) << 16) 1487 #define FW_VI_RXMODE_CMD_PROMISCEN_MASK 0x3 1488 #define FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << 14) 1489 #define FW_VI_RXMODE_CMD_ALLMULTIEN_MASK 0x3 1490 #define FW_VI_RXMODE_CMD_ALLMULTIEN(x) ((x) << 12) 1491 #define FW_VI_RXMODE_CMD_BROADCASTEN_MASK 0x3 1492 #define FW_VI_RXMODE_CMD_BROADCASTEN(x) ((x) << 10) 1493 #define FW_VI_RXMODE_CMD_VLANEXEN_MASK 0x3 1494 #define FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << 8) 1495 1496 struct fw_vi_enable_cmd { 1497 __be32 op_to_viid; 1498 __be32 ien_to_len16; 1499 __be16 blinkdur; 1500 __be16 r3; 1501 __be32 r4; 1502 }; 1503 1504 #define FW_VI_ENABLE_CMD_VIID(x) ((x) << 0) 1505 #define FW_VI_ENABLE_CMD_IEN(x) ((x) << 31) 1506 #define FW_VI_ENABLE_CMD_EEN(x) ((x) << 30) 1507 #define FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << 28) 1508 #define FW_VI_ENABLE_CMD_LED (1U << 29) 1509 1510 /* VI VF stats offset definitions */ 1511 #define VI_VF_NUM_STATS 16 1512 enum fw_vi_stats_vf_index { 1513 FW_VI_VF_STAT_TX_BCAST_BYTES_IX, 1514 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, 1515 FW_VI_VF_STAT_TX_MCAST_BYTES_IX, 1516 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, 1517 FW_VI_VF_STAT_TX_UCAST_BYTES_IX, 1518 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, 1519 FW_VI_VF_STAT_TX_DROP_FRAMES_IX, 1520 FW_VI_VF_STAT_TX_OFLD_BYTES_IX, 1521 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, 1522 FW_VI_VF_STAT_RX_BCAST_BYTES_IX, 1523 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, 1524 FW_VI_VF_STAT_RX_MCAST_BYTES_IX, 1525 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, 1526 FW_VI_VF_STAT_RX_UCAST_BYTES_IX, 1527 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, 1528 FW_VI_VF_STAT_RX_ERR_FRAMES_IX 1529 }; 1530 1531 /* VI PF stats offset definitions */ 1532 #define VI_PF_NUM_STATS 17 1533 enum fw_vi_stats_pf_index { 1534 FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 1535 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 1536 FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 1537 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 1538 FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 1539 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 1540 FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 1541 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 1542 FW_VI_PF_STAT_RX_BYTES_IX, 1543 FW_VI_PF_STAT_RX_FRAMES_IX, 1544 FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 1545 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 1546 FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 1547 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 1548 FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 1549 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 1550 FW_VI_PF_STAT_RX_ERR_FRAMES_IX 1551 }; 1552 1553 struct fw_vi_stats_cmd { 1554 __be32 op_to_viid; 1555 __be32 retval_len16; 1556 union fw_vi_stats { 1557 struct fw_vi_stats_ctl { 1558 __be16 nstats_ix; 1559 __be16 r6; 1560 __be32 r7; 1561 __be64 stat0; 1562 __be64 stat1; 1563 __be64 stat2; 1564 __be64 stat3; 1565 __be64 stat4; 1566 __be64 stat5; 1567 } ctl; 1568 struct fw_vi_stats_pf { 1569 __be64 tx_bcast_bytes; 1570 __be64 tx_bcast_frames; 1571 __be64 tx_mcast_bytes; 1572 __be64 tx_mcast_frames; 1573 __be64 tx_ucast_bytes; 1574 __be64 tx_ucast_frames; 1575 __be64 tx_offload_bytes; 1576 __be64 tx_offload_frames; 1577 __be64 rx_pf_bytes; 1578 __be64 rx_pf_frames; 1579 __be64 rx_bcast_bytes; 1580 __be64 rx_bcast_frames; 1581 __be64 rx_mcast_bytes; 1582 __be64 rx_mcast_frames; 1583 __be64 rx_ucast_bytes; 1584 __be64 rx_ucast_frames; 1585 __be64 rx_err_frames; 1586 } pf; 1587 struct fw_vi_stats_vf { 1588 __be64 tx_bcast_bytes; 1589 __be64 tx_bcast_frames; 1590 __be64 tx_mcast_bytes; 1591 __be64 tx_mcast_frames; 1592 __be64 tx_ucast_bytes; 1593 __be64 tx_ucast_frames; 1594 __be64 tx_drop_frames; 1595 __be64 tx_offload_bytes; 1596 __be64 tx_offload_frames; 1597 __be64 rx_bcast_bytes; 1598 __be64 rx_bcast_frames; 1599 __be64 rx_mcast_bytes; 1600 __be64 rx_mcast_frames; 1601 __be64 rx_ucast_bytes; 1602 __be64 rx_ucast_frames; 1603 __be64 rx_err_frames; 1604 } vf; 1605 } u; 1606 }; 1607 1608 #define FW_VI_STATS_CMD_VIID(x) ((x) << 0) 1609 #define FW_VI_STATS_CMD_NSTATS(x) ((x) << 12) 1610 #define FW_VI_STATS_CMD_IX(x) ((x) << 0) 1611 1612 struct fw_acl_mac_cmd { 1613 __be32 op_to_vfn; 1614 __be32 en_to_len16; 1615 u8 nmac; 1616 u8 r3[7]; 1617 __be16 r4; 1618 u8 macaddr0[6]; 1619 __be16 r5; 1620 u8 macaddr1[6]; 1621 __be16 r6; 1622 u8 macaddr2[6]; 1623 __be16 r7; 1624 u8 macaddr3[6]; 1625 }; 1626 1627 #define FW_ACL_MAC_CMD_PFN(x) ((x) << 8) 1628 #define FW_ACL_MAC_CMD_VFN(x) ((x) << 0) 1629 #define FW_ACL_MAC_CMD_EN(x) ((x) << 31) 1630 1631 struct fw_acl_vlan_cmd { 1632 __be32 op_to_vfn; 1633 __be32 en_to_len16; 1634 u8 nvlan; 1635 u8 dropnovlan_fm; 1636 u8 r3_lo[6]; 1637 __be16 vlanid[16]; 1638 }; 1639 1640 #define FW_ACL_VLAN_CMD_PFN(x) ((x) << 8) 1641 #define FW_ACL_VLAN_CMD_VFN(x) ((x) << 0) 1642 #define FW_ACL_VLAN_CMD_EN(x) ((x) << 31) 1643 #define FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << 7) 1644 #define FW_ACL_VLAN_CMD_FM(x) ((x) << 6) 1645 1646 enum fw_port_cap { 1647 FW_PORT_CAP_SPEED_100M = 0x0001, 1648 FW_PORT_CAP_SPEED_1G = 0x0002, 1649 FW_PORT_CAP_SPEED_2_5G = 0x0004, 1650 FW_PORT_CAP_SPEED_10G = 0x0008, 1651 FW_PORT_CAP_SPEED_40G = 0x0010, 1652 FW_PORT_CAP_SPEED_100G = 0x0020, 1653 FW_PORT_CAP_FC_RX = 0x0040, 1654 FW_PORT_CAP_FC_TX = 0x0080, 1655 FW_PORT_CAP_ANEG = 0x0100, 1656 FW_PORT_CAP_MDI_0 = 0x0200, 1657 FW_PORT_CAP_MDI_1 = 0x0400, 1658 FW_PORT_CAP_BEAN = 0x0800, 1659 FW_PORT_CAP_PMA_LPBK = 0x1000, 1660 FW_PORT_CAP_PCS_LPBK = 0x2000, 1661 FW_PORT_CAP_PHYXS_LPBK = 0x4000, 1662 FW_PORT_CAP_FAR_END_LPBK = 0x8000, 1663 }; 1664 1665 enum fw_port_mdi { 1666 FW_PORT_MDI_UNCHANGED, 1667 FW_PORT_MDI_AUTO, 1668 FW_PORT_MDI_F_STRAIGHT, 1669 FW_PORT_MDI_F_CROSSOVER 1670 }; 1671 1672 #define FW_PORT_MDI(x) ((x) << 9) 1673 1674 enum fw_port_action { 1675 FW_PORT_ACTION_L1_CFG = 0x0001, 1676 FW_PORT_ACTION_L2_CFG = 0x0002, 1677 FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 1678 FW_PORT_ACTION_L2_PPP_CFG = 0x0004, 1679 FW_PORT_ACTION_L2_DCB_CFG = 0x0005, 1680 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006, 1681 FW_PORT_ACTION_DCB_READ_RECV = 0x0007, 1682 FW_PORT_ACTION_DCB_READ_DET = 0x0008, 1683 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, 1684 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, 1685 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, 1686 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, 1687 FW_PORT_ACTION_L1_LPBK = 0x0021, 1688 FW_PORT_ACTION_L1_PMA_LPBK = 0x0022, 1689 FW_PORT_ACTION_L1_PCS_LPBK = 0x0023, 1690 FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024, 1691 FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025, 1692 FW_PORT_ACTION_PHY_RESET = 0x0040, 1693 FW_PORT_ACTION_PMA_RESET = 0x0041, 1694 FW_PORT_ACTION_PCS_RESET = 0x0042, 1695 FW_PORT_ACTION_PHYXS_RESET = 0x0043, 1696 FW_PORT_ACTION_DTEXS_REEST = 0x0044, 1697 FW_PORT_ACTION_AN_RESET = 0x0045 1698 }; 1699 1700 enum fw_port_l2cfg_ctlbf { 1701 FW_PORT_L2_CTLBF_OVLAN0 = 0x01, 1702 FW_PORT_L2_CTLBF_OVLAN1 = 0x02, 1703 FW_PORT_L2_CTLBF_OVLAN2 = 0x04, 1704 FW_PORT_L2_CTLBF_OVLAN3 = 0x08, 1705 FW_PORT_L2_CTLBF_IVLAN = 0x10, 1706 FW_PORT_L2_CTLBF_TXIPG = 0x20 1707 }; 1708 1709 enum fw_port_dcb_versions { 1710 FW_PORT_DCB_VER_UNKNOWN, 1711 FW_PORT_DCB_VER_CEE1D0, 1712 FW_PORT_DCB_VER_CEE1D01, 1713 FW_PORT_DCB_VER_IEEE, 1714 FW_PORT_DCB_VER_AUTO = 7 1715 }; 1716 1717 enum fw_port_dcb_cfg { 1718 FW_PORT_DCB_CFG_PG = 0x01, 1719 FW_PORT_DCB_CFG_PFC = 0x02, 1720 FW_PORT_DCB_CFG_APPL = 0x04 1721 }; 1722 1723 enum fw_port_dcb_cfg_rc { 1724 FW_PORT_DCB_CFG_SUCCESS = 0x0, 1725 FW_PORT_DCB_CFG_ERROR = 0x1 1726 }; 1727 1728 enum fw_port_dcb_type { 1729 FW_PORT_DCB_TYPE_PGID = 0x00, 1730 FW_PORT_DCB_TYPE_PGRATE = 0x01, 1731 FW_PORT_DCB_TYPE_PRIORATE = 0x02, 1732 FW_PORT_DCB_TYPE_PFC = 0x03, 1733 FW_PORT_DCB_TYPE_APP_ID = 0x04, 1734 FW_PORT_DCB_TYPE_CONTROL = 0x05, 1735 }; 1736 1737 enum fw_port_dcb_feature_state { 1738 FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0, 1739 FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1, 1740 FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2, 1741 FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3, 1742 }; 1743 1744 struct fw_port_cmd { 1745 __be32 op_to_portid; 1746 __be32 action_to_len16; 1747 union fw_port { 1748 struct fw_port_l1cfg { 1749 __be32 rcap; 1750 __be32 r; 1751 } l1cfg; 1752 struct fw_port_l2cfg { 1753 __u8 ctlbf; 1754 __u8 ovlan3_to_ivlan0; 1755 __be16 ivlantype; 1756 __be16 txipg_force_pinfo; 1757 __be16 mtu; 1758 __be16 ovlan0mask; 1759 __be16 ovlan0type; 1760 __be16 ovlan1mask; 1761 __be16 ovlan1type; 1762 __be16 ovlan2mask; 1763 __be16 ovlan2type; 1764 __be16 ovlan3mask; 1765 __be16 ovlan3type; 1766 } l2cfg; 1767 struct fw_port_info { 1768 __be32 lstatus_to_modtype; 1769 __be16 pcap; 1770 __be16 acap; 1771 __be16 mtu; 1772 __u8 cbllen; 1773 __u8 auxlinfo; 1774 __u8 dcbxdis_pkd; 1775 __u8 r8_lo[3]; 1776 __be64 r9; 1777 } info; 1778 struct fw_port_diags { 1779 __u8 diagop; 1780 __u8 r[3]; 1781 __be32 diagval; 1782 } diags; 1783 union fw_port_dcb { 1784 struct fw_port_dcb_pgid { 1785 __u8 type; 1786 __u8 apply_pkd; 1787 __u8 r10_lo[2]; 1788 __be32 pgid; 1789 __be64 r11; 1790 } pgid; 1791 struct fw_port_dcb_pgrate { 1792 __u8 type; 1793 __u8 apply_pkd; 1794 __u8 r10_lo[5]; 1795 __u8 num_tcs_supported; 1796 __u8 pgrate[8]; 1797 __u8 tsa[8]; 1798 } pgrate; 1799 struct fw_port_dcb_priorate { 1800 __u8 type; 1801 __u8 apply_pkd; 1802 __u8 r10_lo[6]; 1803 __u8 strict_priorate[8]; 1804 } priorate; 1805 struct fw_port_dcb_pfc { 1806 __u8 type; 1807 __u8 pfcen; 1808 __u8 r10[5]; 1809 __u8 max_pfc_tcs; 1810 __be64 r11; 1811 } pfc; 1812 struct fw_port_app_priority { 1813 __u8 type; 1814 __u8 r10[2]; 1815 __u8 idx; 1816 __u8 user_prio_map; 1817 __u8 sel_field; 1818 __be16 protocolid; 1819 __be64 r12; 1820 } app_priority; 1821 struct fw_port_dcb_control { 1822 __u8 type; 1823 __u8 all_syncd_pkd; 1824 __be16 dcb_version_to_app_state; 1825 __be32 r11; 1826 __be64 r12; 1827 } control; 1828 } dcb; 1829 } u; 1830 }; 1831 1832 #define FW_PORT_CMD_READ (1U << 22) 1833 1834 #define FW_PORT_CMD_PORTID(x) ((x) << 0) 1835 #define FW_PORT_CMD_PORTID_GET(x) (((x) >> 0) & 0xf) 1836 1837 #define FW_PORT_CMD_ACTION(x) ((x) << 16) 1838 #define FW_PORT_CMD_ACTION_GET(x) (((x) >> 16) & 0xffff) 1839 1840 #define FW_PORT_CMD_CTLBF(x) ((x) << 10) 1841 #define FW_PORT_CMD_OVLAN3(x) ((x) << 7) 1842 #define FW_PORT_CMD_OVLAN2(x) ((x) << 6) 1843 #define FW_PORT_CMD_OVLAN1(x) ((x) << 5) 1844 #define FW_PORT_CMD_OVLAN0(x) ((x) << 4) 1845 #define FW_PORT_CMD_IVLAN0(x) ((x) << 3) 1846 1847 #define FW_PORT_CMD_TXIPG(x) ((x) << 19) 1848 1849 #define FW_PORT_CMD_LSTATUS (1U << 31) 1850 #define FW_PORT_CMD_LSTATUS_GET(x) (((x) >> 31) & 0x1) 1851 #define FW_PORT_CMD_LSPEED(x) ((x) << 24) 1852 #define FW_PORT_CMD_LSPEED_GET(x) (((x) >> 24) & 0x3f) 1853 #define FW_PORT_CMD_TXPAUSE (1U << 23) 1854 #define FW_PORT_CMD_RXPAUSE (1U << 22) 1855 #define FW_PORT_CMD_MDIOCAP (1U << 21) 1856 #define FW_PORT_CMD_MDIOADDR_GET(x) (((x) >> 16) & 0x1f) 1857 #define FW_PORT_CMD_LPTXPAUSE (1U << 15) 1858 #define FW_PORT_CMD_LPRXPAUSE (1U << 14) 1859 #define FW_PORT_CMD_PTYPE_MASK 0x1f 1860 #define FW_PORT_CMD_PTYPE_GET(x) (((x) >> 8) & FW_PORT_CMD_PTYPE_MASK) 1861 #define FW_PORT_CMD_MODTYPE_MASK 0x1f 1862 #define FW_PORT_CMD_MODTYPE_GET(x) (((x) >> 0) & FW_PORT_CMD_MODTYPE_MASK) 1863 1864 #define FW_PORT_CMD_DCBXDIS (1U << 7) 1865 #define FW_PORT_CMD_APPLY (1U << 7) 1866 #define FW_PORT_CMD_ALL_SYNCD (1U << 7) 1867 #define FW_PORT_CMD_DCB_VERSION_GET(x) (((x) >> 8) & 0xf) 1868 1869 #define FW_PORT_CMD_PPPEN(x) ((x) << 31) 1870 #define FW_PORT_CMD_TPSRC(x) ((x) << 28) 1871 #define FW_PORT_CMD_NCSISRC(x) ((x) << 24) 1872 1873 #define FW_PORT_CMD_CH0(x) ((x) << 20) 1874 #define FW_PORT_CMD_CH1(x) ((x) << 16) 1875 #define FW_PORT_CMD_CH2(x) ((x) << 12) 1876 #define FW_PORT_CMD_CH3(x) ((x) << 8) 1877 #define FW_PORT_CMD_NCSICH(x) ((x) << 4) 1878 1879 enum fw_port_type { 1880 FW_PORT_TYPE_FIBER_XFI, 1881 FW_PORT_TYPE_FIBER_XAUI, 1882 FW_PORT_TYPE_BT_SGMII, 1883 FW_PORT_TYPE_BT_XFI, 1884 FW_PORT_TYPE_BT_XAUI, 1885 FW_PORT_TYPE_KX4, 1886 FW_PORT_TYPE_CX4, 1887 FW_PORT_TYPE_KX, 1888 FW_PORT_TYPE_KR, 1889 FW_PORT_TYPE_SFP, 1890 FW_PORT_TYPE_BP_AP, 1891 FW_PORT_TYPE_BP4_AP, 1892 FW_PORT_TYPE_QSFP_10G, 1893 FW_PORT_TYPE_QSFP, 1894 FW_PORT_TYPE_BP40_BA, 1895 1896 FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_MASK 1897 }; 1898 1899 enum fw_port_module_type { 1900 FW_PORT_MOD_TYPE_NA, 1901 FW_PORT_MOD_TYPE_LR, 1902 FW_PORT_MOD_TYPE_SR, 1903 FW_PORT_MOD_TYPE_ER, 1904 FW_PORT_MOD_TYPE_TWINAX_PASSIVE, 1905 FW_PORT_MOD_TYPE_TWINAX_ACTIVE, 1906 FW_PORT_MOD_TYPE_LRM, 1907 FW_PORT_MOD_TYPE_ERROR = FW_PORT_CMD_MODTYPE_MASK - 3, 1908 FW_PORT_MOD_TYPE_UNKNOWN = FW_PORT_CMD_MODTYPE_MASK - 2, 1909 FW_PORT_MOD_TYPE_NOTSUPPORTED = FW_PORT_CMD_MODTYPE_MASK - 1, 1910 1911 FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_MASK 1912 }; 1913 1914 enum fw_port_mod_sub_type { 1915 FW_PORT_MOD_SUB_TYPE_NA, 1916 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1, 1917 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2, 1918 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3, 1919 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4, 1920 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5, 1921 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8, 1922 1923 /* The following will never been in the VPD. They are TWINAX cable 1924 * lengths decoded from SFP+ module i2c PROMs. These should 1925 * almost certainly go somewhere else ... 1926 */ 1927 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9, 1928 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA, 1929 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB, 1930 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC, 1931 }; 1932 1933 /* port stats */ 1934 #define FW_NUM_PORT_STATS 50 1935 #define FW_NUM_PORT_TX_STATS 23 1936 #define FW_NUM_PORT_RX_STATS 27 1937 1938 enum fw_port_stats_tx_index { 1939 FW_STAT_TX_PORT_BYTES_IX, 1940 FW_STAT_TX_PORT_FRAMES_IX, 1941 FW_STAT_TX_PORT_BCAST_IX, 1942 FW_STAT_TX_PORT_MCAST_IX, 1943 FW_STAT_TX_PORT_UCAST_IX, 1944 FW_STAT_TX_PORT_ERROR_IX, 1945 FW_STAT_TX_PORT_64B_IX, 1946 FW_STAT_TX_PORT_65B_127B_IX, 1947 FW_STAT_TX_PORT_128B_255B_IX, 1948 FW_STAT_TX_PORT_256B_511B_IX, 1949 FW_STAT_TX_PORT_512B_1023B_IX, 1950 FW_STAT_TX_PORT_1024B_1518B_IX, 1951 FW_STAT_TX_PORT_1519B_MAX_IX, 1952 FW_STAT_TX_PORT_DROP_IX, 1953 FW_STAT_TX_PORT_PAUSE_IX, 1954 FW_STAT_TX_PORT_PPP0_IX, 1955 FW_STAT_TX_PORT_PPP1_IX, 1956 FW_STAT_TX_PORT_PPP2_IX, 1957 FW_STAT_TX_PORT_PPP3_IX, 1958 FW_STAT_TX_PORT_PPP4_IX, 1959 FW_STAT_TX_PORT_PPP5_IX, 1960 FW_STAT_TX_PORT_PPP6_IX, 1961 FW_STAT_TX_PORT_PPP7_IX 1962 }; 1963 1964 enum fw_port_stat_rx_index { 1965 FW_STAT_RX_PORT_BYTES_IX, 1966 FW_STAT_RX_PORT_FRAMES_IX, 1967 FW_STAT_RX_PORT_BCAST_IX, 1968 FW_STAT_RX_PORT_MCAST_IX, 1969 FW_STAT_RX_PORT_UCAST_IX, 1970 FW_STAT_RX_PORT_MTU_ERROR_IX, 1971 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 1972 FW_STAT_RX_PORT_CRC_ERROR_IX, 1973 FW_STAT_RX_PORT_LEN_ERROR_IX, 1974 FW_STAT_RX_PORT_SYM_ERROR_IX, 1975 FW_STAT_RX_PORT_64B_IX, 1976 FW_STAT_RX_PORT_65B_127B_IX, 1977 FW_STAT_RX_PORT_128B_255B_IX, 1978 FW_STAT_RX_PORT_256B_511B_IX, 1979 FW_STAT_RX_PORT_512B_1023B_IX, 1980 FW_STAT_RX_PORT_1024B_1518B_IX, 1981 FW_STAT_RX_PORT_1519B_MAX_IX, 1982 FW_STAT_RX_PORT_PAUSE_IX, 1983 FW_STAT_RX_PORT_PPP0_IX, 1984 FW_STAT_RX_PORT_PPP1_IX, 1985 FW_STAT_RX_PORT_PPP2_IX, 1986 FW_STAT_RX_PORT_PPP3_IX, 1987 FW_STAT_RX_PORT_PPP4_IX, 1988 FW_STAT_RX_PORT_PPP5_IX, 1989 FW_STAT_RX_PORT_PPP6_IX, 1990 FW_STAT_RX_PORT_PPP7_IX, 1991 FW_STAT_RX_PORT_LESS_64B_IX 1992 }; 1993 1994 struct fw_port_stats_cmd { 1995 __be32 op_to_portid; 1996 __be32 retval_len16; 1997 union fw_port_stats { 1998 struct fw_port_stats_ctl { 1999 u8 nstats_bg_bm; 2000 u8 tx_ix; 2001 __be16 r6; 2002 __be32 r7; 2003 __be64 stat0; 2004 __be64 stat1; 2005 __be64 stat2; 2006 __be64 stat3; 2007 __be64 stat4; 2008 __be64 stat5; 2009 } ctl; 2010 struct fw_port_stats_all { 2011 __be64 tx_bytes; 2012 __be64 tx_frames; 2013 __be64 tx_bcast; 2014 __be64 tx_mcast; 2015 __be64 tx_ucast; 2016 __be64 tx_error; 2017 __be64 tx_64b; 2018 __be64 tx_65b_127b; 2019 __be64 tx_128b_255b; 2020 __be64 tx_256b_511b; 2021 __be64 tx_512b_1023b; 2022 __be64 tx_1024b_1518b; 2023 __be64 tx_1519b_max; 2024 __be64 tx_drop; 2025 __be64 tx_pause; 2026 __be64 tx_ppp0; 2027 __be64 tx_ppp1; 2028 __be64 tx_ppp2; 2029 __be64 tx_ppp3; 2030 __be64 tx_ppp4; 2031 __be64 tx_ppp5; 2032 __be64 tx_ppp6; 2033 __be64 tx_ppp7; 2034 __be64 rx_bytes; 2035 __be64 rx_frames; 2036 __be64 rx_bcast; 2037 __be64 rx_mcast; 2038 __be64 rx_ucast; 2039 __be64 rx_mtu_error; 2040 __be64 rx_mtu_crc_error; 2041 __be64 rx_crc_error; 2042 __be64 rx_len_error; 2043 __be64 rx_sym_error; 2044 __be64 rx_64b; 2045 __be64 rx_65b_127b; 2046 __be64 rx_128b_255b; 2047 __be64 rx_256b_511b; 2048 __be64 rx_512b_1023b; 2049 __be64 rx_1024b_1518b; 2050 __be64 rx_1519b_max; 2051 __be64 rx_pause; 2052 __be64 rx_ppp0; 2053 __be64 rx_ppp1; 2054 __be64 rx_ppp2; 2055 __be64 rx_ppp3; 2056 __be64 rx_ppp4; 2057 __be64 rx_ppp5; 2058 __be64 rx_ppp6; 2059 __be64 rx_ppp7; 2060 __be64 rx_less_64b; 2061 __be64 rx_bg_drop; 2062 __be64 rx_bg_trunc; 2063 } all; 2064 } u; 2065 }; 2066 2067 #define FW_PORT_STATS_CMD_NSTATS(x) ((x) << 4) 2068 #define FW_PORT_STATS_CMD_BG_BM(x) ((x) << 0) 2069 #define FW_PORT_STATS_CMD_TX(x) ((x) << 7) 2070 #define FW_PORT_STATS_CMD_IX(x) ((x) << 0) 2071 2072 /* port loopback stats */ 2073 #define FW_NUM_LB_STATS 16 2074 enum fw_port_lb_stats_index { 2075 FW_STAT_LB_PORT_BYTES_IX, 2076 FW_STAT_LB_PORT_FRAMES_IX, 2077 FW_STAT_LB_PORT_BCAST_IX, 2078 FW_STAT_LB_PORT_MCAST_IX, 2079 FW_STAT_LB_PORT_UCAST_IX, 2080 FW_STAT_LB_PORT_ERROR_IX, 2081 FW_STAT_LB_PORT_64B_IX, 2082 FW_STAT_LB_PORT_65B_127B_IX, 2083 FW_STAT_LB_PORT_128B_255B_IX, 2084 FW_STAT_LB_PORT_256B_511B_IX, 2085 FW_STAT_LB_PORT_512B_1023B_IX, 2086 FW_STAT_LB_PORT_1024B_1518B_IX, 2087 FW_STAT_LB_PORT_1519B_MAX_IX, 2088 FW_STAT_LB_PORT_DROP_FRAMES_IX 2089 }; 2090 2091 struct fw_port_lb_stats_cmd { 2092 __be32 op_to_lbport; 2093 __be32 retval_len16; 2094 union fw_port_lb_stats { 2095 struct fw_port_lb_stats_ctl { 2096 u8 nstats_bg_bm; 2097 u8 ix_pkd; 2098 __be16 r6; 2099 __be32 r7; 2100 __be64 stat0; 2101 __be64 stat1; 2102 __be64 stat2; 2103 __be64 stat3; 2104 __be64 stat4; 2105 __be64 stat5; 2106 } ctl; 2107 struct fw_port_lb_stats_all { 2108 __be64 tx_bytes; 2109 __be64 tx_frames; 2110 __be64 tx_bcast; 2111 __be64 tx_mcast; 2112 __be64 tx_ucast; 2113 __be64 tx_error; 2114 __be64 tx_64b; 2115 __be64 tx_65b_127b; 2116 __be64 tx_128b_255b; 2117 __be64 tx_256b_511b; 2118 __be64 tx_512b_1023b; 2119 __be64 tx_1024b_1518b; 2120 __be64 tx_1519b_max; 2121 __be64 rx_lb_drop; 2122 __be64 rx_lb_trunc; 2123 } all; 2124 } u; 2125 }; 2126 2127 #define FW_PORT_LB_STATS_CMD_LBPORT(x) ((x) << 0) 2128 #define FW_PORT_LB_STATS_CMD_NSTATS(x) ((x) << 4) 2129 #define FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << 0) 2130 #define FW_PORT_LB_STATS_CMD_IX(x) ((x) << 0) 2131 2132 struct fw_rss_ind_tbl_cmd { 2133 __be32 op_to_viid; 2134 #define FW_RSS_IND_TBL_CMD_VIID(x) ((x) << 0) 2135 __be32 retval_len16; 2136 __be16 niqid; 2137 __be16 startidx; 2138 __be32 r3; 2139 __be32 iq0_to_iq2; 2140 #define FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << 20) 2141 #define FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << 10) 2142 #define FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << 0) 2143 __be32 iq3_to_iq5; 2144 __be32 iq6_to_iq8; 2145 __be32 iq9_to_iq11; 2146 __be32 iq12_to_iq14; 2147 __be32 iq15_to_iq17; 2148 __be32 iq18_to_iq20; 2149 __be32 iq21_to_iq23; 2150 __be32 iq24_to_iq26; 2151 __be32 iq27_to_iq29; 2152 __be32 iq30_iq31; 2153 __be32 r15_lo; 2154 }; 2155 2156 struct fw_rss_glb_config_cmd { 2157 __be32 op_to_write; 2158 __be32 retval_len16; 2159 union fw_rss_glb_config { 2160 struct fw_rss_glb_config_manual { 2161 __be32 mode_pkd; 2162 __be32 r3; 2163 __be64 r4; 2164 __be64 r5; 2165 } manual; 2166 struct fw_rss_glb_config_basicvirtual { 2167 __be32 mode_pkd; 2168 __be32 synmapen_to_hashtoeplitz; 2169 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN (1U << 8) 2170 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 (1U << 7) 2171 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 (1U << 6) 2172 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 (1U << 5) 2173 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 (1U << 4) 2174 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN (1U << 3) 2175 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN (1U << 2) 2176 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP (1U << 1) 2177 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ (1U << 0) 2178 __be64 r8; 2179 __be64 r9; 2180 } basicvirtual; 2181 } u; 2182 }; 2183 2184 #define FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << 28) 2185 #define FW_RSS_GLB_CONFIG_CMD_MODE_GET(x) (((x) >> 28) & 0xf) 2186 2187 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 2188 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 2189 2190 struct fw_rss_vi_config_cmd { 2191 __be32 op_to_viid; 2192 #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0) 2193 __be32 retval_len16; 2194 union fw_rss_vi_config { 2195 struct fw_rss_vi_config_manual { 2196 __be64 r3; 2197 __be64 r4; 2198 __be64 r5; 2199 } manual; 2200 struct fw_rss_vi_config_basicvirtual { 2201 __be32 r6; 2202 __be32 defaultq_to_udpen; 2203 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) ((x) << 16) 2204 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_GET(x) (((x) >> 16) & 0x3ff) 2205 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN (1U << 4) 2206 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN (1U << 3) 2207 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN (1U << 2) 2208 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN (1U << 1) 2209 #define FW_RSS_VI_CONFIG_CMD_UDPEN (1U << 0) 2210 __be64 r9; 2211 __be64 r10; 2212 } basicvirtual; 2213 } u; 2214 }; 2215 2216 struct fw_clip_cmd { 2217 __be32 op_to_write; 2218 __be32 alloc_to_len16; 2219 __be64 ip_hi; 2220 __be64 ip_lo; 2221 __be32 r4[2]; 2222 }; 2223 2224 #define S_FW_CLIP_CMD_ALLOC 31 2225 #define M_FW_CLIP_CMD_ALLOC 0x1 2226 #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC) 2227 #define G_FW_CLIP_CMD_ALLOC(x) \ 2228 (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC) 2229 #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U) 2230 2231 #define S_FW_CLIP_CMD_FREE 30 2232 #define M_FW_CLIP_CMD_FREE 0x1 2233 #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE) 2234 #define G_FW_CLIP_CMD_FREE(x) \ 2235 (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE) 2236 #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U) 2237 2238 enum fw_error_type { 2239 FW_ERROR_TYPE_EXCEPTION = 0x0, 2240 FW_ERROR_TYPE_HWMODULE = 0x1, 2241 FW_ERROR_TYPE_WR = 0x2, 2242 FW_ERROR_TYPE_ACL = 0x3, 2243 }; 2244 2245 struct fw_error_cmd { 2246 __be32 op_to_type; 2247 __be32 len16_pkd; 2248 union fw_error { 2249 struct fw_error_exception { 2250 __be32 info[6]; 2251 } exception; 2252 struct fw_error_hwmodule { 2253 __be32 regaddr; 2254 __be32 regval; 2255 } hwmodule; 2256 struct fw_error_wr { 2257 __be16 cidx; 2258 __be16 pfn_vfn; 2259 __be32 eqid; 2260 u8 wrhdr[16]; 2261 } wr; 2262 struct fw_error_acl { 2263 __be16 cidx; 2264 __be16 pfn_vfn; 2265 __be32 eqid; 2266 __be16 mv_pkd; 2267 u8 val[6]; 2268 __be64 r4; 2269 } acl; 2270 } u; 2271 }; 2272 2273 struct fw_debug_cmd { 2274 __be32 op_type; 2275 #define FW_DEBUG_CMD_TYPE_GET(x) ((x) & 0xff) 2276 __be32 len16_pkd; 2277 union fw_debug { 2278 struct fw_debug_assert { 2279 __be32 fcid; 2280 __be32 line; 2281 __be32 x; 2282 __be32 y; 2283 u8 filename_0_7[8]; 2284 u8 filename_8_15[8]; 2285 __be64 r3; 2286 } assert; 2287 struct fw_debug_prt { 2288 __be16 dprtstridx; 2289 __be16 r3[3]; 2290 __be32 dprtstrparam0; 2291 __be32 dprtstrparam1; 2292 __be32 dprtstrparam2; 2293 __be32 dprtstrparam3; 2294 } prt; 2295 } u; 2296 }; 2297 2298 #define FW_PCIE_FW_ERR (1U << 31) 2299 #define FW_PCIE_FW_INIT (1U << 30) 2300 #define FW_PCIE_FW_HALT (1U << 29) 2301 #define FW_PCIE_FW_MASTER_VLD (1U << 15) 2302 #define FW_PCIE_FW_MASTER_MASK 0x7 2303 #define FW_PCIE_FW_MASTER_SHIFT 12 2304 #define FW_PCIE_FW_MASTER(x) ((x) << FW_PCIE_FW_MASTER_SHIFT) 2305 #define FW_PCIE_FW_MASTER_GET(x) (((x) >> FW_PCIE_FW_MASTER_SHIFT) & \ 2306 FW_PCIE_FW_MASTER_MASK) 2307 #define FW_PCIE_FW_EVAL_MASK 0x7 2308 #define FW_PCIE_FW_EVAL_SHIFT 24 2309 #define FW_PCIE_FW_EVAL_GET(x) (((x) >> FW_PCIE_FW_EVAL_SHIFT) & \ 2310 FW_PCIE_FW_EVAL_MASK) 2311 2312 struct fw_hdr { 2313 u8 ver; 2314 u8 chip; /* terminator chip type */ 2315 __be16 len512; /* bin length in units of 512-bytes */ 2316 __be32 fw_ver; /* firmware version */ 2317 __be32 tp_microcode_ver; 2318 u8 intfver_nic; 2319 u8 intfver_vnic; 2320 u8 intfver_ofld; 2321 u8 intfver_ri; 2322 u8 intfver_iscsipdu; 2323 u8 intfver_iscsi; 2324 u8 intfver_fcoepdu; 2325 u8 intfver_fcoe; 2326 __u32 reserved2; 2327 __u32 reserved3; 2328 __u32 reserved4; 2329 __be32 flags; 2330 __be32 reserved6[23]; 2331 }; 2332 2333 enum fw_hdr_chip { 2334 FW_HDR_CHIP_T4, 2335 FW_HDR_CHIP_T5 2336 }; 2337 2338 #define FW_HDR_FW_VER_MAJOR_GET(x) (((x) >> 24) & 0xff) 2339 #define FW_HDR_FW_VER_MINOR_GET(x) (((x) >> 16) & 0xff) 2340 #define FW_HDR_FW_VER_MICRO_GET(x) (((x) >> 8) & 0xff) 2341 #define FW_HDR_FW_VER_BUILD_GET(x) (((x) >> 0) & 0xff) 2342 2343 enum fw_hdr_intfver { 2344 FW_HDR_INTFVER_NIC = 0x00, 2345 FW_HDR_INTFVER_VNIC = 0x00, 2346 FW_HDR_INTFVER_OFLD = 0x00, 2347 FW_HDR_INTFVER_RI = 0x00, 2348 FW_HDR_INTFVER_ISCSIPDU = 0x00, 2349 FW_HDR_INTFVER_ISCSI = 0x00, 2350 FW_HDR_INTFVER_FCOEPDU = 0x00, 2351 FW_HDR_INTFVER_FCOE = 0x00, 2352 }; 2353 2354 enum fw_hdr_flags { 2355 FW_HDR_FLAGS_RESET_HALT = 0x00000001, 2356 }; 2357 2358 #endif /* _T4FW_INTERFACE_H_ */ 2359