1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2009-2016 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef _T4FW_INTERFACE_H_ 36 #define _T4FW_INTERFACE_H_ 37 38 enum fw_retval { 39 FW_SUCCESS = 0, /* completed successfully */ 40 FW_EPERM = 1, /* operation not permitted */ 41 FW_ENOENT = 2, /* no such file or directory */ 42 FW_EIO = 5, /* input/output error; hw bad */ 43 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 44 FW_EAGAIN = 11, /* try again */ 45 FW_ENOMEM = 12, /* out of memory */ 46 FW_EFAULT = 14, /* bad address; fw bad */ 47 FW_EBUSY = 16, /* resource busy */ 48 FW_EEXIST = 17, /* file exists */ 49 FW_ENODEV = 19, /* no such device */ 50 FW_EINVAL = 22, /* invalid argument */ 51 FW_ENOSPC = 28, /* no space left on device */ 52 FW_ENOSYS = 38, /* functionality not implemented */ 53 FW_ENODATA = 61, /* no data available */ 54 FW_EPROTO = 71, /* protocol error */ 55 FW_EADDRINUSE = 98, /* address already in use */ 56 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 57 FW_ENETDOWN = 100, /* network is down */ 58 FW_ENETUNREACH = 101, /* network is unreachable */ 59 FW_ENOBUFS = 105, /* no buffer space available */ 60 FW_ETIMEDOUT = 110, /* timeout */ 61 FW_EINPROGRESS = 115, /* fw internal */ 62 FW_SCSI_ABORT_REQUESTED = 128, /* */ 63 FW_SCSI_ABORT_TIMEDOUT = 129, /* */ 64 FW_SCSI_ABORTED = 130, /* */ 65 FW_SCSI_CLOSE_REQUESTED = 131, /* */ 66 FW_ERR_LINK_DOWN = 132, /* */ 67 FW_RDEV_NOT_READY = 133, /* */ 68 FW_ERR_RDEV_LOST = 134, /* */ 69 FW_ERR_RDEV_LOGO = 135, /* */ 70 FW_FCOE_NO_XCHG = 136, /* */ 71 FW_SCSI_RSP_ERR = 137, /* */ 72 FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 73 FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 74 FW_SCSI_OVER_FLOW_ERR = 140, /* */ 75 FW_SCSI_DDP_ERR = 141, /* DDP error*/ 76 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 77 }; 78 79 #define FW_T4VF_SGE_BASE_ADDR 0x0000 80 #define FW_T4VF_MPS_BASE_ADDR 0x0100 81 #define FW_T4VF_PL_BASE_ADDR 0x0200 82 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240 83 #define FW_T4VF_CIM_BASE_ADDR 0x0300 84 85 enum fw_wr_opcodes { 86 FW_FILTER_WR = 0x02, 87 FW_ULPTX_WR = 0x04, 88 FW_TP_WR = 0x05, 89 FW_ETH_TX_PKT_WR = 0x08, 90 FW_OFLD_CONNECTION_WR = 0x2f, 91 FW_FLOWC_WR = 0x0a, 92 FW_OFLD_TX_DATA_WR = 0x0b, 93 FW_CMD_WR = 0x10, 94 FW_ETH_TX_PKT_VM_WR = 0x11, 95 FW_RI_RES_WR = 0x0c, 96 FW_RI_INIT_WR = 0x0d, 97 FW_RI_RDMA_WRITE_WR = 0x14, 98 FW_RI_SEND_WR = 0x15, 99 FW_RI_RDMA_READ_WR = 0x16, 100 FW_RI_RECV_WR = 0x17, 101 FW_RI_BIND_MW_WR = 0x18, 102 FW_RI_FR_NSMR_WR = 0x19, 103 FW_RI_FR_NSMR_TPTE_WR = 0x20, 104 FW_RI_RDMA_WRITE_CMPL_WR = 0x21, 105 FW_RI_INV_LSTAG_WR = 0x1a, 106 FW_ISCSI_TX_DATA_WR = 0x45, 107 FW_PTP_TX_PKT_WR = 0x46, 108 FW_TLSTX_DATA_WR = 0x68, 109 FW_CRYPTO_LOOKASIDE_WR = 0X6d, 110 FW_LASTC2E_WR = 0x70, 111 FW_FILTER2_WR = 0x77 112 }; 113 114 struct fw_wr_hdr { 115 __be32 hi; 116 __be32 lo; 117 }; 118 119 /* work request opcode (hi) */ 120 #define FW_WR_OP_S 24 121 #define FW_WR_OP_M 0xff 122 #define FW_WR_OP_V(x) ((x) << FW_WR_OP_S) 123 #define FW_WR_OP_G(x) (((x) >> FW_WR_OP_S) & FW_WR_OP_M) 124 125 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */ 126 #define FW_WR_ATOMIC_S 23 127 #define FW_WR_ATOMIC_V(x) ((x) << FW_WR_ATOMIC_S) 128 129 /* flush flag (hi) - firmware flushes flushable work request buffered 130 * in the flow context. 131 */ 132 #define FW_WR_FLUSH_S 22 133 #define FW_WR_FLUSH_V(x) ((x) << FW_WR_FLUSH_S) 134 135 /* completion flag (hi) - firmware generates a cpl_fw6_ack */ 136 #define FW_WR_COMPL_S 21 137 #define FW_WR_COMPL_V(x) ((x) << FW_WR_COMPL_S) 138 #define FW_WR_COMPL_F FW_WR_COMPL_V(1U) 139 140 /* work request immediate data length (hi) */ 141 #define FW_WR_IMMDLEN_S 0 142 #define FW_WR_IMMDLEN_M 0xff 143 #define FW_WR_IMMDLEN_V(x) ((x) << FW_WR_IMMDLEN_S) 144 145 /* egress queue status update to associated ingress queue entry (lo) */ 146 #define FW_WR_EQUIQ_S 31 147 #define FW_WR_EQUIQ_V(x) ((x) << FW_WR_EQUIQ_S) 148 #define FW_WR_EQUIQ_F FW_WR_EQUIQ_V(1U) 149 150 /* egress queue status update to egress queue status entry (lo) */ 151 #define FW_WR_EQUEQ_S 30 152 #define FW_WR_EQUEQ_V(x) ((x) << FW_WR_EQUEQ_S) 153 #define FW_WR_EQUEQ_F FW_WR_EQUEQ_V(1U) 154 155 /* flow context identifier (lo) */ 156 #define FW_WR_FLOWID_S 8 157 #define FW_WR_FLOWID_V(x) ((x) << FW_WR_FLOWID_S) 158 159 /* length in units of 16-bytes (lo) */ 160 #define FW_WR_LEN16_S 0 161 #define FW_WR_LEN16_V(x) ((x) << FW_WR_LEN16_S) 162 163 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 164 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327 165 166 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 167 enum fw_filter_wr_cookie { 168 FW_FILTER_WR_SUCCESS, 169 FW_FILTER_WR_FLT_ADDED, 170 FW_FILTER_WR_FLT_DELETED, 171 FW_FILTER_WR_SMT_TBL_FULL, 172 FW_FILTER_WR_EINVAL, 173 }; 174 175 struct fw_filter_wr { 176 __be32 op_pkd; 177 __be32 len16_pkd; 178 __be64 r3; 179 __be32 tid_to_iq; 180 __be32 del_filter_to_l2tix; 181 __be16 ethtype; 182 __be16 ethtypem; 183 __u8 frag_to_ovlan_vldm; 184 __u8 smac_sel; 185 __be16 rx_chan_rx_rpl_iq; 186 __be32 maci_to_matchtypem; 187 __u8 ptcl; 188 __u8 ptclm; 189 __u8 ttyp; 190 __u8 ttypm; 191 __be16 ivlan; 192 __be16 ivlanm; 193 __be16 ovlan; 194 __be16 ovlanm; 195 __u8 lip[16]; 196 __u8 lipm[16]; 197 __u8 fip[16]; 198 __u8 fipm[16]; 199 __be16 lp; 200 __be16 lpm; 201 __be16 fp; 202 __be16 fpm; 203 __be16 r7; 204 __u8 sma[6]; 205 }; 206 207 struct fw_filter2_wr { 208 __be32 op_pkd; 209 __be32 len16_pkd; 210 __be64 r3; 211 __be32 tid_to_iq; 212 __be32 del_filter_to_l2tix; 213 __be16 ethtype; 214 __be16 ethtypem; 215 __u8 frag_to_ovlan_vldm; 216 __u8 smac_sel; 217 __be16 rx_chan_rx_rpl_iq; 218 __be32 maci_to_matchtypem; 219 __u8 ptcl; 220 __u8 ptclm; 221 __u8 ttyp; 222 __u8 ttypm; 223 __be16 ivlan; 224 __be16 ivlanm; 225 __be16 ovlan; 226 __be16 ovlanm; 227 __u8 lip[16]; 228 __u8 lipm[16]; 229 __u8 fip[16]; 230 __u8 fipm[16]; 231 __be16 lp; 232 __be16 lpm; 233 __be16 fp; 234 __be16 fpm; 235 __be16 r7; 236 __u8 sma[6]; 237 __be16 r8; 238 __u8 filter_type_swapmac; 239 __u8 natmode_to_ulp_type; 240 __be16 newlport; 241 __be16 newfport; 242 __u8 newlip[16]; 243 __u8 newfip[16]; 244 __be32 natseqcheck; 245 __be32 r9; 246 __be64 r10; 247 __be64 r11; 248 __be64 r12; 249 __be64 r13; 250 }; 251 252 #define FW_FILTER_WR_TID_S 12 253 #define FW_FILTER_WR_TID_M 0xfffff 254 #define FW_FILTER_WR_TID_V(x) ((x) << FW_FILTER_WR_TID_S) 255 #define FW_FILTER_WR_TID_G(x) \ 256 (((x) >> FW_FILTER_WR_TID_S) & FW_FILTER_WR_TID_M) 257 258 #define FW_FILTER_WR_RQTYPE_S 11 259 #define FW_FILTER_WR_RQTYPE_M 0x1 260 #define FW_FILTER_WR_RQTYPE_V(x) ((x) << FW_FILTER_WR_RQTYPE_S) 261 #define FW_FILTER_WR_RQTYPE_G(x) \ 262 (((x) >> FW_FILTER_WR_RQTYPE_S) & FW_FILTER_WR_RQTYPE_M) 263 #define FW_FILTER_WR_RQTYPE_F FW_FILTER_WR_RQTYPE_V(1U) 264 265 #define FW_FILTER_WR_NOREPLY_S 10 266 #define FW_FILTER_WR_NOREPLY_M 0x1 267 #define FW_FILTER_WR_NOREPLY_V(x) ((x) << FW_FILTER_WR_NOREPLY_S) 268 #define FW_FILTER_WR_NOREPLY_G(x) \ 269 (((x) >> FW_FILTER_WR_NOREPLY_S) & FW_FILTER_WR_NOREPLY_M) 270 #define FW_FILTER_WR_NOREPLY_F FW_FILTER_WR_NOREPLY_V(1U) 271 272 #define FW_FILTER_WR_IQ_S 0 273 #define FW_FILTER_WR_IQ_M 0x3ff 274 #define FW_FILTER_WR_IQ_V(x) ((x) << FW_FILTER_WR_IQ_S) 275 #define FW_FILTER_WR_IQ_G(x) \ 276 (((x) >> FW_FILTER_WR_IQ_S) & FW_FILTER_WR_IQ_M) 277 278 #define FW_FILTER_WR_DEL_FILTER_S 31 279 #define FW_FILTER_WR_DEL_FILTER_M 0x1 280 #define FW_FILTER_WR_DEL_FILTER_V(x) ((x) << FW_FILTER_WR_DEL_FILTER_S) 281 #define FW_FILTER_WR_DEL_FILTER_G(x) \ 282 (((x) >> FW_FILTER_WR_DEL_FILTER_S) & FW_FILTER_WR_DEL_FILTER_M) 283 #define FW_FILTER_WR_DEL_FILTER_F FW_FILTER_WR_DEL_FILTER_V(1U) 284 285 #define FW_FILTER_WR_RPTTID_S 25 286 #define FW_FILTER_WR_RPTTID_M 0x1 287 #define FW_FILTER_WR_RPTTID_V(x) ((x) << FW_FILTER_WR_RPTTID_S) 288 #define FW_FILTER_WR_RPTTID_G(x) \ 289 (((x) >> FW_FILTER_WR_RPTTID_S) & FW_FILTER_WR_RPTTID_M) 290 #define FW_FILTER_WR_RPTTID_F FW_FILTER_WR_RPTTID_V(1U) 291 292 #define FW_FILTER_WR_DROP_S 24 293 #define FW_FILTER_WR_DROP_M 0x1 294 #define FW_FILTER_WR_DROP_V(x) ((x) << FW_FILTER_WR_DROP_S) 295 #define FW_FILTER_WR_DROP_G(x) \ 296 (((x) >> FW_FILTER_WR_DROP_S) & FW_FILTER_WR_DROP_M) 297 #define FW_FILTER_WR_DROP_F FW_FILTER_WR_DROP_V(1U) 298 299 #define FW_FILTER_WR_DIRSTEER_S 23 300 #define FW_FILTER_WR_DIRSTEER_M 0x1 301 #define FW_FILTER_WR_DIRSTEER_V(x) ((x) << FW_FILTER_WR_DIRSTEER_S) 302 #define FW_FILTER_WR_DIRSTEER_G(x) \ 303 (((x) >> FW_FILTER_WR_DIRSTEER_S) & FW_FILTER_WR_DIRSTEER_M) 304 #define FW_FILTER_WR_DIRSTEER_F FW_FILTER_WR_DIRSTEER_V(1U) 305 306 #define FW_FILTER_WR_MASKHASH_S 22 307 #define FW_FILTER_WR_MASKHASH_M 0x1 308 #define FW_FILTER_WR_MASKHASH_V(x) ((x) << FW_FILTER_WR_MASKHASH_S) 309 #define FW_FILTER_WR_MASKHASH_G(x) \ 310 (((x) >> FW_FILTER_WR_MASKHASH_S) & FW_FILTER_WR_MASKHASH_M) 311 #define FW_FILTER_WR_MASKHASH_F FW_FILTER_WR_MASKHASH_V(1U) 312 313 #define FW_FILTER_WR_DIRSTEERHASH_S 21 314 #define FW_FILTER_WR_DIRSTEERHASH_M 0x1 315 #define FW_FILTER_WR_DIRSTEERHASH_V(x) ((x) << FW_FILTER_WR_DIRSTEERHASH_S) 316 #define FW_FILTER_WR_DIRSTEERHASH_G(x) \ 317 (((x) >> FW_FILTER_WR_DIRSTEERHASH_S) & FW_FILTER_WR_DIRSTEERHASH_M) 318 #define FW_FILTER_WR_DIRSTEERHASH_F FW_FILTER_WR_DIRSTEERHASH_V(1U) 319 320 #define FW_FILTER_WR_LPBK_S 20 321 #define FW_FILTER_WR_LPBK_M 0x1 322 #define FW_FILTER_WR_LPBK_V(x) ((x) << FW_FILTER_WR_LPBK_S) 323 #define FW_FILTER_WR_LPBK_G(x) \ 324 (((x) >> FW_FILTER_WR_LPBK_S) & FW_FILTER_WR_LPBK_M) 325 #define FW_FILTER_WR_LPBK_F FW_FILTER_WR_LPBK_V(1U) 326 327 #define FW_FILTER_WR_DMAC_S 19 328 #define FW_FILTER_WR_DMAC_M 0x1 329 #define FW_FILTER_WR_DMAC_V(x) ((x) << FW_FILTER_WR_DMAC_S) 330 #define FW_FILTER_WR_DMAC_G(x) \ 331 (((x) >> FW_FILTER_WR_DMAC_S) & FW_FILTER_WR_DMAC_M) 332 #define FW_FILTER_WR_DMAC_F FW_FILTER_WR_DMAC_V(1U) 333 334 #define FW_FILTER_WR_SMAC_S 18 335 #define FW_FILTER_WR_SMAC_M 0x1 336 #define FW_FILTER_WR_SMAC_V(x) ((x) << FW_FILTER_WR_SMAC_S) 337 #define FW_FILTER_WR_SMAC_G(x) \ 338 (((x) >> FW_FILTER_WR_SMAC_S) & FW_FILTER_WR_SMAC_M) 339 #define FW_FILTER_WR_SMAC_F FW_FILTER_WR_SMAC_V(1U) 340 341 #define FW_FILTER_WR_INSVLAN_S 17 342 #define FW_FILTER_WR_INSVLAN_M 0x1 343 #define FW_FILTER_WR_INSVLAN_V(x) ((x) << FW_FILTER_WR_INSVLAN_S) 344 #define FW_FILTER_WR_INSVLAN_G(x) \ 345 (((x) >> FW_FILTER_WR_INSVLAN_S) & FW_FILTER_WR_INSVLAN_M) 346 #define FW_FILTER_WR_INSVLAN_F FW_FILTER_WR_INSVLAN_V(1U) 347 348 #define FW_FILTER_WR_RMVLAN_S 16 349 #define FW_FILTER_WR_RMVLAN_M 0x1 350 #define FW_FILTER_WR_RMVLAN_V(x) ((x) << FW_FILTER_WR_RMVLAN_S) 351 #define FW_FILTER_WR_RMVLAN_G(x) \ 352 (((x) >> FW_FILTER_WR_RMVLAN_S) & FW_FILTER_WR_RMVLAN_M) 353 #define FW_FILTER_WR_RMVLAN_F FW_FILTER_WR_RMVLAN_V(1U) 354 355 #define FW_FILTER_WR_HITCNTS_S 15 356 #define FW_FILTER_WR_HITCNTS_M 0x1 357 #define FW_FILTER_WR_HITCNTS_V(x) ((x) << FW_FILTER_WR_HITCNTS_S) 358 #define FW_FILTER_WR_HITCNTS_G(x) \ 359 (((x) >> FW_FILTER_WR_HITCNTS_S) & FW_FILTER_WR_HITCNTS_M) 360 #define FW_FILTER_WR_HITCNTS_F FW_FILTER_WR_HITCNTS_V(1U) 361 362 #define FW_FILTER_WR_TXCHAN_S 13 363 #define FW_FILTER_WR_TXCHAN_M 0x3 364 #define FW_FILTER_WR_TXCHAN_V(x) ((x) << FW_FILTER_WR_TXCHAN_S) 365 #define FW_FILTER_WR_TXCHAN_G(x) \ 366 (((x) >> FW_FILTER_WR_TXCHAN_S) & FW_FILTER_WR_TXCHAN_M) 367 368 #define FW_FILTER_WR_PRIO_S 12 369 #define FW_FILTER_WR_PRIO_M 0x1 370 #define FW_FILTER_WR_PRIO_V(x) ((x) << FW_FILTER_WR_PRIO_S) 371 #define FW_FILTER_WR_PRIO_G(x) \ 372 (((x) >> FW_FILTER_WR_PRIO_S) & FW_FILTER_WR_PRIO_M) 373 #define FW_FILTER_WR_PRIO_F FW_FILTER_WR_PRIO_V(1U) 374 375 #define FW_FILTER_WR_L2TIX_S 0 376 #define FW_FILTER_WR_L2TIX_M 0xfff 377 #define FW_FILTER_WR_L2TIX_V(x) ((x) << FW_FILTER_WR_L2TIX_S) 378 #define FW_FILTER_WR_L2TIX_G(x) \ 379 (((x) >> FW_FILTER_WR_L2TIX_S) & FW_FILTER_WR_L2TIX_M) 380 381 #define FW_FILTER_WR_FRAG_S 7 382 #define FW_FILTER_WR_FRAG_M 0x1 383 #define FW_FILTER_WR_FRAG_V(x) ((x) << FW_FILTER_WR_FRAG_S) 384 #define FW_FILTER_WR_FRAG_G(x) \ 385 (((x) >> FW_FILTER_WR_FRAG_S) & FW_FILTER_WR_FRAG_M) 386 #define FW_FILTER_WR_FRAG_F FW_FILTER_WR_FRAG_V(1U) 387 388 #define FW_FILTER_WR_FRAGM_S 6 389 #define FW_FILTER_WR_FRAGM_M 0x1 390 #define FW_FILTER_WR_FRAGM_V(x) ((x) << FW_FILTER_WR_FRAGM_S) 391 #define FW_FILTER_WR_FRAGM_G(x) \ 392 (((x) >> FW_FILTER_WR_FRAGM_S) & FW_FILTER_WR_FRAGM_M) 393 #define FW_FILTER_WR_FRAGM_F FW_FILTER_WR_FRAGM_V(1U) 394 395 #define FW_FILTER_WR_IVLAN_VLD_S 5 396 #define FW_FILTER_WR_IVLAN_VLD_M 0x1 397 #define FW_FILTER_WR_IVLAN_VLD_V(x) ((x) << FW_FILTER_WR_IVLAN_VLD_S) 398 #define FW_FILTER_WR_IVLAN_VLD_G(x) \ 399 (((x) >> FW_FILTER_WR_IVLAN_VLD_S) & FW_FILTER_WR_IVLAN_VLD_M) 400 #define FW_FILTER_WR_IVLAN_VLD_F FW_FILTER_WR_IVLAN_VLD_V(1U) 401 402 #define FW_FILTER_WR_OVLAN_VLD_S 4 403 #define FW_FILTER_WR_OVLAN_VLD_M 0x1 404 #define FW_FILTER_WR_OVLAN_VLD_V(x) ((x) << FW_FILTER_WR_OVLAN_VLD_S) 405 #define FW_FILTER_WR_OVLAN_VLD_G(x) \ 406 (((x) >> FW_FILTER_WR_OVLAN_VLD_S) & FW_FILTER_WR_OVLAN_VLD_M) 407 #define FW_FILTER_WR_OVLAN_VLD_F FW_FILTER_WR_OVLAN_VLD_V(1U) 408 409 #define FW_FILTER_WR_IVLAN_VLDM_S 3 410 #define FW_FILTER_WR_IVLAN_VLDM_M 0x1 411 #define FW_FILTER_WR_IVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_IVLAN_VLDM_S) 412 #define FW_FILTER_WR_IVLAN_VLDM_G(x) \ 413 (((x) >> FW_FILTER_WR_IVLAN_VLDM_S) & FW_FILTER_WR_IVLAN_VLDM_M) 414 #define FW_FILTER_WR_IVLAN_VLDM_F FW_FILTER_WR_IVLAN_VLDM_V(1U) 415 416 #define FW_FILTER_WR_OVLAN_VLDM_S 2 417 #define FW_FILTER_WR_OVLAN_VLDM_M 0x1 418 #define FW_FILTER_WR_OVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_OVLAN_VLDM_S) 419 #define FW_FILTER_WR_OVLAN_VLDM_G(x) \ 420 (((x) >> FW_FILTER_WR_OVLAN_VLDM_S) & FW_FILTER_WR_OVLAN_VLDM_M) 421 #define FW_FILTER_WR_OVLAN_VLDM_F FW_FILTER_WR_OVLAN_VLDM_V(1U) 422 423 #define FW_FILTER_WR_RX_CHAN_S 15 424 #define FW_FILTER_WR_RX_CHAN_M 0x1 425 #define FW_FILTER_WR_RX_CHAN_V(x) ((x) << FW_FILTER_WR_RX_CHAN_S) 426 #define FW_FILTER_WR_RX_CHAN_G(x) \ 427 (((x) >> FW_FILTER_WR_RX_CHAN_S) & FW_FILTER_WR_RX_CHAN_M) 428 #define FW_FILTER_WR_RX_CHAN_F FW_FILTER_WR_RX_CHAN_V(1U) 429 430 #define FW_FILTER_WR_RX_RPL_IQ_S 0 431 #define FW_FILTER_WR_RX_RPL_IQ_M 0x3ff 432 #define FW_FILTER_WR_RX_RPL_IQ_V(x) ((x) << FW_FILTER_WR_RX_RPL_IQ_S) 433 #define FW_FILTER_WR_RX_RPL_IQ_G(x) \ 434 (((x) >> FW_FILTER_WR_RX_RPL_IQ_S) & FW_FILTER_WR_RX_RPL_IQ_M) 435 436 #define FW_FILTER2_WR_FILTER_TYPE_S 1 437 #define FW_FILTER2_WR_FILTER_TYPE_M 0x1 438 #define FW_FILTER2_WR_FILTER_TYPE_V(x) ((x) << FW_FILTER2_WR_FILTER_TYPE_S) 439 #define FW_FILTER2_WR_FILTER_TYPE_G(x) \ 440 (((x) >> FW_FILTER2_WR_FILTER_TYPE_S) & FW_FILTER2_WR_FILTER_TYPE_M) 441 #define FW_FILTER2_WR_FILTER_TYPE_F FW_FILTER2_WR_FILTER_TYPE_V(1U) 442 443 #define FW_FILTER2_WR_NATMODE_S 5 444 #define FW_FILTER2_WR_NATMODE_M 0x7 445 #define FW_FILTER2_WR_NATMODE_V(x) ((x) << FW_FILTER2_WR_NATMODE_S) 446 #define FW_FILTER2_WR_NATMODE_G(x) \ 447 (((x) >> FW_FILTER2_WR_NATMODE_S) & FW_FILTER2_WR_NATMODE_M) 448 449 #define FW_FILTER2_WR_NATFLAGCHECK_S 4 450 #define FW_FILTER2_WR_NATFLAGCHECK_M 0x1 451 #define FW_FILTER2_WR_NATFLAGCHECK_V(x) ((x) << FW_FILTER2_WR_NATFLAGCHECK_S) 452 #define FW_FILTER2_WR_NATFLAGCHECK_G(x) \ 453 (((x) >> FW_FILTER2_WR_NATFLAGCHECK_S) & FW_FILTER2_WR_NATFLAGCHECK_M) 454 #define FW_FILTER2_WR_NATFLAGCHECK_F FW_FILTER2_WR_NATFLAGCHECK_V(1U) 455 456 #define FW_FILTER2_WR_ULP_TYPE_S 0 457 #define FW_FILTER2_WR_ULP_TYPE_M 0xf 458 #define FW_FILTER2_WR_ULP_TYPE_V(x) ((x) << FW_FILTER2_WR_ULP_TYPE_S) 459 #define FW_FILTER2_WR_ULP_TYPE_G(x) \ 460 (((x) >> FW_FILTER2_WR_ULP_TYPE_S) & FW_FILTER2_WR_ULP_TYPE_M) 461 462 #define FW_FILTER_WR_MACI_S 23 463 #define FW_FILTER_WR_MACI_M 0x1ff 464 #define FW_FILTER_WR_MACI_V(x) ((x) << FW_FILTER_WR_MACI_S) 465 #define FW_FILTER_WR_MACI_G(x) \ 466 (((x) >> FW_FILTER_WR_MACI_S) & FW_FILTER_WR_MACI_M) 467 468 #define FW_FILTER_WR_MACIM_S 14 469 #define FW_FILTER_WR_MACIM_M 0x1ff 470 #define FW_FILTER_WR_MACIM_V(x) ((x) << FW_FILTER_WR_MACIM_S) 471 #define FW_FILTER_WR_MACIM_G(x) \ 472 (((x) >> FW_FILTER_WR_MACIM_S) & FW_FILTER_WR_MACIM_M) 473 474 #define FW_FILTER_WR_FCOE_S 13 475 #define FW_FILTER_WR_FCOE_M 0x1 476 #define FW_FILTER_WR_FCOE_V(x) ((x) << FW_FILTER_WR_FCOE_S) 477 #define FW_FILTER_WR_FCOE_G(x) \ 478 (((x) >> FW_FILTER_WR_FCOE_S) & FW_FILTER_WR_FCOE_M) 479 #define FW_FILTER_WR_FCOE_F FW_FILTER_WR_FCOE_V(1U) 480 481 #define FW_FILTER_WR_FCOEM_S 12 482 #define FW_FILTER_WR_FCOEM_M 0x1 483 #define FW_FILTER_WR_FCOEM_V(x) ((x) << FW_FILTER_WR_FCOEM_S) 484 #define FW_FILTER_WR_FCOEM_G(x) \ 485 (((x) >> FW_FILTER_WR_FCOEM_S) & FW_FILTER_WR_FCOEM_M) 486 #define FW_FILTER_WR_FCOEM_F FW_FILTER_WR_FCOEM_V(1U) 487 488 #define FW_FILTER_WR_PORT_S 9 489 #define FW_FILTER_WR_PORT_M 0x7 490 #define FW_FILTER_WR_PORT_V(x) ((x) << FW_FILTER_WR_PORT_S) 491 #define FW_FILTER_WR_PORT_G(x) \ 492 (((x) >> FW_FILTER_WR_PORT_S) & FW_FILTER_WR_PORT_M) 493 494 #define FW_FILTER_WR_PORTM_S 6 495 #define FW_FILTER_WR_PORTM_M 0x7 496 #define FW_FILTER_WR_PORTM_V(x) ((x) << FW_FILTER_WR_PORTM_S) 497 #define FW_FILTER_WR_PORTM_G(x) \ 498 (((x) >> FW_FILTER_WR_PORTM_S) & FW_FILTER_WR_PORTM_M) 499 500 #define FW_FILTER_WR_MATCHTYPE_S 3 501 #define FW_FILTER_WR_MATCHTYPE_M 0x7 502 #define FW_FILTER_WR_MATCHTYPE_V(x) ((x) << FW_FILTER_WR_MATCHTYPE_S) 503 #define FW_FILTER_WR_MATCHTYPE_G(x) \ 504 (((x) >> FW_FILTER_WR_MATCHTYPE_S) & FW_FILTER_WR_MATCHTYPE_M) 505 506 #define FW_FILTER_WR_MATCHTYPEM_S 0 507 #define FW_FILTER_WR_MATCHTYPEM_M 0x7 508 #define FW_FILTER_WR_MATCHTYPEM_V(x) ((x) << FW_FILTER_WR_MATCHTYPEM_S) 509 #define FW_FILTER_WR_MATCHTYPEM_G(x) \ 510 (((x) >> FW_FILTER_WR_MATCHTYPEM_S) & FW_FILTER_WR_MATCHTYPEM_M) 511 512 struct fw_ulptx_wr { 513 __be32 op_to_compl; 514 __be32 flowid_len16; 515 u64 cookie; 516 }; 517 518 #define FW_ULPTX_WR_DATA_S 28 519 #define FW_ULPTX_WR_DATA_M 0x1 520 #define FW_ULPTX_WR_DATA_V(x) ((x) << FW_ULPTX_WR_DATA_S) 521 #define FW_ULPTX_WR_DATA_G(x) \ 522 (((x) >> FW_ULPTX_WR_DATA_S) & FW_ULPTX_WR_DATA_M) 523 #define FW_ULPTX_WR_DATA_F FW_ULPTX_WR_DATA_V(1U) 524 525 struct fw_tp_wr { 526 __be32 op_to_immdlen; 527 __be32 flowid_len16; 528 u64 cookie; 529 }; 530 531 struct fw_eth_tx_pkt_wr { 532 __be32 op_immdlen; 533 __be32 equiq_to_len16; 534 __be64 r3; 535 }; 536 537 struct fw_ofld_connection_wr { 538 __be32 op_compl; 539 __be32 len16_pkd; 540 __u64 cookie; 541 __be64 r2; 542 __be64 r3; 543 struct fw_ofld_connection_le { 544 __be32 version_cpl; 545 __be32 filter; 546 __be32 r1; 547 __be16 lport; 548 __be16 pport; 549 union fw_ofld_connection_leip { 550 struct fw_ofld_connection_le_ipv4 { 551 __be32 pip; 552 __be32 lip; 553 __be64 r0; 554 __be64 r1; 555 __be64 r2; 556 } ipv4; 557 struct fw_ofld_connection_le_ipv6 { 558 __be64 pip_hi; 559 __be64 pip_lo; 560 __be64 lip_hi; 561 __be64 lip_lo; 562 } ipv6; 563 } u; 564 } le; 565 struct fw_ofld_connection_tcb { 566 __be32 t_state_to_astid; 567 __be16 cplrxdataack_cplpassacceptrpl; 568 __be16 rcv_adv; 569 __be32 rcv_nxt; 570 __be32 tx_max; 571 __be64 opt0; 572 __be32 opt2; 573 __be32 r1; 574 __be64 r2; 575 __be64 r3; 576 } tcb; 577 }; 578 579 #define FW_OFLD_CONNECTION_WR_VERSION_S 31 580 #define FW_OFLD_CONNECTION_WR_VERSION_M 0x1 581 #define FW_OFLD_CONNECTION_WR_VERSION_V(x) \ 582 ((x) << FW_OFLD_CONNECTION_WR_VERSION_S) 583 #define FW_OFLD_CONNECTION_WR_VERSION_G(x) \ 584 (((x) >> FW_OFLD_CONNECTION_WR_VERSION_S) & \ 585 FW_OFLD_CONNECTION_WR_VERSION_M) 586 #define FW_OFLD_CONNECTION_WR_VERSION_F \ 587 FW_OFLD_CONNECTION_WR_VERSION_V(1U) 588 589 #define FW_OFLD_CONNECTION_WR_CPL_S 30 590 #define FW_OFLD_CONNECTION_WR_CPL_M 0x1 591 #define FW_OFLD_CONNECTION_WR_CPL_V(x) ((x) << FW_OFLD_CONNECTION_WR_CPL_S) 592 #define FW_OFLD_CONNECTION_WR_CPL_G(x) \ 593 (((x) >> FW_OFLD_CONNECTION_WR_CPL_S) & FW_OFLD_CONNECTION_WR_CPL_M) 594 #define FW_OFLD_CONNECTION_WR_CPL_F FW_OFLD_CONNECTION_WR_CPL_V(1U) 595 596 #define FW_OFLD_CONNECTION_WR_T_STATE_S 28 597 #define FW_OFLD_CONNECTION_WR_T_STATE_M 0xf 598 #define FW_OFLD_CONNECTION_WR_T_STATE_V(x) \ 599 ((x) << FW_OFLD_CONNECTION_WR_T_STATE_S) 600 #define FW_OFLD_CONNECTION_WR_T_STATE_G(x) \ 601 (((x) >> FW_OFLD_CONNECTION_WR_T_STATE_S) & \ 602 FW_OFLD_CONNECTION_WR_T_STATE_M) 603 604 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_S 24 605 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_M 0xf 606 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_V(x) \ 607 ((x) << FW_OFLD_CONNECTION_WR_RCV_SCALE_S) 608 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_G(x) \ 609 (((x) >> FW_OFLD_CONNECTION_WR_RCV_SCALE_S) & \ 610 FW_OFLD_CONNECTION_WR_RCV_SCALE_M) 611 612 #define FW_OFLD_CONNECTION_WR_ASTID_S 0 613 #define FW_OFLD_CONNECTION_WR_ASTID_M 0xffffff 614 #define FW_OFLD_CONNECTION_WR_ASTID_V(x) \ 615 ((x) << FW_OFLD_CONNECTION_WR_ASTID_S) 616 #define FW_OFLD_CONNECTION_WR_ASTID_G(x) \ 617 (((x) >> FW_OFLD_CONNECTION_WR_ASTID_S) & FW_OFLD_CONNECTION_WR_ASTID_M) 618 619 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S 15 620 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M 0x1 621 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(x) \ 622 ((x) << FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) 623 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_G(x) \ 624 (((x) >> FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) & \ 625 FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M) 626 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_F \ 627 FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(1U) 628 629 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S 14 630 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M 0x1 631 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(x) \ 632 ((x) << FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) 633 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_G(x) \ 634 (((x) >> FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) & \ 635 FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M) 636 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_F \ 637 FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(1U) 638 639 enum fw_flowc_mnem_tcpstate { 640 FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */ 641 FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */ 642 FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */ 643 FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */ 644 FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */ 645 FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */ 646 FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and 647 * will resend FIN - equiv ESTAB 648 */ 649 FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, /* haven't gotten ACK for FIN and 650 * will resend FIN but have 651 * received FIN 652 */ 653 FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, /* haven't gotten ACK for FIN and 654 * will resend FIN but have 655 * received FIN 656 */ 657 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK, 658 * waiting for FIN 659 */ 660 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */ 661 }; 662 663 enum fw_flowc_mnem { 664 FW_FLOWC_MNEM_PFNVFN, /* PFN [15:8] VFN [7:0] */ 665 FW_FLOWC_MNEM_CH, 666 FW_FLOWC_MNEM_PORT, 667 FW_FLOWC_MNEM_IQID, 668 FW_FLOWC_MNEM_SNDNXT, 669 FW_FLOWC_MNEM_RCVNXT, 670 FW_FLOWC_MNEM_SNDBUF, 671 FW_FLOWC_MNEM_MSS, 672 FW_FLOWC_MNEM_TXDATAPLEN_MAX, 673 FW_FLOWC_MNEM_TCPSTATE, 674 FW_FLOWC_MNEM_EOSTATE, 675 FW_FLOWC_MNEM_SCHEDCLASS, 676 FW_FLOWC_MNEM_DCBPRIO, 677 FW_FLOWC_MNEM_SND_SCALE, 678 FW_FLOWC_MNEM_RCV_SCALE, 679 FW_FLOWC_MNEM_ULD_MODE, 680 FW_FLOWC_MNEM_MAX, 681 }; 682 683 struct fw_flowc_mnemval { 684 u8 mnemonic; 685 u8 r4[3]; 686 __be32 val; 687 }; 688 689 struct fw_flowc_wr { 690 __be32 op_to_nparams; 691 __be32 flowid_len16; 692 struct fw_flowc_mnemval mnemval[0]; 693 }; 694 695 #define FW_FLOWC_WR_NPARAMS_S 0 696 #define FW_FLOWC_WR_NPARAMS_V(x) ((x) << FW_FLOWC_WR_NPARAMS_S) 697 698 struct fw_ofld_tx_data_wr { 699 __be32 op_to_immdlen; 700 __be32 flowid_len16; 701 __be32 plen; 702 __be32 tunnel_to_proxy; 703 }; 704 705 #define FW_OFLD_TX_DATA_WR_ALIGNPLD_S 30 706 #define FW_OFLD_TX_DATA_WR_ALIGNPLD_V(x) ((x) << FW_OFLD_TX_DATA_WR_ALIGNPLD_S) 707 #define FW_OFLD_TX_DATA_WR_ALIGNPLD_F FW_OFLD_TX_DATA_WR_ALIGNPLD_V(1U) 708 709 #define FW_OFLD_TX_DATA_WR_SHOVE_S 29 710 #define FW_OFLD_TX_DATA_WR_SHOVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SHOVE_S) 711 #define FW_OFLD_TX_DATA_WR_SHOVE_F FW_OFLD_TX_DATA_WR_SHOVE_V(1U) 712 713 #define FW_OFLD_TX_DATA_WR_TUNNEL_S 19 714 #define FW_OFLD_TX_DATA_WR_TUNNEL_V(x) ((x) << FW_OFLD_TX_DATA_WR_TUNNEL_S) 715 716 #define FW_OFLD_TX_DATA_WR_SAVE_S 18 717 #define FW_OFLD_TX_DATA_WR_SAVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SAVE_S) 718 719 #define FW_OFLD_TX_DATA_WR_FLUSH_S 17 720 #define FW_OFLD_TX_DATA_WR_FLUSH_V(x) ((x) << FW_OFLD_TX_DATA_WR_FLUSH_S) 721 #define FW_OFLD_TX_DATA_WR_FLUSH_F FW_OFLD_TX_DATA_WR_FLUSH_V(1U) 722 723 #define FW_OFLD_TX_DATA_WR_URGENT_S 16 724 #define FW_OFLD_TX_DATA_WR_URGENT_V(x) ((x) << FW_OFLD_TX_DATA_WR_URGENT_S) 725 726 #define FW_OFLD_TX_DATA_WR_MORE_S 15 727 #define FW_OFLD_TX_DATA_WR_MORE_V(x) ((x) << FW_OFLD_TX_DATA_WR_MORE_S) 728 729 #define FW_OFLD_TX_DATA_WR_ULPMODE_S 10 730 #define FW_OFLD_TX_DATA_WR_ULPMODE_V(x) ((x) << FW_OFLD_TX_DATA_WR_ULPMODE_S) 731 732 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_S 6 733 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_V(x) \ 734 ((x) << FW_OFLD_TX_DATA_WR_ULPSUBMODE_S) 735 736 struct fw_cmd_wr { 737 __be32 op_dma; 738 __be32 len16_pkd; 739 __be64 cookie_daddr; 740 }; 741 742 #define FW_CMD_WR_DMA_S 17 743 #define FW_CMD_WR_DMA_V(x) ((x) << FW_CMD_WR_DMA_S) 744 745 struct fw_eth_tx_pkt_vm_wr { 746 __be32 op_immdlen; 747 __be32 equiq_to_len16; 748 __be32 r3[2]; 749 u8 ethmacdst[6]; 750 u8 ethmacsrc[6]; 751 __be16 ethtype; 752 __be16 vlantci; 753 }; 754 755 #define FW_CMD_MAX_TIMEOUT 10000 756 757 /* 758 * If a host driver does a HELLO and discovers that there's already a MASTER 759 * selected, we may have to wait for that MASTER to finish issuing RESET, 760 * configuration and INITIALIZE commands. Also, there's a possibility that 761 * our own HELLO may get lost if it happens right as the MASTER is issuign a 762 * RESET command, so we need to be willing to make a few retries of our HELLO. 763 */ 764 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 765 #define FW_CMD_HELLO_RETRIES 3 766 767 768 enum fw_cmd_opcodes { 769 FW_LDST_CMD = 0x01, 770 FW_RESET_CMD = 0x03, 771 FW_HELLO_CMD = 0x04, 772 FW_BYE_CMD = 0x05, 773 FW_INITIALIZE_CMD = 0x06, 774 FW_CAPS_CONFIG_CMD = 0x07, 775 FW_PARAMS_CMD = 0x08, 776 FW_PFVF_CMD = 0x09, 777 FW_IQ_CMD = 0x10, 778 FW_EQ_MNGT_CMD = 0x11, 779 FW_EQ_ETH_CMD = 0x12, 780 FW_EQ_CTRL_CMD = 0x13, 781 FW_EQ_OFLD_CMD = 0x21, 782 FW_VI_CMD = 0x14, 783 FW_VI_MAC_CMD = 0x15, 784 FW_VI_RXMODE_CMD = 0x16, 785 FW_VI_ENABLE_CMD = 0x17, 786 FW_ACL_MAC_CMD = 0x18, 787 FW_ACL_VLAN_CMD = 0x19, 788 FW_VI_STATS_CMD = 0x1a, 789 FW_PORT_CMD = 0x1b, 790 FW_PORT_STATS_CMD = 0x1c, 791 FW_PORT_LB_STATS_CMD = 0x1d, 792 FW_PORT_TRACE_CMD = 0x1e, 793 FW_PORT_TRACE_MMAP_CMD = 0x1f, 794 FW_RSS_IND_TBL_CMD = 0x20, 795 FW_RSS_GLB_CONFIG_CMD = 0x22, 796 FW_RSS_VI_CONFIG_CMD = 0x23, 797 FW_SCHED_CMD = 0x24, 798 FW_DEVLOG_CMD = 0x25, 799 FW_CLIP_CMD = 0x28, 800 FW_PTP_CMD = 0x3e, 801 FW_HMA_CMD = 0x3f, 802 FW_LASTC2E_CMD = 0x40, 803 FW_ERROR_CMD = 0x80, 804 FW_DEBUG_CMD = 0x81, 805 }; 806 807 enum fw_cmd_cap { 808 FW_CMD_CAP_PF = 0x01, 809 FW_CMD_CAP_DMAQ = 0x02, 810 FW_CMD_CAP_PORT = 0x04, 811 FW_CMD_CAP_PORTPROMISC = 0x08, 812 FW_CMD_CAP_PORTSTATS = 0x10, 813 FW_CMD_CAP_VF = 0x80, 814 }; 815 816 /* 817 * Generic command header flit0 818 */ 819 struct fw_cmd_hdr { 820 __be32 hi; 821 __be32 lo; 822 }; 823 824 #define FW_CMD_OP_S 24 825 #define FW_CMD_OP_M 0xff 826 #define FW_CMD_OP_V(x) ((x) << FW_CMD_OP_S) 827 #define FW_CMD_OP_G(x) (((x) >> FW_CMD_OP_S) & FW_CMD_OP_M) 828 829 #define FW_CMD_REQUEST_S 23 830 #define FW_CMD_REQUEST_V(x) ((x) << FW_CMD_REQUEST_S) 831 #define FW_CMD_REQUEST_F FW_CMD_REQUEST_V(1U) 832 833 #define FW_CMD_READ_S 22 834 #define FW_CMD_READ_V(x) ((x) << FW_CMD_READ_S) 835 #define FW_CMD_READ_F FW_CMD_READ_V(1U) 836 837 #define FW_CMD_WRITE_S 21 838 #define FW_CMD_WRITE_V(x) ((x) << FW_CMD_WRITE_S) 839 #define FW_CMD_WRITE_F FW_CMD_WRITE_V(1U) 840 841 #define FW_CMD_EXEC_S 20 842 #define FW_CMD_EXEC_V(x) ((x) << FW_CMD_EXEC_S) 843 #define FW_CMD_EXEC_F FW_CMD_EXEC_V(1U) 844 845 #define FW_CMD_RAMASK_S 20 846 #define FW_CMD_RAMASK_V(x) ((x) << FW_CMD_RAMASK_S) 847 848 #define FW_CMD_RETVAL_S 8 849 #define FW_CMD_RETVAL_M 0xff 850 #define FW_CMD_RETVAL_V(x) ((x) << FW_CMD_RETVAL_S) 851 #define FW_CMD_RETVAL_G(x) (((x) >> FW_CMD_RETVAL_S) & FW_CMD_RETVAL_M) 852 853 #define FW_CMD_LEN16_S 0 854 #define FW_CMD_LEN16_V(x) ((x) << FW_CMD_LEN16_S) 855 856 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 857 858 enum fw_ldst_addrspc { 859 FW_LDST_ADDRSPC_FIRMWARE = 0x0001, 860 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, 861 FW_LDST_ADDRSPC_SGE_INGC = 0x0009, 862 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, 863 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 864 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 865 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 866 FW_LDST_ADDRSPC_TP_MIB = 0x0012, 867 FW_LDST_ADDRSPC_MDIO = 0x0018, 868 FW_LDST_ADDRSPC_MPS = 0x0020, 869 FW_LDST_ADDRSPC_FUNC = 0x0028, 870 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, 871 FW_LDST_ADDRSPC_I2C = 0x0038, 872 }; 873 874 enum fw_ldst_mps_fid { 875 FW_LDST_MPS_ATRB, 876 FW_LDST_MPS_RPLC 877 }; 878 879 enum fw_ldst_func_access_ctl { 880 FW_LDST_FUNC_ACC_CTL_VIID, 881 FW_LDST_FUNC_ACC_CTL_FID 882 }; 883 884 enum fw_ldst_func_mod_index { 885 FW_LDST_FUNC_MPS 886 }; 887 888 struct fw_ldst_cmd { 889 __be32 op_to_addrspace; 890 __be32 cycles_to_len16; 891 union fw_ldst { 892 struct fw_ldst_addrval { 893 __be32 addr; 894 __be32 val; 895 } addrval; 896 struct fw_ldst_idctxt { 897 __be32 physid; 898 __be32 msg_ctxtflush; 899 __be32 ctxt_data7; 900 __be32 ctxt_data6; 901 __be32 ctxt_data5; 902 __be32 ctxt_data4; 903 __be32 ctxt_data3; 904 __be32 ctxt_data2; 905 __be32 ctxt_data1; 906 __be32 ctxt_data0; 907 } idctxt; 908 struct fw_ldst_mdio { 909 __be16 paddr_mmd; 910 __be16 raddr; 911 __be16 vctl; 912 __be16 rval; 913 } mdio; 914 struct fw_ldst_cim_rq { 915 u8 req_first64[8]; 916 u8 req_second64[8]; 917 u8 resp_first64[8]; 918 u8 resp_second64[8]; 919 __be32 r3[2]; 920 } cim_rq; 921 union fw_ldst_mps { 922 struct fw_ldst_mps_rplc { 923 __be16 fid_idx; 924 __be16 rplcpf_pkd; 925 __be32 rplc255_224; 926 __be32 rplc223_192; 927 __be32 rplc191_160; 928 __be32 rplc159_128; 929 __be32 rplc127_96; 930 __be32 rplc95_64; 931 __be32 rplc63_32; 932 __be32 rplc31_0; 933 } rplc; 934 struct fw_ldst_mps_atrb { 935 __be16 fid_mpsid; 936 __be16 r2[3]; 937 __be32 r3[2]; 938 __be32 r4; 939 __be32 atrb; 940 __be16 vlan[16]; 941 } atrb; 942 } mps; 943 struct fw_ldst_func { 944 u8 access_ctl; 945 u8 mod_index; 946 __be16 ctl_id; 947 __be32 offset; 948 __be64 data0; 949 __be64 data1; 950 } func; 951 struct fw_ldst_pcie { 952 u8 ctrl_to_fn; 953 u8 bnum; 954 u8 r; 955 u8 ext_r; 956 u8 select_naccess; 957 u8 pcie_fn; 958 __be16 nset_pkd; 959 __be32 data[12]; 960 } pcie; 961 struct fw_ldst_i2c_deprecated { 962 u8 pid_pkd; 963 u8 base; 964 u8 boffset; 965 u8 data; 966 __be32 r9; 967 } i2c_deprecated; 968 struct fw_ldst_i2c { 969 u8 pid; 970 u8 did; 971 u8 boffset; 972 u8 blen; 973 __be32 r9; 974 __u8 data[48]; 975 } i2c; 976 struct fw_ldst_le { 977 __be32 index; 978 __be32 r9; 979 u8 val[33]; 980 u8 r11[7]; 981 } le; 982 } u; 983 }; 984 985 #define FW_LDST_CMD_ADDRSPACE_S 0 986 #define FW_LDST_CMD_ADDRSPACE_V(x) ((x) << FW_LDST_CMD_ADDRSPACE_S) 987 988 #define FW_LDST_CMD_MSG_S 31 989 #define FW_LDST_CMD_MSG_V(x) ((x) << FW_LDST_CMD_MSG_S) 990 991 #define FW_LDST_CMD_CTXTFLUSH_S 30 992 #define FW_LDST_CMD_CTXTFLUSH_V(x) ((x) << FW_LDST_CMD_CTXTFLUSH_S) 993 #define FW_LDST_CMD_CTXTFLUSH_F FW_LDST_CMD_CTXTFLUSH_V(1U) 994 995 #define FW_LDST_CMD_PADDR_S 8 996 #define FW_LDST_CMD_PADDR_V(x) ((x) << FW_LDST_CMD_PADDR_S) 997 998 #define FW_LDST_CMD_MMD_S 0 999 #define FW_LDST_CMD_MMD_V(x) ((x) << FW_LDST_CMD_MMD_S) 1000 1001 #define FW_LDST_CMD_FID_S 15 1002 #define FW_LDST_CMD_FID_V(x) ((x) << FW_LDST_CMD_FID_S) 1003 1004 #define FW_LDST_CMD_IDX_S 0 1005 #define FW_LDST_CMD_IDX_V(x) ((x) << FW_LDST_CMD_IDX_S) 1006 1007 #define FW_LDST_CMD_RPLCPF_S 0 1008 #define FW_LDST_CMD_RPLCPF_V(x) ((x) << FW_LDST_CMD_RPLCPF_S) 1009 1010 #define FW_LDST_CMD_LC_S 4 1011 #define FW_LDST_CMD_LC_V(x) ((x) << FW_LDST_CMD_LC_S) 1012 #define FW_LDST_CMD_LC_F FW_LDST_CMD_LC_V(1U) 1013 1014 #define FW_LDST_CMD_FN_S 0 1015 #define FW_LDST_CMD_FN_V(x) ((x) << FW_LDST_CMD_FN_S) 1016 1017 #define FW_LDST_CMD_NACCESS_S 0 1018 #define FW_LDST_CMD_NACCESS_V(x) ((x) << FW_LDST_CMD_NACCESS_S) 1019 1020 struct fw_reset_cmd { 1021 __be32 op_to_write; 1022 __be32 retval_len16; 1023 __be32 val; 1024 __be32 halt_pkd; 1025 }; 1026 1027 #define FW_RESET_CMD_HALT_S 31 1028 #define FW_RESET_CMD_HALT_M 0x1 1029 #define FW_RESET_CMD_HALT_V(x) ((x) << FW_RESET_CMD_HALT_S) 1030 #define FW_RESET_CMD_HALT_G(x) \ 1031 (((x) >> FW_RESET_CMD_HALT_S) & FW_RESET_CMD_HALT_M) 1032 #define FW_RESET_CMD_HALT_F FW_RESET_CMD_HALT_V(1U) 1033 1034 enum fw_hellow_cmd { 1035 fw_hello_cmd_stage_os = 0x0 1036 }; 1037 1038 struct fw_hello_cmd { 1039 __be32 op_to_write; 1040 __be32 retval_len16; 1041 __be32 err_to_clearinit; 1042 __be32 fwrev; 1043 }; 1044 1045 #define FW_HELLO_CMD_ERR_S 31 1046 #define FW_HELLO_CMD_ERR_V(x) ((x) << FW_HELLO_CMD_ERR_S) 1047 #define FW_HELLO_CMD_ERR_F FW_HELLO_CMD_ERR_V(1U) 1048 1049 #define FW_HELLO_CMD_INIT_S 30 1050 #define FW_HELLO_CMD_INIT_V(x) ((x) << FW_HELLO_CMD_INIT_S) 1051 #define FW_HELLO_CMD_INIT_F FW_HELLO_CMD_INIT_V(1U) 1052 1053 #define FW_HELLO_CMD_MASTERDIS_S 29 1054 #define FW_HELLO_CMD_MASTERDIS_V(x) ((x) << FW_HELLO_CMD_MASTERDIS_S) 1055 1056 #define FW_HELLO_CMD_MASTERFORCE_S 28 1057 #define FW_HELLO_CMD_MASTERFORCE_V(x) ((x) << FW_HELLO_CMD_MASTERFORCE_S) 1058 1059 #define FW_HELLO_CMD_MBMASTER_S 24 1060 #define FW_HELLO_CMD_MBMASTER_M 0xfU 1061 #define FW_HELLO_CMD_MBMASTER_V(x) ((x) << FW_HELLO_CMD_MBMASTER_S) 1062 #define FW_HELLO_CMD_MBMASTER_G(x) \ 1063 (((x) >> FW_HELLO_CMD_MBMASTER_S) & FW_HELLO_CMD_MBMASTER_M) 1064 1065 #define FW_HELLO_CMD_MBASYNCNOTINT_S 23 1066 #define FW_HELLO_CMD_MBASYNCNOTINT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOTINT_S) 1067 1068 #define FW_HELLO_CMD_MBASYNCNOT_S 20 1069 #define FW_HELLO_CMD_MBASYNCNOT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOT_S) 1070 1071 #define FW_HELLO_CMD_STAGE_S 17 1072 #define FW_HELLO_CMD_STAGE_V(x) ((x) << FW_HELLO_CMD_STAGE_S) 1073 1074 #define FW_HELLO_CMD_CLEARINIT_S 16 1075 #define FW_HELLO_CMD_CLEARINIT_V(x) ((x) << FW_HELLO_CMD_CLEARINIT_S) 1076 #define FW_HELLO_CMD_CLEARINIT_F FW_HELLO_CMD_CLEARINIT_V(1U) 1077 1078 struct fw_bye_cmd { 1079 __be32 op_to_write; 1080 __be32 retval_len16; 1081 __be64 r3; 1082 }; 1083 1084 struct fw_initialize_cmd { 1085 __be32 op_to_write; 1086 __be32 retval_len16; 1087 __be64 r3; 1088 }; 1089 1090 enum fw_caps_config_hm { 1091 FW_CAPS_CONFIG_HM_PCIE = 0x00000001, 1092 FW_CAPS_CONFIG_HM_PL = 0x00000002, 1093 FW_CAPS_CONFIG_HM_SGE = 0x00000004, 1094 FW_CAPS_CONFIG_HM_CIM = 0x00000008, 1095 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, 1096 FW_CAPS_CONFIG_HM_TP = 0x00000020, 1097 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, 1098 FW_CAPS_CONFIG_HM_PMRX = 0x00000080, 1099 FW_CAPS_CONFIG_HM_PMTX = 0x00000100, 1100 FW_CAPS_CONFIG_HM_MC = 0x00000200, 1101 FW_CAPS_CONFIG_HM_LE = 0x00000400, 1102 FW_CAPS_CONFIG_HM_MPS = 0x00000800, 1103 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, 1104 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, 1105 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, 1106 FW_CAPS_CONFIG_HM_MI = 0x00008000, 1107 FW_CAPS_CONFIG_HM_I2CM = 0x00010000, 1108 FW_CAPS_CONFIG_HM_NCSI = 0x00020000, 1109 FW_CAPS_CONFIG_HM_SMB = 0x00040000, 1110 FW_CAPS_CONFIG_HM_MA = 0x00080000, 1111 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, 1112 FW_CAPS_CONFIG_HM_PMU = 0x00200000, 1113 FW_CAPS_CONFIG_HM_UART = 0x00400000, 1114 FW_CAPS_CONFIG_HM_SF = 0x00800000, 1115 }; 1116 1117 enum fw_caps_config_nbm { 1118 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, 1119 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, 1120 }; 1121 1122 enum fw_caps_config_link { 1123 FW_CAPS_CONFIG_LINK_PPP = 0x00000001, 1124 FW_CAPS_CONFIG_LINK_QFC = 0x00000002, 1125 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, 1126 }; 1127 1128 enum fw_caps_config_switch { 1129 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, 1130 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, 1131 }; 1132 1133 enum fw_caps_config_nic { 1134 FW_CAPS_CONFIG_NIC = 0x00000001, 1135 FW_CAPS_CONFIG_NIC_VM = 0x00000002, 1136 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020, 1137 }; 1138 1139 enum fw_caps_config_ofld { 1140 FW_CAPS_CONFIG_OFLD = 0x00000001, 1141 }; 1142 1143 enum fw_caps_config_rdma { 1144 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, 1145 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, 1146 }; 1147 1148 enum fw_caps_config_iscsi { 1149 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, 1150 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, 1151 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, 1152 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, 1153 }; 1154 1155 enum fw_caps_config_crypto { 1156 FW_CAPS_CONFIG_CRYPTO_LOOKASIDE = 0x00000001, 1157 FW_CAPS_CONFIG_TLS_INLINE = 0x00000002, 1158 FW_CAPS_CONFIG_IPSEC_INLINE = 0x00000004, 1159 }; 1160 1161 enum fw_caps_config_fcoe { 1162 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 1163 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 1164 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 1165 }; 1166 1167 enum fw_memtype_cf { 1168 FW_MEMTYPE_CF_EDC0 = 0x0, 1169 FW_MEMTYPE_CF_EDC1 = 0x1, 1170 FW_MEMTYPE_CF_EXTMEM = 0x2, 1171 FW_MEMTYPE_CF_FLASH = 0x4, 1172 FW_MEMTYPE_CF_INTERNAL = 0x5, 1173 FW_MEMTYPE_CF_EXTMEM1 = 0x6, 1174 FW_MEMTYPE_CF_HMA = 0x7, 1175 }; 1176 1177 struct fw_caps_config_cmd { 1178 __be32 op_to_write; 1179 __be32 cfvalid_to_len16; 1180 __be32 r2; 1181 __be32 hwmbitmap; 1182 __be16 nbmcaps; 1183 __be16 linkcaps; 1184 __be16 switchcaps; 1185 __be16 r3; 1186 __be16 niccaps; 1187 __be16 ofldcaps; 1188 __be16 rdmacaps; 1189 __be16 cryptocaps; 1190 __be16 iscsicaps; 1191 __be16 fcoecaps; 1192 __be32 cfcsum; 1193 __be32 finiver; 1194 __be32 finicsum; 1195 }; 1196 1197 #define FW_CAPS_CONFIG_CMD_CFVALID_S 27 1198 #define FW_CAPS_CONFIG_CMD_CFVALID_V(x) ((x) << FW_CAPS_CONFIG_CMD_CFVALID_S) 1199 #define FW_CAPS_CONFIG_CMD_CFVALID_F FW_CAPS_CONFIG_CMD_CFVALID_V(1U) 1200 1201 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S 24 1202 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(x) \ 1203 ((x) << FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S) 1204 1205 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S 16 1206 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(x) \ 1207 ((x) << FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S) 1208 1209 /* 1210 * params command mnemonics 1211 */ 1212 enum fw_params_mnem { 1213 FW_PARAMS_MNEM_DEV = 1, /* device params */ 1214 FW_PARAMS_MNEM_PFVF = 2, /* function params */ 1215 FW_PARAMS_MNEM_REG = 3, /* limited register access */ 1216 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 1217 FW_PARAMS_MNEM_CHNET = 5, /* chnet params */ 1218 FW_PARAMS_MNEM_LAST 1219 }; 1220 1221 /* 1222 * device parameters 1223 */ 1224 1225 #define FW_PARAMS_PARAM_FILTER_MODE_S 16 1226 #define FW_PARAMS_PARAM_FILTER_MODE_M 0xffff 1227 #define FW_PARAMS_PARAM_FILTER_MODE_V(x) \ 1228 ((x) << FW_PARAMS_PARAM_FILTER_MODE_S) 1229 #define FW_PARAMS_PARAM_FILTER_MODE_G(x) \ 1230 (((x) >> FW_PARAMS_PARAM_FILTER_MODE_S) & \ 1231 FW_PARAMS_PARAM_FILTER_MODE_M) 1232 1233 #define FW_PARAMS_PARAM_FILTER_MASK_S 0 1234 #define FW_PARAMS_PARAM_FILTER_MASK_M 0xffff 1235 #define FW_PARAMS_PARAM_FILTER_MASK_V(x) \ 1236 ((x) << FW_PARAMS_PARAM_FILTER_MASK_S) 1237 #define FW_PARAMS_PARAM_FILTER_MASK_G(x) \ 1238 (((x) >> FW_PARAMS_PARAM_FILTER_MASK_S) & \ 1239 FW_PARAMS_PARAM_FILTER_MASK_M) 1240 1241 enum fw_params_param_dev { 1242 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 1243 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 1244 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs 1245 * allocated by the device's 1246 * Lookup Engine 1247 */ 1248 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, 1249 FW_PARAMS_PARAM_DEV_INTVER_NIC = 0x04, 1250 FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05, 1251 FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06, 1252 FW_PARAMS_PARAM_DEV_INTVER_RI = 0x07, 1253 FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08, 1254 FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09, 1255 FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A, 1256 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, 1257 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, 1258 FW_PARAMS_PARAM_DEV_CF = 0x0D, 1259 FW_PARAMS_PARAM_DEV_PHYFW = 0x0F, 1260 FW_PARAMS_PARAM_DEV_DIAG = 0x11, 1261 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD */ 1262 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER = 0x14, /* max supported adap IRD */ 1263 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, 1264 FW_PARAMS_PARAM_DEV_FWCACHE = 0x18, 1265 FW_PARAMS_PARAM_DEV_SCFGREV = 0x1A, 1266 FW_PARAMS_PARAM_DEV_VPDREV = 0x1B, 1267 FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR = 0x1C, 1268 FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D, 1269 FW_PARAMS_PARAM_DEV_MPSBGMAP = 0x1E, 1270 FW_PARAMS_PARAM_DEV_TPCHMAP = 0x1F, 1271 FW_PARAMS_PARAM_DEV_HMA_SIZE = 0x20, 1272 FW_PARAMS_PARAM_DEV_RDMA_WRITE_WITH_IMM = 0x21, 1273 FW_PARAMS_PARAM_DEV_RI_WRITE_CMPL_WR = 0x24, 1274 FW_PARAMS_PARAM_DEV_OPAQUE_VIID_SMT_EXTN = 0x27, 1275 FW_PARAMS_PARAM_DEV_HASHFILTER_WITH_OFLD = 0x28, 1276 FW_PARAMS_PARAM_DEV_DBQ_TIMER = 0x29, 1277 FW_PARAMS_PARAM_DEV_DBQ_TIMERTICK = 0x2A, 1278 FW_PARAMS_PARAM_DEV_FILTER = 0x2E, 1279 }; 1280 1281 /* 1282 * physical and virtual function parameters 1283 */ 1284 enum fw_params_param_pfvf { 1285 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, 1286 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, 1287 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, 1288 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 1289 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 1290 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 1291 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 1292 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, 1293 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, 1294 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, 1295 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, 1296 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, 1297 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, 1298 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, 1299 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, 1300 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, 1301 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, 1302 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, 1303 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, 1304 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 1305 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 1306 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15, 1307 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16, 1308 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17, 1309 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18, 1310 FW_PARAMS_PARAM_PFVF_SRQ_START = 0x19, 1311 FW_PARAMS_PARAM_PFVF_SRQ_END = 0x1A, 1312 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, 1313 FW_PARAMS_PARAM_PFVF_VIID = 0x24, 1314 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 1315 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 1316 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 1317 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 1318 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 1319 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 1320 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, 1321 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 1322 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 1323 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, 1324 FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F, 1325 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30, 1326 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31, 1327 FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32, 1328 FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33, 1329 FW_PARAMS_PARAM_PFVF_TLS_START = 0x34, 1330 FW_PARAMS_PARAM_PFVF_TLS_END = 0x35, 1331 FW_PARAMS_PARAM_PFVF_RAWF_START = 0x36, 1332 FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37, 1333 FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x39, 1334 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A, 1335 FW_PARAMS_PARAM_PFVF_LINK_STATE = 0x40, 1336 }; 1337 1338 /* Virtual link state as seen by the specified VF */ 1339 enum vf_link_states { 1340 FW_VF_LINK_STATE_AUTO = 0x00, 1341 FW_VF_LINK_STATE_ENABLE = 0x01, 1342 FW_VF_LINK_STATE_DISABLE = 0x02, 1343 }; 1344 1345 /* 1346 * dma queue parameters 1347 */ 1348 enum fw_params_param_dmaq { 1349 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 1350 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 1351 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 1352 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 1353 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, 1354 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13, 1355 FW_PARAMS_PARAM_DMAQ_EQ_TIMERIX = 0x15, 1356 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20, 1357 }; 1358 1359 enum fw_params_param_dev_phyfw { 1360 FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00, 1361 FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01, 1362 }; 1363 1364 enum fw_params_param_dev_diag { 1365 FW_PARAM_DEV_DIAG_TMP = 0x00, 1366 FW_PARAM_DEV_DIAG_VDD = 0x01, 1367 FW_PARAM_DEV_DIAG_MAXTMPTHRESH = 0x02, 1368 }; 1369 1370 enum fw_params_param_dev_filter { 1371 FW_PARAM_DEV_FILTER_VNIC_MODE = 0x00, 1372 FW_PARAM_DEV_FILTER_MODE_MASK = 0x01, 1373 }; 1374 1375 enum fw_params_param_dev_fwcache { 1376 FW_PARAM_DEV_FWCACHE_FLUSH = 0x00, 1377 FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01, 1378 }; 1379 1380 #define FW_PARAMS_MNEM_S 24 1381 #define FW_PARAMS_MNEM_V(x) ((x) << FW_PARAMS_MNEM_S) 1382 1383 #define FW_PARAMS_PARAM_X_S 16 1384 #define FW_PARAMS_PARAM_X_V(x) ((x) << FW_PARAMS_PARAM_X_S) 1385 1386 #define FW_PARAMS_PARAM_Y_S 8 1387 #define FW_PARAMS_PARAM_Y_M 0xffU 1388 #define FW_PARAMS_PARAM_Y_V(x) ((x) << FW_PARAMS_PARAM_Y_S) 1389 #define FW_PARAMS_PARAM_Y_G(x) (((x) >> FW_PARAMS_PARAM_Y_S) &\ 1390 FW_PARAMS_PARAM_Y_M) 1391 1392 #define FW_PARAMS_PARAM_Z_S 0 1393 #define FW_PARAMS_PARAM_Z_M 0xffu 1394 #define FW_PARAMS_PARAM_Z_V(x) ((x) << FW_PARAMS_PARAM_Z_S) 1395 #define FW_PARAMS_PARAM_Z_G(x) (((x) >> FW_PARAMS_PARAM_Z_S) &\ 1396 FW_PARAMS_PARAM_Z_M) 1397 1398 #define FW_PARAMS_PARAM_XYZ_S 0 1399 #define FW_PARAMS_PARAM_XYZ_V(x) ((x) << FW_PARAMS_PARAM_XYZ_S) 1400 1401 #define FW_PARAMS_PARAM_YZ_S 0 1402 #define FW_PARAMS_PARAM_YZ_V(x) ((x) << FW_PARAMS_PARAM_YZ_S) 1403 1404 struct fw_params_cmd { 1405 __be32 op_to_vfn; 1406 __be32 retval_len16; 1407 struct fw_params_param { 1408 __be32 mnem; 1409 __be32 val; 1410 } param[7]; 1411 }; 1412 1413 #define FW_PARAMS_CMD_PFN_S 8 1414 #define FW_PARAMS_CMD_PFN_V(x) ((x) << FW_PARAMS_CMD_PFN_S) 1415 1416 #define FW_PARAMS_CMD_VFN_S 0 1417 #define FW_PARAMS_CMD_VFN_V(x) ((x) << FW_PARAMS_CMD_VFN_S) 1418 1419 struct fw_pfvf_cmd { 1420 __be32 op_to_vfn; 1421 __be32 retval_len16; 1422 __be32 niqflint_niq; 1423 __be32 type_to_neq; 1424 __be32 tc_to_nexactf; 1425 __be32 r_caps_to_nethctrl; 1426 __be16 nricq; 1427 __be16 nriqp; 1428 __be32 r4; 1429 }; 1430 1431 #define FW_PFVF_CMD_PFN_S 8 1432 #define FW_PFVF_CMD_PFN_V(x) ((x) << FW_PFVF_CMD_PFN_S) 1433 1434 #define FW_PFVF_CMD_VFN_S 0 1435 #define FW_PFVF_CMD_VFN_V(x) ((x) << FW_PFVF_CMD_VFN_S) 1436 1437 #define FW_PFVF_CMD_NIQFLINT_S 20 1438 #define FW_PFVF_CMD_NIQFLINT_M 0xfff 1439 #define FW_PFVF_CMD_NIQFLINT_V(x) ((x) << FW_PFVF_CMD_NIQFLINT_S) 1440 #define FW_PFVF_CMD_NIQFLINT_G(x) \ 1441 (((x) >> FW_PFVF_CMD_NIQFLINT_S) & FW_PFVF_CMD_NIQFLINT_M) 1442 1443 #define FW_PFVF_CMD_NIQ_S 0 1444 #define FW_PFVF_CMD_NIQ_M 0xfffff 1445 #define FW_PFVF_CMD_NIQ_V(x) ((x) << FW_PFVF_CMD_NIQ_S) 1446 #define FW_PFVF_CMD_NIQ_G(x) \ 1447 (((x) >> FW_PFVF_CMD_NIQ_S) & FW_PFVF_CMD_NIQ_M) 1448 1449 #define FW_PFVF_CMD_TYPE_S 31 1450 #define FW_PFVF_CMD_TYPE_M 0x1 1451 #define FW_PFVF_CMD_TYPE_V(x) ((x) << FW_PFVF_CMD_TYPE_S) 1452 #define FW_PFVF_CMD_TYPE_G(x) \ 1453 (((x) >> FW_PFVF_CMD_TYPE_S) & FW_PFVF_CMD_TYPE_M) 1454 #define FW_PFVF_CMD_TYPE_F FW_PFVF_CMD_TYPE_V(1U) 1455 1456 #define FW_PFVF_CMD_CMASK_S 24 1457 #define FW_PFVF_CMD_CMASK_M 0xf 1458 #define FW_PFVF_CMD_CMASK_V(x) ((x) << FW_PFVF_CMD_CMASK_S) 1459 #define FW_PFVF_CMD_CMASK_G(x) \ 1460 (((x) >> FW_PFVF_CMD_CMASK_S) & FW_PFVF_CMD_CMASK_M) 1461 1462 #define FW_PFVF_CMD_PMASK_S 20 1463 #define FW_PFVF_CMD_PMASK_M 0xf 1464 #define FW_PFVF_CMD_PMASK_V(x) ((x) << FW_PFVF_CMD_PMASK_S) 1465 #define FW_PFVF_CMD_PMASK_G(x) \ 1466 (((x) >> FW_PFVF_CMD_PMASK_S) & FW_PFVF_CMD_PMASK_M) 1467 1468 #define FW_PFVF_CMD_NEQ_S 0 1469 #define FW_PFVF_CMD_NEQ_M 0xfffff 1470 #define FW_PFVF_CMD_NEQ_V(x) ((x) << FW_PFVF_CMD_NEQ_S) 1471 #define FW_PFVF_CMD_NEQ_G(x) \ 1472 (((x) >> FW_PFVF_CMD_NEQ_S) & FW_PFVF_CMD_NEQ_M) 1473 1474 #define FW_PFVF_CMD_TC_S 24 1475 #define FW_PFVF_CMD_TC_M 0xff 1476 #define FW_PFVF_CMD_TC_V(x) ((x) << FW_PFVF_CMD_TC_S) 1477 #define FW_PFVF_CMD_TC_G(x) (((x) >> FW_PFVF_CMD_TC_S) & FW_PFVF_CMD_TC_M) 1478 1479 #define FW_PFVF_CMD_NVI_S 16 1480 #define FW_PFVF_CMD_NVI_M 0xff 1481 #define FW_PFVF_CMD_NVI_V(x) ((x) << FW_PFVF_CMD_NVI_S) 1482 #define FW_PFVF_CMD_NVI_G(x) (((x) >> FW_PFVF_CMD_NVI_S) & FW_PFVF_CMD_NVI_M) 1483 1484 #define FW_PFVF_CMD_NEXACTF_S 0 1485 #define FW_PFVF_CMD_NEXACTF_M 0xffff 1486 #define FW_PFVF_CMD_NEXACTF_V(x) ((x) << FW_PFVF_CMD_NEXACTF_S) 1487 #define FW_PFVF_CMD_NEXACTF_G(x) \ 1488 (((x) >> FW_PFVF_CMD_NEXACTF_S) & FW_PFVF_CMD_NEXACTF_M) 1489 1490 #define FW_PFVF_CMD_R_CAPS_S 24 1491 #define FW_PFVF_CMD_R_CAPS_M 0xff 1492 #define FW_PFVF_CMD_R_CAPS_V(x) ((x) << FW_PFVF_CMD_R_CAPS_S) 1493 #define FW_PFVF_CMD_R_CAPS_G(x) \ 1494 (((x) >> FW_PFVF_CMD_R_CAPS_S) & FW_PFVF_CMD_R_CAPS_M) 1495 1496 #define FW_PFVF_CMD_WX_CAPS_S 16 1497 #define FW_PFVF_CMD_WX_CAPS_M 0xff 1498 #define FW_PFVF_CMD_WX_CAPS_V(x) ((x) << FW_PFVF_CMD_WX_CAPS_S) 1499 #define FW_PFVF_CMD_WX_CAPS_G(x) \ 1500 (((x) >> FW_PFVF_CMD_WX_CAPS_S) & FW_PFVF_CMD_WX_CAPS_M) 1501 1502 #define FW_PFVF_CMD_NETHCTRL_S 0 1503 #define FW_PFVF_CMD_NETHCTRL_M 0xffff 1504 #define FW_PFVF_CMD_NETHCTRL_V(x) ((x) << FW_PFVF_CMD_NETHCTRL_S) 1505 #define FW_PFVF_CMD_NETHCTRL_G(x) \ 1506 (((x) >> FW_PFVF_CMD_NETHCTRL_S) & FW_PFVF_CMD_NETHCTRL_M) 1507 1508 enum fw_iq_type { 1509 FW_IQ_TYPE_FL_INT_CAP, 1510 FW_IQ_TYPE_NO_FL_INT_CAP 1511 }; 1512 1513 enum fw_iq_iqtype { 1514 FW_IQ_IQTYPE_OTHER, 1515 FW_IQ_IQTYPE_NIC, 1516 FW_IQ_IQTYPE_OFLD, 1517 }; 1518 1519 struct fw_iq_cmd { 1520 __be32 op_to_vfn; 1521 __be32 alloc_to_len16; 1522 __be16 physiqid; 1523 __be16 iqid; 1524 __be16 fl0id; 1525 __be16 fl1id; 1526 __be32 type_to_iqandstindex; 1527 __be16 iqdroprss_to_iqesize; 1528 __be16 iqsize; 1529 __be64 iqaddr; 1530 __be32 iqns_to_fl0congen; 1531 __be16 fl0dcaen_to_fl0cidxfthresh; 1532 __be16 fl0size; 1533 __be64 fl0addr; 1534 __be32 fl1cngchmap_to_fl1congen; 1535 __be16 fl1dcaen_to_fl1cidxfthresh; 1536 __be16 fl1size; 1537 __be64 fl1addr; 1538 }; 1539 1540 #define FW_IQ_CMD_PFN_S 8 1541 #define FW_IQ_CMD_PFN_V(x) ((x) << FW_IQ_CMD_PFN_S) 1542 1543 #define FW_IQ_CMD_VFN_S 0 1544 #define FW_IQ_CMD_VFN_V(x) ((x) << FW_IQ_CMD_VFN_S) 1545 1546 #define FW_IQ_CMD_ALLOC_S 31 1547 #define FW_IQ_CMD_ALLOC_V(x) ((x) << FW_IQ_CMD_ALLOC_S) 1548 #define FW_IQ_CMD_ALLOC_F FW_IQ_CMD_ALLOC_V(1U) 1549 1550 #define FW_IQ_CMD_FREE_S 30 1551 #define FW_IQ_CMD_FREE_V(x) ((x) << FW_IQ_CMD_FREE_S) 1552 #define FW_IQ_CMD_FREE_F FW_IQ_CMD_FREE_V(1U) 1553 1554 #define FW_IQ_CMD_MODIFY_S 29 1555 #define FW_IQ_CMD_MODIFY_V(x) ((x) << FW_IQ_CMD_MODIFY_S) 1556 #define FW_IQ_CMD_MODIFY_F FW_IQ_CMD_MODIFY_V(1U) 1557 1558 #define FW_IQ_CMD_IQSTART_S 28 1559 #define FW_IQ_CMD_IQSTART_V(x) ((x) << FW_IQ_CMD_IQSTART_S) 1560 #define FW_IQ_CMD_IQSTART_F FW_IQ_CMD_IQSTART_V(1U) 1561 1562 #define FW_IQ_CMD_IQSTOP_S 27 1563 #define FW_IQ_CMD_IQSTOP_V(x) ((x) << FW_IQ_CMD_IQSTOP_S) 1564 #define FW_IQ_CMD_IQSTOP_F FW_IQ_CMD_IQSTOP_V(1U) 1565 1566 #define FW_IQ_CMD_TYPE_S 29 1567 #define FW_IQ_CMD_TYPE_V(x) ((x) << FW_IQ_CMD_TYPE_S) 1568 1569 #define FW_IQ_CMD_IQASYNCH_S 28 1570 #define FW_IQ_CMD_IQASYNCH_V(x) ((x) << FW_IQ_CMD_IQASYNCH_S) 1571 1572 #define FW_IQ_CMD_VIID_S 16 1573 #define FW_IQ_CMD_VIID_V(x) ((x) << FW_IQ_CMD_VIID_S) 1574 1575 #define FW_IQ_CMD_IQANDST_S 15 1576 #define FW_IQ_CMD_IQANDST_V(x) ((x) << FW_IQ_CMD_IQANDST_S) 1577 1578 #define FW_IQ_CMD_IQANUS_S 14 1579 #define FW_IQ_CMD_IQANUS_V(x) ((x) << FW_IQ_CMD_IQANUS_S) 1580 1581 #define FW_IQ_CMD_IQANUD_S 12 1582 #define FW_IQ_CMD_IQANUD_V(x) ((x) << FW_IQ_CMD_IQANUD_S) 1583 1584 #define FW_IQ_CMD_IQANDSTINDEX_S 0 1585 #define FW_IQ_CMD_IQANDSTINDEX_V(x) ((x) << FW_IQ_CMD_IQANDSTINDEX_S) 1586 1587 #define FW_IQ_CMD_IQDROPRSS_S 15 1588 #define FW_IQ_CMD_IQDROPRSS_V(x) ((x) << FW_IQ_CMD_IQDROPRSS_S) 1589 #define FW_IQ_CMD_IQDROPRSS_F FW_IQ_CMD_IQDROPRSS_V(1U) 1590 1591 #define FW_IQ_CMD_IQGTSMODE_S 14 1592 #define FW_IQ_CMD_IQGTSMODE_V(x) ((x) << FW_IQ_CMD_IQGTSMODE_S) 1593 #define FW_IQ_CMD_IQGTSMODE_F FW_IQ_CMD_IQGTSMODE_V(1U) 1594 1595 #define FW_IQ_CMD_IQPCIECH_S 12 1596 #define FW_IQ_CMD_IQPCIECH_V(x) ((x) << FW_IQ_CMD_IQPCIECH_S) 1597 1598 #define FW_IQ_CMD_IQDCAEN_S 11 1599 #define FW_IQ_CMD_IQDCAEN_V(x) ((x) << FW_IQ_CMD_IQDCAEN_S) 1600 1601 #define FW_IQ_CMD_IQDCACPU_S 6 1602 #define FW_IQ_CMD_IQDCACPU_V(x) ((x) << FW_IQ_CMD_IQDCACPU_S) 1603 1604 #define FW_IQ_CMD_IQINTCNTTHRESH_S 4 1605 #define FW_IQ_CMD_IQINTCNTTHRESH_V(x) ((x) << FW_IQ_CMD_IQINTCNTTHRESH_S) 1606 1607 #define FW_IQ_CMD_IQO_S 3 1608 #define FW_IQ_CMD_IQO_V(x) ((x) << FW_IQ_CMD_IQO_S) 1609 #define FW_IQ_CMD_IQO_F FW_IQ_CMD_IQO_V(1U) 1610 1611 #define FW_IQ_CMD_IQCPRIO_S 2 1612 #define FW_IQ_CMD_IQCPRIO_V(x) ((x) << FW_IQ_CMD_IQCPRIO_S) 1613 1614 #define FW_IQ_CMD_IQESIZE_S 0 1615 #define FW_IQ_CMD_IQESIZE_V(x) ((x) << FW_IQ_CMD_IQESIZE_S) 1616 1617 #define FW_IQ_CMD_IQNS_S 31 1618 #define FW_IQ_CMD_IQNS_V(x) ((x) << FW_IQ_CMD_IQNS_S) 1619 1620 #define FW_IQ_CMD_IQRO_S 30 1621 #define FW_IQ_CMD_IQRO_V(x) ((x) << FW_IQ_CMD_IQRO_S) 1622 1623 #define FW_IQ_CMD_IQFLINTIQHSEN_S 28 1624 #define FW_IQ_CMD_IQFLINTIQHSEN_V(x) ((x) << FW_IQ_CMD_IQFLINTIQHSEN_S) 1625 1626 #define FW_IQ_CMD_IQFLINTCONGEN_S 27 1627 #define FW_IQ_CMD_IQFLINTCONGEN_V(x) ((x) << FW_IQ_CMD_IQFLINTCONGEN_S) 1628 #define FW_IQ_CMD_IQFLINTCONGEN_F FW_IQ_CMD_IQFLINTCONGEN_V(1U) 1629 1630 #define FW_IQ_CMD_IQFLINTISCSIC_S 26 1631 #define FW_IQ_CMD_IQFLINTISCSIC_V(x) ((x) << FW_IQ_CMD_IQFLINTISCSIC_S) 1632 1633 #define FW_IQ_CMD_IQTYPE_S 24 1634 #define FW_IQ_CMD_IQTYPE_M 0x3 1635 #define FW_IQ_CMD_IQTYPE_V(x) ((x) << FW_IQ_CMD_IQTYPE_S) 1636 #define FW_IQ_CMD_IQTYPE_G(x) \ 1637 (((x) >> FW_IQ_CMD_IQTYPE_S) & FW_IQ_CMD_IQTYPE_M) 1638 1639 #define FW_IQ_CMD_FL0CNGCHMAP_S 20 1640 #define FW_IQ_CMD_FL0CNGCHMAP_V(x) ((x) << FW_IQ_CMD_FL0CNGCHMAP_S) 1641 1642 #define FW_IQ_CMD_FL0CACHELOCK_S 15 1643 #define FW_IQ_CMD_FL0CACHELOCK_V(x) ((x) << FW_IQ_CMD_FL0CACHELOCK_S) 1644 1645 #define FW_IQ_CMD_FL0DBP_S 14 1646 #define FW_IQ_CMD_FL0DBP_V(x) ((x) << FW_IQ_CMD_FL0DBP_S) 1647 1648 #define FW_IQ_CMD_FL0DATANS_S 13 1649 #define FW_IQ_CMD_FL0DATANS_V(x) ((x) << FW_IQ_CMD_FL0DATANS_S) 1650 1651 #define FW_IQ_CMD_FL0DATARO_S 12 1652 #define FW_IQ_CMD_FL0DATARO_V(x) ((x) << FW_IQ_CMD_FL0DATARO_S) 1653 #define FW_IQ_CMD_FL0DATARO_F FW_IQ_CMD_FL0DATARO_V(1U) 1654 1655 #define FW_IQ_CMD_FL0CONGCIF_S 11 1656 #define FW_IQ_CMD_FL0CONGCIF_V(x) ((x) << FW_IQ_CMD_FL0CONGCIF_S) 1657 #define FW_IQ_CMD_FL0CONGCIF_F FW_IQ_CMD_FL0CONGCIF_V(1U) 1658 1659 #define FW_IQ_CMD_FL0ONCHIP_S 10 1660 #define FW_IQ_CMD_FL0ONCHIP_V(x) ((x) << FW_IQ_CMD_FL0ONCHIP_S) 1661 1662 #define FW_IQ_CMD_FL0STATUSPGNS_S 9 1663 #define FW_IQ_CMD_FL0STATUSPGNS_V(x) ((x) << FW_IQ_CMD_FL0STATUSPGNS_S) 1664 1665 #define FW_IQ_CMD_FL0STATUSPGRO_S 8 1666 #define FW_IQ_CMD_FL0STATUSPGRO_V(x) ((x) << FW_IQ_CMD_FL0STATUSPGRO_S) 1667 1668 #define FW_IQ_CMD_FL0FETCHNS_S 7 1669 #define FW_IQ_CMD_FL0FETCHNS_V(x) ((x) << FW_IQ_CMD_FL0FETCHNS_S) 1670 1671 #define FW_IQ_CMD_FL0FETCHRO_S 6 1672 #define FW_IQ_CMD_FL0FETCHRO_V(x) ((x) << FW_IQ_CMD_FL0FETCHRO_S) 1673 #define FW_IQ_CMD_FL0FETCHRO_F FW_IQ_CMD_FL0FETCHRO_V(1U) 1674 1675 #define FW_IQ_CMD_FL0HOSTFCMODE_S 4 1676 #define FW_IQ_CMD_FL0HOSTFCMODE_V(x) ((x) << FW_IQ_CMD_FL0HOSTFCMODE_S) 1677 1678 #define FW_IQ_CMD_FL0CPRIO_S 3 1679 #define FW_IQ_CMD_FL0CPRIO_V(x) ((x) << FW_IQ_CMD_FL0CPRIO_S) 1680 1681 #define FW_IQ_CMD_FL0PADEN_S 2 1682 #define FW_IQ_CMD_FL0PADEN_V(x) ((x) << FW_IQ_CMD_FL0PADEN_S) 1683 #define FW_IQ_CMD_FL0PADEN_F FW_IQ_CMD_FL0PADEN_V(1U) 1684 1685 #define FW_IQ_CMD_FL0PACKEN_S 1 1686 #define FW_IQ_CMD_FL0PACKEN_V(x) ((x) << FW_IQ_CMD_FL0PACKEN_S) 1687 #define FW_IQ_CMD_FL0PACKEN_F FW_IQ_CMD_FL0PACKEN_V(1U) 1688 1689 #define FW_IQ_CMD_FL0CONGEN_S 0 1690 #define FW_IQ_CMD_FL0CONGEN_V(x) ((x) << FW_IQ_CMD_FL0CONGEN_S) 1691 #define FW_IQ_CMD_FL0CONGEN_F FW_IQ_CMD_FL0CONGEN_V(1U) 1692 1693 #define FW_IQ_CMD_FL0DCAEN_S 15 1694 #define FW_IQ_CMD_FL0DCAEN_V(x) ((x) << FW_IQ_CMD_FL0DCAEN_S) 1695 1696 #define FW_IQ_CMD_FL0DCACPU_S 10 1697 #define FW_IQ_CMD_FL0DCACPU_V(x) ((x) << FW_IQ_CMD_FL0DCACPU_S) 1698 1699 #define FW_IQ_CMD_FL0FBMIN_S 7 1700 #define FW_IQ_CMD_FL0FBMIN_V(x) ((x) << FW_IQ_CMD_FL0FBMIN_S) 1701 1702 #define FW_IQ_CMD_FL0FBMAX_S 4 1703 #define FW_IQ_CMD_FL0FBMAX_V(x) ((x) << FW_IQ_CMD_FL0FBMAX_S) 1704 1705 #define FW_IQ_CMD_FL0CIDXFTHRESHO_S 3 1706 #define FW_IQ_CMD_FL0CIDXFTHRESHO_V(x) ((x) << FW_IQ_CMD_FL0CIDXFTHRESHO_S) 1707 #define FW_IQ_CMD_FL0CIDXFTHRESHO_F FW_IQ_CMD_FL0CIDXFTHRESHO_V(1U) 1708 1709 #define FW_IQ_CMD_FL0CIDXFTHRESH_S 0 1710 #define FW_IQ_CMD_FL0CIDXFTHRESH_V(x) ((x) << FW_IQ_CMD_FL0CIDXFTHRESH_S) 1711 1712 #define FW_IQ_CMD_FL1CNGCHMAP_S 20 1713 #define FW_IQ_CMD_FL1CNGCHMAP_V(x) ((x) << FW_IQ_CMD_FL1CNGCHMAP_S) 1714 1715 #define FW_IQ_CMD_FL1CACHELOCK_S 15 1716 #define FW_IQ_CMD_FL1CACHELOCK_V(x) ((x) << FW_IQ_CMD_FL1CACHELOCK_S) 1717 1718 #define FW_IQ_CMD_FL1DBP_S 14 1719 #define FW_IQ_CMD_FL1DBP_V(x) ((x) << FW_IQ_CMD_FL1DBP_S) 1720 1721 #define FW_IQ_CMD_FL1DATANS_S 13 1722 #define FW_IQ_CMD_FL1DATANS_V(x) ((x) << FW_IQ_CMD_FL1DATANS_S) 1723 1724 #define FW_IQ_CMD_FL1DATARO_S 12 1725 #define FW_IQ_CMD_FL1DATARO_V(x) ((x) << FW_IQ_CMD_FL1DATARO_S) 1726 1727 #define FW_IQ_CMD_FL1CONGCIF_S 11 1728 #define FW_IQ_CMD_FL1CONGCIF_V(x) ((x) << FW_IQ_CMD_FL1CONGCIF_S) 1729 1730 #define FW_IQ_CMD_FL1ONCHIP_S 10 1731 #define FW_IQ_CMD_FL1ONCHIP_V(x) ((x) << FW_IQ_CMD_FL1ONCHIP_S) 1732 1733 #define FW_IQ_CMD_FL1STATUSPGNS_S 9 1734 #define FW_IQ_CMD_FL1STATUSPGNS_V(x) ((x) << FW_IQ_CMD_FL1STATUSPGNS_S) 1735 1736 #define FW_IQ_CMD_FL1STATUSPGRO_S 8 1737 #define FW_IQ_CMD_FL1STATUSPGRO_V(x) ((x) << FW_IQ_CMD_FL1STATUSPGRO_S) 1738 1739 #define FW_IQ_CMD_FL1FETCHNS_S 7 1740 #define FW_IQ_CMD_FL1FETCHNS_V(x) ((x) << FW_IQ_CMD_FL1FETCHNS_S) 1741 1742 #define FW_IQ_CMD_FL1FETCHRO_S 6 1743 #define FW_IQ_CMD_FL1FETCHRO_V(x) ((x) << FW_IQ_CMD_FL1FETCHRO_S) 1744 1745 #define FW_IQ_CMD_FL1HOSTFCMODE_S 4 1746 #define FW_IQ_CMD_FL1HOSTFCMODE_V(x) ((x) << FW_IQ_CMD_FL1HOSTFCMODE_S) 1747 1748 #define FW_IQ_CMD_FL1CPRIO_S 3 1749 #define FW_IQ_CMD_FL1CPRIO_V(x) ((x) << FW_IQ_CMD_FL1CPRIO_S) 1750 1751 #define FW_IQ_CMD_FL1PADEN_S 2 1752 #define FW_IQ_CMD_FL1PADEN_V(x) ((x) << FW_IQ_CMD_FL1PADEN_S) 1753 #define FW_IQ_CMD_FL1PADEN_F FW_IQ_CMD_FL1PADEN_V(1U) 1754 1755 #define FW_IQ_CMD_FL1PACKEN_S 1 1756 #define FW_IQ_CMD_FL1PACKEN_V(x) ((x) << FW_IQ_CMD_FL1PACKEN_S) 1757 #define FW_IQ_CMD_FL1PACKEN_F FW_IQ_CMD_FL1PACKEN_V(1U) 1758 1759 #define FW_IQ_CMD_FL1CONGEN_S 0 1760 #define FW_IQ_CMD_FL1CONGEN_V(x) ((x) << FW_IQ_CMD_FL1CONGEN_S) 1761 #define FW_IQ_CMD_FL1CONGEN_F FW_IQ_CMD_FL1CONGEN_V(1U) 1762 1763 #define FW_IQ_CMD_FL1DCAEN_S 15 1764 #define FW_IQ_CMD_FL1DCAEN_V(x) ((x) << FW_IQ_CMD_FL1DCAEN_S) 1765 1766 #define FW_IQ_CMD_FL1DCACPU_S 10 1767 #define FW_IQ_CMD_FL1DCACPU_V(x) ((x) << FW_IQ_CMD_FL1DCACPU_S) 1768 1769 #define FW_IQ_CMD_FL1FBMIN_S 7 1770 #define FW_IQ_CMD_FL1FBMIN_V(x) ((x) << FW_IQ_CMD_FL1FBMIN_S) 1771 1772 #define FW_IQ_CMD_FL1FBMAX_S 4 1773 #define FW_IQ_CMD_FL1FBMAX_V(x) ((x) << FW_IQ_CMD_FL1FBMAX_S) 1774 1775 #define FW_IQ_CMD_FL1CIDXFTHRESHO_S 3 1776 #define FW_IQ_CMD_FL1CIDXFTHRESHO_V(x) ((x) << FW_IQ_CMD_FL1CIDXFTHRESHO_S) 1777 #define FW_IQ_CMD_FL1CIDXFTHRESHO_F FW_IQ_CMD_FL1CIDXFTHRESHO_V(1U) 1778 1779 #define FW_IQ_CMD_FL1CIDXFTHRESH_S 0 1780 #define FW_IQ_CMD_FL1CIDXFTHRESH_V(x) ((x) << FW_IQ_CMD_FL1CIDXFTHRESH_S) 1781 1782 struct fw_eq_eth_cmd { 1783 __be32 op_to_vfn; 1784 __be32 alloc_to_len16; 1785 __be32 eqid_pkd; 1786 __be32 physeqid_pkd; 1787 __be32 fetchszm_to_iqid; 1788 __be32 dcaen_to_eqsize; 1789 __be64 eqaddr; 1790 __be32 autoequiqe_to_viid; 1791 __be32 timeren_timerix; 1792 __be64 r9; 1793 }; 1794 1795 #define FW_EQ_ETH_CMD_PFN_S 8 1796 #define FW_EQ_ETH_CMD_PFN_V(x) ((x) << FW_EQ_ETH_CMD_PFN_S) 1797 1798 #define FW_EQ_ETH_CMD_VFN_S 0 1799 #define FW_EQ_ETH_CMD_VFN_V(x) ((x) << FW_EQ_ETH_CMD_VFN_S) 1800 1801 #define FW_EQ_ETH_CMD_ALLOC_S 31 1802 #define FW_EQ_ETH_CMD_ALLOC_V(x) ((x) << FW_EQ_ETH_CMD_ALLOC_S) 1803 #define FW_EQ_ETH_CMD_ALLOC_F FW_EQ_ETH_CMD_ALLOC_V(1U) 1804 1805 #define FW_EQ_ETH_CMD_FREE_S 30 1806 #define FW_EQ_ETH_CMD_FREE_V(x) ((x) << FW_EQ_ETH_CMD_FREE_S) 1807 #define FW_EQ_ETH_CMD_FREE_F FW_EQ_ETH_CMD_FREE_V(1U) 1808 1809 #define FW_EQ_ETH_CMD_MODIFY_S 29 1810 #define FW_EQ_ETH_CMD_MODIFY_V(x) ((x) << FW_EQ_ETH_CMD_MODIFY_S) 1811 #define FW_EQ_ETH_CMD_MODIFY_F FW_EQ_ETH_CMD_MODIFY_V(1U) 1812 1813 #define FW_EQ_ETH_CMD_EQSTART_S 28 1814 #define FW_EQ_ETH_CMD_EQSTART_V(x) ((x) << FW_EQ_ETH_CMD_EQSTART_S) 1815 #define FW_EQ_ETH_CMD_EQSTART_F FW_EQ_ETH_CMD_EQSTART_V(1U) 1816 1817 #define FW_EQ_ETH_CMD_EQSTOP_S 27 1818 #define FW_EQ_ETH_CMD_EQSTOP_V(x) ((x) << FW_EQ_ETH_CMD_EQSTOP_S) 1819 #define FW_EQ_ETH_CMD_EQSTOP_F FW_EQ_ETH_CMD_EQSTOP_V(1U) 1820 1821 #define FW_EQ_ETH_CMD_EQID_S 0 1822 #define FW_EQ_ETH_CMD_EQID_M 0xfffff 1823 #define FW_EQ_ETH_CMD_EQID_V(x) ((x) << FW_EQ_ETH_CMD_EQID_S) 1824 #define FW_EQ_ETH_CMD_EQID_G(x) \ 1825 (((x) >> FW_EQ_ETH_CMD_EQID_S) & FW_EQ_ETH_CMD_EQID_M) 1826 1827 #define FW_EQ_ETH_CMD_PHYSEQID_S 0 1828 #define FW_EQ_ETH_CMD_PHYSEQID_M 0xfffff 1829 #define FW_EQ_ETH_CMD_PHYSEQID_V(x) ((x) << FW_EQ_ETH_CMD_PHYSEQID_S) 1830 #define FW_EQ_ETH_CMD_PHYSEQID_G(x) \ 1831 (((x) >> FW_EQ_ETH_CMD_PHYSEQID_S) & FW_EQ_ETH_CMD_PHYSEQID_M) 1832 1833 #define FW_EQ_ETH_CMD_FETCHSZM_S 26 1834 #define FW_EQ_ETH_CMD_FETCHSZM_V(x) ((x) << FW_EQ_ETH_CMD_FETCHSZM_S) 1835 #define FW_EQ_ETH_CMD_FETCHSZM_F FW_EQ_ETH_CMD_FETCHSZM_V(1U) 1836 1837 #define FW_EQ_ETH_CMD_STATUSPGNS_S 25 1838 #define FW_EQ_ETH_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_ETH_CMD_STATUSPGNS_S) 1839 1840 #define FW_EQ_ETH_CMD_STATUSPGRO_S 24 1841 #define FW_EQ_ETH_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_ETH_CMD_STATUSPGRO_S) 1842 1843 #define FW_EQ_ETH_CMD_FETCHNS_S 23 1844 #define FW_EQ_ETH_CMD_FETCHNS_V(x) ((x) << FW_EQ_ETH_CMD_FETCHNS_S) 1845 1846 #define FW_EQ_ETH_CMD_FETCHRO_S 22 1847 #define FW_EQ_ETH_CMD_FETCHRO_V(x) ((x) << FW_EQ_ETH_CMD_FETCHRO_S) 1848 #define FW_EQ_ETH_CMD_FETCHRO_F FW_EQ_ETH_CMD_FETCHRO_V(1U) 1849 1850 #define FW_EQ_ETH_CMD_HOSTFCMODE_S 20 1851 #define FW_EQ_ETH_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_ETH_CMD_HOSTFCMODE_S) 1852 1853 #define FW_EQ_ETH_CMD_CPRIO_S 19 1854 #define FW_EQ_ETH_CMD_CPRIO_V(x) ((x) << FW_EQ_ETH_CMD_CPRIO_S) 1855 1856 #define FW_EQ_ETH_CMD_ONCHIP_S 18 1857 #define FW_EQ_ETH_CMD_ONCHIP_V(x) ((x) << FW_EQ_ETH_CMD_ONCHIP_S) 1858 1859 #define FW_EQ_ETH_CMD_PCIECHN_S 16 1860 #define FW_EQ_ETH_CMD_PCIECHN_V(x) ((x) << FW_EQ_ETH_CMD_PCIECHN_S) 1861 1862 #define FW_EQ_ETH_CMD_IQID_S 0 1863 #define FW_EQ_ETH_CMD_IQID_V(x) ((x) << FW_EQ_ETH_CMD_IQID_S) 1864 1865 #define FW_EQ_ETH_CMD_DCAEN_S 31 1866 #define FW_EQ_ETH_CMD_DCAEN_V(x) ((x) << FW_EQ_ETH_CMD_DCAEN_S) 1867 1868 #define FW_EQ_ETH_CMD_DCACPU_S 26 1869 #define FW_EQ_ETH_CMD_DCACPU_V(x) ((x) << FW_EQ_ETH_CMD_DCACPU_S) 1870 1871 #define FW_EQ_ETH_CMD_FBMIN_S 23 1872 #define FW_EQ_ETH_CMD_FBMIN_V(x) ((x) << FW_EQ_ETH_CMD_FBMIN_S) 1873 1874 #define FW_EQ_ETH_CMD_FBMAX_S 20 1875 #define FW_EQ_ETH_CMD_FBMAX_V(x) ((x) << FW_EQ_ETH_CMD_FBMAX_S) 1876 1877 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_S 19 1878 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESHO_S) 1879 1880 #define FW_EQ_ETH_CMD_CIDXFTHRESH_S 16 1881 #define FW_EQ_ETH_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESH_S) 1882 1883 #define FW_EQ_ETH_CMD_EQSIZE_S 0 1884 #define FW_EQ_ETH_CMD_EQSIZE_V(x) ((x) << FW_EQ_ETH_CMD_EQSIZE_S) 1885 1886 #define FW_EQ_ETH_CMD_AUTOEQUIQE_S 31 1887 #define FW_EQ_ETH_CMD_AUTOEQUIQE_V(x) ((x) << FW_EQ_ETH_CMD_AUTOEQUIQE_S) 1888 #define FW_EQ_ETH_CMD_AUTOEQUIQE_F FW_EQ_ETH_CMD_AUTOEQUIQE_V(1U) 1889 1890 #define FW_EQ_ETH_CMD_AUTOEQUEQE_S 30 1891 #define FW_EQ_ETH_CMD_AUTOEQUEQE_V(x) ((x) << FW_EQ_ETH_CMD_AUTOEQUEQE_S) 1892 #define FW_EQ_ETH_CMD_AUTOEQUEQE_F FW_EQ_ETH_CMD_AUTOEQUEQE_V(1U) 1893 1894 #define FW_EQ_ETH_CMD_VIID_S 16 1895 #define FW_EQ_ETH_CMD_VIID_V(x) ((x) << FW_EQ_ETH_CMD_VIID_S) 1896 1897 #define FW_EQ_ETH_CMD_TIMEREN_S 3 1898 #define FW_EQ_ETH_CMD_TIMEREN_M 0x1 1899 #define FW_EQ_ETH_CMD_TIMEREN_V(x) ((x) << FW_EQ_ETH_CMD_TIMEREN_S) 1900 #define FW_EQ_ETH_CMD_TIMEREN_G(x) \ 1901 (((x) >> FW_EQ_ETH_CMD_TIMEREN_S) & FW_EQ_ETH_CMD_TIMEREN_M) 1902 #define FW_EQ_ETH_CMD_TIMEREN_F FW_EQ_ETH_CMD_TIMEREN_V(1U) 1903 1904 #define FW_EQ_ETH_CMD_TIMERIX_S 0 1905 #define FW_EQ_ETH_CMD_TIMERIX_M 0x7 1906 #define FW_EQ_ETH_CMD_TIMERIX_V(x) ((x) << FW_EQ_ETH_CMD_TIMERIX_S) 1907 #define FW_EQ_ETH_CMD_TIMERIX_G(x) \ 1908 (((x) >> FW_EQ_ETH_CMD_TIMERIX_S) & FW_EQ_ETH_CMD_TIMERIX_M) 1909 1910 struct fw_eq_ctrl_cmd { 1911 __be32 op_to_vfn; 1912 __be32 alloc_to_len16; 1913 __be32 cmpliqid_eqid; 1914 __be32 physeqid_pkd; 1915 __be32 fetchszm_to_iqid; 1916 __be32 dcaen_to_eqsize; 1917 __be64 eqaddr; 1918 }; 1919 1920 #define FW_EQ_CTRL_CMD_PFN_S 8 1921 #define FW_EQ_CTRL_CMD_PFN_V(x) ((x) << FW_EQ_CTRL_CMD_PFN_S) 1922 1923 #define FW_EQ_CTRL_CMD_VFN_S 0 1924 #define FW_EQ_CTRL_CMD_VFN_V(x) ((x) << FW_EQ_CTRL_CMD_VFN_S) 1925 1926 #define FW_EQ_CTRL_CMD_ALLOC_S 31 1927 #define FW_EQ_CTRL_CMD_ALLOC_V(x) ((x) << FW_EQ_CTRL_CMD_ALLOC_S) 1928 #define FW_EQ_CTRL_CMD_ALLOC_F FW_EQ_CTRL_CMD_ALLOC_V(1U) 1929 1930 #define FW_EQ_CTRL_CMD_FREE_S 30 1931 #define FW_EQ_CTRL_CMD_FREE_V(x) ((x) << FW_EQ_CTRL_CMD_FREE_S) 1932 #define FW_EQ_CTRL_CMD_FREE_F FW_EQ_CTRL_CMD_FREE_V(1U) 1933 1934 #define FW_EQ_CTRL_CMD_MODIFY_S 29 1935 #define FW_EQ_CTRL_CMD_MODIFY_V(x) ((x) << FW_EQ_CTRL_CMD_MODIFY_S) 1936 #define FW_EQ_CTRL_CMD_MODIFY_F FW_EQ_CTRL_CMD_MODIFY_V(1U) 1937 1938 #define FW_EQ_CTRL_CMD_EQSTART_S 28 1939 #define FW_EQ_CTRL_CMD_EQSTART_V(x) ((x) << FW_EQ_CTRL_CMD_EQSTART_S) 1940 #define FW_EQ_CTRL_CMD_EQSTART_F FW_EQ_CTRL_CMD_EQSTART_V(1U) 1941 1942 #define FW_EQ_CTRL_CMD_EQSTOP_S 27 1943 #define FW_EQ_CTRL_CMD_EQSTOP_V(x) ((x) << FW_EQ_CTRL_CMD_EQSTOP_S) 1944 #define FW_EQ_CTRL_CMD_EQSTOP_F FW_EQ_CTRL_CMD_EQSTOP_V(1U) 1945 1946 #define FW_EQ_CTRL_CMD_CMPLIQID_S 20 1947 #define FW_EQ_CTRL_CMD_CMPLIQID_V(x) ((x) << FW_EQ_CTRL_CMD_CMPLIQID_S) 1948 1949 #define FW_EQ_CTRL_CMD_EQID_S 0 1950 #define FW_EQ_CTRL_CMD_EQID_M 0xfffff 1951 #define FW_EQ_CTRL_CMD_EQID_V(x) ((x) << FW_EQ_CTRL_CMD_EQID_S) 1952 #define FW_EQ_CTRL_CMD_EQID_G(x) \ 1953 (((x) >> FW_EQ_CTRL_CMD_EQID_S) & FW_EQ_CTRL_CMD_EQID_M) 1954 1955 #define FW_EQ_CTRL_CMD_PHYSEQID_S 0 1956 #define FW_EQ_CTRL_CMD_PHYSEQID_M 0xfffff 1957 #define FW_EQ_CTRL_CMD_PHYSEQID_G(x) \ 1958 (((x) >> FW_EQ_CTRL_CMD_PHYSEQID_S) & FW_EQ_CTRL_CMD_PHYSEQID_M) 1959 1960 #define FW_EQ_CTRL_CMD_FETCHSZM_S 26 1961 #define FW_EQ_CTRL_CMD_FETCHSZM_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHSZM_S) 1962 #define FW_EQ_CTRL_CMD_FETCHSZM_F FW_EQ_CTRL_CMD_FETCHSZM_V(1U) 1963 1964 #define FW_EQ_CTRL_CMD_STATUSPGNS_S 25 1965 #define FW_EQ_CTRL_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_CTRL_CMD_STATUSPGNS_S) 1966 #define FW_EQ_CTRL_CMD_STATUSPGNS_F FW_EQ_CTRL_CMD_STATUSPGNS_V(1U) 1967 1968 #define FW_EQ_CTRL_CMD_STATUSPGRO_S 24 1969 #define FW_EQ_CTRL_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_CTRL_CMD_STATUSPGRO_S) 1970 #define FW_EQ_CTRL_CMD_STATUSPGRO_F FW_EQ_CTRL_CMD_STATUSPGRO_V(1U) 1971 1972 #define FW_EQ_CTRL_CMD_FETCHNS_S 23 1973 #define FW_EQ_CTRL_CMD_FETCHNS_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHNS_S) 1974 #define FW_EQ_CTRL_CMD_FETCHNS_F FW_EQ_CTRL_CMD_FETCHNS_V(1U) 1975 1976 #define FW_EQ_CTRL_CMD_FETCHRO_S 22 1977 #define FW_EQ_CTRL_CMD_FETCHRO_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHRO_S) 1978 #define FW_EQ_CTRL_CMD_FETCHRO_F FW_EQ_CTRL_CMD_FETCHRO_V(1U) 1979 1980 #define FW_EQ_CTRL_CMD_HOSTFCMODE_S 20 1981 #define FW_EQ_CTRL_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_CTRL_CMD_HOSTFCMODE_S) 1982 1983 #define FW_EQ_CTRL_CMD_CPRIO_S 19 1984 #define FW_EQ_CTRL_CMD_CPRIO_V(x) ((x) << FW_EQ_CTRL_CMD_CPRIO_S) 1985 1986 #define FW_EQ_CTRL_CMD_ONCHIP_S 18 1987 #define FW_EQ_CTRL_CMD_ONCHIP_V(x) ((x) << FW_EQ_CTRL_CMD_ONCHIP_S) 1988 1989 #define FW_EQ_CTRL_CMD_PCIECHN_S 16 1990 #define FW_EQ_CTRL_CMD_PCIECHN_V(x) ((x) << FW_EQ_CTRL_CMD_PCIECHN_S) 1991 1992 #define FW_EQ_CTRL_CMD_IQID_S 0 1993 #define FW_EQ_CTRL_CMD_IQID_V(x) ((x) << FW_EQ_CTRL_CMD_IQID_S) 1994 1995 #define FW_EQ_CTRL_CMD_DCAEN_S 31 1996 #define FW_EQ_CTRL_CMD_DCAEN_V(x) ((x) << FW_EQ_CTRL_CMD_DCAEN_S) 1997 1998 #define FW_EQ_CTRL_CMD_DCACPU_S 26 1999 #define FW_EQ_CTRL_CMD_DCACPU_V(x) ((x) << FW_EQ_CTRL_CMD_DCACPU_S) 2000 2001 #define FW_EQ_CTRL_CMD_FBMIN_S 23 2002 #define FW_EQ_CTRL_CMD_FBMIN_V(x) ((x) << FW_EQ_CTRL_CMD_FBMIN_S) 2003 2004 #define FW_EQ_CTRL_CMD_FBMAX_S 20 2005 #define FW_EQ_CTRL_CMD_FBMAX_V(x) ((x) << FW_EQ_CTRL_CMD_FBMAX_S) 2006 2007 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_S 19 2008 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_V(x) \ 2009 ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESHO_S) 2010 2011 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_S 16 2012 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESH_S) 2013 2014 #define FW_EQ_CTRL_CMD_EQSIZE_S 0 2015 #define FW_EQ_CTRL_CMD_EQSIZE_V(x) ((x) << FW_EQ_CTRL_CMD_EQSIZE_S) 2016 2017 struct fw_eq_ofld_cmd { 2018 __be32 op_to_vfn; 2019 __be32 alloc_to_len16; 2020 __be32 eqid_pkd; 2021 __be32 physeqid_pkd; 2022 __be32 fetchszm_to_iqid; 2023 __be32 dcaen_to_eqsize; 2024 __be64 eqaddr; 2025 }; 2026 2027 #define FW_EQ_OFLD_CMD_PFN_S 8 2028 #define FW_EQ_OFLD_CMD_PFN_V(x) ((x) << FW_EQ_OFLD_CMD_PFN_S) 2029 2030 #define FW_EQ_OFLD_CMD_VFN_S 0 2031 #define FW_EQ_OFLD_CMD_VFN_V(x) ((x) << FW_EQ_OFLD_CMD_VFN_S) 2032 2033 #define FW_EQ_OFLD_CMD_ALLOC_S 31 2034 #define FW_EQ_OFLD_CMD_ALLOC_V(x) ((x) << FW_EQ_OFLD_CMD_ALLOC_S) 2035 #define FW_EQ_OFLD_CMD_ALLOC_F FW_EQ_OFLD_CMD_ALLOC_V(1U) 2036 2037 #define FW_EQ_OFLD_CMD_FREE_S 30 2038 #define FW_EQ_OFLD_CMD_FREE_V(x) ((x) << FW_EQ_OFLD_CMD_FREE_S) 2039 #define FW_EQ_OFLD_CMD_FREE_F FW_EQ_OFLD_CMD_FREE_V(1U) 2040 2041 #define FW_EQ_OFLD_CMD_MODIFY_S 29 2042 #define FW_EQ_OFLD_CMD_MODIFY_V(x) ((x) << FW_EQ_OFLD_CMD_MODIFY_S) 2043 #define FW_EQ_OFLD_CMD_MODIFY_F FW_EQ_OFLD_CMD_MODIFY_V(1U) 2044 2045 #define FW_EQ_OFLD_CMD_EQSTART_S 28 2046 #define FW_EQ_OFLD_CMD_EQSTART_V(x) ((x) << FW_EQ_OFLD_CMD_EQSTART_S) 2047 #define FW_EQ_OFLD_CMD_EQSTART_F FW_EQ_OFLD_CMD_EQSTART_V(1U) 2048 2049 #define FW_EQ_OFLD_CMD_EQSTOP_S 27 2050 #define FW_EQ_OFLD_CMD_EQSTOP_V(x) ((x) << FW_EQ_OFLD_CMD_EQSTOP_S) 2051 #define FW_EQ_OFLD_CMD_EQSTOP_F FW_EQ_OFLD_CMD_EQSTOP_V(1U) 2052 2053 #define FW_EQ_OFLD_CMD_EQID_S 0 2054 #define FW_EQ_OFLD_CMD_EQID_M 0xfffff 2055 #define FW_EQ_OFLD_CMD_EQID_V(x) ((x) << FW_EQ_OFLD_CMD_EQID_S) 2056 #define FW_EQ_OFLD_CMD_EQID_G(x) \ 2057 (((x) >> FW_EQ_OFLD_CMD_EQID_S) & FW_EQ_OFLD_CMD_EQID_M) 2058 2059 #define FW_EQ_OFLD_CMD_PHYSEQID_S 0 2060 #define FW_EQ_OFLD_CMD_PHYSEQID_M 0xfffff 2061 #define FW_EQ_OFLD_CMD_PHYSEQID_G(x) \ 2062 (((x) >> FW_EQ_OFLD_CMD_PHYSEQID_S) & FW_EQ_OFLD_CMD_PHYSEQID_M) 2063 2064 #define FW_EQ_OFLD_CMD_FETCHSZM_S 26 2065 #define FW_EQ_OFLD_CMD_FETCHSZM_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHSZM_S) 2066 2067 #define FW_EQ_OFLD_CMD_STATUSPGNS_S 25 2068 #define FW_EQ_OFLD_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_OFLD_CMD_STATUSPGNS_S) 2069 2070 #define FW_EQ_OFLD_CMD_STATUSPGRO_S 24 2071 #define FW_EQ_OFLD_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_OFLD_CMD_STATUSPGRO_S) 2072 2073 #define FW_EQ_OFLD_CMD_FETCHNS_S 23 2074 #define FW_EQ_OFLD_CMD_FETCHNS_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHNS_S) 2075 2076 #define FW_EQ_OFLD_CMD_FETCHRO_S 22 2077 #define FW_EQ_OFLD_CMD_FETCHRO_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHRO_S) 2078 #define FW_EQ_OFLD_CMD_FETCHRO_F FW_EQ_OFLD_CMD_FETCHRO_V(1U) 2079 2080 #define FW_EQ_OFLD_CMD_HOSTFCMODE_S 20 2081 #define FW_EQ_OFLD_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_OFLD_CMD_HOSTFCMODE_S) 2082 2083 #define FW_EQ_OFLD_CMD_CPRIO_S 19 2084 #define FW_EQ_OFLD_CMD_CPRIO_V(x) ((x) << FW_EQ_OFLD_CMD_CPRIO_S) 2085 2086 #define FW_EQ_OFLD_CMD_ONCHIP_S 18 2087 #define FW_EQ_OFLD_CMD_ONCHIP_V(x) ((x) << FW_EQ_OFLD_CMD_ONCHIP_S) 2088 2089 #define FW_EQ_OFLD_CMD_PCIECHN_S 16 2090 #define FW_EQ_OFLD_CMD_PCIECHN_V(x) ((x) << FW_EQ_OFLD_CMD_PCIECHN_S) 2091 2092 #define FW_EQ_OFLD_CMD_IQID_S 0 2093 #define FW_EQ_OFLD_CMD_IQID_V(x) ((x) << FW_EQ_OFLD_CMD_IQID_S) 2094 2095 #define FW_EQ_OFLD_CMD_DCAEN_S 31 2096 #define FW_EQ_OFLD_CMD_DCAEN_V(x) ((x) << FW_EQ_OFLD_CMD_DCAEN_S) 2097 2098 #define FW_EQ_OFLD_CMD_DCACPU_S 26 2099 #define FW_EQ_OFLD_CMD_DCACPU_V(x) ((x) << FW_EQ_OFLD_CMD_DCACPU_S) 2100 2101 #define FW_EQ_OFLD_CMD_FBMIN_S 23 2102 #define FW_EQ_OFLD_CMD_FBMIN_V(x) ((x) << FW_EQ_OFLD_CMD_FBMIN_S) 2103 2104 #define FW_EQ_OFLD_CMD_FBMAX_S 20 2105 #define FW_EQ_OFLD_CMD_FBMAX_V(x) ((x) << FW_EQ_OFLD_CMD_FBMAX_S) 2106 2107 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_S 19 2108 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_V(x) \ 2109 ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESHO_S) 2110 2111 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_S 16 2112 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESH_S) 2113 2114 #define FW_EQ_OFLD_CMD_EQSIZE_S 0 2115 #define FW_EQ_OFLD_CMD_EQSIZE_V(x) ((x) << FW_EQ_OFLD_CMD_EQSIZE_S) 2116 2117 /* 2118 * Macros for VIID parsing: 2119 * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number 2120 */ 2121 2122 #define FW_VIID_PFN_S 8 2123 #define FW_VIID_PFN_M 0x7 2124 #define FW_VIID_PFN_G(x) (((x) >> FW_VIID_PFN_S) & FW_VIID_PFN_M) 2125 2126 #define FW_VIID_VIVLD_S 7 2127 #define FW_VIID_VIVLD_M 0x1 2128 #define FW_VIID_VIVLD_G(x) (((x) >> FW_VIID_VIVLD_S) & FW_VIID_VIVLD_M) 2129 2130 #define FW_VIID_VIN_S 0 2131 #define FW_VIID_VIN_M 0x7F 2132 #define FW_VIID_VIN_G(x) (((x) >> FW_VIID_VIN_S) & FW_VIID_VIN_M) 2133 2134 struct fw_vi_cmd { 2135 __be32 op_to_vfn; 2136 __be32 alloc_to_len16; 2137 __be16 type_viid; 2138 u8 mac[6]; 2139 u8 portid_pkd; 2140 u8 nmac; 2141 u8 nmac0[6]; 2142 __be16 rsssize_pkd; 2143 u8 nmac1[6]; 2144 __be16 idsiiq_pkd; 2145 u8 nmac2[6]; 2146 __be16 idseiq_pkd; 2147 u8 nmac3[6]; 2148 __be64 r9; 2149 __be64 r10; 2150 }; 2151 2152 #define FW_VI_CMD_PFN_S 8 2153 #define FW_VI_CMD_PFN_V(x) ((x) << FW_VI_CMD_PFN_S) 2154 2155 #define FW_VI_CMD_VFN_S 0 2156 #define FW_VI_CMD_VFN_V(x) ((x) << FW_VI_CMD_VFN_S) 2157 2158 #define FW_VI_CMD_ALLOC_S 31 2159 #define FW_VI_CMD_ALLOC_V(x) ((x) << FW_VI_CMD_ALLOC_S) 2160 #define FW_VI_CMD_ALLOC_F FW_VI_CMD_ALLOC_V(1U) 2161 2162 #define FW_VI_CMD_FREE_S 30 2163 #define FW_VI_CMD_FREE_V(x) ((x) << FW_VI_CMD_FREE_S) 2164 #define FW_VI_CMD_FREE_F FW_VI_CMD_FREE_V(1U) 2165 2166 #define FW_VI_CMD_VFVLD_S 24 2167 #define FW_VI_CMD_VFVLD_M 0x1 2168 #define FW_VI_CMD_VFVLD_V(x) ((x) << FW_VI_CMD_VFVLD_S) 2169 #define FW_VI_CMD_VFVLD_G(x) \ 2170 (((x) >> FW_VI_CMD_VFVLD_S) & FW_VI_CMD_VFVLD_M) 2171 #define FW_VI_CMD_VFVLD_F FW_VI_CMD_VFVLD_V(1U) 2172 2173 #define FW_VI_CMD_VIN_S 16 2174 #define FW_VI_CMD_VIN_M 0xff 2175 #define FW_VI_CMD_VIN_V(x) ((x) << FW_VI_CMD_VIN_S) 2176 #define FW_VI_CMD_VIN_G(x) \ 2177 (((x) >> FW_VI_CMD_VIN_S) & FW_VI_CMD_VIN_M) 2178 2179 #define FW_VI_CMD_VIID_S 0 2180 #define FW_VI_CMD_VIID_M 0xfff 2181 #define FW_VI_CMD_VIID_V(x) ((x) << FW_VI_CMD_VIID_S) 2182 #define FW_VI_CMD_VIID_G(x) (((x) >> FW_VI_CMD_VIID_S) & FW_VI_CMD_VIID_M) 2183 2184 #define FW_VI_CMD_PORTID_S 4 2185 #define FW_VI_CMD_PORTID_M 0xf 2186 #define FW_VI_CMD_PORTID_V(x) ((x) << FW_VI_CMD_PORTID_S) 2187 #define FW_VI_CMD_PORTID_G(x) \ 2188 (((x) >> FW_VI_CMD_PORTID_S) & FW_VI_CMD_PORTID_M) 2189 2190 #define FW_VI_CMD_RSSSIZE_S 0 2191 #define FW_VI_CMD_RSSSIZE_M 0x7ff 2192 #define FW_VI_CMD_RSSSIZE_G(x) \ 2193 (((x) >> FW_VI_CMD_RSSSIZE_S) & FW_VI_CMD_RSSSIZE_M) 2194 2195 /* Special VI_MAC command index ids */ 2196 #define FW_VI_MAC_ADD_MAC 0x3FF 2197 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 2198 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD 2199 #define FW_VI_MAC_ID_BASED_FREE 0x3FC 2200 #define FW_CLS_TCAM_NUM_ENTRIES 336 2201 2202 enum fw_vi_mac_smac { 2203 FW_VI_MAC_MPS_TCAM_ENTRY, 2204 FW_VI_MAC_MPS_TCAM_ONLY, 2205 FW_VI_MAC_SMT_ONLY, 2206 FW_VI_MAC_SMT_AND_MPSTCAM 2207 }; 2208 2209 enum fw_vi_mac_result { 2210 FW_VI_MAC_R_SUCCESS, 2211 FW_VI_MAC_R_F_NONEXISTENT_NOMEM, 2212 FW_VI_MAC_R_SMAC_FAIL, 2213 FW_VI_MAC_R_F_ACL_CHECK 2214 }; 2215 2216 enum fw_vi_mac_entry_types { 2217 FW_VI_MAC_TYPE_EXACTMAC, 2218 FW_VI_MAC_TYPE_HASHVEC, 2219 FW_VI_MAC_TYPE_RAW, 2220 FW_VI_MAC_TYPE_EXACTMAC_VNI, 2221 }; 2222 2223 struct fw_vi_mac_cmd { 2224 __be32 op_to_viid; 2225 __be32 freemacs_to_len16; 2226 union fw_vi_mac { 2227 struct fw_vi_mac_exact { 2228 __be16 valid_to_idx; 2229 u8 macaddr[6]; 2230 } exact[7]; 2231 struct fw_vi_mac_hash { 2232 __be64 hashvec; 2233 } hash; 2234 struct fw_vi_mac_raw { 2235 __be32 raw_idx_pkd; 2236 __be32 data0_pkd; 2237 __be32 data1[2]; 2238 __be64 data0m_pkd; 2239 __be32 data1m[2]; 2240 } raw; 2241 struct fw_vi_mac_vni { 2242 __be16 valid_to_idx; 2243 __u8 macaddr[6]; 2244 __be16 r7; 2245 __u8 macaddr_mask[6]; 2246 __be32 lookup_type_to_vni; 2247 __be32 vni_mask_pkd; 2248 } exact_vni[2]; 2249 } u; 2250 }; 2251 2252 #define FW_VI_MAC_CMD_SMTID_S 12 2253 #define FW_VI_MAC_CMD_SMTID_M 0xff 2254 #define FW_VI_MAC_CMD_SMTID_V(x) ((x) << FW_VI_MAC_CMD_SMTID_S) 2255 #define FW_VI_MAC_CMD_SMTID_G(x) \ 2256 (((x) >> FW_VI_MAC_CMD_SMTID_S) & FW_VI_MAC_CMD_SMTID_M) 2257 2258 #define FW_VI_MAC_CMD_VIID_S 0 2259 #define FW_VI_MAC_CMD_VIID_V(x) ((x) << FW_VI_MAC_CMD_VIID_S) 2260 2261 #define FW_VI_MAC_CMD_FREEMACS_S 31 2262 #define FW_VI_MAC_CMD_FREEMACS_V(x) ((x) << FW_VI_MAC_CMD_FREEMACS_S) 2263 2264 #define FW_VI_MAC_CMD_ENTRY_TYPE_S 23 2265 #define FW_VI_MAC_CMD_ENTRY_TYPE_M 0x7 2266 #define FW_VI_MAC_CMD_ENTRY_TYPE_V(x) ((x) << FW_VI_MAC_CMD_ENTRY_TYPE_S) 2267 #define FW_VI_MAC_CMD_ENTRY_TYPE_G(x) \ 2268 (((x) >> FW_VI_MAC_CMD_ENTRY_TYPE_S) & FW_VI_MAC_CMD_ENTRY_TYPE_M) 2269 2270 #define FW_VI_MAC_CMD_HASHVECEN_S 23 2271 #define FW_VI_MAC_CMD_HASHVECEN_V(x) ((x) << FW_VI_MAC_CMD_HASHVECEN_S) 2272 #define FW_VI_MAC_CMD_HASHVECEN_F FW_VI_MAC_CMD_HASHVECEN_V(1U) 2273 2274 #define FW_VI_MAC_CMD_HASHUNIEN_S 22 2275 #define FW_VI_MAC_CMD_HASHUNIEN_V(x) ((x) << FW_VI_MAC_CMD_HASHUNIEN_S) 2276 2277 #define FW_VI_MAC_CMD_VALID_S 15 2278 #define FW_VI_MAC_CMD_VALID_V(x) ((x) << FW_VI_MAC_CMD_VALID_S) 2279 #define FW_VI_MAC_CMD_VALID_F FW_VI_MAC_CMD_VALID_V(1U) 2280 2281 #define FW_VI_MAC_CMD_PRIO_S 12 2282 #define FW_VI_MAC_CMD_PRIO_V(x) ((x) << FW_VI_MAC_CMD_PRIO_S) 2283 2284 #define FW_VI_MAC_CMD_SMAC_RESULT_S 10 2285 #define FW_VI_MAC_CMD_SMAC_RESULT_M 0x3 2286 #define FW_VI_MAC_CMD_SMAC_RESULT_V(x) ((x) << FW_VI_MAC_CMD_SMAC_RESULT_S) 2287 #define FW_VI_MAC_CMD_SMAC_RESULT_G(x) \ 2288 (((x) >> FW_VI_MAC_CMD_SMAC_RESULT_S) & FW_VI_MAC_CMD_SMAC_RESULT_M) 2289 2290 #define FW_VI_MAC_CMD_IDX_S 0 2291 #define FW_VI_MAC_CMD_IDX_M 0x3ff 2292 #define FW_VI_MAC_CMD_IDX_V(x) ((x) << FW_VI_MAC_CMD_IDX_S) 2293 #define FW_VI_MAC_CMD_IDX_G(x) \ 2294 (((x) >> FW_VI_MAC_CMD_IDX_S) & FW_VI_MAC_CMD_IDX_M) 2295 2296 #define FW_VI_MAC_CMD_RAW_IDX_S 16 2297 #define FW_VI_MAC_CMD_RAW_IDX_M 0xffff 2298 #define FW_VI_MAC_CMD_RAW_IDX_V(x) ((x) << FW_VI_MAC_CMD_RAW_IDX_S) 2299 #define FW_VI_MAC_CMD_RAW_IDX_G(x) \ 2300 (((x) >> FW_VI_MAC_CMD_RAW_IDX_S) & FW_VI_MAC_CMD_RAW_IDX_M) 2301 2302 #define FW_VI_MAC_CMD_LOOKUP_TYPE_S 31 2303 #define FW_VI_MAC_CMD_LOOKUP_TYPE_M 0x1 2304 #define FW_VI_MAC_CMD_LOOKUP_TYPE_V(x) ((x) << FW_VI_MAC_CMD_LOOKUP_TYPE_S) 2305 #define FW_VI_MAC_CMD_LOOKUP_TYPE_G(x) \ 2306 (((x) >> FW_VI_MAC_CMD_LOOKUP_TYPE_S) & FW_VI_MAC_CMD_LOOKUP_TYPE_M) 2307 #define FW_VI_MAC_CMD_LOOKUP_TYPE_F FW_VI_MAC_CMD_LOOKUP_TYPE_V(1U) 2308 2309 #define FW_VI_MAC_CMD_DIP_HIT_S 30 2310 #define FW_VI_MAC_CMD_DIP_HIT_M 0x1 2311 #define FW_VI_MAC_CMD_DIP_HIT_V(x) ((x) << FW_VI_MAC_CMD_DIP_HIT_S) 2312 #define FW_VI_MAC_CMD_DIP_HIT_G(x) \ 2313 (((x) >> FW_VI_MAC_CMD_DIP_HIT_S) & FW_VI_MAC_CMD_DIP_HIT_M) 2314 #define FW_VI_MAC_CMD_DIP_HIT_F FW_VI_MAC_CMD_DIP_HIT_V(1U) 2315 2316 #define FW_VI_MAC_CMD_VNI_S 0 2317 #define FW_VI_MAC_CMD_VNI_M 0xffffff 2318 #define FW_VI_MAC_CMD_VNI_V(x) ((x) << FW_VI_MAC_CMD_VNI_S) 2319 #define FW_VI_MAC_CMD_VNI_G(x) \ 2320 (((x) >> FW_VI_MAC_CMD_VNI_S) & FW_VI_MAC_CMD_VNI_M) 2321 2322 #define FW_VI_MAC_CMD_VNI_MASK_S 0 2323 #define FW_VI_MAC_CMD_VNI_MASK_M 0xffffff 2324 #define FW_VI_MAC_CMD_VNI_MASK_V(x) ((x) << FW_VI_MAC_CMD_VNI_MASK_S) 2325 #define FW_VI_MAC_CMD_VNI_MASK_G(x) \ 2326 (((x) >> FW_VI_MAC_CMD_VNI_MASK_S) & FW_VI_MAC_CMD_VNI_MASK_M) 2327 2328 #define FW_RXMODE_MTU_NO_CHG 65535 2329 2330 struct fw_vi_rxmode_cmd { 2331 __be32 op_to_viid; 2332 __be32 retval_len16; 2333 __be32 mtu_to_vlanexen; 2334 __be32 r4_lo; 2335 }; 2336 2337 #define FW_VI_RXMODE_CMD_VIID_S 0 2338 #define FW_VI_RXMODE_CMD_VIID_V(x) ((x) << FW_VI_RXMODE_CMD_VIID_S) 2339 2340 #define FW_VI_RXMODE_CMD_MTU_S 16 2341 #define FW_VI_RXMODE_CMD_MTU_M 0xffff 2342 #define FW_VI_RXMODE_CMD_MTU_V(x) ((x) << FW_VI_RXMODE_CMD_MTU_S) 2343 2344 #define FW_VI_RXMODE_CMD_PROMISCEN_S 14 2345 #define FW_VI_RXMODE_CMD_PROMISCEN_M 0x3 2346 #define FW_VI_RXMODE_CMD_PROMISCEN_V(x) ((x) << FW_VI_RXMODE_CMD_PROMISCEN_S) 2347 2348 #define FW_VI_RXMODE_CMD_ALLMULTIEN_S 12 2349 #define FW_VI_RXMODE_CMD_ALLMULTIEN_M 0x3 2350 #define FW_VI_RXMODE_CMD_ALLMULTIEN_V(x) \ 2351 ((x) << FW_VI_RXMODE_CMD_ALLMULTIEN_S) 2352 2353 #define FW_VI_RXMODE_CMD_BROADCASTEN_S 10 2354 #define FW_VI_RXMODE_CMD_BROADCASTEN_M 0x3 2355 #define FW_VI_RXMODE_CMD_BROADCASTEN_V(x) \ 2356 ((x) << FW_VI_RXMODE_CMD_BROADCASTEN_S) 2357 2358 #define FW_VI_RXMODE_CMD_VLANEXEN_S 8 2359 #define FW_VI_RXMODE_CMD_VLANEXEN_M 0x3 2360 #define FW_VI_RXMODE_CMD_VLANEXEN_V(x) ((x) << FW_VI_RXMODE_CMD_VLANEXEN_S) 2361 2362 struct fw_vi_enable_cmd { 2363 __be32 op_to_viid; 2364 __be32 ien_to_len16; 2365 __be16 blinkdur; 2366 __be16 r3; 2367 __be32 r4; 2368 }; 2369 2370 #define FW_VI_ENABLE_CMD_VIID_S 0 2371 #define FW_VI_ENABLE_CMD_VIID_V(x) ((x) << FW_VI_ENABLE_CMD_VIID_S) 2372 2373 #define FW_VI_ENABLE_CMD_IEN_S 31 2374 #define FW_VI_ENABLE_CMD_IEN_V(x) ((x) << FW_VI_ENABLE_CMD_IEN_S) 2375 2376 #define FW_VI_ENABLE_CMD_EEN_S 30 2377 #define FW_VI_ENABLE_CMD_EEN_V(x) ((x) << FW_VI_ENABLE_CMD_EEN_S) 2378 2379 #define FW_VI_ENABLE_CMD_LED_S 29 2380 #define FW_VI_ENABLE_CMD_LED_V(x) ((x) << FW_VI_ENABLE_CMD_LED_S) 2381 #define FW_VI_ENABLE_CMD_LED_F FW_VI_ENABLE_CMD_LED_V(1U) 2382 2383 #define FW_VI_ENABLE_CMD_DCB_INFO_S 28 2384 #define FW_VI_ENABLE_CMD_DCB_INFO_V(x) ((x) << FW_VI_ENABLE_CMD_DCB_INFO_S) 2385 2386 /* VI VF stats offset definitions */ 2387 #define VI_VF_NUM_STATS 16 2388 enum fw_vi_stats_vf_index { 2389 FW_VI_VF_STAT_TX_BCAST_BYTES_IX, 2390 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, 2391 FW_VI_VF_STAT_TX_MCAST_BYTES_IX, 2392 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, 2393 FW_VI_VF_STAT_TX_UCAST_BYTES_IX, 2394 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, 2395 FW_VI_VF_STAT_TX_DROP_FRAMES_IX, 2396 FW_VI_VF_STAT_TX_OFLD_BYTES_IX, 2397 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, 2398 FW_VI_VF_STAT_RX_BCAST_BYTES_IX, 2399 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, 2400 FW_VI_VF_STAT_RX_MCAST_BYTES_IX, 2401 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, 2402 FW_VI_VF_STAT_RX_UCAST_BYTES_IX, 2403 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, 2404 FW_VI_VF_STAT_RX_ERR_FRAMES_IX 2405 }; 2406 2407 /* VI PF stats offset definitions */ 2408 #define VI_PF_NUM_STATS 17 2409 enum fw_vi_stats_pf_index { 2410 FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 2411 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 2412 FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 2413 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 2414 FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 2415 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 2416 FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 2417 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 2418 FW_VI_PF_STAT_RX_BYTES_IX, 2419 FW_VI_PF_STAT_RX_FRAMES_IX, 2420 FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 2421 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 2422 FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 2423 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 2424 FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 2425 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 2426 FW_VI_PF_STAT_RX_ERR_FRAMES_IX 2427 }; 2428 2429 struct fw_vi_stats_cmd { 2430 __be32 op_to_viid; 2431 __be32 retval_len16; 2432 union fw_vi_stats { 2433 struct fw_vi_stats_ctl { 2434 __be16 nstats_ix; 2435 __be16 r6; 2436 __be32 r7; 2437 __be64 stat0; 2438 __be64 stat1; 2439 __be64 stat2; 2440 __be64 stat3; 2441 __be64 stat4; 2442 __be64 stat5; 2443 } ctl; 2444 struct fw_vi_stats_pf { 2445 __be64 tx_bcast_bytes; 2446 __be64 tx_bcast_frames; 2447 __be64 tx_mcast_bytes; 2448 __be64 tx_mcast_frames; 2449 __be64 tx_ucast_bytes; 2450 __be64 tx_ucast_frames; 2451 __be64 tx_offload_bytes; 2452 __be64 tx_offload_frames; 2453 __be64 rx_pf_bytes; 2454 __be64 rx_pf_frames; 2455 __be64 rx_bcast_bytes; 2456 __be64 rx_bcast_frames; 2457 __be64 rx_mcast_bytes; 2458 __be64 rx_mcast_frames; 2459 __be64 rx_ucast_bytes; 2460 __be64 rx_ucast_frames; 2461 __be64 rx_err_frames; 2462 } pf; 2463 struct fw_vi_stats_vf { 2464 __be64 tx_bcast_bytes; 2465 __be64 tx_bcast_frames; 2466 __be64 tx_mcast_bytes; 2467 __be64 tx_mcast_frames; 2468 __be64 tx_ucast_bytes; 2469 __be64 tx_ucast_frames; 2470 __be64 tx_drop_frames; 2471 __be64 tx_offload_bytes; 2472 __be64 tx_offload_frames; 2473 __be64 rx_bcast_bytes; 2474 __be64 rx_bcast_frames; 2475 __be64 rx_mcast_bytes; 2476 __be64 rx_mcast_frames; 2477 __be64 rx_ucast_bytes; 2478 __be64 rx_ucast_frames; 2479 __be64 rx_err_frames; 2480 } vf; 2481 } u; 2482 }; 2483 2484 #define FW_VI_STATS_CMD_VIID_S 0 2485 #define FW_VI_STATS_CMD_VIID_V(x) ((x) << FW_VI_STATS_CMD_VIID_S) 2486 2487 #define FW_VI_STATS_CMD_NSTATS_S 12 2488 #define FW_VI_STATS_CMD_NSTATS_V(x) ((x) << FW_VI_STATS_CMD_NSTATS_S) 2489 2490 #define FW_VI_STATS_CMD_IX_S 0 2491 #define FW_VI_STATS_CMD_IX_V(x) ((x) << FW_VI_STATS_CMD_IX_S) 2492 2493 struct fw_acl_mac_cmd { 2494 __be32 op_to_vfn; 2495 __be32 en_to_len16; 2496 u8 nmac; 2497 u8 r3[7]; 2498 __be16 r4; 2499 u8 macaddr0[6]; 2500 __be16 r5; 2501 u8 macaddr1[6]; 2502 __be16 r6; 2503 u8 macaddr2[6]; 2504 __be16 r7; 2505 u8 macaddr3[6]; 2506 }; 2507 2508 #define FW_ACL_MAC_CMD_PFN_S 8 2509 #define FW_ACL_MAC_CMD_PFN_V(x) ((x) << FW_ACL_MAC_CMD_PFN_S) 2510 2511 #define FW_ACL_MAC_CMD_VFN_S 0 2512 #define FW_ACL_MAC_CMD_VFN_V(x) ((x) << FW_ACL_MAC_CMD_VFN_S) 2513 2514 #define FW_ACL_MAC_CMD_EN_S 31 2515 #define FW_ACL_MAC_CMD_EN_V(x) ((x) << FW_ACL_MAC_CMD_EN_S) 2516 2517 struct fw_acl_vlan_cmd { 2518 __be32 op_to_vfn; 2519 __be32 en_to_len16; 2520 u8 nvlan; 2521 u8 dropnovlan_fm; 2522 u8 r3_lo[6]; 2523 __be16 vlanid[16]; 2524 }; 2525 2526 #define FW_ACL_VLAN_CMD_PFN_S 8 2527 #define FW_ACL_VLAN_CMD_PFN_V(x) ((x) << FW_ACL_VLAN_CMD_PFN_S) 2528 2529 #define FW_ACL_VLAN_CMD_VFN_S 0 2530 #define FW_ACL_VLAN_CMD_VFN_V(x) ((x) << FW_ACL_VLAN_CMD_VFN_S) 2531 2532 #define FW_ACL_VLAN_CMD_EN_S 31 2533 #define FW_ACL_VLAN_CMD_EN_M 0x1 2534 #define FW_ACL_VLAN_CMD_EN_V(x) ((x) << FW_ACL_VLAN_CMD_EN_S) 2535 #define FW_ACL_VLAN_CMD_EN_G(x) \ 2536 (((x) >> S_FW_ACL_VLAN_CMD_EN_S) & FW_ACL_VLAN_CMD_EN_M) 2537 #define FW_ACL_VLAN_CMD_EN_F FW_ACL_VLAN_CMD_EN_V(1U) 2538 2539 #define FW_ACL_VLAN_CMD_DROPNOVLAN_S 7 2540 #define FW_ACL_VLAN_CMD_DROPNOVLAN_V(x) ((x) << FW_ACL_VLAN_CMD_DROPNOVLAN_S) 2541 #define FW_ACL_VLAN_CMD_DROPNOVLAN_F FW_ACL_VLAN_CMD_DROPNOVLAN_V(1U) 2542 2543 #define FW_ACL_VLAN_CMD_FM_S 6 2544 #define FW_ACL_VLAN_CMD_FM_M 0x1 2545 #define FW_ACL_VLAN_CMD_FM_V(x) ((x) << FW_ACL_VLAN_CMD_FM_S) 2546 #define FW_ACL_VLAN_CMD_FM_G(x) \ 2547 (((x) >> FW_ACL_VLAN_CMD_FM_S) & FW_ACL_VLAN_CMD_FM_M) 2548 #define FW_ACL_VLAN_CMD_FM_F FW_ACL_VLAN_CMD_FM_V(1U) 2549 2550 /* old 16-bit port capabilities bitmap (fw_port_cap16_t) */ 2551 enum fw_port_cap { 2552 FW_PORT_CAP_SPEED_100M = 0x0001, 2553 FW_PORT_CAP_SPEED_1G = 0x0002, 2554 FW_PORT_CAP_SPEED_25G = 0x0004, 2555 FW_PORT_CAP_SPEED_10G = 0x0008, 2556 FW_PORT_CAP_SPEED_40G = 0x0010, 2557 FW_PORT_CAP_SPEED_100G = 0x0020, 2558 FW_PORT_CAP_FC_RX = 0x0040, 2559 FW_PORT_CAP_FC_TX = 0x0080, 2560 FW_PORT_CAP_ANEG = 0x0100, 2561 FW_PORT_CAP_MDIAUTO = 0x0200, 2562 FW_PORT_CAP_MDISTRAIGHT = 0x0400, 2563 FW_PORT_CAP_FEC_RS = 0x0800, 2564 FW_PORT_CAP_FEC_BASER_RS = 0x1000, 2565 FW_PORT_CAP_FORCE_PAUSE = 0x2000, 2566 FW_PORT_CAP_802_3_PAUSE = 0x4000, 2567 FW_PORT_CAP_802_3_ASM_DIR = 0x8000, 2568 }; 2569 2570 #define FW_PORT_CAP_SPEED_S 0 2571 #define FW_PORT_CAP_SPEED_M 0x3f 2572 #define FW_PORT_CAP_SPEED_V(x) ((x) << FW_PORT_CAP_SPEED_S) 2573 #define FW_PORT_CAP_SPEED_G(x) \ 2574 (((x) >> FW_PORT_CAP_SPEED_S) & FW_PORT_CAP_SPEED_M) 2575 2576 enum fw_port_mdi { 2577 FW_PORT_CAP_MDI_UNCHANGED, 2578 FW_PORT_CAP_MDI_AUTO, 2579 FW_PORT_CAP_MDI_F_STRAIGHT, 2580 FW_PORT_CAP_MDI_F_CROSSOVER 2581 }; 2582 2583 #define FW_PORT_CAP_MDI_S 9 2584 #define FW_PORT_CAP_MDI_V(x) ((x) << FW_PORT_CAP_MDI_S) 2585 2586 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */ 2587 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL 2588 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL 2589 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL 2590 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL 2591 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL 2592 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL 2593 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL 2594 #define FW_PORT_CAP32_SPEED_200G 0x00000080UL 2595 #define FW_PORT_CAP32_SPEED_400G 0x00000100UL 2596 #define FW_PORT_CAP32_SPEED_RESERVED1 0x00000200UL 2597 #define FW_PORT_CAP32_SPEED_RESERVED2 0x00000400UL 2598 #define FW_PORT_CAP32_SPEED_RESERVED3 0x00000800UL 2599 #define FW_PORT_CAP32_RESERVED1 0x0000f000UL 2600 #define FW_PORT_CAP32_FC_RX 0x00010000UL 2601 #define FW_PORT_CAP32_FC_TX 0x00020000UL 2602 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL 2603 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL 2604 #define FW_PORT_CAP32_ANEG 0x00100000UL 2605 #define FW_PORT_CAP32_MDIAUTO 0x00200000UL 2606 #define FW_PORT_CAP32_MDISTRAIGHT 0x00400000UL 2607 #define FW_PORT_CAP32_FEC_RS 0x00800000UL 2608 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL 2609 #define FW_PORT_CAP32_FEC_RESERVED1 0x02000000UL 2610 #define FW_PORT_CAP32_FEC_RESERVED2 0x04000000UL 2611 #define FW_PORT_CAP32_FEC_RESERVED3 0x08000000UL 2612 #define FW_PORT_CAP32_FORCE_PAUSE 0x10000000UL 2613 #define FW_PORT_CAP32_RESERVED2 0xe0000000UL 2614 2615 #define FW_PORT_CAP32_SPEED_S 0 2616 #define FW_PORT_CAP32_SPEED_M 0xfff 2617 #define FW_PORT_CAP32_SPEED_V(x) ((x) << FW_PORT_CAP32_SPEED_S) 2618 #define FW_PORT_CAP32_SPEED_G(x) \ 2619 (((x) >> FW_PORT_CAP32_SPEED_S) & FW_PORT_CAP32_SPEED_M) 2620 2621 #define FW_PORT_CAP32_FC_S 16 2622 #define FW_PORT_CAP32_FC_M 0x3 2623 #define FW_PORT_CAP32_FC_V(x) ((x) << FW_PORT_CAP32_FC_S) 2624 #define FW_PORT_CAP32_FC_G(x) \ 2625 (((x) >> FW_PORT_CAP32_FC_S) & FW_PORT_CAP32_FC_M) 2626 2627 #define FW_PORT_CAP32_802_3_S 18 2628 #define FW_PORT_CAP32_802_3_M 0x3 2629 #define FW_PORT_CAP32_802_3_V(x) ((x) << FW_PORT_CAP32_802_3_S) 2630 #define FW_PORT_CAP32_802_3_G(x) \ 2631 (((x) >> FW_PORT_CAP32_802_3_S) & FW_PORT_CAP32_802_3_M) 2632 2633 #define FW_PORT_CAP32_ANEG_S 20 2634 #define FW_PORT_CAP32_ANEG_M 0x1 2635 #define FW_PORT_CAP32_ANEG_V(x) ((x) << FW_PORT_CAP32_ANEG_S) 2636 #define FW_PORT_CAP32_ANEG_G(x) \ 2637 (((x) >> FW_PORT_CAP32_ANEG_S) & FW_PORT_CAP32_ANEG_M) 2638 2639 enum fw_port_mdi32 { 2640 FW_PORT_CAP32_MDI_UNCHANGED, 2641 FW_PORT_CAP32_MDI_AUTO, 2642 FW_PORT_CAP32_MDI_F_STRAIGHT, 2643 FW_PORT_CAP32_MDI_F_CROSSOVER 2644 }; 2645 2646 #define FW_PORT_CAP32_MDI_S 21 2647 #define FW_PORT_CAP32_MDI_M 3 2648 #define FW_PORT_CAP32_MDI_V(x) ((x) << FW_PORT_CAP32_MDI_S) 2649 #define FW_PORT_CAP32_MDI_G(x) \ 2650 (((x) >> FW_PORT_CAP32_MDI_S) & FW_PORT_CAP32_MDI_M) 2651 2652 #define FW_PORT_CAP32_FEC_S 23 2653 #define FW_PORT_CAP32_FEC_M 0x1f 2654 #define FW_PORT_CAP32_FEC_V(x) ((x) << FW_PORT_CAP32_FEC_S) 2655 #define FW_PORT_CAP32_FEC_G(x) \ 2656 (((x) >> FW_PORT_CAP32_FEC_S) & FW_PORT_CAP32_FEC_M) 2657 2658 /* macros to isolate various 32-bit Port Capabilities sub-fields */ 2659 #define CAP32_SPEED(__cap32) \ 2660 (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) & __cap32) 2661 2662 #define CAP32_FEC(__cap32) \ 2663 (FW_PORT_CAP32_FEC_V(FW_PORT_CAP32_FEC_M) & __cap32) 2664 2665 enum fw_port_action { 2666 FW_PORT_ACTION_L1_CFG = 0x0001, 2667 FW_PORT_ACTION_L2_CFG = 0x0002, 2668 FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 2669 FW_PORT_ACTION_L2_PPP_CFG = 0x0004, 2670 FW_PORT_ACTION_L2_DCB_CFG = 0x0005, 2671 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006, 2672 FW_PORT_ACTION_DCB_READ_RECV = 0x0007, 2673 FW_PORT_ACTION_DCB_READ_DET = 0x0008, 2674 FW_PORT_ACTION_L1_CFG32 = 0x0009, 2675 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a, 2676 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, 2677 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, 2678 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, 2679 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, 2680 FW_PORT_ACTION_L1_LPBK = 0x0021, 2681 FW_PORT_ACTION_L1_PMA_LPBK = 0x0022, 2682 FW_PORT_ACTION_L1_PCS_LPBK = 0x0023, 2683 FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024, 2684 FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025, 2685 FW_PORT_ACTION_PHY_RESET = 0x0040, 2686 FW_PORT_ACTION_PMA_RESET = 0x0041, 2687 FW_PORT_ACTION_PCS_RESET = 0x0042, 2688 FW_PORT_ACTION_PHYXS_RESET = 0x0043, 2689 FW_PORT_ACTION_DTEXS_REEST = 0x0044, 2690 FW_PORT_ACTION_AN_RESET = 0x0045 2691 }; 2692 2693 enum fw_port_l2cfg_ctlbf { 2694 FW_PORT_L2_CTLBF_OVLAN0 = 0x01, 2695 FW_PORT_L2_CTLBF_OVLAN1 = 0x02, 2696 FW_PORT_L2_CTLBF_OVLAN2 = 0x04, 2697 FW_PORT_L2_CTLBF_OVLAN3 = 0x08, 2698 FW_PORT_L2_CTLBF_IVLAN = 0x10, 2699 FW_PORT_L2_CTLBF_TXIPG = 0x20 2700 }; 2701 2702 enum fw_port_dcb_versions { 2703 FW_PORT_DCB_VER_UNKNOWN, 2704 FW_PORT_DCB_VER_CEE1D0, 2705 FW_PORT_DCB_VER_CEE1D01, 2706 FW_PORT_DCB_VER_IEEE, 2707 FW_PORT_DCB_VER_AUTO = 7 2708 }; 2709 2710 enum fw_port_dcb_cfg { 2711 FW_PORT_DCB_CFG_PG = 0x01, 2712 FW_PORT_DCB_CFG_PFC = 0x02, 2713 FW_PORT_DCB_CFG_APPL = 0x04 2714 }; 2715 2716 enum fw_port_dcb_cfg_rc { 2717 FW_PORT_DCB_CFG_SUCCESS = 0x0, 2718 FW_PORT_DCB_CFG_ERROR = 0x1 2719 }; 2720 2721 enum fw_port_dcb_type { 2722 FW_PORT_DCB_TYPE_PGID = 0x00, 2723 FW_PORT_DCB_TYPE_PGRATE = 0x01, 2724 FW_PORT_DCB_TYPE_PRIORATE = 0x02, 2725 FW_PORT_DCB_TYPE_PFC = 0x03, 2726 FW_PORT_DCB_TYPE_APP_ID = 0x04, 2727 FW_PORT_DCB_TYPE_CONTROL = 0x05, 2728 }; 2729 2730 enum fw_port_dcb_feature_state { 2731 FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0, 2732 FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1, 2733 FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2, 2734 FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3, 2735 }; 2736 2737 struct fw_port_cmd { 2738 __be32 op_to_portid; 2739 __be32 action_to_len16; 2740 union fw_port { 2741 struct fw_port_l1cfg { 2742 __be32 rcap; 2743 __be32 r; 2744 } l1cfg; 2745 struct fw_port_l2cfg { 2746 __u8 ctlbf; 2747 __u8 ovlan3_to_ivlan0; 2748 __be16 ivlantype; 2749 __be16 txipg_force_pinfo; 2750 __be16 mtu; 2751 __be16 ovlan0mask; 2752 __be16 ovlan0type; 2753 __be16 ovlan1mask; 2754 __be16 ovlan1type; 2755 __be16 ovlan2mask; 2756 __be16 ovlan2type; 2757 __be16 ovlan3mask; 2758 __be16 ovlan3type; 2759 } l2cfg; 2760 struct fw_port_info { 2761 __be32 lstatus_to_modtype; 2762 __be16 pcap; 2763 __be16 acap; 2764 __be16 mtu; 2765 __u8 cbllen; 2766 __u8 auxlinfo; 2767 __u8 dcbxdis_pkd; 2768 __u8 r8_lo; 2769 __be16 lpacap; 2770 __be64 r9; 2771 } info; 2772 struct fw_port_diags { 2773 __u8 diagop; 2774 __u8 r[3]; 2775 __be32 diagval; 2776 } diags; 2777 union fw_port_dcb { 2778 struct fw_port_dcb_pgid { 2779 __u8 type; 2780 __u8 apply_pkd; 2781 __u8 r10_lo[2]; 2782 __be32 pgid; 2783 __be64 r11; 2784 } pgid; 2785 struct fw_port_dcb_pgrate { 2786 __u8 type; 2787 __u8 apply_pkd; 2788 __u8 r10_lo[5]; 2789 __u8 num_tcs_supported; 2790 __u8 pgrate[8]; 2791 __u8 tsa[8]; 2792 } pgrate; 2793 struct fw_port_dcb_priorate { 2794 __u8 type; 2795 __u8 apply_pkd; 2796 __u8 r10_lo[6]; 2797 __u8 strict_priorate[8]; 2798 } priorate; 2799 struct fw_port_dcb_pfc { 2800 __u8 type; 2801 __u8 pfcen; 2802 __u8 r10[5]; 2803 __u8 max_pfc_tcs; 2804 __be64 r11; 2805 } pfc; 2806 struct fw_port_app_priority { 2807 __u8 type; 2808 __u8 r10[2]; 2809 __u8 idx; 2810 __u8 user_prio_map; 2811 __u8 sel_field; 2812 __be16 protocolid; 2813 __be64 r12; 2814 } app_priority; 2815 struct fw_port_dcb_control { 2816 __u8 type; 2817 __u8 all_syncd_pkd; 2818 __be16 dcb_version_to_app_state; 2819 __be32 r11; 2820 __be64 r12; 2821 } control; 2822 } dcb; 2823 struct fw_port_l1cfg32 { 2824 __be32 rcap32; 2825 __be32 r; 2826 } l1cfg32; 2827 struct fw_port_info32 { 2828 __be32 lstatus32_to_cbllen32; 2829 __be32 auxlinfo32_mtu32; 2830 __be32 linkattr32; 2831 __be32 pcaps32; 2832 __be32 acaps32; 2833 __be32 lpacaps32; 2834 } info32; 2835 } u; 2836 }; 2837 2838 #define FW_PORT_CMD_READ_S 22 2839 #define FW_PORT_CMD_READ_V(x) ((x) << FW_PORT_CMD_READ_S) 2840 #define FW_PORT_CMD_READ_F FW_PORT_CMD_READ_V(1U) 2841 2842 #define FW_PORT_CMD_PORTID_S 0 2843 #define FW_PORT_CMD_PORTID_M 0xf 2844 #define FW_PORT_CMD_PORTID_V(x) ((x) << FW_PORT_CMD_PORTID_S) 2845 #define FW_PORT_CMD_PORTID_G(x) \ 2846 (((x) >> FW_PORT_CMD_PORTID_S) & FW_PORT_CMD_PORTID_M) 2847 2848 #define FW_PORT_CMD_ACTION_S 16 2849 #define FW_PORT_CMD_ACTION_M 0xffff 2850 #define FW_PORT_CMD_ACTION_V(x) ((x) << FW_PORT_CMD_ACTION_S) 2851 #define FW_PORT_CMD_ACTION_G(x) \ 2852 (((x) >> FW_PORT_CMD_ACTION_S) & FW_PORT_CMD_ACTION_M) 2853 2854 #define FW_PORT_CMD_OVLAN3_S 7 2855 #define FW_PORT_CMD_OVLAN3_V(x) ((x) << FW_PORT_CMD_OVLAN3_S) 2856 2857 #define FW_PORT_CMD_OVLAN2_S 6 2858 #define FW_PORT_CMD_OVLAN2_V(x) ((x) << FW_PORT_CMD_OVLAN2_S) 2859 2860 #define FW_PORT_CMD_OVLAN1_S 5 2861 #define FW_PORT_CMD_OVLAN1_V(x) ((x) << FW_PORT_CMD_OVLAN1_S) 2862 2863 #define FW_PORT_CMD_OVLAN0_S 4 2864 #define FW_PORT_CMD_OVLAN0_V(x) ((x) << FW_PORT_CMD_OVLAN0_S) 2865 2866 #define FW_PORT_CMD_IVLAN0_S 3 2867 #define FW_PORT_CMD_IVLAN0_V(x) ((x) << FW_PORT_CMD_IVLAN0_S) 2868 2869 #define FW_PORT_CMD_TXIPG_S 3 2870 #define FW_PORT_CMD_TXIPG_V(x) ((x) << FW_PORT_CMD_TXIPG_S) 2871 2872 #define FW_PORT_CMD_LSTATUS_S 31 2873 #define FW_PORT_CMD_LSTATUS_M 0x1 2874 #define FW_PORT_CMD_LSTATUS_V(x) ((x) << FW_PORT_CMD_LSTATUS_S) 2875 #define FW_PORT_CMD_LSTATUS_G(x) \ 2876 (((x) >> FW_PORT_CMD_LSTATUS_S) & FW_PORT_CMD_LSTATUS_M) 2877 #define FW_PORT_CMD_LSTATUS_F FW_PORT_CMD_LSTATUS_V(1U) 2878 2879 #define FW_PORT_CMD_LSPEED_S 24 2880 #define FW_PORT_CMD_LSPEED_M 0x3f 2881 #define FW_PORT_CMD_LSPEED_V(x) ((x) << FW_PORT_CMD_LSPEED_S) 2882 #define FW_PORT_CMD_LSPEED_G(x) \ 2883 (((x) >> FW_PORT_CMD_LSPEED_S) & FW_PORT_CMD_LSPEED_M) 2884 2885 #define FW_PORT_CMD_TXPAUSE_S 23 2886 #define FW_PORT_CMD_TXPAUSE_V(x) ((x) << FW_PORT_CMD_TXPAUSE_S) 2887 #define FW_PORT_CMD_TXPAUSE_F FW_PORT_CMD_TXPAUSE_V(1U) 2888 2889 #define FW_PORT_CMD_RXPAUSE_S 22 2890 #define FW_PORT_CMD_RXPAUSE_V(x) ((x) << FW_PORT_CMD_RXPAUSE_S) 2891 #define FW_PORT_CMD_RXPAUSE_F FW_PORT_CMD_RXPAUSE_V(1U) 2892 2893 #define FW_PORT_CMD_MDIOCAP_S 21 2894 #define FW_PORT_CMD_MDIOCAP_V(x) ((x) << FW_PORT_CMD_MDIOCAP_S) 2895 #define FW_PORT_CMD_MDIOCAP_F FW_PORT_CMD_MDIOCAP_V(1U) 2896 2897 #define FW_PORT_CMD_MDIOADDR_S 16 2898 #define FW_PORT_CMD_MDIOADDR_M 0x1f 2899 #define FW_PORT_CMD_MDIOADDR_G(x) \ 2900 (((x) >> FW_PORT_CMD_MDIOADDR_S) & FW_PORT_CMD_MDIOADDR_M) 2901 2902 #define FW_PORT_CMD_LPTXPAUSE_S 15 2903 #define FW_PORT_CMD_LPTXPAUSE_V(x) ((x) << FW_PORT_CMD_LPTXPAUSE_S) 2904 #define FW_PORT_CMD_LPTXPAUSE_F FW_PORT_CMD_LPTXPAUSE_V(1U) 2905 2906 #define FW_PORT_CMD_LPRXPAUSE_S 14 2907 #define FW_PORT_CMD_LPRXPAUSE_V(x) ((x) << FW_PORT_CMD_LPRXPAUSE_S) 2908 #define FW_PORT_CMD_LPRXPAUSE_F FW_PORT_CMD_LPRXPAUSE_V(1U) 2909 2910 #define FW_PORT_CMD_PTYPE_S 8 2911 #define FW_PORT_CMD_PTYPE_M 0x1f 2912 #define FW_PORT_CMD_PTYPE_G(x) \ 2913 (((x) >> FW_PORT_CMD_PTYPE_S) & FW_PORT_CMD_PTYPE_M) 2914 2915 #define FW_PORT_CMD_LINKDNRC_S 5 2916 #define FW_PORT_CMD_LINKDNRC_M 0x7 2917 #define FW_PORT_CMD_LINKDNRC_G(x) \ 2918 (((x) >> FW_PORT_CMD_LINKDNRC_S) & FW_PORT_CMD_LINKDNRC_M) 2919 2920 #define FW_PORT_CMD_MODTYPE_S 0 2921 #define FW_PORT_CMD_MODTYPE_M 0x1f 2922 #define FW_PORT_CMD_MODTYPE_V(x) ((x) << FW_PORT_CMD_MODTYPE_S) 2923 #define FW_PORT_CMD_MODTYPE_G(x) \ 2924 (((x) >> FW_PORT_CMD_MODTYPE_S) & FW_PORT_CMD_MODTYPE_M) 2925 2926 #define FW_PORT_CMD_DCBXDIS_S 7 2927 #define FW_PORT_CMD_DCBXDIS_V(x) ((x) << FW_PORT_CMD_DCBXDIS_S) 2928 #define FW_PORT_CMD_DCBXDIS_F FW_PORT_CMD_DCBXDIS_V(1U) 2929 2930 #define FW_PORT_CMD_APPLY_S 7 2931 #define FW_PORT_CMD_APPLY_V(x) ((x) << FW_PORT_CMD_APPLY_S) 2932 #define FW_PORT_CMD_APPLY_F FW_PORT_CMD_APPLY_V(1U) 2933 2934 #define FW_PORT_CMD_ALL_SYNCD_S 7 2935 #define FW_PORT_CMD_ALL_SYNCD_V(x) ((x) << FW_PORT_CMD_ALL_SYNCD_S) 2936 #define FW_PORT_CMD_ALL_SYNCD_F FW_PORT_CMD_ALL_SYNCD_V(1U) 2937 2938 #define FW_PORT_CMD_DCB_VERSION_S 12 2939 #define FW_PORT_CMD_DCB_VERSION_M 0x7 2940 #define FW_PORT_CMD_DCB_VERSION_G(x) \ 2941 (((x) >> FW_PORT_CMD_DCB_VERSION_S) & FW_PORT_CMD_DCB_VERSION_M) 2942 2943 #define FW_PORT_CMD_LSTATUS32_S 31 2944 #define FW_PORT_CMD_LSTATUS32_M 0x1 2945 #define FW_PORT_CMD_LSTATUS32_V(x) ((x) << FW_PORT_CMD_LSTATUS32_S) 2946 #define FW_PORT_CMD_LSTATUS32_G(x) \ 2947 (((x) >> FW_PORT_CMD_LSTATUS32_S) & FW_PORT_CMD_LSTATUS32_M) 2948 #define FW_PORT_CMD_LSTATUS32_F FW_PORT_CMD_LSTATUS32_V(1U) 2949 2950 #define FW_PORT_CMD_LINKDNRC32_S 28 2951 #define FW_PORT_CMD_LINKDNRC32_M 0x7 2952 #define FW_PORT_CMD_LINKDNRC32_V(x) ((x) << FW_PORT_CMD_LINKDNRC32_S) 2953 #define FW_PORT_CMD_LINKDNRC32_G(x) \ 2954 (((x) >> FW_PORT_CMD_LINKDNRC32_S) & FW_PORT_CMD_LINKDNRC32_M) 2955 2956 #define FW_PORT_CMD_DCBXDIS32_S 27 2957 #define FW_PORT_CMD_DCBXDIS32_M 0x1 2958 #define FW_PORT_CMD_DCBXDIS32_V(x) ((x) << FW_PORT_CMD_DCBXDIS32_S) 2959 #define FW_PORT_CMD_DCBXDIS32_G(x) \ 2960 (((x) >> FW_PORT_CMD_DCBXDIS32_S) & FW_PORT_CMD_DCBXDIS32_M) 2961 #define FW_PORT_CMD_DCBXDIS32_F FW_PORT_CMD_DCBXDIS32_V(1U) 2962 2963 #define FW_PORT_CMD_MDIOCAP32_S 26 2964 #define FW_PORT_CMD_MDIOCAP32_M 0x1 2965 #define FW_PORT_CMD_MDIOCAP32_V(x) ((x) << FW_PORT_CMD_MDIOCAP32_S) 2966 #define FW_PORT_CMD_MDIOCAP32_G(x) \ 2967 (((x) >> FW_PORT_CMD_MDIOCAP32_S) & FW_PORT_CMD_MDIOCAP32_M) 2968 #define FW_PORT_CMD_MDIOCAP32_F FW_PORT_CMD_MDIOCAP32_V(1U) 2969 2970 #define FW_PORT_CMD_MDIOADDR32_S 21 2971 #define FW_PORT_CMD_MDIOADDR32_M 0x1f 2972 #define FW_PORT_CMD_MDIOADDR32_V(x) ((x) << FW_PORT_CMD_MDIOADDR32_S) 2973 #define FW_PORT_CMD_MDIOADDR32_G(x) \ 2974 (((x) >> FW_PORT_CMD_MDIOADDR32_S) & FW_PORT_CMD_MDIOADDR32_M) 2975 2976 #define FW_PORT_CMD_PORTTYPE32_S 13 2977 #define FW_PORT_CMD_PORTTYPE32_M 0xff 2978 #define FW_PORT_CMD_PORTTYPE32_V(x) ((x) << FW_PORT_CMD_PORTTYPE32_S) 2979 #define FW_PORT_CMD_PORTTYPE32_G(x) \ 2980 (((x) >> FW_PORT_CMD_PORTTYPE32_S) & FW_PORT_CMD_PORTTYPE32_M) 2981 2982 #define FW_PORT_CMD_MODTYPE32_S 8 2983 #define FW_PORT_CMD_MODTYPE32_M 0x1f 2984 #define FW_PORT_CMD_MODTYPE32_V(x) ((x) << FW_PORT_CMD_MODTYPE32_S) 2985 #define FW_PORT_CMD_MODTYPE32_G(x) \ 2986 (((x) >> FW_PORT_CMD_MODTYPE32_S) & FW_PORT_CMD_MODTYPE32_M) 2987 2988 #define FW_PORT_CMD_CBLLEN32_S 0 2989 #define FW_PORT_CMD_CBLLEN32_M 0xff 2990 #define FW_PORT_CMD_CBLLEN32_V(x) ((x) << FW_PORT_CMD_CBLLEN32_S) 2991 #define FW_PORT_CMD_CBLLEN32_G(x) \ 2992 (((x) >> FW_PORT_CMD_CBLLEN32_S) & FW_PORT_CMD_CBLLEN32_M) 2993 2994 #define FW_PORT_CMD_AUXLINFO32_S 24 2995 #define FW_PORT_CMD_AUXLINFO32_M 0xff 2996 #define FW_PORT_CMD_AUXLINFO32_V(x) ((x) << FW_PORT_CMD_AUXLINFO32_S) 2997 #define FW_PORT_CMD_AUXLINFO32_G(x) \ 2998 (((x) >> FW_PORT_CMD_AUXLINFO32_S) & FW_PORT_CMD_AUXLINFO32_M) 2999 3000 #define FW_PORT_AUXLINFO32_KX4_S 2 3001 #define FW_PORT_AUXLINFO32_KX4_M 0x1 3002 #define FW_PORT_AUXLINFO32_KX4_V(x) \ 3003 ((x) << FW_PORT_AUXLINFO32_KX4_S) 3004 #define FW_PORT_AUXLINFO32_KX4_G(x) \ 3005 (((x) >> FW_PORT_AUXLINFO32_KX4_S) & FW_PORT_AUXLINFO32_KX4_M) 3006 #define FW_PORT_AUXLINFO32_KX4_F FW_PORT_AUXLINFO32_KX4_V(1U) 3007 3008 #define FW_PORT_AUXLINFO32_KR_S 1 3009 #define FW_PORT_AUXLINFO32_KR_M 0x1 3010 #define FW_PORT_AUXLINFO32_KR_V(x) \ 3011 ((x) << FW_PORT_AUXLINFO32_KR_S) 3012 #define FW_PORT_AUXLINFO32_KR_G(x) \ 3013 (((x) >> FW_PORT_AUXLINFO32_KR_S) & FW_PORT_AUXLINFO32_KR_M) 3014 #define FW_PORT_AUXLINFO32_KR_F FW_PORT_AUXLINFO32_KR_V(1U) 3015 3016 #define FW_PORT_CMD_MTU32_S 0 3017 #define FW_PORT_CMD_MTU32_M 0xffff 3018 #define FW_PORT_CMD_MTU32_V(x) ((x) << FW_PORT_CMD_MTU32_S) 3019 #define FW_PORT_CMD_MTU32_G(x) \ 3020 (((x) >> FW_PORT_CMD_MTU32_S) & FW_PORT_CMD_MTU32_M) 3021 3022 enum fw_port_type { 3023 FW_PORT_TYPE_FIBER_XFI, 3024 FW_PORT_TYPE_FIBER_XAUI, 3025 FW_PORT_TYPE_BT_SGMII, 3026 FW_PORT_TYPE_BT_XFI, 3027 FW_PORT_TYPE_BT_XAUI, 3028 FW_PORT_TYPE_KX4, 3029 FW_PORT_TYPE_CX4, 3030 FW_PORT_TYPE_KX, 3031 FW_PORT_TYPE_KR, 3032 FW_PORT_TYPE_SFP, 3033 FW_PORT_TYPE_BP_AP, 3034 FW_PORT_TYPE_BP4_AP, 3035 FW_PORT_TYPE_QSFP_10G, 3036 FW_PORT_TYPE_QSA, 3037 FW_PORT_TYPE_QSFP, 3038 FW_PORT_TYPE_BP40_BA, 3039 FW_PORT_TYPE_KR4_100G, 3040 FW_PORT_TYPE_CR4_QSFP, 3041 FW_PORT_TYPE_CR_QSFP, 3042 FW_PORT_TYPE_CR2_QSFP, 3043 FW_PORT_TYPE_SFP28, 3044 FW_PORT_TYPE_KR_SFP28, 3045 FW_PORT_TYPE_KR_XLAUI, 3046 3047 FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_M 3048 }; 3049 3050 enum fw_port_module_type { 3051 FW_PORT_MOD_TYPE_NA, 3052 FW_PORT_MOD_TYPE_LR, 3053 FW_PORT_MOD_TYPE_SR, 3054 FW_PORT_MOD_TYPE_ER, 3055 FW_PORT_MOD_TYPE_TWINAX_PASSIVE, 3056 FW_PORT_MOD_TYPE_TWINAX_ACTIVE, 3057 FW_PORT_MOD_TYPE_LRM, 3058 FW_PORT_MOD_TYPE_ERROR = FW_PORT_CMD_MODTYPE_M - 3, 3059 FW_PORT_MOD_TYPE_UNKNOWN = FW_PORT_CMD_MODTYPE_M - 2, 3060 FW_PORT_MOD_TYPE_NOTSUPPORTED = FW_PORT_CMD_MODTYPE_M - 1, 3061 3062 FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_M 3063 }; 3064 3065 enum fw_port_mod_sub_type { 3066 FW_PORT_MOD_SUB_TYPE_NA, 3067 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1, 3068 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2, 3069 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3, 3070 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4, 3071 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5, 3072 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8, 3073 3074 /* The following will never been in the VPD. They are TWINAX cable 3075 * lengths decoded from SFP+ module i2c PROMs. These should 3076 * almost certainly go somewhere else ... 3077 */ 3078 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9, 3079 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA, 3080 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB, 3081 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC, 3082 }; 3083 3084 enum fw_port_stats_tx_index { 3085 FW_STAT_TX_PORT_BYTES_IX = 0, 3086 FW_STAT_TX_PORT_FRAMES_IX, 3087 FW_STAT_TX_PORT_BCAST_IX, 3088 FW_STAT_TX_PORT_MCAST_IX, 3089 FW_STAT_TX_PORT_UCAST_IX, 3090 FW_STAT_TX_PORT_ERROR_IX, 3091 FW_STAT_TX_PORT_64B_IX, 3092 FW_STAT_TX_PORT_65B_127B_IX, 3093 FW_STAT_TX_PORT_128B_255B_IX, 3094 FW_STAT_TX_PORT_256B_511B_IX, 3095 FW_STAT_TX_PORT_512B_1023B_IX, 3096 FW_STAT_TX_PORT_1024B_1518B_IX, 3097 FW_STAT_TX_PORT_1519B_MAX_IX, 3098 FW_STAT_TX_PORT_DROP_IX, 3099 FW_STAT_TX_PORT_PAUSE_IX, 3100 FW_STAT_TX_PORT_PPP0_IX, 3101 FW_STAT_TX_PORT_PPP1_IX, 3102 FW_STAT_TX_PORT_PPP2_IX, 3103 FW_STAT_TX_PORT_PPP3_IX, 3104 FW_STAT_TX_PORT_PPP4_IX, 3105 FW_STAT_TX_PORT_PPP5_IX, 3106 FW_STAT_TX_PORT_PPP6_IX, 3107 FW_STAT_TX_PORT_PPP7_IX, 3108 FW_NUM_PORT_TX_STATS 3109 }; 3110 3111 enum fw_port_stat_rx_index { 3112 FW_STAT_RX_PORT_BYTES_IX = 0, 3113 FW_STAT_RX_PORT_FRAMES_IX, 3114 FW_STAT_RX_PORT_BCAST_IX, 3115 FW_STAT_RX_PORT_MCAST_IX, 3116 FW_STAT_RX_PORT_UCAST_IX, 3117 FW_STAT_RX_PORT_MTU_ERROR_IX, 3118 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 3119 FW_STAT_RX_PORT_CRC_ERROR_IX, 3120 FW_STAT_RX_PORT_LEN_ERROR_IX, 3121 FW_STAT_RX_PORT_SYM_ERROR_IX, 3122 FW_STAT_RX_PORT_64B_IX, 3123 FW_STAT_RX_PORT_65B_127B_IX, 3124 FW_STAT_RX_PORT_128B_255B_IX, 3125 FW_STAT_RX_PORT_256B_511B_IX, 3126 FW_STAT_RX_PORT_512B_1023B_IX, 3127 FW_STAT_RX_PORT_1024B_1518B_IX, 3128 FW_STAT_RX_PORT_1519B_MAX_IX, 3129 FW_STAT_RX_PORT_PAUSE_IX, 3130 FW_STAT_RX_PORT_PPP0_IX, 3131 FW_STAT_RX_PORT_PPP1_IX, 3132 FW_STAT_RX_PORT_PPP2_IX, 3133 FW_STAT_RX_PORT_PPP3_IX, 3134 FW_STAT_RX_PORT_PPP4_IX, 3135 FW_STAT_RX_PORT_PPP5_IX, 3136 FW_STAT_RX_PORT_PPP6_IX, 3137 FW_STAT_RX_PORT_PPP7_IX, 3138 FW_STAT_RX_PORT_LESS_64B_IX, 3139 FW_STAT_RX_PORT_MAC_ERROR_IX, 3140 FW_NUM_PORT_RX_STATS 3141 }; 3142 3143 /* port stats */ 3144 #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + FW_NUM_PORT_RX_STATS) 3145 3146 struct fw_port_stats_cmd { 3147 __be32 op_to_portid; 3148 __be32 retval_len16; 3149 union fw_port_stats { 3150 struct fw_port_stats_ctl { 3151 u8 nstats_bg_bm; 3152 u8 tx_ix; 3153 __be16 r6; 3154 __be32 r7; 3155 __be64 stat0; 3156 __be64 stat1; 3157 __be64 stat2; 3158 __be64 stat3; 3159 __be64 stat4; 3160 __be64 stat5; 3161 } ctl; 3162 struct fw_port_stats_all { 3163 __be64 tx_bytes; 3164 __be64 tx_frames; 3165 __be64 tx_bcast; 3166 __be64 tx_mcast; 3167 __be64 tx_ucast; 3168 __be64 tx_error; 3169 __be64 tx_64b; 3170 __be64 tx_65b_127b; 3171 __be64 tx_128b_255b; 3172 __be64 tx_256b_511b; 3173 __be64 tx_512b_1023b; 3174 __be64 tx_1024b_1518b; 3175 __be64 tx_1519b_max; 3176 __be64 tx_drop; 3177 __be64 tx_pause; 3178 __be64 tx_ppp0; 3179 __be64 tx_ppp1; 3180 __be64 tx_ppp2; 3181 __be64 tx_ppp3; 3182 __be64 tx_ppp4; 3183 __be64 tx_ppp5; 3184 __be64 tx_ppp6; 3185 __be64 tx_ppp7; 3186 __be64 rx_bytes; 3187 __be64 rx_frames; 3188 __be64 rx_bcast; 3189 __be64 rx_mcast; 3190 __be64 rx_ucast; 3191 __be64 rx_mtu_error; 3192 __be64 rx_mtu_crc_error; 3193 __be64 rx_crc_error; 3194 __be64 rx_len_error; 3195 __be64 rx_sym_error; 3196 __be64 rx_64b; 3197 __be64 rx_65b_127b; 3198 __be64 rx_128b_255b; 3199 __be64 rx_256b_511b; 3200 __be64 rx_512b_1023b; 3201 __be64 rx_1024b_1518b; 3202 __be64 rx_1519b_max; 3203 __be64 rx_pause; 3204 __be64 rx_ppp0; 3205 __be64 rx_ppp1; 3206 __be64 rx_ppp2; 3207 __be64 rx_ppp3; 3208 __be64 rx_ppp4; 3209 __be64 rx_ppp5; 3210 __be64 rx_ppp6; 3211 __be64 rx_ppp7; 3212 __be64 rx_less_64b; 3213 __be64 rx_bg_drop; 3214 __be64 rx_bg_trunc; 3215 } all; 3216 } u; 3217 }; 3218 3219 /* port loopback stats */ 3220 #define FW_NUM_LB_STATS 16 3221 enum fw_port_lb_stats_index { 3222 FW_STAT_LB_PORT_BYTES_IX, 3223 FW_STAT_LB_PORT_FRAMES_IX, 3224 FW_STAT_LB_PORT_BCAST_IX, 3225 FW_STAT_LB_PORT_MCAST_IX, 3226 FW_STAT_LB_PORT_UCAST_IX, 3227 FW_STAT_LB_PORT_ERROR_IX, 3228 FW_STAT_LB_PORT_64B_IX, 3229 FW_STAT_LB_PORT_65B_127B_IX, 3230 FW_STAT_LB_PORT_128B_255B_IX, 3231 FW_STAT_LB_PORT_256B_511B_IX, 3232 FW_STAT_LB_PORT_512B_1023B_IX, 3233 FW_STAT_LB_PORT_1024B_1518B_IX, 3234 FW_STAT_LB_PORT_1519B_MAX_IX, 3235 FW_STAT_LB_PORT_DROP_FRAMES_IX 3236 }; 3237 3238 struct fw_port_lb_stats_cmd { 3239 __be32 op_to_lbport; 3240 __be32 retval_len16; 3241 union fw_port_lb_stats { 3242 struct fw_port_lb_stats_ctl { 3243 u8 nstats_bg_bm; 3244 u8 ix_pkd; 3245 __be16 r6; 3246 __be32 r7; 3247 __be64 stat0; 3248 __be64 stat1; 3249 __be64 stat2; 3250 __be64 stat3; 3251 __be64 stat4; 3252 __be64 stat5; 3253 } ctl; 3254 struct fw_port_lb_stats_all { 3255 __be64 tx_bytes; 3256 __be64 tx_frames; 3257 __be64 tx_bcast; 3258 __be64 tx_mcast; 3259 __be64 tx_ucast; 3260 __be64 tx_error; 3261 __be64 tx_64b; 3262 __be64 tx_65b_127b; 3263 __be64 tx_128b_255b; 3264 __be64 tx_256b_511b; 3265 __be64 tx_512b_1023b; 3266 __be64 tx_1024b_1518b; 3267 __be64 tx_1519b_max; 3268 __be64 rx_lb_drop; 3269 __be64 rx_lb_trunc; 3270 } all; 3271 } u; 3272 }; 3273 3274 enum fw_ptp_subop { 3275 /* none */ 3276 FW_PTP_SC_INIT_TIMER = 0x00, 3277 FW_PTP_SC_TX_TYPE = 0x01, 3278 /* init */ 3279 FW_PTP_SC_RXTIME_STAMP = 0x08, 3280 FW_PTP_SC_RDRX_TYPE = 0x09, 3281 /* ts */ 3282 FW_PTP_SC_ADJ_FREQ = 0x10, 3283 FW_PTP_SC_ADJ_TIME = 0x11, 3284 FW_PTP_SC_ADJ_FTIME = 0x12, 3285 FW_PTP_SC_WALL_CLOCK = 0x13, 3286 FW_PTP_SC_GET_TIME = 0x14, 3287 FW_PTP_SC_SET_TIME = 0x15, 3288 }; 3289 3290 struct fw_ptp_cmd { 3291 __be32 op_to_portid; 3292 __be32 retval_len16; 3293 union fw_ptp { 3294 struct fw_ptp_sc { 3295 __u8 sc; 3296 __u8 r3[7]; 3297 } scmd; 3298 struct fw_ptp_init { 3299 __u8 sc; 3300 __u8 txchan; 3301 __be16 absid; 3302 __be16 mode; 3303 __be16 r3; 3304 } init; 3305 struct fw_ptp_ts { 3306 __u8 sc; 3307 __u8 sign; 3308 __be16 r3; 3309 __be32 ppb; 3310 __be64 tm; 3311 } ts; 3312 } u; 3313 __be64 r3; 3314 }; 3315 3316 #define FW_PTP_CMD_PORTID_S 0 3317 #define FW_PTP_CMD_PORTID_M 0xf 3318 #define FW_PTP_CMD_PORTID_V(x) ((x) << FW_PTP_CMD_PORTID_S) 3319 #define FW_PTP_CMD_PORTID_G(x) \ 3320 (((x) >> FW_PTP_CMD_PORTID_S) & FW_PTP_CMD_PORTID_M) 3321 3322 struct fw_rss_ind_tbl_cmd { 3323 __be32 op_to_viid; 3324 __be32 retval_len16; 3325 __be16 niqid; 3326 __be16 startidx; 3327 __be32 r3; 3328 __be32 iq0_to_iq2; 3329 __be32 iq3_to_iq5; 3330 __be32 iq6_to_iq8; 3331 __be32 iq9_to_iq11; 3332 __be32 iq12_to_iq14; 3333 __be32 iq15_to_iq17; 3334 __be32 iq18_to_iq20; 3335 __be32 iq21_to_iq23; 3336 __be32 iq24_to_iq26; 3337 __be32 iq27_to_iq29; 3338 __be32 iq30_iq31; 3339 __be32 r15_lo; 3340 }; 3341 3342 #define FW_RSS_IND_TBL_CMD_VIID_S 0 3343 #define FW_RSS_IND_TBL_CMD_VIID_V(x) ((x) << FW_RSS_IND_TBL_CMD_VIID_S) 3344 3345 #define FW_RSS_IND_TBL_CMD_IQ0_S 20 3346 #define FW_RSS_IND_TBL_CMD_IQ0_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ0_S) 3347 3348 #define FW_RSS_IND_TBL_CMD_IQ1_S 10 3349 #define FW_RSS_IND_TBL_CMD_IQ1_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ1_S) 3350 3351 #define FW_RSS_IND_TBL_CMD_IQ2_S 0 3352 #define FW_RSS_IND_TBL_CMD_IQ2_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ2_S) 3353 3354 struct fw_rss_glb_config_cmd { 3355 __be32 op_to_write; 3356 __be32 retval_len16; 3357 union fw_rss_glb_config { 3358 struct fw_rss_glb_config_manual { 3359 __be32 mode_pkd; 3360 __be32 r3; 3361 __be64 r4; 3362 __be64 r5; 3363 } manual; 3364 struct fw_rss_glb_config_basicvirtual { 3365 __be32 mode_pkd; 3366 __be32 synmapen_to_hashtoeplitz; 3367 __be64 r8; 3368 __be64 r9; 3369 } basicvirtual; 3370 } u; 3371 }; 3372 3373 #define FW_RSS_GLB_CONFIG_CMD_MODE_S 28 3374 #define FW_RSS_GLB_CONFIG_CMD_MODE_M 0xf 3375 #define FW_RSS_GLB_CONFIG_CMD_MODE_V(x) ((x) << FW_RSS_GLB_CONFIG_CMD_MODE_S) 3376 #define FW_RSS_GLB_CONFIG_CMD_MODE_G(x) \ 3377 (((x) >> FW_RSS_GLB_CONFIG_CMD_MODE_S) & FW_RSS_GLB_CONFIG_CMD_MODE_M) 3378 3379 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 3380 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 3381 3382 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S 8 3383 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(x) \ 3384 ((x) << FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S) 3385 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_F \ 3386 FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(1U) 3387 3388 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S 7 3389 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(x) \ 3390 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S) 3391 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_F \ 3392 FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(1U) 3393 3394 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S 6 3395 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(x) \ 3396 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S) 3397 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_F \ 3398 FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(1U) 3399 3400 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S 5 3401 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(x) \ 3402 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S) 3403 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_F \ 3404 FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(1U) 3405 3406 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S 4 3407 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(x) \ 3408 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S) 3409 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_F \ 3410 FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(1U) 3411 3412 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S 3 3413 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(x) \ 3414 ((x) << FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S) 3415 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_F \ 3416 FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(1U) 3417 3418 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S 2 3419 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(x) \ 3420 ((x) << FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S) 3421 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F \ 3422 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(1U) 3423 3424 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S 1 3425 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(x) \ 3426 ((x) << FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S) 3427 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F \ 3428 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(1U) 3429 3430 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S 0 3431 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(x) \ 3432 ((x) << FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S) 3433 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F \ 3434 FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(1U) 3435 3436 struct fw_rss_vi_config_cmd { 3437 __be32 op_to_viid; 3438 #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0) 3439 __be32 retval_len16; 3440 union fw_rss_vi_config { 3441 struct fw_rss_vi_config_manual { 3442 __be64 r3; 3443 __be64 r4; 3444 __be64 r5; 3445 } manual; 3446 struct fw_rss_vi_config_basicvirtual { 3447 __be32 r6; 3448 __be32 defaultq_to_udpen; 3449 __be64 r9; 3450 __be64 r10; 3451 } basicvirtual; 3452 } u; 3453 }; 3454 3455 #define FW_RSS_VI_CONFIG_CMD_VIID_S 0 3456 #define FW_RSS_VI_CONFIG_CMD_VIID_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_VIID_S) 3457 3458 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S 16 3459 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M 0x3ff 3460 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(x) \ 3461 ((x) << FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) 3462 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_G(x) \ 3463 (((x) >> FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) & \ 3464 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M) 3465 3466 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S 4 3467 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(x) \ 3468 ((x) << FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S) 3469 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F \ 3470 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(1U) 3471 3472 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S 3 3473 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(x) \ 3474 ((x) << FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S) 3475 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F \ 3476 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(1U) 3477 3478 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S 2 3479 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(x) \ 3480 ((x) << FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S) 3481 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F \ 3482 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(1U) 3483 3484 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S 1 3485 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(x) \ 3486 ((x) << FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S) 3487 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F \ 3488 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(1U) 3489 3490 #define FW_RSS_VI_CONFIG_CMD_UDPEN_S 0 3491 #define FW_RSS_VI_CONFIG_CMD_UDPEN_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_UDPEN_S) 3492 #define FW_RSS_VI_CONFIG_CMD_UDPEN_F FW_RSS_VI_CONFIG_CMD_UDPEN_V(1U) 3493 3494 enum fw_sched_sc { 3495 FW_SCHED_SC_PARAMS = 1, 3496 }; 3497 3498 struct fw_sched_cmd { 3499 __be32 op_to_write; 3500 __be32 retval_len16; 3501 union fw_sched { 3502 struct fw_sched_config { 3503 __u8 sc; 3504 __u8 type; 3505 __u8 minmaxen; 3506 __u8 r3[5]; 3507 __u8 nclasses[4]; 3508 __be32 r4; 3509 } config; 3510 struct fw_sched_params { 3511 __u8 sc; 3512 __u8 type; 3513 __u8 level; 3514 __u8 mode; 3515 __u8 unit; 3516 __u8 rate; 3517 __u8 ch; 3518 __u8 cl; 3519 __be32 min; 3520 __be32 max; 3521 __be16 weight; 3522 __be16 pktsize; 3523 __be16 burstsize; 3524 __be16 r4; 3525 } params; 3526 } u; 3527 }; 3528 3529 struct fw_clip_cmd { 3530 __be32 op_to_write; 3531 __be32 alloc_to_len16; 3532 __be64 ip_hi; 3533 __be64 ip_lo; 3534 __be32 r4[2]; 3535 }; 3536 3537 #define FW_CLIP_CMD_ALLOC_S 31 3538 #define FW_CLIP_CMD_ALLOC_V(x) ((x) << FW_CLIP_CMD_ALLOC_S) 3539 #define FW_CLIP_CMD_ALLOC_F FW_CLIP_CMD_ALLOC_V(1U) 3540 3541 #define FW_CLIP_CMD_FREE_S 30 3542 #define FW_CLIP_CMD_FREE_V(x) ((x) << FW_CLIP_CMD_FREE_S) 3543 #define FW_CLIP_CMD_FREE_F FW_CLIP_CMD_FREE_V(1U) 3544 3545 enum fw_error_type { 3546 FW_ERROR_TYPE_EXCEPTION = 0x0, 3547 FW_ERROR_TYPE_HWMODULE = 0x1, 3548 FW_ERROR_TYPE_WR = 0x2, 3549 FW_ERROR_TYPE_ACL = 0x3, 3550 }; 3551 3552 struct fw_error_cmd { 3553 __be32 op_to_type; 3554 __be32 len16_pkd; 3555 union fw_error { 3556 struct fw_error_exception { 3557 __be32 info[6]; 3558 } exception; 3559 struct fw_error_hwmodule { 3560 __be32 regaddr; 3561 __be32 regval; 3562 } hwmodule; 3563 struct fw_error_wr { 3564 __be16 cidx; 3565 __be16 pfn_vfn; 3566 __be32 eqid; 3567 u8 wrhdr[16]; 3568 } wr; 3569 struct fw_error_acl { 3570 __be16 cidx; 3571 __be16 pfn_vfn; 3572 __be32 eqid; 3573 __be16 mv_pkd; 3574 u8 val[6]; 3575 __be64 r4; 3576 } acl; 3577 } u; 3578 }; 3579 3580 struct fw_debug_cmd { 3581 __be32 op_type; 3582 __be32 len16_pkd; 3583 union fw_debug { 3584 struct fw_debug_assert { 3585 __be32 fcid; 3586 __be32 line; 3587 __be32 x; 3588 __be32 y; 3589 u8 filename_0_7[8]; 3590 u8 filename_8_15[8]; 3591 __be64 r3; 3592 } assert; 3593 struct fw_debug_prt { 3594 __be16 dprtstridx; 3595 __be16 r3[3]; 3596 __be32 dprtstrparam0; 3597 __be32 dprtstrparam1; 3598 __be32 dprtstrparam2; 3599 __be32 dprtstrparam3; 3600 } prt; 3601 } u; 3602 }; 3603 3604 #define FW_DEBUG_CMD_TYPE_S 0 3605 #define FW_DEBUG_CMD_TYPE_M 0xff 3606 #define FW_DEBUG_CMD_TYPE_G(x) \ 3607 (((x) >> FW_DEBUG_CMD_TYPE_S) & FW_DEBUG_CMD_TYPE_M) 3608 3609 struct fw_hma_cmd { 3610 __be32 op_pkd; 3611 __be32 retval_len16; 3612 __be32 mode_to_pcie_params; 3613 __be32 naddr_size; 3614 __be32 addr_size_pkd; 3615 __be32 r6; 3616 __be64 phy_address[5]; 3617 }; 3618 3619 #define FW_HMA_CMD_MODE_S 31 3620 #define FW_HMA_CMD_MODE_M 0x1 3621 #define FW_HMA_CMD_MODE_V(x) ((x) << FW_HMA_CMD_MODE_S) 3622 #define FW_HMA_CMD_MODE_G(x) \ 3623 (((x) >> FW_HMA_CMD_MODE_S) & FW_HMA_CMD_MODE_M) 3624 #define FW_HMA_CMD_MODE_F FW_HMA_CMD_MODE_V(1U) 3625 3626 #define FW_HMA_CMD_SOC_S 30 3627 #define FW_HMA_CMD_SOC_M 0x1 3628 #define FW_HMA_CMD_SOC_V(x) ((x) << FW_HMA_CMD_SOC_S) 3629 #define FW_HMA_CMD_SOC_G(x) (((x) >> FW_HMA_CMD_SOC_S) & FW_HMA_CMD_SOC_M) 3630 #define FW_HMA_CMD_SOC_F FW_HMA_CMD_SOC_V(1U) 3631 3632 #define FW_HMA_CMD_EOC_S 29 3633 #define FW_HMA_CMD_EOC_M 0x1 3634 #define FW_HMA_CMD_EOC_V(x) ((x) << FW_HMA_CMD_EOC_S) 3635 #define FW_HMA_CMD_EOC_G(x) (((x) >> FW_HMA_CMD_EOC_S) & FW_HMA_CMD_EOC_M) 3636 #define FW_HMA_CMD_EOC_F FW_HMA_CMD_EOC_V(1U) 3637 3638 #define FW_HMA_CMD_PCIE_PARAMS_S 0 3639 #define FW_HMA_CMD_PCIE_PARAMS_M 0x7ffffff 3640 #define FW_HMA_CMD_PCIE_PARAMS_V(x) ((x) << FW_HMA_CMD_PCIE_PARAMS_S) 3641 #define FW_HMA_CMD_PCIE_PARAMS_G(x) \ 3642 (((x) >> FW_HMA_CMD_PCIE_PARAMS_S) & FW_HMA_CMD_PCIE_PARAMS_M) 3643 3644 #define FW_HMA_CMD_NADDR_S 12 3645 #define FW_HMA_CMD_NADDR_M 0x3f 3646 #define FW_HMA_CMD_NADDR_V(x) ((x) << FW_HMA_CMD_NADDR_S) 3647 #define FW_HMA_CMD_NADDR_G(x) \ 3648 (((x) >> FW_HMA_CMD_NADDR_S) & FW_HMA_CMD_NADDR_M) 3649 3650 #define FW_HMA_CMD_SIZE_S 0 3651 #define FW_HMA_CMD_SIZE_M 0xfff 3652 #define FW_HMA_CMD_SIZE_V(x) ((x) << FW_HMA_CMD_SIZE_S) 3653 #define FW_HMA_CMD_SIZE_G(x) \ 3654 (((x) >> FW_HMA_CMD_SIZE_S) & FW_HMA_CMD_SIZE_M) 3655 3656 #define FW_HMA_CMD_ADDR_SIZE_S 11 3657 #define FW_HMA_CMD_ADDR_SIZE_M 0x1fffff 3658 #define FW_HMA_CMD_ADDR_SIZE_V(x) ((x) << FW_HMA_CMD_ADDR_SIZE_S) 3659 #define FW_HMA_CMD_ADDR_SIZE_G(x) \ 3660 (((x) >> FW_HMA_CMD_ADDR_SIZE_S) & FW_HMA_CMD_ADDR_SIZE_M) 3661 3662 enum pcie_fw_eval { 3663 PCIE_FW_EVAL_CRASH = 0, 3664 }; 3665 3666 #define PCIE_FW_ERR_S 31 3667 #define PCIE_FW_ERR_V(x) ((x) << PCIE_FW_ERR_S) 3668 #define PCIE_FW_ERR_F PCIE_FW_ERR_V(1U) 3669 3670 #define PCIE_FW_INIT_S 30 3671 #define PCIE_FW_INIT_V(x) ((x) << PCIE_FW_INIT_S) 3672 #define PCIE_FW_INIT_F PCIE_FW_INIT_V(1U) 3673 3674 #define PCIE_FW_HALT_S 29 3675 #define PCIE_FW_HALT_V(x) ((x) << PCIE_FW_HALT_S) 3676 #define PCIE_FW_HALT_F PCIE_FW_HALT_V(1U) 3677 3678 #define PCIE_FW_EVAL_S 24 3679 #define PCIE_FW_EVAL_M 0x7 3680 #define PCIE_FW_EVAL_G(x) (((x) >> PCIE_FW_EVAL_S) & PCIE_FW_EVAL_M) 3681 3682 #define PCIE_FW_MASTER_VLD_S 15 3683 #define PCIE_FW_MASTER_VLD_V(x) ((x) << PCIE_FW_MASTER_VLD_S) 3684 #define PCIE_FW_MASTER_VLD_F PCIE_FW_MASTER_VLD_V(1U) 3685 3686 #define PCIE_FW_MASTER_S 12 3687 #define PCIE_FW_MASTER_M 0x7 3688 #define PCIE_FW_MASTER_V(x) ((x) << PCIE_FW_MASTER_S) 3689 #define PCIE_FW_MASTER_G(x) (((x) >> PCIE_FW_MASTER_S) & PCIE_FW_MASTER_M) 3690 3691 struct fw_hdr { 3692 u8 ver; 3693 u8 chip; /* terminator chip type */ 3694 __be16 len512; /* bin length in units of 512-bytes */ 3695 __be32 fw_ver; /* firmware version */ 3696 __be32 tp_microcode_ver; 3697 u8 intfver_nic; 3698 u8 intfver_vnic; 3699 u8 intfver_ofld; 3700 u8 intfver_ri; 3701 u8 intfver_iscsipdu; 3702 u8 intfver_iscsi; 3703 u8 intfver_fcoepdu; 3704 u8 intfver_fcoe; 3705 __u32 reserved2; 3706 __u32 reserved3; 3707 __u32 reserved4; 3708 __be32 flags; 3709 __be32 reserved6[23]; 3710 }; 3711 3712 enum fw_hdr_chip { 3713 FW_HDR_CHIP_T4, 3714 FW_HDR_CHIP_T5, 3715 FW_HDR_CHIP_T6 3716 }; 3717 3718 #define FW_HDR_FW_VER_MAJOR_S 24 3719 #define FW_HDR_FW_VER_MAJOR_M 0xff 3720 #define FW_HDR_FW_VER_MAJOR_V(x) \ 3721 ((x) << FW_HDR_FW_VER_MAJOR_S) 3722 #define FW_HDR_FW_VER_MAJOR_G(x) \ 3723 (((x) >> FW_HDR_FW_VER_MAJOR_S) & FW_HDR_FW_VER_MAJOR_M) 3724 3725 #define FW_HDR_FW_VER_MINOR_S 16 3726 #define FW_HDR_FW_VER_MINOR_M 0xff 3727 #define FW_HDR_FW_VER_MINOR_V(x) \ 3728 ((x) << FW_HDR_FW_VER_MINOR_S) 3729 #define FW_HDR_FW_VER_MINOR_G(x) \ 3730 (((x) >> FW_HDR_FW_VER_MINOR_S) & FW_HDR_FW_VER_MINOR_M) 3731 3732 #define FW_HDR_FW_VER_MICRO_S 8 3733 #define FW_HDR_FW_VER_MICRO_M 0xff 3734 #define FW_HDR_FW_VER_MICRO_V(x) \ 3735 ((x) << FW_HDR_FW_VER_MICRO_S) 3736 #define FW_HDR_FW_VER_MICRO_G(x) \ 3737 (((x) >> FW_HDR_FW_VER_MICRO_S) & FW_HDR_FW_VER_MICRO_M) 3738 3739 #define FW_HDR_FW_VER_BUILD_S 0 3740 #define FW_HDR_FW_VER_BUILD_M 0xff 3741 #define FW_HDR_FW_VER_BUILD_V(x) \ 3742 ((x) << FW_HDR_FW_VER_BUILD_S) 3743 #define FW_HDR_FW_VER_BUILD_G(x) \ 3744 (((x) >> FW_HDR_FW_VER_BUILD_S) & FW_HDR_FW_VER_BUILD_M) 3745 3746 enum fw_hdr_intfver { 3747 FW_HDR_INTFVER_NIC = 0x00, 3748 FW_HDR_INTFVER_VNIC = 0x00, 3749 FW_HDR_INTFVER_OFLD = 0x00, 3750 FW_HDR_INTFVER_RI = 0x00, 3751 FW_HDR_INTFVER_ISCSIPDU = 0x00, 3752 FW_HDR_INTFVER_ISCSI = 0x00, 3753 FW_HDR_INTFVER_FCOEPDU = 0x00, 3754 FW_HDR_INTFVER_FCOE = 0x00, 3755 }; 3756 3757 enum fw_hdr_flags { 3758 FW_HDR_FLAGS_RESET_HALT = 0x00000001, 3759 }; 3760 3761 /* length of the formatting string */ 3762 #define FW_DEVLOG_FMT_LEN 192 3763 3764 /* maximum number of the formatting string parameters */ 3765 #define FW_DEVLOG_FMT_PARAMS_NUM 8 3766 3767 /* priority levels */ 3768 enum fw_devlog_level { 3769 FW_DEVLOG_LEVEL_EMERG = 0x0, 3770 FW_DEVLOG_LEVEL_CRIT = 0x1, 3771 FW_DEVLOG_LEVEL_ERR = 0x2, 3772 FW_DEVLOG_LEVEL_NOTICE = 0x3, 3773 FW_DEVLOG_LEVEL_INFO = 0x4, 3774 FW_DEVLOG_LEVEL_DEBUG = 0x5, 3775 FW_DEVLOG_LEVEL_MAX = 0x5, 3776 }; 3777 3778 /* facilities that may send a log message */ 3779 enum fw_devlog_facility { 3780 FW_DEVLOG_FACILITY_CORE = 0x00, 3781 FW_DEVLOG_FACILITY_CF = 0x01, 3782 FW_DEVLOG_FACILITY_SCHED = 0x02, 3783 FW_DEVLOG_FACILITY_TIMER = 0x04, 3784 FW_DEVLOG_FACILITY_RES = 0x06, 3785 FW_DEVLOG_FACILITY_HW = 0x08, 3786 FW_DEVLOG_FACILITY_FLR = 0x10, 3787 FW_DEVLOG_FACILITY_DMAQ = 0x12, 3788 FW_DEVLOG_FACILITY_PHY = 0x14, 3789 FW_DEVLOG_FACILITY_MAC = 0x16, 3790 FW_DEVLOG_FACILITY_PORT = 0x18, 3791 FW_DEVLOG_FACILITY_VI = 0x1A, 3792 FW_DEVLOG_FACILITY_FILTER = 0x1C, 3793 FW_DEVLOG_FACILITY_ACL = 0x1E, 3794 FW_DEVLOG_FACILITY_TM = 0x20, 3795 FW_DEVLOG_FACILITY_QFC = 0x22, 3796 FW_DEVLOG_FACILITY_DCB = 0x24, 3797 FW_DEVLOG_FACILITY_ETH = 0x26, 3798 FW_DEVLOG_FACILITY_OFLD = 0x28, 3799 FW_DEVLOG_FACILITY_RI = 0x2A, 3800 FW_DEVLOG_FACILITY_ISCSI = 0x2C, 3801 FW_DEVLOG_FACILITY_FCOE = 0x2E, 3802 FW_DEVLOG_FACILITY_FOISCSI = 0x30, 3803 FW_DEVLOG_FACILITY_FOFCOE = 0x32, 3804 FW_DEVLOG_FACILITY_CHNET = 0x34, 3805 FW_DEVLOG_FACILITY_MAX = 0x34, 3806 }; 3807 3808 /* log message format */ 3809 struct fw_devlog_e { 3810 __be64 timestamp; 3811 __be32 seqno; 3812 __be16 reserved1; 3813 __u8 level; 3814 __u8 facility; 3815 __u8 fmt[FW_DEVLOG_FMT_LEN]; 3816 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM]; 3817 __be32 reserved3[4]; 3818 }; 3819 3820 struct fw_devlog_cmd { 3821 __be32 op_to_write; 3822 __be32 retval_len16; 3823 __u8 level; 3824 __u8 r2[7]; 3825 __be32 memtype_devlog_memaddr16_devlog; 3826 __be32 memsize_devlog; 3827 __be32 r3[2]; 3828 }; 3829 3830 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S 28 3831 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M 0xf 3832 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(x) \ 3833 (((x) >> FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S) & \ 3834 FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M) 3835 3836 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S 0 3837 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M 0xfffffff 3838 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(x) \ 3839 (((x) >> FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S) & \ 3840 FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M) 3841 3842 /* P C I E F W P F 7 R E G I S T E R */ 3843 3844 /* PF7 stores the Firmware Device Log parameters which allows Host Drivers to 3845 * access the "devlog" which needing to contact firmware. The encoding is 3846 * mostly the same as that returned by the DEVLOG command except for the size 3847 * which is encoded as the number of entries in multiples-1 of 128 here rather 3848 * than the memory size as is done in the DEVLOG command. Thus, 0 means 128 3849 * and 15 means 2048. This of course in turn constrains the allowed values 3850 * for the devlog size ... 3851 */ 3852 #define PCIE_FW_PF_DEVLOG 7 3853 3854 #define PCIE_FW_PF_DEVLOG_NENTRIES128_S 28 3855 #define PCIE_FW_PF_DEVLOG_NENTRIES128_M 0xf 3856 #define PCIE_FW_PF_DEVLOG_NENTRIES128_V(x) \ 3857 ((x) << PCIE_FW_PF_DEVLOG_NENTRIES128_S) 3858 #define PCIE_FW_PF_DEVLOG_NENTRIES128_G(x) \ 3859 (((x) >> PCIE_FW_PF_DEVLOG_NENTRIES128_S) & \ 3860 PCIE_FW_PF_DEVLOG_NENTRIES128_M) 3861 3862 #define PCIE_FW_PF_DEVLOG_ADDR16_S 4 3863 #define PCIE_FW_PF_DEVLOG_ADDR16_M 0xffffff 3864 #define PCIE_FW_PF_DEVLOG_ADDR16_V(x) ((x) << PCIE_FW_PF_DEVLOG_ADDR16_S) 3865 #define PCIE_FW_PF_DEVLOG_ADDR16_G(x) \ 3866 (((x) >> PCIE_FW_PF_DEVLOG_ADDR16_S) & PCIE_FW_PF_DEVLOG_ADDR16_M) 3867 3868 #define PCIE_FW_PF_DEVLOG_MEMTYPE_S 0 3869 #define PCIE_FW_PF_DEVLOG_MEMTYPE_M 0xf 3870 #define PCIE_FW_PF_DEVLOG_MEMTYPE_V(x) ((x) << PCIE_FW_PF_DEVLOG_MEMTYPE_S) 3871 #define PCIE_FW_PF_DEVLOG_MEMTYPE_G(x) \ 3872 (((x) >> PCIE_FW_PF_DEVLOG_MEMTYPE_S) & PCIE_FW_PF_DEVLOG_MEMTYPE_M) 3873 3874 #define MAX_IMM_OFLD_TX_DATA_WR_LEN (0xff + sizeof(struct fw_ofld_tx_data_wr)) 3875 3876 struct fw_crypto_lookaside_wr { 3877 __be32 op_to_cctx_size; 3878 __be32 len16_pkd; 3879 __be32 session_id; 3880 __be32 rx_chid_to_rx_q_id; 3881 __be32 key_addr; 3882 __be32 pld_size_hash_size; 3883 __be64 cookie; 3884 }; 3885 3886 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_S 24 3887 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_M 0xff 3888 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_V(x) \ 3889 ((x) << FW_CRYPTO_LOOKASIDE_WR_OPCODE_S) 3890 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_G(x) \ 3891 (((x) >> FW_CRYPTO_LOOKASIDE_WR_OPCODE_S) & \ 3892 FW_CRYPTO_LOOKASIDE_WR_OPCODE_M) 3893 3894 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_S 23 3895 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_M 0x1 3896 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_V(x) \ 3897 ((x) << FW_CRYPTO_LOOKASIDE_WR_COMPL_S) 3898 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_G(x) \ 3899 (((x) >> FW_CRYPTO_LOOKASIDE_WR_COMPL_S) & \ 3900 FW_CRYPTO_LOOKASIDE_WR_COMPL_M) 3901 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_F FW_CRYPTO_LOOKASIDE_WR_COMPL_V(1U) 3902 3903 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S 15 3904 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M 0xff 3905 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_V(x) \ 3906 ((x) << FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S) 3907 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_G(x) \ 3908 (((x) >> FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S) & \ 3909 FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M) 3910 3911 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S 5 3912 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M 0x3 3913 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_V(x) \ 3914 ((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S) 3915 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_G(x) \ 3916 (((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S) & \ 3917 FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M) 3918 3919 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S 0 3920 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M 0x1f 3921 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_V(x) \ 3922 ((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S) 3923 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_G(x) \ 3924 (((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S) & \ 3925 FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M) 3926 3927 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_S 0 3928 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_M 0xff 3929 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_V(x) \ 3930 ((x) << FW_CRYPTO_LOOKASIDE_WR_LEN16_S) 3931 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_G(x) \ 3932 (((x) >> FW_CRYPTO_LOOKASIDE_WR_LEN16_S) & \ 3933 FW_CRYPTO_LOOKASIDE_WR_LEN16_M) 3934 3935 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S 29 3936 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M 0x3 3937 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_V(x) \ 3938 ((x) << FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S) 3939 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_G(x) \ 3940 (((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S) & \ 3941 FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M) 3942 3943 #define FW_CRYPTO_LOOKASIDE_WR_LCB_S 27 3944 #define FW_CRYPTO_LOOKASIDE_WR_LCB_M 0x3 3945 #define FW_CRYPTO_LOOKASIDE_WR_LCB_V(x) \ 3946 ((x) << FW_CRYPTO_LOOKASIDE_WR_LCB_S) 3947 #define FW_CRYPTO_LOOKASIDE_WR_LCB_G(x) \ 3948 (((x) >> FW_CRYPTO_LOOKASIDE_WR_LCB_S) & FW_CRYPTO_LOOKASIDE_WR_LCB_M) 3949 3950 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_S 25 3951 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_M 0x3 3952 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_V(x) \ 3953 ((x) << FW_CRYPTO_LOOKASIDE_WR_PHASH_S) 3954 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_G(x) \ 3955 (((x) >> FW_CRYPTO_LOOKASIDE_WR_PHASH_S) & \ 3956 FW_CRYPTO_LOOKASIDE_WR_PHASH_M) 3957 3958 #define FW_CRYPTO_LOOKASIDE_WR_IV_S 23 3959 #define FW_CRYPTO_LOOKASIDE_WR_IV_M 0x3 3960 #define FW_CRYPTO_LOOKASIDE_WR_IV_V(x) \ 3961 ((x) << FW_CRYPTO_LOOKASIDE_WR_IV_S) 3962 #define FW_CRYPTO_LOOKASIDE_WR_IV_G(x) \ 3963 (((x) >> FW_CRYPTO_LOOKASIDE_WR_IV_S) & FW_CRYPTO_LOOKASIDE_WR_IV_M) 3964 3965 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_S 15 3966 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_M 0xff 3967 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_V(x) \ 3968 ((x) << FW_CRYPTO_LOOKASIDE_WR_FQIDX_S) 3969 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_G(x) \ 3970 (((x) >> FW_CRYPTO_LOOKASIDE_WR_FQIDX_S) & \ 3971 FW_CRYPTO_LOOKASIDE_WR_FQIDX_M) 3972 3973 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_S 10 3974 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_M 0x3 3975 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_V(x) \ 3976 ((x) << FW_CRYPTO_LOOKASIDE_WR_TX_CH_S) 3977 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_G(x) \ 3978 (((x) >> FW_CRYPTO_LOOKASIDE_WR_TX_CH_S) & \ 3979 FW_CRYPTO_LOOKASIDE_WR_TX_CH_M) 3980 3981 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S 0 3982 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M 0x3ff 3983 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_V(x) \ 3984 ((x) << FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S) 3985 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_G(x) \ 3986 (((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S) & \ 3987 FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M) 3988 3989 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S 24 3990 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M 0xff 3991 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_V(x) \ 3992 ((x) << FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S) 3993 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_G(x) \ 3994 (((x) >> FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S) & \ 3995 FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M) 3996 3997 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S 17 3998 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M 0x7f 3999 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_V(x) \ 4000 ((x) << FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S) 4001 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_G(x) \ 4002 (((x) >> FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S) & \ 4003 FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M) 4004 4005 struct fw_tlstx_data_wr { 4006 __be32 op_to_immdlen; 4007 __be32 flowid_len16; 4008 __be32 plen; 4009 __be32 lsodisable_to_flags; 4010 __be32 r5; 4011 __be32 ctxloc_to_exp; 4012 __be16 mfs; 4013 __be16 adjustedplen_pkd; 4014 __be16 expinplenmax_pkd; 4015 u8 pdusinplenmax_pkd; 4016 u8 r10; 4017 }; 4018 4019 #define FW_TLSTX_DATA_WR_OPCODE_S 24 4020 #define FW_TLSTX_DATA_WR_OPCODE_M 0xff 4021 #define FW_TLSTX_DATA_WR_OPCODE_V(x) ((x) << FW_TLSTX_DATA_WR_OPCODE_S) 4022 #define FW_TLSTX_DATA_WR_OPCODE_G(x) \ 4023 (((x) >> FW_TLSTX_DATA_WR_OPCODE_S) & FW_TLSTX_DATA_WR_OPCODE_M) 4024 4025 #define FW_TLSTX_DATA_WR_COMPL_S 21 4026 #define FW_TLSTX_DATA_WR_COMPL_M 0x1 4027 #define FW_TLSTX_DATA_WR_COMPL_V(x) ((x) << FW_TLSTX_DATA_WR_COMPL_S) 4028 #define FW_TLSTX_DATA_WR_COMPL_G(x) \ 4029 (((x) >> FW_TLSTX_DATA_WR_COMPL_S) & FW_TLSTX_DATA_WR_COMPL_M) 4030 #define FW_TLSTX_DATA_WR_COMPL_F FW_TLSTX_DATA_WR_COMPL_V(1U) 4031 4032 #define FW_TLSTX_DATA_WR_IMMDLEN_S 0 4033 #define FW_TLSTX_DATA_WR_IMMDLEN_M 0xff 4034 #define FW_TLSTX_DATA_WR_IMMDLEN_V(x) ((x) << FW_TLSTX_DATA_WR_IMMDLEN_S) 4035 #define FW_TLSTX_DATA_WR_IMMDLEN_G(x) \ 4036 (((x) >> FW_TLSTX_DATA_WR_IMMDLEN_S) & FW_TLSTX_DATA_WR_IMMDLEN_M) 4037 4038 #define FW_TLSTX_DATA_WR_FLOWID_S 8 4039 #define FW_TLSTX_DATA_WR_FLOWID_M 0xfffff 4040 #define FW_TLSTX_DATA_WR_FLOWID_V(x) ((x) << FW_TLSTX_DATA_WR_FLOWID_S) 4041 #define FW_TLSTX_DATA_WR_FLOWID_G(x) \ 4042 (((x) >> FW_TLSTX_DATA_WR_FLOWID_S) & FW_TLSTX_DATA_WR_FLOWID_M) 4043 4044 #define FW_TLSTX_DATA_WR_LEN16_S 0 4045 #define FW_TLSTX_DATA_WR_LEN16_M 0xff 4046 #define FW_TLSTX_DATA_WR_LEN16_V(x) ((x) << FW_TLSTX_DATA_WR_LEN16_S) 4047 #define FW_TLSTX_DATA_WR_LEN16_G(x) \ 4048 (((x) >> FW_TLSTX_DATA_WR_LEN16_S) & FW_TLSTX_DATA_WR_LEN16_M) 4049 4050 #define FW_TLSTX_DATA_WR_LSODISABLE_S 31 4051 #define FW_TLSTX_DATA_WR_LSODISABLE_M 0x1 4052 #define FW_TLSTX_DATA_WR_LSODISABLE_V(x) \ 4053 ((x) << FW_TLSTX_DATA_WR_LSODISABLE_S) 4054 #define FW_TLSTX_DATA_WR_LSODISABLE_G(x) \ 4055 (((x) >> FW_TLSTX_DATA_WR_LSODISABLE_S) & FW_TLSTX_DATA_WR_LSODISABLE_M) 4056 #define FW_TLSTX_DATA_WR_LSODISABLE_F FW_TLSTX_DATA_WR_LSODISABLE_V(1U) 4057 4058 #define FW_TLSTX_DATA_WR_ALIGNPLD_S 30 4059 #define FW_TLSTX_DATA_WR_ALIGNPLD_M 0x1 4060 #define FW_TLSTX_DATA_WR_ALIGNPLD_V(x) ((x) << FW_TLSTX_DATA_WR_ALIGNPLD_S) 4061 #define FW_TLSTX_DATA_WR_ALIGNPLD_G(x) \ 4062 (((x) >> FW_TLSTX_DATA_WR_ALIGNPLD_S) & FW_TLSTX_DATA_WR_ALIGNPLD_M) 4063 #define FW_TLSTX_DATA_WR_ALIGNPLD_F FW_TLSTX_DATA_WR_ALIGNPLD_V(1U) 4064 4065 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_S 29 4066 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_M 0x1 4067 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_V(x) \ 4068 ((x) << FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_S) 4069 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_G(x) \ 4070 (((x) >> FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_S) & \ 4071 FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_M) 4072 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_F FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_V(1U) 4073 4074 #define FW_TLSTX_DATA_WR_FLAGS_S 0 4075 #define FW_TLSTX_DATA_WR_FLAGS_M 0xfffffff 4076 #define FW_TLSTX_DATA_WR_FLAGS_V(x) ((x) << FW_TLSTX_DATA_WR_FLAGS_S) 4077 #define FW_TLSTX_DATA_WR_FLAGS_G(x) \ 4078 (((x) >> FW_TLSTX_DATA_WR_FLAGS_S) & FW_TLSTX_DATA_WR_FLAGS_M) 4079 4080 #define FW_TLSTX_DATA_WR_CTXLOC_S 30 4081 #define FW_TLSTX_DATA_WR_CTXLOC_M 0x3 4082 #define FW_TLSTX_DATA_WR_CTXLOC_V(x) ((x) << FW_TLSTX_DATA_WR_CTXLOC_S) 4083 #define FW_TLSTX_DATA_WR_CTXLOC_G(x) \ 4084 (((x) >> FW_TLSTX_DATA_WR_CTXLOC_S) & FW_TLSTX_DATA_WR_CTXLOC_M) 4085 4086 #define FW_TLSTX_DATA_WR_IVDSGL_S 29 4087 #define FW_TLSTX_DATA_WR_IVDSGL_M 0x1 4088 #define FW_TLSTX_DATA_WR_IVDSGL_V(x) ((x) << FW_TLSTX_DATA_WR_IVDSGL_S) 4089 #define FW_TLSTX_DATA_WR_IVDSGL_G(x) \ 4090 (((x) >> FW_TLSTX_DATA_WR_IVDSGL_S) & FW_TLSTX_DATA_WR_IVDSGL_M) 4091 #define FW_TLSTX_DATA_WR_IVDSGL_F FW_TLSTX_DATA_WR_IVDSGL_V(1U) 4092 4093 #define FW_TLSTX_DATA_WR_KEYSIZE_S 24 4094 #define FW_TLSTX_DATA_WR_KEYSIZE_M 0x1f 4095 #define FW_TLSTX_DATA_WR_KEYSIZE_V(x) ((x) << FW_TLSTX_DATA_WR_KEYSIZE_S) 4096 #define FW_TLSTX_DATA_WR_KEYSIZE_G(x) \ 4097 (((x) >> FW_TLSTX_DATA_WR_KEYSIZE_S) & FW_TLSTX_DATA_WR_KEYSIZE_M) 4098 4099 #define FW_TLSTX_DATA_WR_NUMIVS_S 14 4100 #define FW_TLSTX_DATA_WR_NUMIVS_M 0xff 4101 #define FW_TLSTX_DATA_WR_NUMIVS_V(x) ((x) << FW_TLSTX_DATA_WR_NUMIVS_S) 4102 #define FW_TLSTX_DATA_WR_NUMIVS_G(x) \ 4103 (((x) >> FW_TLSTX_DATA_WR_NUMIVS_S) & FW_TLSTX_DATA_WR_NUMIVS_M) 4104 4105 #define FW_TLSTX_DATA_WR_EXP_S 0 4106 #define FW_TLSTX_DATA_WR_EXP_M 0x3fff 4107 #define FW_TLSTX_DATA_WR_EXP_V(x) ((x) << FW_TLSTX_DATA_WR_EXP_S) 4108 #define FW_TLSTX_DATA_WR_EXP_G(x) \ 4109 (((x) >> FW_TLSTX_DATA_WR_EXP_S) & FW_TLSTX_DATA_WR_EXP_M) 4110 4111 #define FW_TLSTX_DATA_WR_ADJUSTEDPLEN_S 1 4112 #define FW_TLSTX_DATA_WR_ADJUSTEDPLEN_V(x) \ 4113 ((x) << FW_TLSTX_DATA_WR_ADJUSTEDPLEN_S) 4114 4115 #define FW_TLSTX_DATA_WR_EXPINPLENMAX_S 4 4116 #define FW_TLSTX_DATA_WR_EXPINPLENMAX_V(x) \ 4117 ((x) << FW_TLSTX_DATA_WR_EXPINPLENMAX_S) 4118 4119 #define FW_TLSTX_DATA_WR_PDUSINPLENMAX_S 2 4120 #define FW_TLSTX_DATA_WR_PDUSINPLENMAX_V(x) \ 4121 ((x) << FW_TLSTX_DATA_WR_PDUSINPLENMAX_S) 4122 4123 #endif /* _T4FW_INTERFACE_H_ */ 4124