1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2009-2016 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef _T4FW_INTERFACE_H_ 36 #define _T4FW_INTERFACE_H_ 37 38 enum fw_retval { 39 FW_SUCCESS = 0, /* completed successfully */ 40 FW_EPERM = 1, /* operation not permitted */ 41 FW_ENOENT = 2, /* no such file or directory */ 42 FW_EIO = 5, /* input/output error; hw bad */ 43 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 44 FW_EAGAIN = 11, /* try again */ 45 FW_ENOMEM = 12, /* out of memory */ 46 FW_EFAULT = 14, /* bad address; fw bad */ 47 FW_EBUSY = 16, /* resource busy */ 48 FW_EEXIST = 17, /* file exists */ 49 FW_ENODEV = 19, /* no such device */ 50 FW_EINVAL = 22, /* invalid argument */ 51 FW_ENOSPC = 28, /* no space left on device */ 52 FW_ENOSYS = 38, /* functionality not implemented */ 53 FW_ENODATA = 61, /* no data available */ 54 FW_EPROTO = 71, /* protocol error */ 55 FW_EADDRINUSE = 98, /* address already in use */ 56 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 57 FW_ENETDOWN = 100, /* network is down */ 58 FW_ENETUNREACH = 101, /* network is unreachable */ 59 FW_ENOBUFS = 105, /* no buffer space available */ 60 FW_ETIMEDOUT = 110, /* timeout */ 61 FW_EINPROGRESS = 115, /* fw internal */ 62 FW_SCSI_ABORT_REQUESTED = 128, /* */ 63 FW_SCSI_ABORT_TIMEDOUT = 129, /* */ 64 FW_SCSI_ABORTED = 130, /* */ 65 FW_SCSI_CLOSE_REQUESTED = 131, /* */ 66 FW_ERR_LINK_DOWN = 132, /* */ 67 FW_RDEV_NOT_READY = 133, /* */ 68 FW_ERR_RDEV_LOST = 134, /* */ 69 FW_ERR_RDEV_LOGO = 135, /* */ 70 FW_FCOE_NO_XCHG = 136, /* */ 71 FW_SCSI_RSP_ERR = 137, /* */ 72 FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 73 FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 74 FW_SCSI_OVER_FLOW_ERR = 140, /* */ 75 FW_SCSI_DDP_ERR = 141, /* DDP error*/ 76 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 77 }; 78 79 #define FW_T4VF_SGE_BASE_ADDR 0x0000 80 #define FW_T4VF_MPS_BASE_ADDR 0x0100 81 #define FW_T4VF_PL_BASE_ADDR 0x0200 82 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240 83 #define FW_T4VF_CIM_BASE_ADDR 0x0300 84 85 enum fw_wr_opcodes { 86 FW_FILTER_WR = 0x02, 87 FW_ULPTX_WR = 0x04, 88 FW_TP_WR = 0x05, 89 FW_ETH_TX_PKT_WR = 0x08, 90 FW_OFLD_CONNECTION_WR = 0x2f, 91 FW_FLOWC_WR = 0x0a, 92 FW_OFLD_TX_DATA_WR = 0x0b, 93 FW_CMD_WR = 0x10, 94 FW_ETH_TX_PKT_VM_WR = 0x11, 95 FW_RI_RES_WR = 0x0c, 96 FW_RI_INIT_WR = 0x0d, 97 FW_RI_RDMA_WRITE_WR = 0x14, 98 FW_RI_SEND_WR = 0x15, 99 FW_RI_RDMA_READ_WR = 0x16, 100 FW_RI_RECV_WR = 0x17, 101 FW_RI_BIND_MW_WR = 0x18, 102 FW_RI_FR_NSMR_WR = 0x19, 103 FW_RI_FR_NSMR_TPTE_WR = 0x20, 104 FW_RI_INV_LSTAG_WR = 0x1a, 105 FW_ISCSI_TX_DATA_WR = 0x45, 106 FW_PTP_TX_PKT_WR = 0x46, 107 FW_CRYPTO_LOOKASIDE_WR = 0X6d, 108 FW_LASTC2E_WR = 0x70 109 }; 110 111 struct fw_wr_hdr { 112 __be32 hi; 113 __be32 lo; 114 }; 115 116 /* work request opcode (hi) */ 117 #define FW_WR_OP_S 24 118 #define FW_WR_OP_M 0xff 119 #define FW_WR_OP_V(x) ((x) << FW_WR_OP_S) 120 #define FW_WR_OP_G(x) (((x) >> FW_WR_OP_S) & FW_WR_OP_M) 121 122 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */ 123 #define FW_WR_ATOMIC_S 23 124 #define FW_WR_ATOMIC_V(x) ((x) << FW_WR_ATOMIC_S) 125 126 /* flush flag (hi) - firmware flushes flushable work request buffered 127 * in the flow context. 128 */ 129 #define FW_WR_FLUSH_S 22 130 #define FW_WR_FLUSH_V(x) ((x) << FW_WR_FLUSH_S) 131 132 /* completion flag (hi) - firmware generates a cpl_fw6_ack */ 133 #define FW_WR_COMPL_S 21 134 #define FW_WR_COMPL_V(x) ((x) << FW_WR_COMPL_S) 135 #define FW_WR_COMPL_F FW_WR_COMPL_V(1U) 136 137 /* work request immediate data length (hi) */ 138 #define FW_WR_IMMDLEN_S 0 139 #define FW_WR_IMMDLEN_M 0xff 140 #define FW_WR_IMMDLEN_V(x) ((x) << FW_WR_IMMDLEN_S) 141 142 /* egress queue status update to associated ingress queue entry (lo) */ 143 #define FW_WR_EQUIQ_S 31 144 #define FW_WR_EQUIQ_V(x) ((x) << FW_WR_EQUIQ_S) 145 #define FW_WR_EQUIQ_F FW_WR_EQUIQ_V(1U) 146 147 /* egress queue status update to egress queue status entry (lo) */ 148 #define FW_WR_EQUEQ_S 30 149 #define FW_WR_EQUEQ_V(x) ((x) << FW_WR_EQUEQ_S) 150 #define FW_WR_EQUEQ_F FW_WR_EQUEQ_V(1U) 151 152 /* flow context identifier (lo) */ 153 #define FW_WR_FLOWID_S 8 154 #define FW_WR_FLOWID_V(x) ((x) << FW_WR_FLOWID_S) 155 156 /* length in units of 16-bytes (lo) */ 157 #define FW_WR_LEN16_S 0 158 #define FW_WR_LEN16_V(x) ((x) << FW_WR_LEN16_S) 159 160 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 161 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327 162 163 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 164 enum fw_filter_wr_cookie { 165 FW_FILTER_WR_SUCCESS, 166 FW_FILTER_WR_FLT_ADDED, 167 FW_FILTER_WR_FLT_DELETED, 168 FW_FILTER_WR_SMT_TBL_FULL, 169 FW_FILTER_WR_EINVAL, 170 }; 171 172 struct fw_filter_wr { 173 __be32 op_pkd; 174 __be32 len16_pkd; 175 __be64 r3; 176 __be32 tid_to_iq; 177 __be32 del_filter_to_l2tix; 178 __be16 ethtype; 179 __be16 ethtypem; 180 __u8 frag_to_ovlan_vldm; 181 __u8 smac_sel; 182 __be16 rx_chan_rx_rpl_iq; 183 __be32 maci_to_matchtypem; 184 __u8 ptcl; 185 __u8 ptclm; 186 __u8 ttyp; 187 __u8 ttypm; 188 __be16 ivlan; 189 __be16 ivlanm; 190 __be16 ovlan; 191 __be16 ovlanm; 192 __u8 lip[16]; 193 __u8 lipm[16]; 194 __u8 fip[16]; 195 __u8 fipm[16]; 196 __be16 lp; 197 __be16 lpm; 198 __be16 fp; 199 __be16 fpm; 200 __be16 r7; 201 __u8 sma[6]; 202 }; 203 204 #define FW_FILTER_WR_TID_S 12 205 #define FW_FILTER_WR_TID_M 0xfffff 206 #define FW_FILTER_WR_TID_V(x) ((x) << FW_FILTER_WR_TID_S) 207 #define FW_FILTER_WR_TID_G(x) \ 208 (((x) >> FW_FILTER_WR_TID_S) & FW_FILTER_WR_TID_M) 209 210 #define FW_FILTER_WR_RQTYPE_S 11 211 #define FW_FILTER_WR_RQTYPE_M 0x1 212 #define FW_FILTER_WR_RQTYPE_V(x) ((x) << FW_FILTER_WR_RQTYPE_S) 213 #define FW_FILTER_WR_RQTYPE_G(x) \ 214 (((x) >> FW_FILTER_WR_RQTYPE_S) & FW_FILTER_WR_RQTYPE_M) 215 #define FW_FILTER_WR_RQTYPE_F FW_FILTER_WR_RQTYPE_V(1U) 216 217 #define FW_FILTER_WR_NOREPLY_S 10 218 #define FW_FILTER_WR_NOREPLY_M 0x1 219 #define FW_FILTER_WR_NOREPLY_V(x) ((x) << FW_FILTER_WR_NOREPLY_S) 220 #define FW_FILTER_WR_NOREPLY_G(x) \ 221 (((x) >> FW_FILTER_WR_NOREPLY_S) & FW_FILTER_WR_NOREPLY_M) 222 #define FW_FILTER_WR_NOREPLY_F FW_FILTER_WR_NOREPLY_V(1U) 223 224 #define FW_FILTER_WR_IQ_S 0 225 #define FW_FILTER_WR_IQ_M 0x3ff 226 #define FW_FILTER_WR_IQ_V(x) ((x) << FW_FILTER_WR_IQ_S) 227 #define FW_FILTER_WR_IQ_G(x) \ 228 (((x) >> FW_FILTER_WR_IQ_S) & FW_FILTER_WR_IQ_M) 229 230 #define FW_FILTER_WR_DEL_FILTER_S 31 231 #define FW_FILTER_WR_DEL_FILTER_M 0x1 232 #define FW_FILTER_WR_DEL_FILTER_V(x) ((x) << FW_FILTER_WR_DEL_FILTER_S) 233 #define FW_FILTER_WR_DEL_FILTER_G(x) \ 234 (((x) >> FW_FILTER_WR_DEL_FILTER_S) & FW_FILTER_WR_DEL_FILTER_M) 235 #define FW_FILTER_WR_DEL_FILTER_F FW_FILTER_WR_DEL_FILTER_V(1U) 236 237 #define FW_FILTER_WR_RPTTID_S 25 238 #define FW_FILTER_WR_RPTTID_M 0x1 239 #define FW_FILTER_WR_RPTTID_V(x) ((x) << FW_FILTER_WR_RPTTID_S) 240 #define FW_FILTER_WR_RPTTID_G(x) \ 241 (((x) >> FW_FILTER_WR_RPTTID_S) & FW_FILTER_WR_RPTTID_M) 242 #define FW_FILTER_WR_RPTTID_F FW_FILTER_WR_RPTTID_V(1U) 243 244 #define FW_FILTER_WR_DROP_S 24 245 #define FW_FILTER_WR_DROP_M 0x1 246 #define FW_FILTER_WR_DROP_V(x) ((x) << FW_FILTER_WR_DROP_S) 247 #define FW_FILTER_WR_DROP_G(x) \ 248 (((x) >> FW_FILTER_WR_DROP_S) & FW_FILTER_WR_DROP_M) 249 #define FW_FILTER_WR_DROP_F FW_FILTER_WR_DROP_V(1U) 250 251 #define FW_FILTER_WR_DIRSTEER_S 23 252 #define FW_FILTER_WR_DIRSTEER_M 0x1 253 #define FW_FILTER_WR_DIRSTEER_V(x) ((x) << FW_FILTER_WR_DIRSTEER_S) 254 #define FW_FILTER_WR_DIRSTEER_G(x) \ 255 (((x) >> FW_FILTER_WR_DIRSTEER_S) & FW_FILTER_WR_DIRSTEER_M) 256 #define FW_FILTER_WR_DIRSTEER_F FW_FILTER_WR_DIRSTEER_V(1U) 257 258 #define FW_FILTER_WR_MASKHASH_S 22 259 #define FW_FILTER_WR_MASKHASH_M 0x1 260 #define FW_FILTER_WR_MASKHASH_V(x) ((x) << FW_FILTER_WR_MASKHASH_S) 261 #define FW_FILTER_WR_MASKHASH_G(x) \ 262 (((x) >> FW_FILTER_WR_MASKHASH_S) & FW_FILTER_WR_MASKHASH_M) 263 #define FW_FILTER_WR_MASKHASH_F FW_FILTER_WR_MASKHASH_V(1U) 264 265 #define FW_FILTER_WR_DIRSTEERHASH_S 21 266 #define FW_FILTER_WR_DIRSTEERHASH_M 0x1 267 #define FW_FILTER_WR_DIRSTEERHASH_V(x) ((x) << FW_FILTER_WR_DIRSTEERHASH_S) 268 #define FW_FILTER_WR_DIRSTEERHASH_G(x) \ 269 (((x) >> FW_FILTER_WR_DIRSTEERHASH_S) & FW_FILTER_WR_DIRSTEERHASH_M) 270 #define FW_FILTER_WR_DIRSTEERHASH_F FW_FILTER_WR_DIRSTEERHASH_V(1U) 271 272 #define FW_FILTER_WR_LPBK_S 20 273 #define FW_FILTER_WR_LPBK_M 0x1 274 #define FW_FILTER_WR_LPBK_V(x) ((x) << FW_FILTER_WR_LPBK_S) 275 #define FW_FILTER_WR_LPBK_G(x) \ 276 (((x) >> FW_FILTER_WR_LPBK_S) & FW_FILTER_WR_LPBK_M) 277 #define FW_FILTER_WR_LPBK_F FW_FILTER_WR_LPBK_V(1U) 278 279 #define FW_FILTER_WR_DMAC_S 19 280 #define FW_FILTER_WR_DMAC_M 0x1 281 #define FW_FILTER_WR_DMAC_V(x) ((x) << FW_FILTER_WR_DMAC_S) 282 #define FW_FILTER_WR_DMAC_G(x) \ 283 (((x) >> FW_FILTER_WR_DMAC_S) & FW_FILTER_WR_DMAC_M) 284 #define FW_FILTER_WR_DMAC_F FW_FILTER_WR_DMAC_V(1U) 285 286 #define FW_FILTER_WR_SMAC_S 18 287 #define FW_FILTER_WR_SMAC_M 0x1 288 #define FW_FILTER_WR_SMAC_V(x) ((x) << FW_FILTER_WR_SMAC_S) 289 #define FW_FILTER_WR_SMAC_G(x) \ 290 (((x) >> FW_FILTER_WR_SMAC_S) & FW_FILTER_WR_SMAC_M) 291 #define FW_FILTER_WR_SMAC_F FW_FILTER_WR_SMAC_V(1U) 292 293 #define FW_FILTER_WR_INSVLAN_S 17 294 #define FW_FILTER_WR_INSVLAN_M 0x1 295 #define FW_FILTER_WR_INSVLAN_V(x) ((x) << FW_FILTER_WR_INSVLAN_S) 296 #define FW_FILTER_WR_INSVLAN_G(x) \ 297 (((x) >> FW_FILTER_WR_INSVLAN_S) & FW_FILTER_WR_INSVLAN_M) 298 #define FW_FILTER_WR_INSVLAN_F FW_FILTER_WR_INSVLAN_V(1U) 299 300 #define FW_FILTER_WR_RMVLAN_S 16 301 #define FW_FILTER_WR_RMVLAN_M 0x1 302 #define FW_FILTER_WR_RMVLAN_V(x) ((x) << FW_FILTER_WR_RMVLAN_S) 303 #define FW_FILTER_WR_RMVLAN_G(x) \ 304 (((x) >> FW_FILTER_WR_RMVLAN_S) & FW_FILTER_WR_RMVLAN_M) 305 #define FW_FILTER_WR_RMVLAN_F FW_FILTER_WR_RMVLAN_V(1U) 306 307 #define FW_FILTER_WR_HITCNTS_S 15 308 #define FW_FILTER_WR_HITCNTS_M 0x1 309 #define FW_FILTER_WR_HITCNTS_V(x) ((x) << FW_FILTER_WR_HITCNTS_S) 310 #define FW_FILTER_WR_HITCNTS_G(x) \ 311 (((x) >> FW_FILTER_WR_HITCNTS_S) & FW_FILTER_WR_HITCNTS_M) 312 #define FW_FILTER_WR_HITCNTS_F FW_FILTER_WR_HITCNTS_V(1U) 313 314 #define FW_FILTER_WR_TXCHAN_S 13 315 #define FW_FILTER_WR_TXCHAN_M 0x3 316 #define FW_FILTER_WR_TXCHAN_V(x) ((x) << FW_FILTER_WR_TXCHAN_S) 317 #define FW_FILTER_WR_TXCHAN_G(x) \ 318 (((x) >> FW_FILTER_WR_TXCHAN_S) & FW_FILTER_WR_TXCHAN_M) 319 320 #define FW_FILTER_WR_PRIO_S 12 321 #define FW_FILTER_WR_PRIO_M 0x1 322 #define FW_FILTER_WR_PRIO_V(x) ((x) << FW_FILTER_WR_PRIO_S) 323 #define FW_FILTER_WR_PRIO_G(x) \ 324 (((x) >> FW_FILTER_WR_PRIO_S) & FW_FILTER_WR_PRIO_M) 325 #define FW_FILTER_WR_PRIO_F FW_FILTER_WR_PRIO_V(1U) 326 327 #define FW_FILTER_WR_L2TIX_S 0 328 #define FW_FILTER_WR_L2TIX_M 0xfff 329 #define FW_FILTER_WR_L2TIX_V(x) ((x) << FW_FILTER_WR_L2TIX_S) 330 #define FW_FILTER_WR_L2TIX_G(x) \ 331 (((x) >> FW_FILTER_WR_L2TIX_S) & FW_FILTER_WR_L2TIX_M) 332 333 #define FW_FILTER_WR_FRAG_S 7 334 #define FW_FILTER_WR_FRAG_M 0x1 335 #define FW_FILTER_WR_FRAG_V(x) ((x) << FW_FILTER_WR_FRAG_S) 336 #define FW_FILTER_WR_FRAG_G(x) \ 337 (((x) >> FW_FILTER_WR_FRAG_S) & FW_FILTER_WR_FRAG_M) 338 #define FW_FILTER_WR_FRAG_F FW_FILTER_WR_FRAG_V(1U) 339 340 #define FW_FILTER_WR_FRAGM_S 6 341 #define FW_FILTER_WR_FRAGM_M 0x1 342 #define FW_FILTER_WR_FRAGM_V(x) ((x) << FW_FILTER_WR_FRAGM_S) 343 #define FW_FILTER_WR_FRAGM_G(x) \ 344 (((x) >> FW_FILTER_WR_FRAGM_S) & FW_FILTER_WR_FRAGM_M) 345 #define FW_FILTER_WR_FRAGM_F FW_FILTER_WR_FRAGM_V(1U) 346 347 #define FW_FILTER_WR_IVLAN_VLD_S 5 348 #define FW_FILTER_WR_IVLAN_VLD_M 0x1 349 #define FW_FILTER_WR_IVLAN_VLD_V(x) ((x) << FW_FILTER_WR_IVLAN_VLD_S) 350 #define FW_FILTER_WR_IVLAN_VLD_G(x) \ 351 (((x) >> FW_FILTER_WR_IVLAN_VLD_S) & FW_FILTER_WR_IVLAN_VLD_M) 352 #define FW_FILTER_WR_IVLAN_VLD_F FW_FILTER_WR_IVLAN_VLD_V(1U) 353 354 #define FW_FILTER_WR_OVLAN_VLD_S 4 355 #define FW_FILTER_WR_OVLAN_VLD_M 0x1 356 #define FW_FILTER_WR_OVLAN_VLD_V(x) ((x) << FW_FILTER_WR_OVLAN_VLD_S) 357 #define FW_FILTER_WR_OVLAN_VLD_G(x) \ 358 (((x) >> FW_FILTER_WR_OVLAN_VLD_S) & FW_FILTER_WR_OVLAN_VLD_M) 359 #define FW_FILTER_WR_OVLAN_VLD_F FW_FILTER_WR_OVLAN_VLD_V(1U) 360 361 #define FW_FILTER_WR_IVLAN_VLDM_S 3 362 #define FW_FILTER_WR_IVLAN_VLDM_M 0x1 363 #define FW_FILTER_WR_IVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_IVLAN_VLDM_S) 364 #define FW_FILTER_WR_IVLAN_VLDM_G(x) \ 365 (((x) >> FW_FILTER_WR_IVLAN_VLDM_S) & FW_FILTER_WR_IVLAN_VLDM_M) 366 #define FW_FILTER_WR_IVLAN_VLDM_F FW_FILTER_WR_IVLAN_VLDM_V(1U) 367 368 #define FW_FILTER_WR_OVLAN_VLDM_S 2 369 #define FW_FILTER_WR_OVLAN_VLDM_M 0x1 370 #define FW_FILTER_WR_OVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_OVLAN_VLDM_S) 371 #define FW_FILTER_WR_OVLAN_VLDM_G(x) \ 372 (((x) >> FW_FILTER_WR_OVLAN_VLDM_S) & FW_FILTER_WR_OVLAN_VLDM_M) 373 #define FW_FILTER_WR_OVLAN_VLDM_F FW_FILTER_WR_OVLAN_VLDM_V(1U) 374 375 #define FW_FILTER_WR_RX_CHAN_S 15 376 #define FW_FILTER_WR_RX_CHAN_M 0x1 377 #define FW_FILTER_WR_RX_CHAN_V(x) ((x) << FW_FILTER_WR_RX_CHAN_S) 378 #define FW_FILTER_WR_RX_CHAN_G(x) \ 379 (((x) >> FW_FILTER_WR_RX_CHAN_S) & FW_FILTER_WR_RX_CHAN_M) 380 #define FW_FILTER_WR_RX_CHAN_F FW_FILTER_WR_RX_CHAN_V(1U) 381 382 #define FW_FILTER_WR_RX_RPL_IQ_S 0 383 #define FW_FILTER_WR_RX_RPL_IQ_M 0x3ff 384 #define FW_FILTER_WR_RX_RPL_IQ_V(x) ((x) << FW_FILTER_WR_RX_RPL_IQ_S) 385 #define FW_FILTER_WR_RX_RPL_IQ_G(x) \ 386 (((x) >> FW_FILTER_WR_RX_RPL_IQ_S) & FW_FILTER_WR_RX_RPL_IQ_M) 387 388 #define FW_FILTER_WR_MACI_S 23 389 #define FW_FILTER_WR_MACI_M 0x1ff 390 #define FW_FILTER_WR_MACI_V(x) ((x) << FW_FILTER_WR_MACI_S) 391 #define FW_FILTER_WR_MACI_G(x) \ 392 (((x) >> FW_FILTER_WR_MACI_S) & FW_FILTER_WR_MACI_M) 393 394 #define FW_FILTER_WR_MACIM_S 14 395 #define FW_FILTER_WR_MACIM_M 0x1ff 396 #define FW_FILTER_WR_MACIM_V(x) ((x) << FW_FILTER_WR_MACIM_S) 397 #define FW_FILTER_WR_MACIM_G(x) \ 398 (((x) >> FW_FILTER_WR_MACIM_S) & FW_FILTER_WR_MACIM_M) 399 400 #define FW_FILTER_WR_FCOE_S 13 401 #define FW_FILTER_WR_FCOE_M 0x1 402 #define FW_FILTER_WR_FCOE_V(x) ((x) << FW_FILTER_WR_FCOE_S) 403 #define FW_FILTER_WR_FCOE_G(x) \ 404 (((x) >> FW_FILTER_WR_FCOE_S) & FW_FILTER_WR_FCOE_M) 405 #define FW_FILTER_WR_FCOE_F FW_FILTER_WR_FCOE_V(1U) 406 407 #define FW_FILTER_WR_FCOEM_S 12 408 #define FW_FILTER_WR_FCOEM_M 0x1 409 #define FW_FILTER_WR_FCOEM_V(x) ((x) << FW_FILTER_WR_FCOEM_S) 410 #define FW_FILTER_WR_FCOEM_G(x) \ 411 (((x) >> FW_FILTER_WR_FCOEM_S) & FW_FILTER_WR_FCOEM_M) 412 #define FW_FILTER_WR_FCOEM_F FW_FILTER_WR_FCOEM_V(1U) 413 414 #define FW_FILTER_WR_PORT_S 9 415 #define FW_FILTER_WR_PORT_M 0x7 416 #define FW_FILTER_WR_PORT_V(x) ((x) << FW_FILTER_WR_PORT_S) 417 #define FW_FILTER_WR_PORT_G(x) \ 418 (((x) >> FW_FILTER_WR_PORT_S) & FW_FILTER_WR_PORT_M) 419 420 #define FW_FILTER_WR_PORTM_S 6 421 #define FW_FILTER_WR_PORTM_M 0x7 422 #define FW_FILTER_WR_PORTM_V(x) ((x) << FW_FILTER_WR_PORTM_S) 423 #define FW_FILTER_WR_PORTM_G(x) \ 424 (((x) >> FW_FILTER_WR_PORTM_S) & FW_FILTER_WR_PORTM_M) 425 426 #define FW_FILTER_WR_MATCHTYPE_S 3 427 #define FW_FILTER_WR_MATCHTYPE_M 0x7 428 #define FW_FILTER_WR_MATCHTYPE_V(x) ((x) << FW_FILTER_WR_MATCHTYPE_S) 429 #define FW_FILTER_WR_MATCHTYPE_G(x) \ 430 (((x) >> FW_FILTER_WR_MATCHTYPE_S) & FW_FILTER_WR_MATCHTYPE_M) 431 432 #define FW_FILTER_WR_MATCHTYPEM_S 0 433 #define FW_FILTER_WR_MATCHTYPEM_M 0x7 434 #define FW_FILTER_WR_MATCHTYPEM_V(x) ((x) << FW_FILTER_WR_MATCHTYPEM_S) 435 #define FW_FILTER_WR_MATCHTYPEM_G(x) \ 436 (((x) >> FW_FILTER_WR_MATCHTYPEM_S) & FW_FILTER_WR_MATCHTYPEM_M) 437 438 struct fw_ulptx_wr { 439 __be32 op_to_compl; 440 __be32 flowid_len16; 441 u64 cookie; 442 }; 443 444 struct fw_tp_wr { 445 __be32 op_to_immdlen; 446 __be32 flowid_len16; 447 u64 cookie; 448 }; 449 450 struct fw_eth_tx_pkt_wr { 451 __be32 op_immdlen; 452 __be32 equiq_to_len16; 453 __be64 r3; 454 }; 455 456 struct fw_ofld_connection_wr { 457 __be32 op_compl; 458 __be32 len16_pkd; 459 __u64 cookie; 460 __be64 r2; 461 __be64 r3; 462 struct fw_ofld_connection_le { 463 __be32 version_cpl; 464 __be32 filter; 465 __be32 r1; 466 __be16 lport; 467 __be16 pport; 468 union fw_ofld_connection_leip { 469 struct fw_ofld_connection_le_ipv4 { 470 __be32 pip; 471 __be32 lip; 472 __be64 r0; 473 __be64 r1; 474 __be64 r2; 475 } ipv4; 476 struct fw_ofld_connection_le_ipv6 { 477 __be64 pip_hi; 478 __be64 pip_lo; 479 __be64 lip_hi; 480 __be64 lip_lo; 481 } ipv6; 482 } u; 483 } le; 484 struct fw_ofld_connection_tcb { 485 __be32 t_state_to_astid; 486 __be16 cplrxdataack_cplpassacceptrpl; 487 __be16 rcv_adv; 488 __be32 rcv_nxt; 489 __be32 tx_max; 490 __be64 opt0; 491 __be32 opt2; 492 __be32 r1; 493 __be64 r2; 494 __be64 r3; 495 } tcb; 496 }; 497 498 #define FW_OFLD_CONNECTION_WR_VERSION_S 31 499 #define FW_OFLD_CONNECTION_WR_VERSION_M 0x1 500 #define FW_OFLD_CONNECTION_WR_VERSION_V(x) \ 501 ((x) << FW_OFLD_CONNECTION_WR_VERSION_S) 502 #define FW_OFLD_CONNECTION_WR_VERSION_G(x) \ 503 (((x) >> FW_OFLD_CONNECTION_WR_VERSION_S) & \ 504 FW_OFLD_CONNECTION_WR_VERSION_M) 505 #define FW_OFLD_CONNECTION_WR_VERSION_F \ 506 FW_OFLD_CONNECTION_WR_VERSION_V(1U) 507 508 #define FW_OFLD_CONNECTION_WR_CPL_S 30 509 #define FW_OFLD_CONNECTION_WR_CPL_M 0x1 510 #define FW_OFLD_CONNECTION_WR_CPL_V(x) ((x) << FW_OFLD_CONNECTION_WR_CPL_S) 511 #define FW_OFLD_CONNECTION_WR_CPL_G(x) \ 512 (((x) >> FW_OFLD_CONNECTION_WR_CPL_S) & FW_OFLD_CONNECTION_WR_CPL_M) 513 #define FW_OFLD_CONNECTION_WR_CPL_F FW_OFLD_CONNECTION_WR_CPL_V(1U) 514 515 #define FW_OFLD_CONNECTION_WR_T_STATE_S 28 516 #define FW_OFLD_CONNECTION_WR_T_STATE_M 0xf 517 #define FW_OFLD_CONNECTION_WR_T_STATE_V(x) \ 518 ((x) << FW_OFLD_CONNECTION_WR_T_STATE_S) 519 #define FW_OFLD_CONNECTION_WR_T_STATE_G(x) \ 520 (((x) >> FW_OFLD_CONNECTION_WR_T_STATE_S) & \ 521 FW_OFLD_CONNECTION_WR_T_STATE_M) 522 523 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_S 24 524 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_M 0xf 525 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_V(x) \ 526 ((x) << FW_OFLD_CONNECTION_WR_RCV_SCALE_S) 527 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_G(x) \ 528 (((x) >> FW_OFLD_CONNECTION_WR_RCV_SCALE_S) & \ 529 FW_OFLD_CONNECTION_WR_RCV_SCALE_M) 530 531 #define FW_OFLD_CONNECTION_WR_ASTID_S 0 532 #define FW_OFLD_CONNECTION_WR_ASTID_M 0xffffff 533 #define FW_OFLD_CONNECTION_WR_ASTID_V(x) \ 534 ((x) << FW_OFLD_CONNECTION_WR_ASTID_S) 535 #define FW_OFLD_CONNECTION_WR_ASTID_G(x) \ 536 (((x) >> FW_OFLD_CONNECTION_WR_ASTID_S) & FW_OFLD_CONNECTION_WR_ASTID_M) 537 538 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S 15 539 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M 0x1 540 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(x) \ 541 ((x) << FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) 542 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_G(x) \ 543 (((x) >> FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) & \ 544 FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M) 545 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_F \ 546 FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(1U) 547 548 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S 14 549 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M 0x1 550 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(x) \ 551 ((x) << FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) 552 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_G(x) \ 553 (((x) >> FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) & \ 554 FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M) 555 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_F \ 556 FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(1U) 557 558 enum fw_flowc_mnem { 559 FW_FLOWC_MNEM_PFNVFN, /* PFN [15:8] VFN [7:0] */ 560 FW_FLOWC_MNEM_CH, 561 FW_FLOWC_MNEM_PORT, 562 FW_FLOWC_MNEM_IQID, 563 FW_FLOWC_MNEM_SNDNXT, 564 FW_FLOWC_MNEM_RCVNXT, 565 FW_FLOWC_MNEM_SNDBUF, 566 FW_FLOWC_MNEM_MSS, 567 FW_FLOWC_MNEM_TXDATAPLEN_MAX, 568 FW_FLOWC_MNEM_TCPSTATE, 569 FW_FLOWC_MNEM_EOSTATE, 570 FW_FLOWC_MNEM_SCHEDCLASS, 571 FW_FLOWC_MNEM_DCBPRIO, 572 FW_FLOWC_MNEM_SND_SCALE, 573 FW_FLOWC_MNEM_RCV_SCALE, 574 }; 575 576 struct fw_flowc_mnemval { 577 u8 mnemonic; 578 u8 r4[3]; 579 __be32 val; 580 }; 581 582 struct fw_flowc_wr { 583 __be32 op_to_nparams; 584 __be32 flowid_len16; 585 struct fw_flowc_mnemval mnemval[0]; 586 }; 587 588 #define FW_FLOWC_WR_NPARAMS_S 0 589 #define FW_FLOWC_WR_NPARAMS_V(x) ((x) << FW_FLOWC_WR_NPARAMS_S) 590 591 struct fw_ofld_tx_data_wr { 592 __be32 op_to_immdlen; 593 __be32 flowid_len16; 594 __be32 plen; 595 __be32 tunnel_to_proxy; 596 }; 597 598 #define FW_OFLD_TX_DATA_WR_TUNNEL_S 19 599 #define FW_OFLD_TX_DATA_WR_TUNNEL_V(x) ((x) << FW_OFLD_TX_DATA_WR_TUNNEL_S) 600 601 #define FW_OFLD_TX_DATA_WR_SAVE_S 18 602 #define FW_OFLD_TX_DATA_WR_SAVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SAVE_S) 603 604 #define FW_OFLD_TX_DATA_WR_FLUSH_S 17 605 #define FW_OFLD_TX_DATA_WR_FLUSH_V(x) ((x) << FW_OFLD_TX_DATA_WR_FLUSH_S) 606 #define FW_OFLD_TX_DATA_WR_FLUSH_F FW_OFLD_TX_DATA_WR_FLUSH_V(1U) 607 608 #define FW_OFLD_TX_DATA_WR_URGENT_S 16 609 #define FW_OFLD_TX_DATA_WR_URGENT_V(x) ((x) << FW_OFLD_TX_DATA_WR_URGENT_S) 610 611 #define FW_OFLD_TX_DATA_WR_MORE_S 15 612 #define FW_OFLD_TX_DATA_WR_MORE_V(x) ((x) << FW_OFLD_TX_DATA_WR_MORE_S) 613 614 #define FW_OFLD_TX_DATA_WR_SHOVE_S 14 615 #define FW_OFLD_TX_DATA_WR_SHOVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SHOVE_S) 616 #define FW_OFLD_TX_DATA_WR_SHOVE_F FW_OFLD_TX_DATA_WR_SHOVE_V(1U) 617 618 #define FW_OFLD_TX_DATA_WR_ULPMODE_S 10 619 #define FW_OFLD_TX_DATA_WR_ULPMODE_V(x) ((x) << FW_OFLD_TX_DATA_WR_ULPMODE_S) 620 621 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_S 6 622 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_V(x) \ 623 ((x) << FW_OFLD_TX_DATA_WR_ULPSUBMODE_S) 624 625 struct fw_cmd_wr { 626 __be32 op_dma; 627 __be32 len16_pkd; 628 __be64 cookie_daddr; 629 }; 630 631 #define FW_CMD_WR_DMA_S 17 632 #define FW_CMD_WR_DMA_V(x) ((x) << FW_CMD_WR_DMA_S) 633 634 struct fw_eth_tx_pkt_vm_wr { 635 __be32 op_immdlen; 636 __be32 equiq_to_len16; 637 __be32 r3[2]; 638 u8 ethmacdst[6]; 639 u8 ethmacsrc[6]; 640 __be16 ethtype; 641 __be16 vlantci; 642 }; 643 644 #define FW_CMD_MAX_TIMEOUT 10000 645 646 /* 647 * If a host driver does a HELLO and discovers that there's already a MASTER 648 * selected, we may have to wait for that MASTER to finish issuing RESET, 649 * configuration and INITIALIZE commands. Also, there's a possibility that 650 * our own HELLO may get lost if it happens right as the MASTER is issuign a 651 * RESET command, so we need to be willing to make a few retries of our HELLO. 652 */ 653 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 654 #define FW_CMD_HELLO_RETRIES 3 655 656 657 enum fw_cmd_opcodes { 658 FW_LDST_CMD = 0x01, 659 FW_RESET_CMD = 0x03, 660 FW_HELLO_CMD = 0x04, 661 FW_BYE_CMD = 0x05, 662 FW_INITIALIZE_CMD = 0x06, 663 FW_CAPS_CONFIG_CMD = 0x07, 664 FW_PARAMS_CMD = 0x08, 665 FW_PFVF_CMD = 0x09, 666 FW_IQ_CMD = 0x10, 667 FW_EQ_MNGT_CMD = 0x11, 668 FW_EQ_ETH_CMD = 0x12, 669 FW_EQ_CTRL_CMD = 0x13, 670 FW_EQ_OFLD_CMD = 0x21, 671 FW_VI_CMD = 0x14, 672 FW_VI_MAC_CMD = 0x15, 673 FW_VI_RXMODE_CMD = 0x16, 674 FW_VI_ENABLE_CMD = 0x17, 675 FW_ACL_MAC_CMD = 0x18, 676 FW_ACL_VLAN_CMD = 0x19, 677 FW_VI_STATS_CMD = 0x1a, 678 FW_PORT_CMD = 0x1b, 679 FW_PORT_STATS_CMD = 0x1c, 680 FW_PORT_LB_STATS_CMD = 0x1d, 681 FW_PORT_TRACE_CMD = 0x1e, 682 FW_PORT_TRACE_MMAP_CMD = 0x1f, 683 FW_RSS_IND_TBL_CMD = 0x20, 684 FW_RSS_GLB_CONFIG_CMD = 0x22, 685 FW_RSS_VI_CONFIG_CMD = 0x23, 686 FW_SCHED_CMD = 0x24, 687 FW_DEVLOG_CMD = 0x25, 688 FW_CLIP_CMD = 0x28, 689 FW_PTP_CMD = 0x3e, 690 FW_LASTC2E_CMD = 0x40, 691 FW_ERROR_CMD = 0x80, 692 FW_DEBUG_CMD = 0x81, 693 }; 694 695 enum fw_cmd_cap { 696 FW_CMD_CAP_PF = 0x01, 697 FW_CMD_CAP_DMAQ = 0x02, 698 FW_CMD_CAP_PORT = 0x04, 699 FW_CMD_CAP_PORTPROMISC = 0x08, 700 FW_CMD_CAP_PORTSTATS = 0x10, 701 FW_CMD_CAP_VF = 0x80, 702 }; 703 704 /* 705 * Generic command header flit0 706 */ 707 struct fw_cmd_hdr { 708 __be32 hi; 709 __be32 lo; 710 }; 711 712 #define FW_CMD_OP_S 24 713 #define FW_CMD_OP_M 0xff 714 #define FW_CMD_OP_V(x) ((x) << FW_CMD_OP_S) 715 #define FW_CMD_OP_G(x) (((x) >> FW_CMD_OP_S) & FW_CMD_OP_M) 716 717 #define FW_CMD_REQUEST_S 23 718 #define FW_CMD_REQUEST_V(x) ((x) << FW_CMD_REQUEST_S) 719 #define FW_CMD_REQUEST_F FW_CMD_REQUEST_V(1U) 720 721 #define FW_CMD_READ_S 22 722 #define FW_CMD_READ_V(x) ((x) << FW_CMD_READ_S) 723 #define FW_CMD_READ_F FW_CMD_READ_V(1U) 724 725 #define FW_CMD_WRITE_S 21 726 #define FW_CMD_WRITE_V(x) ((x) << FW_CMD_WRITE_S) 727 #define FW_CMD_WRITE_F FW_CMD_WRITE_V(1U) 728 729 #define FW_CMD_EXEC_S 20 730 #define FW_CMD_EXEC_V(x) ((x) << FW_CMD_EXEC_S) 731 #define FW_CMD_EXEC_F FW_CMD_EXEC_V(1U) 732 733 #define FW_CMD_RAMASK_S 20 734 #define FW_CMD_RAMASK_V(x) ((x) << FW_CMD_RAMASK_S) 735 736 #define FW_CMD_RETVAL_S 8 737 #define FW_CMD_RETVAL_M 0xff 738 #define FW_CMD_RETVAL_V(x) ((x) << FW_CMD_RETVAL_S) 739 #define FW_CMD_RETVAL_G(x) (((x) >> FW_CMD_RETVAL_S) & FW_CMD_RETVAL_M) 740 741 #define FW_CMD_LEN16_S 0 742 #define FW_CMD_LEN16_V(x) ((x) << FW_CMD_LEN16_S) 743 744 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 745 746 enum fw_ldst_addrspc { 747 FW_LDST_ADDRSPC_FIRMWARE = 0x0001, 748 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, 749 FW_LDST_ADDRSPC_SGE_INGC = 0x0009, 750 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, 751 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 752 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 753 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 754 FW_LDST_ADDRSPC_TP_MIB = 0x0012, 755 FW_LDST_ADDRSPC_MDIO = 0x0018, 756 FW_LDST_ADDRSPC_MPS = 0x0020, 757 FW_LDST_ADDRSPC_FUNC = 0x0028, 758 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, 759 }; 760 761 enum fw_ldst_mps_fid { 762 FW_LDST_MPS_ATRB, 763 FW_LDST_MPS_RPLC 764 }; 765 766 enum fw_ldst_func_access_ctl { 767 FW_LDST_FUNC_ACC_CTL_VIID, 768 FW_LDST_FUNC_ACC_CTL_FID 769 }; 770 771 enum fw_ldst_func_mod_index { 772 FW_LDST_FUNC_MPS 773 }; 774 775 struct fw_ldst_cmd { 776 __be32 op_to_addrspace; 777 __be32 cycles_to_len16; 778 union fw_ldst { 779 struct fw_ldst_addrval { 780 __be32 addr; 781 __be32 val; 782 } addrval; 783 struct fw_ldst_idctxt { 784 __be32 physid; 785 __be32 msg_ctxtflush; 786 __be32 ctxt_data7; 787 __be32 ctxt_data6; 788 __be32 ctxt_data5; 789 __be32 ctxt_data4; 790 __be32 ctxt_data3; 791 __be32 ctxt_data2; 792 __be32 ctxt_data1; 793 __be32 ctxt_data0; 794 } idctxt; 795 struct fw_ldst_mdio { 796 __be16 paddr_mmd; 797 __be16 raddr; 798 __be16 vctl; 799 __be16 rval; 800 } mdio; 801 struct fw_ldst_cim_rq { 802 u8 req_first64[8]; 803 u8 req_second64[8]; 804 u8 resp_first64[8]; 805 u8 resp_second64[8]; 806 __be32 r3[2]; 807 } cim_rq; 808 union fw_ldst_mps { 809 struct fw_ldst_mps_rplc { 810 __be16 fid_idx; 811 __be16 rplcpf_pkd; 812 __be32 rplc255_224; 813 __be32 rplc223_192; 814 __be32 rplc191_160; 815 __be32 rplc159_128; 816 __be32 rplc127_96; 817 __be32 rplc95_64; 818 __be32 rplc63_32; 819 __be32 rplc31_0; 820 } rplc; 821 struct fw_ldst_mps_atrb { 822 __be16 fid_mpsid; 823 __be16 r2[3]; 824 __be32 r3[2]; 825 __be32 r4; 826 __be32 atrb; 827 __be16 vlan[16]; 828 } atrb; 829 } mps; 830 struct fw_ldst_func { 831 u8 access_ctl; 832 u8 mod_index; 833 __be16 ctl_id; 834 __be32 offset; 835 __be64 data0; 836 __be64 data1; 837 } func; 838 struct fw_ldst_pcie { 839 u8 ctrl_to_fn; 840 u8 bnum; 841 u8 r; 842 u8 ext_r; 843 u8 select_naccess; 844 u8 pcie_fn; 845 __be16 nset_pkd; 846 __be32 data[12]; 847 } pcie; 848 struct fw_ldst_i2c_deprecated { 849 u8 pid_pkd; 850 u8 base; 851 u8 boffset; 852 u8 data; 853 __be32 r9; 854 } i2c_deprecated; 855 struct fw_ldst_i2c { 856 u8 pid; 857 u8 did; 858 u8 boffset; 859 u8 blen; 860 __be32 r9; 861 __u8 data[48]; 862 } i2c; 863 struct fw_ldst_le { 864 __be32 index; 865 __be32 r9; 866 u8 val[33]; 867 u8 r11[7]; 868 } le; 869 } u; 870 }; 871 872 #define FW_LDST_CMD_ADDRSPACE_S 0 873 #define FW_LDST_CMD_ADDRSPACE_V(x) ((x) << FW_LDST_CMD_ADDRSPACE_S) 874 875 #define FW_LDST_CMD_MSG_S 31 876 #define FW_LDST_CMD_MSG_V(x) ((x) << FW_LDST_CMD_MSG_S) 877 878 #define FW_LDST_CMD_CTXTFLUSH_S 30 879 #define FW_LDST_CMD_CTXTFLUSH_V(x) ((x) << FW_LDST_CMD_CTXTFLUSH_S) 880 #define FW_LDST_CMD_CTXTFLUSH_F FW_LDST_CMD_CTXTFLUSH_V(1U) 881 882 #define FW_LDST_CMD_PADDR_S 8 883 #define FW_LDST_CMD_PADDR_V(x) ((x) << FW_LDST_CMD_PADDR_S) 884 885 #define FW_LDST_CMD_MMD_S 0 886 #define FW_LDST_CMD_MMD_V(x) ((x) << FW_LDST_CMD_MMD_S) 887 888 #define FW_LDST_CMD_FID_S 15 889 #define FW_LDST_CMD_FID_V(x) ((x) << FW_LDST_CMD_FID_S) 890 891 #define FW_LDST_CMD_IDX_S 0 892 #define FW_LDST_CMD_IDX_V(x) ((x) << FW_LDST_CMD_IDX_S) 893 894 #define FW_LDST_CMD_RPLCPF_S 0 895 #define FW_LDST_CMD_RPLCPF_V(x) ((x) << FW_LDST_CMD_RPLCPF_S) 896 897 #define FW_LDST_CMD_LC_S 4 898 #define FW_LDST_CMD_LC_V(x) ((x) << FW_LDST_CMD_LC_S) 899 #define FW_LDST_CMD_LC_F FW_LDST_CMD_LC_V(1U) 900 901 #define FW_LDST_CMD_FN_S 0 902 #define FW_LDST_CMD_FN_V(x) ((x) << FW_LDST_CMD_FN_S) 903 904 #define FW_LDST_CMD_NACCESS_S 0 905 #define FW_LDST_CMD_NACCESS_V(x) ((x) << FW_LDST_CMD_NACCESS_S) 906 907 struct fw_reset_cmd { 908 __be32 op_to_write; 909 __be32 retval_len16; 910 __be32 val; 911 __be32 halt_pkd; 912 }; 913 914 #define FW_RESET_CMD_HALT_S 31 915 #define FW_RESET_CMD_HALT_M 0x1 916 #define FW_RESET_CMD_HALT_V(x) ((x) << FW_RESET_CMD_HALT_S) 917 #define FW_RESET_CMD_HALT_G(x) \ 918 (((x) >> FW_RESET_CMD_HALT_S) & FW_RESET_CMD_HALT_M) 919 #define FW_RESET_CMD_HALT_F FW_RESET_CMD_HALT_V(1U) 920 921 enum fw_hellow_cmd { 922 fw_hello_cmd_stage_os = 0x0 923 }; 924 925 struct fw_hello_cmd { 926 __be32 op_to_write; 927 __be32 retval_len16; 928 __be32 err_to_clearinit; 929 __be32 fwrev; 930 }; 931 932 #define FW_HELLO_CMD_ERR_S 31 933 #define FW_HELLO_CMD_ERR_V(x) ((x) << FW_HELLO_CMD_ERR_S) 934 #define FW_HELLO_CMD_ERR_F FW_HELLO_CMD_ERR_V(1U) 935 936 #define FW_HELLO_CMD_INIT_S 30 937 #define FW_HELLO_CMD_INIT_V(x) ((x) << FW_HELLO_CMD_INIT_S) 938 #define FW_HELLO_CMD_INIT_F FW_HELLO_CMD_INIT_V(1U) 939 940 #define FW_HELLO_CMD_MASTERDIS_S 29 941 #define FW_HELLO_CMD_MASTERDIS_V(x) ((x) << FW_HELLO_CMD_MASTERDIS_S) 942 943 #define FW_HELLO_CMD_MASTERFORCE_S 28 944 #define FW_HELLO_CMD_MASTERFORCE_V(x) ((x) << FW_HELLO_CMD_MASTERFORCE_S) 945 946 #define FW_HELLO_CMD_MBMASTER_S 24 947 #define FW_HELLO_CMD_MBMASTER_M 0xfU 948 #define FW_HELLO_CMD_MBMASTER_V(x) ((x) << FW_HELLO_CMD_MBMASTER_S) 949 #define FW_HELLO_CMD_MBMASTER_G(x) \ 950 (((x) >> FW_HELLO_CMD_MBMASTER_S) & FW_HELLO_CMD_MBMASTER_M) 951 952 #define FW_HELLO_CMD_MBASYNCNOTINT_S 23 953 #define FW_HELLO_CMD_MBASYNCNOTINT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOTINT_S) 954 955 #define FW_HELLO_CMD_MBASYNCNOT_S 20 956 #define FW_HELLO_CMD_MBASYNCNOT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOT_S) 957 958 #define FW_HELLO_CMD_STAGE_S 17 959 #define FW_HELLO_CMD_STAGE_V(x) ((x) << FW_HELLO_CMD_STAGE_S) 960 961 #define FW_HELLO_CMD_CLEARINIT_S 16 962 #define FW_HELLO_CMD_CLEARINIT_V(x) ((x) << FW_HELLO_CMD_CLEARINIT_S) 963 #define FW_HELLO_CMD_CLEARINIT_F FW_HELLO_CMD_CLEARINIT_V(1U) 964 965 struct fw_bye_cmd { 966 __be32 op_to_write; 967 __be32 retval_len16; 968 __be64 r3; 969 }; 970 971 struct fw_initialize_cmd { 972 __be32 op_to_write; 973 __be32 retval_len16; 974 __be64 r3; 975 }; 976 977 enum fw_caps_config_hm { 978 FW_CAPS_CONFIG_HM_PCIE = 0x00000001, 979 FW_CAPS_CONFIG_HM_PL = 0x00000002, 980 FW_CAPS_CONFIG_HM_SGE = 0x00000004, 981 FW_CAPS_CONFIG_HM_CIM = 0x00000008, 982 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, 983 FW_CAPS_CONFIG_HM_TP = 0x00000020, 984 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, 985 FW_CAPS_CONFIG_HM_PMRX = 0x00000080, 986 FW_CAPS_CONFIG_HM_PMTX = 0x00000100, 987 FW_CAPS_CONFIG_HM_MC = 0x00000200, 988 FW_CAPS_CONFIG_HM_LE = 0x00000400, 989 FW_CAPS_CONFIG_HM_MPS = 0x00000800, 990 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, 991 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, 992 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, 993 FW_CAPS_CONFIG_HM_MI = 0x00008000, 994 FW_CAPS_CONFIG_HM_I2CM = 0x00010000, 995 FW_CAPS_CONFIG_HM_NCSI = 0x00020000, 996 FW_CAPS_CONFIG_HM_SMB = 0x00040000, 997 FW_CAPS_CONFIG_HM_MA = 0x00080000, 998 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, 999 FW_CAPS_CONFIG_HM_PMU = 0x00200000, 1000 FW_CAPS_CONFIG_HM_UART = 0x00400000, 1001 FW_CAPS_CONFIG_HM_SF = 0x00800000, 1002 }; 1003 1004 enum fw_caps_config_nbm { 1005 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, 1006 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, 1007 }; 1008 1009 enum fw_caps_config_link { 1010 FW_CAPS_CONFIG_LINK_PPP = 0x00000001, 1011 FW_CAPS_CONFIG_LINK_QFC = 0x00000002, 1012 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, 1013 }; 1014 1015 enum fw_caps_config_switch { 1016 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, 1017 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, 1018 }; 1019 1020 enum fw_caps_config_nic { 1021 FW_CAPS_CONFIG_NIC = 0x00000001, 1022 FW_CAPS_CONFIG_NIC_VM = 0x00000002, 1023 }; 1024 1025 enum fw_caps_config_ofld { 1026 FW_CAPS_CONFIG_OFLD = 0x00000001, 1027 }; 1028 1029 enum fw_caps_config_rdma { 1030 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, 1031 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, 1032 }; 1033 1034 enum fw_caps_config_iscsi { 1035 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, 1036 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, 1037 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, 1038 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, 1039 }; 1040 1041 enum fw_caps_config_fcoe { 1042 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 1043 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 1044 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 1045 }; 1046 1047 enum fw_memtype_cf { 1048 FW_MEMTYPE_CF_EDC0 = 0x0, 1049 FW_MEMTYPE_CF_EDC1 = 0x1, 1050 FW_MEMTYPE_CF_EXTMEM = 0x2, 1051 FW_MEMTYPE_CF_FLASH = 0x4, 1052 FW_MEMTYPE_CF_INTERNAL = 0x5, 1053 FW_MEMTYPE_CF_EXTMEM1 = 0x6, 1054 }; 1055 1056 struct fw_caps_config_cmd { 1057 __be32 op_to_write; 1058 __be32 cfvalid_to_len16; 1059 __be32 r2; 1060 __be32 hwmbitmap; 1061 __be16 nbmcaps; 1062 __be16 linkcaps; 1063 __be16 switchcaps; 1064 __be16 r3; 1065 __be16 niccaps; 1066 __be16 ofldcaps; 1067 __be16 rdmacaps; 1068 __be16 cryptocaps; 1069 __be16 iscsicaps; 1070 __be16 fcoecaps; 1071 __be32 cfcsum; 1072 __be32 finiver; 1073 __be32 finicsum; 1074 }; 1075 1076 #define FW_CAPS_CONFIG_CMD_CFVALID_S 27 1077 #define FW_CAPS_CONFIG_CMD_CFVALID_V(x) ((x) << FW_CAPS_CONFIG_CMD_CFVALID_S) 1078 #define FW_CAPS_CONFIG_CMD_CFVALID_F FW_CAPS_CONFIG_CMD_CFVALID_V(1U) 1079 1080 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S 24 1081 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(x) \ 1082 ((x) << FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S) 1083 1084 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S 16 1085 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(x) \ 1086 ((x) << FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S) 1087 1088 /* 1089 * params command mnemonics 1090 */ 1091 enum fw_params_mnem { 1092 FW_PARAMS_MNEM_DEV = 1, /* device params */ 1093 FW_PARAMS_MNEM_PFVF = 2, /* function params */ 1094 FW_PARAMS_MNEM_REG = 3, /* limited register access */ 1095 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 1096 FW_PARAMS_MNEM_CHNET = 5, /* chnet params */ 1097 FW_PARAMS_MNEM_LAST 1098 }; 1099 1100 /* 1101 * device parameters 1102 */ 1103 enum fw_params_param_dev { 1104 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 1105 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 1106 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs 1107 * allocated by the device's 1108 * Lookup Engine 1109 */ 1110 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, 1111 FW_PARAMS_PARAM_DEV_INTVER_NIC = 0x04, 1112 FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05, 1113 FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06, 1114 FW_PARAMS_PARAM_DEV_INTVER_RI = 0x07, 1115 FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08, 1116 FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09, 1117 FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A, 1118 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, 1119 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, 1120 FW_PARAMS_PARAM_DEV_CF = 0x0D, 1121 FW_PARAMS_PARAM_DEV_PHYFW = 0x0F, 1122 FW_PARAMS_PARAM_DEV_DIAG = 0x11, 1123 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD */ 1124 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER = 0x14, /* max supported adap IRD */ 1125 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, 1126 FW_PARAMS_PARAM_DEV_FWCACHE = 0x18, 1127 FW_PARAMS_PARAM_DEV_SCFGREV = 0x1A, 1128 FW_PARAMS_PARAM_DEV_VPDREV = 0x1B, 1129 FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR = 0x1C, 1130 FW_PARAMS_PARAM_DEV_MPSBGMAP = 0x1E, 1131 }; 1132 1133 /* 1134 * physical and virtual function parameters 1135 */ 1136 enum fw_params_param_pfvf { 1137 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, 1138 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, 1139 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, 1140 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 1141 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 1142 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 1143 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 1144 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, 1145 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, 1146 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, 1147 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, 1148 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, 1149 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, 1150 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, 1151 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, 1152 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, 1153 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, 1154 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, 1155 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, 1156 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 1157 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 1158 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15, 1159 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16, 1160 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17, 1161 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18, 1162 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, 1163 FW_PARAMS_PARAM_PFVF_VIID = 0x24, 1164 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 1165 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 1166 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 1167 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 1168 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 1169 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 1170 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, 1171 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 1172 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 1173 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, 1174 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30, 1175 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31, 1176 FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x32, 1177 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A, 1178 }; 1179 1180 /* 1181 * dma queue parameters 1182 */ 1183 enum fw_params_param_dmaq { 1184 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 1185 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 1186 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 1187 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 1188 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, 1189 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13, 1190 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20, 1191 }; 1192 1193 enum fw_params_param_dev_phyfw { 1194 FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00, 1195 FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01, 1196 }; 1197 1198 enum fw_params_param_dev_diag { 1199 FW_PARAM_DEV_DIAG_TMP = 0x00, 1200 FW_PARAM_DEV_DIAG_VDD = 0x01, 1201 }; 1202 1203 enum fw_params_param_dev_fwcache { 1204 FW_PARAM_DEV_FWCACHE_FLUSH = 0x00, 1205 FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01, 1206 }; 1207 1208 #define FW_PARAMS_MNEM_S 24 1209 #define FW_PARAMS_MNEM_V(x) ((x) << FW_PARAMS_MNEM_S) 1210 1211 #define FW_PARAMS_PARAM_X_S 16 1212 #define FW_PARAMS_PARAM_X_V(x) ((x) << FW_PARAMS_PARAM_X_S) 1213 1214 #define FW_PARAMS_PARAM_Y_S 8 1215 #define FW_PARAMS_PARAM_Y_M 0xffU 1216 #define FW_PARAMS_PARAM_Y_V(x) ((x) << FW_PARAMS_PARAM_Y_S) 1217 #define FW_PARAMS_PARAM_Y_G(x) (((x) >> FW_PARAMS_PARAM_Y_S) &\ 1218 FW_PARAMS_PARAM_Y_M) 1219 1220 #define FW_PARAMS_PARAM_Z_S 0 1221 #define FW_PARAMS_PARAM_Z_M 0xffu 1222 #define FW_PARAMS_PARAM_Z_V(x) ((x) << FW_PARAMS_PARAM_Z_S) 1223 #define FW_PARAMS_PARAM_Z_G(x) (((x) >> FW_PARAMS_PARAM_Z_S) &\ 1224 FW_PARAMS_PARAM_Z_M) 1225 1226 #define FW_PARAMS_PARAM_XYZ_S 0 1227 #define FW_PARAMS_PARAM_XYZ_V(x) ((x) << FW_PARAMS_PARAM_XYZ_S) 1228 1229 #define FW_PARAMS_PARAM_YZ_S 0 1230 #define FW_PARAMS_PARAM_YZ_V(x) ((x) << FW_PARAMS_PARAM_YZ_S) 1231 1232 struct fw_params_cmd { 1233 __be32 op_to_vfn; 1234 __be32 retval_len16; 1235 struct fw_params_param { 1236 __be32 mnem; 1237 __be32 val; 1238 } param[7]; 1239 }; 1240 1241 #define FW_PARAMS_CMD_PFN_S 8 1242 #define FW_PARAMS_CMD_PFN_V(x) ((x) << FW_PARAMS_CMD_PFN_S) 1243 1244 #define FW_PARAMS_CMD_VFN_S 0 1245 #define FW_PARAMS_CMD_VFN_V(x) ((x) << FW_PARAMS_CMD_VFN_S) 1246 1247 struct fw_pfvf_cmd { 1248 __be32 op_to_vfn; 1249 __be32 retval_len16; 1250 __be32 niqflint_niq; 1251 __be32 type_to_neq; 1252 __be32 tc_to_nexactf; 1253 __be32 r_caps_to_nethctrl; 1254 __be16 nricq; 1255 __be16 nriqp; 1256 __be32 r4; 1257 }; 1258 1259 #define FW_PFVF_CMD_PFN_S 8 1260 #define FW_PFVF_CMD_PFN_V(x) ((x) << FW_PFVF_CMD_PFN_S) 1261 1262 #define FW_PFVF_CMD_VFN_S 0 1263 #define FW_PFVF_CMD_VFN_V(x) ((x) << FW_PFVF_CMD_VFN_S) 1264 1265 #define FW_PFVF_CMD_NIQFLINT_S 20 1266 #define FW_PFVF_CMD_NIQFLINT_M 0xfff 1267 #define FW_PFVF_CMD_NIQFLINT_V(x) ((x) << FW_PFVF_CMD_NIQFLINT_S) 1268 #define FW_PFVF_CMD_NIQFLINT_G(x) \ 1269 (((x) >> FW_PFVF_CMD_NIQFLINT_S) & FW_PFVF_CMD_NIQFLINT_M) 1270 1271 #define FW_PFVF_CMD_NIQ_S 0 1272 #define FW_PFVF_CMD_NIQ_M 0xfffff 1273 #define FW_PFVF_CMD_NIQ_V(x) ((x) << FW_PFVF_CMD_NIQ_S) 1274 #define FW_PFVF_CMD_NIQ_G(x) \ 1275 (((x) >> FW_PFVF_CMD_NIQ_S) & FW_PFVF_CMD_NIQ_M) 1276 1277 #define FW_PFVF_CMD_TYPE_S 31 1278 #define FW_PFVF_CMD_TYPE_M 0x1 1279 #define FW_PFVF_CMD_TYPE_V(x) ((x) << FW_PFVF_CMD_TYPE_S) 1280 #define FW_PFVF_CMD_TYPE_G(x) \ 1281 (((x) >> FW_PFVF_CMD_TYPE_S) & FW_PFVF_CMD_TYPE_M) 1282 #define FW_PFVF_CMD_TYPE_F FW_PFVF_CMD_TYPE_V(1U) 1283 1284 #define FW_PFVF_CMD_CMASK_S 24 1285 #define FW_PFVF_CMD_CMASK_M 0xf 1286 #define FW_PFVF_CMD_CMASK_V(x) ((x) << FW_PFVF_CMD_CMASK_S) 1287 #define FW_PFVF_CMD_CMASK_G(x) \ 1288 (((x) >> FW_PFVF_CMD_CMASK_S) & FW_PFVF_CMD_CMASK_M) 1289 1290 #define FW_PFVF_CMD_PMASK_S 20 1291 #define FW_PFVF_CMD_PMASK_M 0xf 1292 #define FW_PFVF_CMD_PMASK_V(x) ((x) << FW_PFVF_CMD_PMASK_S) 1293 #define FW_PFVF_CMD_PMASK_G(x) \ 1294 (((x) >> FW_PFVF_CMD_PMASK_S) & FW_PFVF_CMD_PMASK_M) 1295 1296 #define FW_PFVF_CMD_NEQ_S 0 1297 #define FW_PFVF_CMD_NEQ_M 0xfffff 1298 #define FW_PFVF_CMD_NEQ_V(x) ((x) << FW_PFVF_CMD_NEQ_S) 1299 #define FW_PFVF_CMD_NEQ_G(x) \ 1300 (((x) >> FW_PFVF_CMD_NEQ_S) & FW_PFVF_CMD_NEQ_M) 1301 1302 #define FW_PFVF_CMD_TC_S 24 1303 #define FW_PFVF_CMD_TC_M 0xff 1304 #define FW_PFVF_CMD_TC_V(x) ((x) << FW_PFVF_CMD_TC_S) 1305 #define FW_PFVF_CMD_TC_G(x) (((x) >> FW_PFVF_CMD_TC_S) & FW_PFVF_CMD_TC_M) 1306 1307 #define FW_PFVF_CMD_NVI_S 16 1308 #define FW_PFVF_CMD_NVI_M 0xff 1309 #define FW_PFVF_CMD_NVI_V(x) ((x) << FW_PFVF_CMD_NVI_S) 1310 #define FW_PFVF_CMD_NVI_G(x) (((x) >> FW_PFVF_CMD_NVI_S) & FW_PFVF_CMD_NVI_M) 1311 1312 #define FW_PFVF_CMD_NEXACTF_S 0 1313 #define FW_PFVF_CMD_NEXACTF_M 0xffff 1314 #define FW_PFVF_CMD_NEXACTF_V(x) ((x) << FW_PFVF_CMD_NEXACTF_S) 1315 #define FW_PFVF_CMD_NEXACTF_G(x) \ 1316 (((x) >> FW_PFVF_CMD_NEXACTF_S) & FW_PFVF_CMD_NEXACTF_M) 1317 1318 #define FW_PFVF_CMD_R_CAPS_S 24 1319 #define FW_PFVF_CMD_R_CAPS_M 0xff 1320 #define FW_PFVF_CMD_R_CAPS_V(x) ((x) << FW_PFVF_CMD_R_CAPS_S) 1321 #define FW_PFVF_CMD_R_CAPS_G(x) \ 1322 (((x) >> FW_PFVF_CMD_R_CAPS_S) & FW_PFVF_CMD_R_CAPS_M) 1323 1324 #define FW_PFVF_CMD_WX_CAPS_S 16 1325 #define FW_PFVF_CMD_WX_CAPS_M 0xff 1326 #define FW_PFVF_CMD_WX_CAPS_V(x) ((x) << FW_PFVF_CMD_WX_CAPS_S) 1327 #define FW_PFVF_CMD_WX_CAPS_G(x) \ 1328 (((x) >> FW_PFVF_CMD_WX_CAPS_S) & FW_PFVF_CMD_WX_CAPS_M) 1329 1330 #define FW_PFVF_CMD_NETHCTRL_S 0 1331 #define FW_PFVF_CMD_NETHCTRL_M 0xffff 1332 #define FW_PFVF_CMD_NETHCTRL_V(x) ((x) << FW_PFVF_CMD_NETHCTRL_S) 1333 #define FW_PFVF_CMD_NETHCTRL_G(x) \ 1334 (((x) >> FW_PFVF_CMD_NETHCTRL_S) & FW_PFVF_CMD_NETHCTRL_M) 1335 1336 enum fw_iq_type { 1337 FW_IQ_TYPE_FL_INT_CAP, 1338 FW_IQ_TYPE_NO_FL_INT_CAP 1339 }; 1340 1341 struct fw_iq_cmd { 1342 __be32 op_to_vfn; 1343 __be32 alloc_to_len16; 1344 __be16 physiqid; 1345 __be16 iqid; 1346 __be16 fl0id; 1347 __be16 fl1id; 1348 __be32 type_to_iqandstindex; 1349 __be16 iqdroprss_to_iqesize; 1350 __be16 iqsize; 1351 __be64 iqaddr; 1352 __be32 iqns_to_fl0congen; 1353 __be16 fl0dcaen_to_fl0cidxfthresh; 1354 __be16 fl0size; 1355 __be64 fl0addr; 1356 __be32 fl1cngchmap_to_fl1congen; 1357 __be16 fl1dcaen_to_fl1cidxfthresh; 1358 __be16 fl1size; 1359 __be64 fl1addr; 1360 }; 1361 1362 #define FW_IQ_CMD_PFN_S 8 1363 #define FW_IQ_CMD_PFN_V(x) ((x) << FW_IQ_CMD_PFN_S) 1364 1365 #define FW_IQ_CMD_VFN_S 0 1366 #define FW_IQ_CMD_VFN_V(x) ((x) << FW_IQ_CMD_VFN_S) 1367 1368 #define FW_IQ_CMD_ALLOC_S 31 1369 #define FW_IQ_CMD_ALLOC_V(x) ((x) << FW_IQ_CMD_ALLOC_S) 1370 #define FW_IQ_CMD_ALLOC_F FW_IQ_CMD_ALLOC_V(1U) 1371 1372 #define FW_IQ_CMD_FREE_S 30 1373 #define FW_IQ_CMD_FREE_V(x) ((x) << FW_IQ_CMD_FREE_S) 1374 #define FW_IQ_CMD_FREE_F FW_IQ_CMD_FREE_V(1U) 1375 1376 #define FW_IQ_CMD_MODIFY_S 29 1377 #define FW_IQ_CMD_MODIFY_V(x) ((x) << FW_IQ_CMD_MODIFY_S) 1378 #define FW_IQ_CMD_MODIFY_F FW_IQ_CMD_MODIFY_V(1U) 1379 1380 #define FW_IQ_CMD_IQSTART_S 28 1381 #define FW_IQ_CMD_IQSTART_V(x) ((x) << FW_IQ_CMD_IQSTART_S) 1382 #define FW_IQ_CMD_IQSTART_F FW_IQ_CMD_IQSTART_V(1U) 1383 1384 #define FW_IQ_CMD_IQSTOP_S 27 1385 #define FW_IQ_CMD_IQSTOP_V(x) ((x) << FW_IQ_CMD_IQSTOP_S) 1386 #define FW_IQ_CMD_IQSTOP_F FW_IQ_CMD_IQSTOP_V(1U) 1387 1388 #define FW_IQ_CMD_TYPE_S 29 1389 #define FW_IQ_CMD_TYPE_V(x) ((x) << FW_IQ_CMD_TYPE_S) 1390 1391 #define FW_IQ_CMD_IQASYNCH_S 28 1392 #define FW_IQ_CMD_IQASYNCH_V(x) ((x) << FW_IQ_CMD_IQASYNCH_S) 1393 1394 #define FW_IQ_CMD_VIID_S 16 1395 #define FW_IQ_CMD_VIID_V(x) ((x) << FW_IQ_CMD_VIID_S) 1396 1397 #define FW_IQ_CMD_IQANDST_S 15 1398 #define FW_IQ_CMD_IQANDST_V(x) ((x) << FW_IQ_CMD_IQANDST_S) 1399 1400 #define FW_IQ_CMD_IQANUS_S 14 1401 #define FW_IQ_CMD_IQANUS_V(x) ((x) << FW_IQ_CMD_IQANUS_S) 1402 1403 #define FW_IQ_CMD_IQANUD_S 12 1404 #define FW_IQ_CMD_IQANUD_V(x) ((x) << FW_IQ_CMD_IQANUD_S) 1405 1406 #define FW_IQ_CMD_IQANDSTINDEX_S 0 1407 #define FW_IQ_CMD_IQANDSTINDEX_V(x) ((x) << FW_IQ_CMD_IQANDSTINDEX_S) 1408 1409 #define FW_IQ_CMD_IQDROPRSS_S 15 1410 #define FW_IQ_CMD_IQDROPRSS_V(x) ((x) << FW_IQ_CMD_IQDROPRSS_S) 1411 #define FW_IQ_CMD_IQDROPRSS_F FW_IQ_CMD_IQDROPRSS_V(1U) 1412 1413 #define FW_IQ_CMD_IQGTSMODE_S 14 1414 #define FW_IQ_CMD_IQGTSMODE_V(x) ((x) << FW_IQ_CMD_IQGTSMODE_S) 1415 #define FW_IQ_CMD_IQGTSMODE_F FW_IQ_CMD_IQGTSMODE_V(1U) 1416 1417 #define FW_IQ_CMD_IQPCIECH_S 12 1418 #define FW_IQ_CMD_IQPCIECH_V(x) ((x) << FW_IQ_CMD_IQPCIECH_S) 1419 1420 #define FW_IQ_CMD_IQDCAEN_S 11 1421 #define FW_IQ_CMD_IQDCAEN_V(x) ((x) << FW_IQ_CMD_IQDCAEN_S) 1422 1423 #define FW_IQ_CMD_IQDCACPU_S 6 1424 #define FW_IQ_CMD_IQDCACPU_V(x) ((x) << FW_IQ_CMD_IQDCACPU_S) 1425 1426 #define FW_IQ_CMD_IQINTCNTTHRESH_S 4 1427 #define FW_IQ_CMD_IQINTCNTTHRESH_V(x) ((x) << FW_IQ_CMD_IQINTCNTTHRESH_S) 1428 1429 #define FW_IQ_CMD_IQO_S 3 1430 #define FW_IQ_CMD_IQO_V(x) ((x) << FW_IQ_CMD_IQO_S) 1431 #define FW_IQ_CMD_IQO_F FW_IQ_CMD_IQO_V(1U) 1432 1433 #define FW_IQ_CMD_IQCPRIO_S 2 1434 #define FW_IQ_CMD_IQCPRIO_V(x) ((x) << FW_IQ_CMD_IQCPRIO_S) 1435 1436 #define FW_IQ_CMD_IQESIZE_S 0 1437 #define FW_IQ_CMD_IQESIZE_V(x) ((x) << FW_IQ_CMD_IQESIZE_S) 1438 1439 #define FW_IQ_CMD_IQNS_S 31 1440 #define FW_IQ_CMD_IQNS_V(x) ((x) << FW_IQ_CMD_IQNS_S) 1441 1442 #define FW_IQ_CMD_IQRO_S 30 1443 #define FW_IQ_CMD_IQRO_V(x) ((x) << FW_IQ_CMD_IQRO_S) 1444 1445 #define FW_IQ_CMD_IQFLINTIQHSEN_S 28 1446 #define FW_IQ_CMD_IQFLINTIQHSEN_V(x) ((x) << FW_IQ_CMD_IQFLINTIQHSEN_S) 1447 1448 #define FW_IQ_CMD_IQFLINTCONGEN_S 27 1449 #define FW_IQ_CMD_IQFLINTCONGEN_V(x) ((x) << FW_IQ_CMD_IQFLINTCONGEN_S) 1450 #define FW_IQ_CMD_IQFLINTCONGEN_F FW_IQ_CMD_IQFLINTCONGEN_V(1U) 1451 1452 #define FW_IQ_CMD_IQFLINTISCSIC_S 26 1453 #define FW_IQ_CMD_IQFLINTISCSIC_V(x) ((x) << FW_IQ_CMD_IQFLINTISCSIC_S) 1454 1455 #define FW_IQ_CMD_FL0CNGCHMAP_S 20 1456 #define FW_IQ_CMD_FL0CNGCHMAP_V(x) ((x) << FW_IQ_CMD_FL0CNGCHMAP_S) 1457 1458 #define FW_IQ_CMD_FL0CACHELOCK_S 15 1459 #define FW_IQ_CMD_FL0CACHELOCK_V(x) ((x) << FW_IQ_CMD_FL0CACHELOCK_S) 1460 1461 #define FW_IQ_CMD_FL0DBP_S 14 1462 #define FW_IQ_CMD_FL0DBP_V(x) ((x) << FW_IQ_CMD_FL0DBP_S) 1463 1464 #define FW_IQ_CMD_FL0DATANS_S 13 1465 #define FW_IQ_CMD_FL0DATANS_V(x) ((x) << FW_IQ_CMD_FL0DATANS_S) 1466 1467 #define FW_IQ_CMD_FL0DATARO_S 12 1468 #define FW_IQ_CMD_FL0DATARO_V(x) ((x) << FW_IQ_CMD_FL0DATARO_S) 1469 #define FW_IQ_CMD_FL0DATARO_F FW_IQ_CMD_FL0DATARO_V(1U) 1470 1471 #define FW_IQ_CMD_FL0CONGCIF_S 11 1472 #define FW_IQ_CMD_FL0CONGCIF_V(x) ((x) << FW_IQ_CMD_FL0CONGCIF_S) 1473 #define FW_IQ_CMD_FL0CONGCIF_F FW_IQ_CMD_FL0CONGCIF_V(1U) 1474 1475 #define FW_IQ_CMD_FL0ONCHIP_S 10 1476 #define FW_IQ_CMD_FL0ONCHIP_V(x) ((x) << FW_IQ_CMD_FL0ONCHIP_S) 1477 1478 #define FW_IQ_CMD_FL0STATUSPGNS_S 9 1479 #define FW_IQ_CMD_FL0STATUSPGNS_V(x) ((x) << FW_IQ_CMD_FL0STATUSPGNS_S) 1480 1481 #define FW_IQ_CMD_FL0STATUSPGRO_S 8 1482 #define FW_IQ_CMD_FL0STATUSPGRO_V(x) ((x) << FW_IQ_CMD_FL0STATUSPGRO_S) 1483 1484 #define FW_IQ_CMD_FL0FETCHNS_S 7 1485 #define FW_IQ_CMD_FL0FETCHNS_V(x) ((x) << FW_IQ_CMD_FL0FETCHNS_S) 1486 1487 #define FW_IQ_CMD_FL0FETCHRO_S 6 1488 #define FW_IQ_CMD_FL0FETCHRO_V(x) ((x) << FW_IQ_CMD_FL0FETCHRO_S) 1489 #define FW_IQ_CMD_FL0FETCHRO_F FW_IQ_CMD_FL0FETCHRO_V(1U) 1490 1491 #define FW_IQ_CMD_FL0HOSTFCMODE_S 4 1492 #define FW_IQ_CMD_FL0HOSTFCMODE_V(x) ((x) << FW_IQ_CMD_FL0HOSTFCMODE_S) 1493 1494 #define FW_IQ_CMD_FL0CPRIO_S 3 1495 #define FW_IQ_CMD_FL0CPRIO_V(x) ((x) << FW_IQ_CMD_FL0CPRIO_S) 1496 1497 #define FW_IQ_CMD_FL0PADEN_S 2 1498 #define FW_IQ_CMD_FL0PADEN_V(x) ((x) << FW_IQ_CMD_FL0PADEN_S) 1499 #define FW_IQ_CMD_FL0PADEN_F FW_IQ_CMD_FL0PADEN_V(1U) 1500 1501 #define FW_IQ_CMD_FL0PACKEN_S 1 1502 #define FW_IQ_CMD_FL0PACKEN_V(x) ((x) << FW_IQ_CMD_FL0PACKEN_S) 1503 #define FW_IQ_CMD_FL0PACKEN_F FW_IQ_CMD_FL0PACKEN_V(1U) 1504 1505 #define FW_IQ_CMD_FL0CONGEN_S 0 1506 #define FW_IQ_CMD_FL0CONGEN_V(x) ((x) << FW_IQ_CMD_FL0CONGEN_S) 1507 #define FW_IQ_CMD_FL0CONGEN_F FW_IQ_CMD_FL0CONGEN_V(1U) 1508 1509 #define FW_IQ_CMD_FL0DCAEN_S 15 1510 #define FW_IQ_CMD_FL0DCAEN_V(x) ((x) << FW_IQ_CMD_FL0DCAEN_S) 1511 1512 #define FW_IQ_CMD_FL0DCACPU_S 10 1513 #define FW_IQ_CMD_FL0DCACPU_V(x) ((x) << FW_IQ_CMD_FL0DCACPU_S) 1514 1515 #define FW_IQ_CMD_FL0FBMIN_S 7 1516 #define FW_IQ_CMD_FL0FBMIN_V(x) ((x) << FW_IQ_CMD_FL0FBMIN_S) 1517 1518 #define FW_IQ_CMD_FL0FBMAX_S 4 1519 #define FW_IQ_CMD_FL0FBMAX_V(x) ((x) << FW_IQ_CMD_FL0FBMAX_S) 1520 1521 #define FW_IQ_CMD_FL0CIDXFTHRESHO_S 3 1522 #define FW_IQ_CMD_FL0CIDXFTHRESHO_V(x) ((x) << FW_IQ_CMD_FL0CIDXFTHRESHO_S) 1523 #define FW_IQ_CMD_FL0CIDXFTHRESHO_F FW_IQ_CMD_FL0CIDXFTHRESHO_V(1U) 1524 1525 #define FW_IQ_CMD_FL0CIDXFTHRESH_S 0 1526 #define FW_IQ_CMD_FL0CIDXFTHRESH_V(x) ((x) << FW_IQ_CMD_FL0CIDXFTHRESH_S) 1527 1528 #define FW_IQ_CMD_FL1CNGCHMAP_S 20 1529 #define FW_IQ_CMD_FL1CNGCHMAP_V(x) ((x) << FW_IQ_CMD_FL1CNGCHMAP_S) 1530 1531 #define FW_IQ_CMD_FL1CACHELOCK_S 15 1532 #define FW_IQ_CMD_FL1CACHELOCK_V(x) ((x) << FW_IQ_CMD_FL1CACHELOCK_S) 1533 1534 #define FW_IQ_CMD_FL1DBP_S 14 1535 #define FW_IQ_CMD_FL1DBP_V(x) ((x) << FW_IQ_CMD_FL1DBP_S) 1536 1537 #define FW_IQ_CMD_FL1DATANS_S 13 1538 #define FW_IQ_CMD_FL1DATANS_V(x) ((x) << FW_IQ_CMD_FL1DATANS_S) 1539 1540 #define FW_IQ_CMD_FL1DATARO_S 12 1541 #define FW_IQ_CMD_FL1DATARO_V(x) ((x) << FW_IQ_CMD_FL1DATARO_S) 1542 1543 #define FW_IQ_CMD_FL1CONGCIF_S 11 1544 #define FW_IQ_CMD_FL1CONGCIF_V(x) ((x) << FW_IQ_CMD_FL1CONGCIF_S) 1545 1546 #define FW_IQ_CMD_FL1ONCHIP_S 10 1547 #define FW_IQ_CMD_FL1ONCHIP_V(x) ((x) << FW_IQ_CMD_FL1ONCHIP_S) 1548 1549 #define FW_IQ_CMD_FL1STATUSPGNS_S 9 1550 #define FW_IQ_CMD_FL1STATUSPGNS_V(x) ((x) << FW_IQ_CMD_FL1STATUSPGNS_S) 1551 1552 #define FW_IQ_CMD_FL1STATUSPGRO_S 8 1553 #define FW_IQ_CMD_FL1STATUSPGRO_V(x) ((x) << FW_IQ_CMD_FL1STATUSPGRO_S) 1554 1555 #define FW_IQ_CMD_FL1FETCHNS_S 7 1556 #define FW_IQ_CMD_FL1FETCHNS_V(x) ((x) << FW_IQ_CMD_FL1FETCHNS_S) 1557 1558 #define FW_IQ_CMD_FL1FETCHRO_S 6 1559 #define FW_IQ_CMD_FL1FETCHRO_V(x) ((x) << FW_IQ_CMD_FL1FETCHRO_S) 1560 1561 #define FW_IQ_CMD_FL1HOSTFCMODE_S 4 1562 #define FW_IQ_CMD_FL1HOSTFCMODE_V(x) ((x) << FW_IQ_CMD_FL1HOSTFCMODE_S) 1563 1564 #define FW_IQ_CMD_FL1CPRIO_S 3 1565 #define FW_IQ_CMD_FL1CPRIO_V(x) ((x) << FW_IQ_CMD_FL1CPRIO_S) 1566 1567 #define FW_IQ_CMD_FL1PADEN_S 2 1568 #define FW_IQ_CMD_FL1PADEN_V(x) ((x) << FW_IQ_CMD_FL1PADEN_S) 1569 #define FW_IQ_CMD_FL1PADEN_F FW_IQ_CMD_FL1PADEN_V(1U) 1570 1571 #define FW_IQ_CMD_FL1PACKEN_S 1 1572 #define FW_IQ_CMD_FL1PACKEN_V(x) ((x) << FW_IQ_CMD_FL1PACKEN_S) 1573 #define FW_IQ_CMD_FL1PACKEN_F FW_IQ_CMD_FL1PACKEN_V(1U) 1574 1575 #define FW_IQ_CMD_FL1CONGEN_S 0 1576 #define FW_IQ_CMD_FL1CONGEN_V(x) ((x) << FW_IQ_CMD_FL1CONGEN_S) 1577 #define FW_IQ_CMD_FL1CONGEN_F FW_IQ_CMD_FL1CONGEN_V(1U) 1578 1579 #define FW_IQ_CMD_FL1DCAEN_S 15 1580 #define FW_IQ_CMD_FL1DCAEN_V(x) ((x) << FW_IQ_CMD_FL1DCAEN_S) 1581 1582 #define FW_IQ_CMD_FL1DCACPU_S 10 1583 #define FW_IQ_CMD_FL1DCACPU_V(x) ((x) << FW_IQ_CMD_FL1DCACPU_S) 1584 1585 #define FW_IQ_CMD_FL1FBMIN_S 7 1586 #define FW_IQ_CMD_FL1FBMIN_V(x) ((x) << FW_IQ_CMD_FL1FBMIN_S) 1587 1588 #define FW_IQ_CMD_FL1FBMAX_S 4 1589 #define FW_IQ_CMD_FL1FBMAX_V(x) ((x) << FW_IQ_CMD_FL1FBMAX_S) 1590 1591 #define FW_IQ_CMD_FL1CIDXFTHRESHO_S 3 1592 #define FW_IQ_CMD_FL1CIDXFTHRESHO_V(x) ((x) << FW_IQ_CMD_FL1CIDXFTHRESHO_S) 1593 #define FW_IQ_CMD_FL1CIDXFTHRESHO_F FW_IQ_CMD_FL1CIDXFTHRESHO_V(1U) 1594 1595 #define FW_IQ_CMD_FL1CIDXFTHRESH_S 0 1596 #define FW_IQ_CMD_FL1CIDXFTHRESH_V(x) ((x) << FW_IQ_CMD_FL1CIDXFTHRESH_S) 1597 1598 struct fw_eq_eth_cmd { 1599 __be32 op_to_vfn; 1600 __be32 alloc_to_len16; 1601 __be32 eqid_pkd; 1602 __be32 physeqid_pkd; 1603 __be32 fetchszm_to_iqid; 1604 __be32 dcaen_to_eqsize; 1605 __be64 eqaddr; 1606 __be32 viid_pkd; 1607 __be32 r8_lo; 1608 __be64 r9; 1609 }; 1610 1611 #define FW_EQ_ETH_CMD_PFN_S 8 1612 #define FW_EQ_ETH_CMD_PFN_V(x) ((x) << FW_EQ_ETH_CMD_PFN_S) 1613 1614 #define FW_EQ_ETH_CMD_VFN_S 0 1615 #define FW_EQ_ETH_CMD_VFN_V(x) ((x) << FW_EQ_ETH_CMD_VFN_S) 1616 1617 #define FW_EQ_ETH_CMD_ALLOC_S 31 1618 #define FW_EQ_ETH_CMD_ALLOC_V(x) ((x) << FW_EQ_ETH_CMD_ALLOC_S) 1619 #define FW_EQ_ETH_CMD_ALLOC_F FW_EQ_ETH_CMD_ALLOC_V(1U) 1620 1621 #define FW_EQ_ETH_CMD_FREE_S 30 1622 #define FW_EQ_ETH_CMD_FREE_V(x) ((x) << FW_EQ_ETH_CMD_FREE_S) 1623 #define FW_EQ_ETH_CMD_FREE_F FW_EQ_ETH_CMD_FREE_V(1U) 1624 1625 #define FW_EQ_ETH_CMD_MODIFY_S 29 1626 #define FW_EQ_ETH_CMD_MODIFY_V(x) ((x) << FW_EQ_ETH_CMD_MODIFY_S) 1627 #define FW_EQ_ETH_CMD_MODIFY_F FW_EQ_ETH_CMD_MODIFY_V(1U) 1628 1629 #define FW_EQ_ETH_CMD_EQSTART_S 28 1630 #define FW_EQ_ETH_CMD_EQSTART_V(x) ((x) << FW_EQ_ETH_CMD_EQSTART_S) 1631 #define FW_EQ_ETH_CMD_EQSTART_F FW_EQ_ETH_CMD_EQSTART_V(1U) 1632 1633 #define FW_EQ_ETH_CMD_EQSTOP_S 27 1634 #define FW_EQ_ETH_CMD_EQSTOP_V(x) ((x) << FW_EQ_ETH_CMD_EQSTOP_S) 1635 #define FW_EQ_ETH_CMD_EQSTOP_F FW_EQ_ETH_CMD_EQSTOP_V(1U) 1636 1637 #define FW_EQ_ETH_CMD_EQID_S 0 1638 #define FW_EQ_ETH_CMD_EQID_M 0xfffff 1639 #define FW_EQ_ETH_CMD_EQID_V(x) ((x) << FW_EQ_ETH_CMD_EQID_S) 1640 #define FW_EQ_ETH_CMD_EQID_G(x) \ 1641 (((x) >> FW_EQ_ETH_CMD_EQID_S) & FW_EQ_ETH_CMD_EQID_M) 1642 1643 #define FW_EQ_ETH_CMD_PHYSEQID_S 0 1644 #define FW_EQ_ETH_CMD_PHYSEQID_M 0xfffff 1645 #define FW_EQ_ETH_CMD_PHYSEQID_V(x) ((x) << FW_EQ_ETH_CMD_PHYSEQID_S) 1646 #define FW_EQ_ETH_CMD_PHYSEQID_G(x) \ 1647 (((x) >> FW_EQ_ETH_CMD_PHYSEQID_S) & FW_EQ_ETH_CMD_PHYSEQID_M) 1648 1649 #define FW_EQ_ETH_CMD_FETCHSZM_S 26 1650 #define FW_EQ_ETH_CMD_FETCHSZM_V(x) ((x) << FW_EQ_ETH_CMD_FETCHSZM_S) 1651 #define FW_EQ_ETH_CMD_FETCHSZM_F FW_EQ_ETH_CMD_FETCHSZM_V(1U) 1652 1653 #define FW_EQ_ETH_CMD_STATUSPGNS_S 25 1654 #define FW_EQ_ETH_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_ETH_CMD_STATUSPGNS_S) 1655 1656 #define FW_EQ_ETH_CMD_STATUSPGRO_S 24 1657 #define FW_EQ_ETH_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_ETH_CMD_STATUSPGRO_S) 1658 1659 #define FW_EQ_ETH_CMD_FETCHNS_S 23 1660 #define FW_EQ_ETH_CMD_FETCHNS_V(x) ((x) << FW_EQ_ETH_CMD_FETCHNS_S) 1661 1662 #define FW_EQ_ETH_CMD_FETCHRO_S 22 1663 #define FW_EQ_ETH_CMD_FETCHRO_V(x) ((x) << FW_EQ_ETH_CMD_FETCHRO_S) 1664 #define FW_EQ_ETH_CMD_FETCHRO_F FW_EQ_ETH_CMD_FETCHRO_V(1U) 1665 1666 #define FW_EQ_ETH_CMD_HOSTFCMODE_S 20 1667 #define FW_EQ_ETH_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_ETH_CMD_HOSTFCMODE_S) 1668 1669 #define FW_EQ_ETH_CMD_CPRIO_S 19 1670 #define FW_EQ_ETH_CMD_CPRIO_V(x) ((x) << FW_EQ_ETH_CMD_CPRIO_S) 1671 1672 #define FW_EQ_ETH_CMD_ONCHIP_S 18 1673 #define FW_EQ_ETH_CMD_ONCHIP_V(x) ((x) << FW_EQ_ETH_CMD_ONCHIP_S) 1674 1675 #define FW_EQ_ETH_CMD_PCIECHN_S 16 1676 #define FW_EQ_ETH_CMD_PCIECHN_V(x) ((x) << FW_EQ_ETH_CMD_PCIECHN_S) 1677 1678 #define FW_EQ_ETH_CMD_IQID_S 0 1679 #define FW_EQ_ETH_CMD_IQID_V(x) ((x) << FW_EQ_ETH_CMD_IQID_S) 1680 1681 #define FW_EQ_ETH_CMD_DCAEN_S 31 1682 #define FW_EQ_ETH_CMD_DCAEN_V(x) ((x) << FW_EQ_ETH_CMD_DCAEN_S) 1683 1684 #define FW_EQ_ETH_CMD_DCACPU_S 26 1685 #define FW_EQ_ETH_CMD_DCACPU_V(x) ((x) << FW_EQ_ETH_CMD_DCACPU_S) 1686 1687 #define FW_EQ_ETH_CMD_FBMIN_S 23 1688 #define FW_EQ_ETH_CMD_FBMIN_V(x) ((x) << FW_EQ_ETH_CMD_FBMIN_S) 1689 1690 #define FW_EQ_ETH_CMD_FBMAX_S 20 1691 #define FW_EQ_ETH_CMD_FBMAX_V(x) ((x) << FW_EQ_ETH_CMD_FBMAX_S) 1692 1693 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_S 19 1694 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESHO_S) 1695 1696 #define FW_EQ_ETH_CMD_CIDXFTHRESH_S 16 1697 #define FW_EQ_ETH_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESH_S) 1698 1699 #define FW_EQ_ETH_CMD_EQSIZE_S 0 1700 #define FW_EQ_ETH_CMD_EQSIZE_V(x) ((x) << FW_EQ_ETH_CMD_EQSIZE_S) 1701 1702 #define FW_EQ_ETH_CMD_AUTOEQUEQE_S 30 1703 #define FW_EQ_ETH_CMD_AUTOEQUEQE_V(x) ((x) << FW_EQ_ETH_CMD_AUTOEQUEQE_S) 1704 #define FW_EQ_ETH_CMD_AUTOEQUEQE_F FW_EQ_ETH_CMD_AUTOEQUEQE_V(1U) 1705 1706 #define FW_EQ_ETH_CMD_VIID_S 16 1707 #define FW_EQ_ETH_CMD_VIID_V(x) ((x) << FW_EQ_ETH_CMD_VIID_S) 1708 1709 struct fw_eq_ctrl_cmd { 1710 __be32 op_to_vfn; 1711 __be32 alloc_to_len16; 1712 __be32 cmpliqid_eqid; 1713 __be32 physeqid_pkd; 1714 __be32 fetchszm_to_iqid; 1715 __be32 dcaen_to_eqsize; 1716 __be64 eqaddr; 1717 }; 1718 1719 #define FW_EQ_CTRL_CMD_PFN_S 8 1720 #define FW_EQ_CTRL_CMD_PFN_V(x) ((x) << FW_EQ_CTRL_CMD_PFN_S) 1721 1722 #define FW_EQ_CTRL_CMD_VFN_S 0 1723 #define FW_EQ_CTRL_CMD_VFN_V(x) ((x) << FW_EQ_CTRL_CMD_VFN_S) 1724 1725 #define FW_EQ_CTRL_CMD_ALLOC_S 31 1726 #define FW_EQ_CTRL_CMD_ALLOC_V(x) ((x) << FW_EQ_CTRL_CMD_ALLOC_S) 1727 #define FW_EQ_CTRL_CMD_ALLOC_F FW_EQ_CTRL_CMD_ALLOC_V(1U) 1728 1729 #define FW_EQ_CTRL_CMD_FREE_S 30 1730 #define FW_EQ_CTRL_CMD_FREE_V(x) ((x) << FW_EQ_CTRL_CMD_FREE_S) 1731 #define FW_EQ_CTRL_CMD_FREE_F FW_EQ_CTRL_CMD_FREE_V(1U) 1732 1733 #define FW_EQ_CTRL_CMD_MODIFY_S 29 1734 #define FW_EQ_CTRL_CMD_MODIFY_V(x) ((x) << FW_EQ_CTRL_CMD_MODIFY_S) 1735 #define FW_EQ_CTRL_CMD_MODIFY_F FW_EQ_CTRL_CMD_MODIFY_V(1U) 1736 1737 #define FW_EQ_CTRL_CMD_EQSTART_S 28 1738 #define FW_EQ_CTRL_CMD_EQSTART_V(x) ((x) << FW_EQ_CTRL_CMD_EQSTART_S) 1739 #define FW_EQ_CTRL_CMD_EQSTART_F FW_EQ_CTRL_CMD_EQSTART_V(1U) 1740 1741 #define FW_EQ_CTRL_CMD_EQSTOP_S 27 1742 #define FW_EQ_CTRL_CMD_EQSTOP_V(x) ((x) << FW_EQ_CTRL_CMD_EQSTOP_S) 1743 #define FW_EQ_CTRL_CMD_EQSTOP_F FW_EQ_CTRL_CMD_EQSTOP_V(1U) 1744 1745 #define FW_EQ_CTRL_CMD_CMPLIQID_S 20 1746 #define FW_EQ_CTRL_CMD_CMPLIQID_V(x) ((x) << FW_EQ_CTRL_CMD_CMPLIQID_S) 1747 1748 #define FW_EQ_CTRL_CMD_EQID_S 0 1749 #define FW_EQ_CTRL_CMD_EQID_M 0xfffff 1750 #define FW_EQ_CTRL_CMD_EQID_V(x) ((x) << FW_EQ_CTRL_CMD_EQID_S) 1751 #define FW_EQ_CTRL_CMD_EQID_G(x) \ 1752 (((x) >> FW_EQ_CTRL_CMD_EQID_S) & FW_EQ_CTRL_CMD_EQID_M) 1753 1754 #define FW_EQ_CTRL_CMD_PHYSEQID_S 0 1755 #define FW_EQ_CTRL_CMD_PHYSEQID_M 0xfffff 1756 #define FW_EQ_CTRL_CMD_PHYSEQID_G(x) \ 1757 (((x) >> FW_EQ_CTRL_CMD_PHYSEQID_S) & FW_EQ_CTRL_CMD_PHYSEQID_M) 1758 1759 #define FW_EQ_CTRL_CMD_FETCHSZM_S 26 1760 #define FW_EQ_CTRL_CMD_FETCHSZM_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHSZM_S) 1761 #define FW_EQ_CTRL_CMD_FETCHSZM_F FW_EQ_CTRL_CMD_FETCHSZM_V(1U) 1762 1763 #define FW_EQ_CTRL_CMD_STATUSPGNS_S 25 1764 #define FW_EQ_CTRL_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_CTRL_CMD_STATUSPGNS_S) 1765 #define FW_EQ_CTRL_CMD_STATUSPGNS_F FW_EQ_CTRL_CMD_STATUSPGNS_V(1U) 1766 1767 #define FW_EQ_CTRL_CMD_STATUSPGRO_S 24 1768 #define FW_EQ_CTRL_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_CTRL_CMD_STATUSPGRO_S) 1769 #define FW_EQ_CTRL_CMD_STATUSPGRO_F FW_EQ_CTRL_CMD_STATUSPGRO_V(1U) 1770 1771 #define FW_EQ_CTRL_CMD_FETCHNS_S 23 1772 #define FW_EQ_CTRL_CMD_FETCHNS_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHNS_S) 1773 #define FW_EQ_CTRL_CMD_FETCHNS_F FW_EQ_CTRL_CMD_FETCHNS_V(1U) 1774 1775 #define FW_EQ_CTRL_CMD_FETCHRO_S 22 1776 #define FW_EQ_CTRL_CMD_FETCHRO_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHRO_S) 1777 #define FW_EQ_CTRL_CMD_FETCHRO_F FW_EQ_CTRL_CMD_FETCHRO_V(1U) 1778 1779 #define FW_EQ_CTRL_CMD_HOSTFCMODE_S 20 1780 #define FW_EQ_CTRL_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_CTRL_CMD_HOSTFCMODE_S) 1781 1782 #define FW_EQ_CTRL_CMD_CPRIO_S 19 1783 #define FW_EQ_CTRL_CMD_CPRIO_V(x) ((x) << FW_EQ_CTRL_CMD_CPRIO_S) 1784 1785 #define FW_EQ_CTRL_CMD_ONCHIP_S 18 1786 #define FW_EQ_CTRL_CMD_ONCHIP_V(x) ((x) << FW_EQ_CTRL_CMD_ONCHIP_S) 1787 1788 #define FW_EQ_CTRL_CMD_PCIECHN_S 16 1789 #define FW_EQ_CTRL_CMD_PCIECHN_V(x) ((x) << FW_EQ_CTRL_CMD_PCIECHN_S) 1790 1791 #define FW_EQ_CTRL_CMD_IQID_S 0 1792 #define FW_EQ_CTRL_CMD_IQID_V(x) ((x) << FW_EQ_CTRL_CMD_IQID_S) 1793 1794 #define FW_EQ_CTRL_CMD_DCAEN_S 31 1795 #define FW_EQ_CTRL_CMD_DCAEN_V(x) ((x) << FW_EQ_CTRL_CMD_DCAEN_S) 1796 1797 #define FW_EQ_CTRL_CMD_DCACPU_S 26 1798 #define FW_EQ_CTRL_CMD_DCACPU_V(x) ((x) << FW_EQ_CTRL_CMD_DCACPU_S) 1799 1800 #define FW_EQ_CTRL_CMD_FBMIN_S 23 1801 #define FW_EQ_CTRL_CMD_FBMIN_V(x) ((x) << FW_EQ_CTRL_CMD_FBMIN_S) 1802 1803 #define FW_EQ_CTRL_CMD_FBMAX_S 20 1804 #define FW_EQ_CTRL_CMD_FBMAX_V(x) ((x) << FW_EQ_CTRL_CMD_FBMAX_S) 1805 1806 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_S 19 1807 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_V(x) \ 1808 ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESHO_S) 1809 1810 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_S 16 1811 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESH_S) 1812 1813 #define FW_EQ_CTRL_CMD_EQSIZE_S 0 1814 #define FW_EQ_CTRL_CMD_EQSIZE_V(x) ((x) << FW_EQ_CTRL_CMD_EQSIZE_S) 1815 1816 struct fw_eq_ofld_cmd { 1817 __be32 op_to_vfn; 1818 __be32 alloc_to_len16; 1819 __be32 eqid_pkd; 1820 __be32 physeqid_pkd; 1821 __be32 fetchszm_to_iqid; 1822 __be32 dcaen_to_eqsize; 1823 __be64 eqaddr; 1824 }; 1825 1826 #define FW_EQ_OFLD_CMD_PFN_S 8 1827 #define FW_EQ_OFLD_CMD_PFN_V(x) ((x) << FW_EQ_OFLD_CMD_PFN_S) 1828 1829 #define FW_EQ_OFLD_CMD_VFN_S 0 1830 #define FW_EQ_OFLD_CMD_VFN_V(x) ((x) << FW_EQ_OFLD_CMD_VFN_S) 1831 1832 #define FW_EQ_OFLD_CMD_ALLOC_S 31 1833 #define FW_EQ_OFLD_CMD_ALLOC_V(x) ((x) << FW_EQ_OFLD_CMD_ALLOC_S) 1834 #define FW_EQ_OFLD_CMD_ALLOC_F FW_EQ_OFLD_CMD_ALLOC_V(1U) 1835 1836 #define FW_EQ_OFLD_CMD_FREE_S 30 1837 #define FW_EQ_OFLD_CMD_FREE_V(x) ((x) << FW_EQ_OFLD_CMD_FREE_S) 1838 #define FW_EQ_OFLD_CMD_FREE_F FW_EQ_OFLD_CMD_FREE_V(1U) 1839 1840 #define FW_EQ_OFLD_CMD_MODIFY_S 29 1841 #define FW_EQ_OFLD_CMD_MODIFY_V(x) ((x) << FW_EQ_OFLD_CMD_MODIFY_S) 1842 #define FW_EQ_OFLD_CMD_MODIFY_F FW_EQ_OFLD_CMD_MODIFY_V(1U) 1843 1844 #define FW_EQ_OFLD_CMD_EQSTART_S 28 1845 #define FW_EQ_OFLD_CMD_EQSTART_V(x) ((x) << FW_EQ_OFLD_CMD_EQSTART_S) 1846 #define FW_EQ_OFLD_CMD_EQSTART_F FW_EQ_OFLD_CMD_EQSTART_V(1U) 1847 1848 #define FW_EQ_OFLD_CMD_EQSTOP_S 27 1849 #define FW_EQ_OFLD_CMD_EQSTOP_V(x) ((x) << FW_EQ_OFLD_CMD_EQSTOP_S) 1850 #define FW_EQ_OFLD_CMD_EQSTOP_F FW_EQ_OFLD_CMD_EQSTOP_V(1U) 1851 1852 #define FW_EQ_OFLD_CMD_EQID_S 0 1853 #define FW_EQ_OFLD_CMD_EQID_M 0xfffff 1854 #define FW_EQ_OFLD_CMD_EQID_V(x) ((x) << FW_EQ_OFLD_CMD_EQID_S) 1855 #define FW_EQ_OFLD_CMD_EQID_G(x) \ 1856 (((x) >> FW_EQ_OFLD_CMD_EQID_S) & FW_EQ_OFLD_CMD_EQID_M) 1857 1858 #define FW_EQ_OFLD_CMD_PHYSEQID_S 0 1859 #define FW_EQ_OFLD_CMD_PHYSEQID_M 0xfffff 1860 #define FW_EQ_OFLD_CMD_PHYSEQID_G(x) \ 1861 (((x) >> FW_EQ_OFLD_CMD_PHYSEQID_S) & FW_EQ_OFLD_CMD_PHYSEQID_M) 1862 1863 #define FW_EQ_OFLD_CMD_FETCHSZM_S 26 1864 #define FW_EQ_OFLD_CMD_FETCHSZM_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHSZM_S) 1865 1866 #define FW_EQ_OFLD_CMD_STATUSPGNS_S 25 1867 #define FW_EQ_OFLD_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_OFLD_CMD_STATUSPGNS_S) 1868 1869 #define FW_EQ_OFLD_CMD_STATUSPGRO_S 24 1870 #define FW_EQ_OFLD_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_OFLD_CMD_STATUSPGRO_S) 1871 1872 #define FW_EQ_OFLD_CMD_FETCHNS_S 23 1873 #define FW_EQ_OFLD_CMD_FETCHNS_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHNS_S) 1874 1875 #define FW_EQ_OFLD_CMD_FETCHRO_S 22 1876 #define FW_EQ_OFLD_CMD_FETCHRO_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHRO_S) 1877 #define FW_EQ_OFLD_CMD_FETCHRO_F FW_EQ_OFLD_CMD_FETCHRO_V(1U) 1878 1879 #define FW_EQ_OFLD_CMD_HOSTFCMODE_S 20 1880 #define FW_EQ_OFLD_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_OFLD_CMD_HOSTFCMODE_S) 1881 1882 #define FW_EQ_OFLD_CMD_CPRIO_S 19 1883 #define FW_EQ_OFLD_CMD_CPRIO_V(x) ((x) << FW_EQ_OFLD_CMD_CPRIO_S) 1884 1885 #define FW_EQ_OFLD_CMD_ONCHIP_S 18 1886 #define FW_EQ_OFLD_CMD_ONCHIP_V(x) ((x) << FW_EQ_OFLD_CMD_ONCHIP_S) 1887 1888 #define FW_EQ_OFLD_CMD_PCIECHN_S 16 1889 #define FW_EQ_OFLD_CMD_PCIECHN_V(x) ((x) << FW_EQ_OFLD_CMD_PCIECHN_S) 1890 1891 #define FW_EQ_OFLD_CMD_IQID_S 0 1892 #define FW_EQ_OFLD_CMD_IQID_V(x) ((x) << FW_EQ_OFLD_CMD_IQID_S) 1893 1894 #define FW_EQ_OFLD_CMD_DCAEN_S 31 1895 #define FW_EQ_OFLD_CMD_DCAEN_V(x) ((x) << FW_EQ_OFLD_CMD_DCAEN_S) 1896 1897 #define FW_EQ_OFLD_CMD_DCACPU_S 26 1898 #define FW_EQ_OFLD_CMD_DCACPU_V(x) ((x) << FW_EQ_OFLD_CMD_DCACPU_S) 1899 1900 #define FW_EQ_OFLD_CMD_FBMIN_S 23 1901 #define FW_EQ_OFLD_CMD_FBMIN_V(x) ((x) << FW_EQ_OFLD_CMD_FBMIN_S) 1902 1903 #define FW_EQ_OFLD_CMD_FBMAX_S 20 1904 #define FW_EQ_OFLD_CMD_FBMAX_V(x) ((x) << FW_EQ_OFLD_CMD_FBMAX_S) 1905 1906 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_S 19 1907 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_V(x) \ 1908 ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESHO_S) 1909 1910 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_S 16 1911 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESH_S) 1912 1913 #define FW_EQ_OFLD_CMD_EQSIZE_S 0 1914 #define FW_EQ_OFLD_CMD_EQSIZE_V(x) ((x) << FW_EQ_OFLD_CMD_EQSIZE_S) 1915 1916 /* 1917 * Macros for VIID parsing: 1918 * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number 1919 */ 1920 1921 #define FW_VIID_PFN_S 8 1922 #define FW_VIID_PFN_M 0x7 1923 #define FW_VIID_PFN_G(x) (((x) >> FW_VIID_PFN_S) & FW_VIID_PFN_M) 1924 1925 #define FW_VIID_VIVLD_S 7 1926 #define FW_VIID_VIVLD_M 0x1 1927 #define FW_VIID_VIVLD_G(x) (((x) >> FW_VIID_VIVLD_S) & FW_VIID_VIVLD_M) 1928 1929 #define FW_VIID_VIN_S 0 1930 #define FW_VIID_VIN_M 0x7F 1931 #define FW_VIID_VIN_G(x) (((x) >> FW_VIID_VIN_S) & FW_VIID_VIN_M) 1932 1933 struct fw_vi_cmd { 1934 __be32 op_to_vfn; 1935 __be32 alloc_to_len16; 1936 __be16 type_viid; 1937 u8 mac[6]; 1938 u8 portid_pkd; 1939 u8 nmac; 1940 u8 nmac0[6]; 1941 __be16 rsssize_pkd; 1942 u8 nmac1[6]; 1943 __be16 idsiiq_pkd; 1944 u8 nmac2[6]; 1945 __be16 idseiq_pkd; 1946 u8 nmac3[6]; 1947 __be64 r9; 1948 __be64 r10; 1949 }; 1950 1951 #define FW_VI_CMD_PFN_S 8 1952 #define FW_VI_CMD_PFN_V(x) ((x) << FW_VI_CMD_PFN_S) 1953 1954 #define FW_VI_CMD_VFN_S 0 1955 #define FW_VI_CMD_VFN_V(x) ((x) << FW_VI_CMD_VFN_S) 1956 1957 #define FW_VI_CMD_ALLOC_S 31 1958 #define FW_VI_CMD_ALLOC_V(x) ((x) << FW_VI_CMD_ALLOC_S) 1959 #define FW_VI_CMD_ALLOC_F FW_VI_CMD_ALLOC_V(1U) 1960 1961 #define FW_VI_CMD_FREE_S 30 1962 #define FW_VI_CMD_FREE_V(x) ((x) << FW_VI_CMD_FREE_S) 1963 #define FW_VI_CMD_FREE_F FW_VI_CMD_FREE_V(1U) 1964 1965 #define FW_VI_CMD_VIID_S 0 1966 #define FW_VI_CMD_VIID_M 0xfff 1967 #define FW_VI_CMD_VIID_V(x) ((x) << FW_VI_CMD_VIID_S) 1968 #define FW_VI_CMD_VIID_G(x) (((x) >> FW_VI_CMD_VIID_S) & FW_VI_CMD_VIID_M) 1969 1970 #define FW_VI_CMD_PORTID_S 4 1971 #define FW_VI_CMD_PORTID_M 0xf 1972 #define FW_VI_CMD_PORTID_V(x) ((x) << FW_VI_CMD_PORTID_S) 1973 #define FW_VI_CMD_PORTID_G(x) \ 1974 (((x) >> FW_VI_CMD_PORTID_S) & FW_VI_CMD_PORTID_M) 1975 1976 #define FW_VI_CMD_RSSSIZE_S 0 1977 #define FW_VI_CMD_RSSSIZE_M 0x7ff 1978 #define FW_VI_CMD_RSSSIZE_G(x) \ 1979 (((x) >> FW_VI_CMD_RSSSIZE_S) & FW_VI_CMD_RSSSIZE_M) 1980 1981 /* Special VI_MAC command index ids */ 1982 #define FW_VI_MAC_ADD_MAC 0x3FF 1983 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 1984 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD 1985 #define FW_CLS_TCAM_NUM_ENTRIES 336 1986 1987 enum fw_vi_mac_smac { 1988 FW_VI_MAC_MPS_TCAM_ENTRY, 1989 FW_VI_MAC_MPS_TCAM_ONLY, 1990 FW_VI_MAC_SMT_ONLY, 1991 FW_VI_MAC_SMT_AND_MPSTCAM 1992 }; 1993 1994 enum fw_vi_mac_result { 1995 FW_VI_MAC_R_SUCCESS, 1996 FW_VI_MAC_R_F_NONEXISTENT_NOMEM, 1997 FW_VI_MAC_R_SMAC_FAIL, 1998 FW_VI_MAC_R_F_ACL_CHECK 1999 }; 2000 2001 struct fw_vi_mac_cmd { 2002 __be32 op_to_viid; 2003 __be32 freemacs_to_len16; 2004 union fw_vi_mac { 2005 struct fw_vi_mac_exact { 2006 __be16 valid_to_idx; 2007 u8 macaddr[6]; 2008 } exact[7]; 2009 struct fw_vi_mac_hash { 2010 __be64 hashvec; 2011 } hash; 2012 } u; 2013 }; 2014 2015 #define FW_VI_MAC_CMD_VIID_S 0 2016 #define FW_VI_MAC_CMD_VIID_V(x) ((x) << FW_VI_MAC_CMD_VIID_S) 2017 2018 #define FW_VI_MAC_CMD_FREEMACS_S 31 2019 #define FW_VI_MAC_CMD_FREEMACS_V(x) ((x) << FW_VI_MAC_CMD_FREEMACS_S) 2020 2021 #define FW_VI_MAC_CMD_HASHVECEN_S 23 2022 #define FW_VI_MAC_CMD_HASHVECEN_V(x) ((x) << FW_VI_MAC_CMD_HASHVECEN_S) 2023 #define FW_VI_MAC_CMD_HASHVECEN_F FW_VI_MAC_CMD_HASHVECEN_V(1U) 2024 2025 #define FW_VI_MAC_CMD_HASHUNIEN_S 22 2026 #define FW_VI_MAC_CMD_HASHUNIEN_V(x) ((x) << FW_VI_MAC_CMD_HASHUNIEN_S) 2027 2028 #define FW_VI_MAC_CMD_VALID_S 15 2029 #define FW_VI_MAC_CMD_VALID_V(x) ((x) << FW_VI_MAC_CMD_VALID_S) 2030 #define FW_VI_MAC_CMD_VALID_F FW_VI_MAC_CMD_VALID_V(1U) 2031 2032 #define FW_VI_MAC_CMD_PRIO_S 12 2033 #define FW_VI_MAC_CMD_PRIO_V(x) ((x) << FW_VI_MAC_CMD_PRIO_S) 2034 2035 #define FW_VI_MAC_CMD_SMAC_RESULT_S 10 2036 #define FW_VI_MAC_CMD_SMAC_RESULT_M 0x3 2037 #define FW_VI_MAC_CMD_SMAC_RESULT_V(x) ((x) << FW_VI_MAC_CMD_SMAC_RESULT_S) 2038 #define FW_VI_MAC_CMD_SMAC_RESULT_G(x) \ 2039 (((x) >> FW_VI_MAC_CMD_SMAC_RESULT_S) & FW_VI_MAC_CMD_SMAC_RESULT_M) 2040 2041 #define FW_VI_MAC_CMD_IDX_S 0 2042 #define FW_VI_MAC_CMD_IDX_M 0x3ff 2043 #define FW_VI_MAC_CMD_IDX_V(x) ((x) << FW_VI_MAC_CMD_IDX_S) 2044 #define FW_VI_MAC_CMD_IDX_G(x) \ 2045 (((x) >> FW_VI_MAC_CMD_IDX_S) & FW_VI_MAC_CMD_IDX_M) 2046 2047 #define FW_RXMODE_MTU_NO_CHG 65535 2048 2049 struct fw_vi_rxmode_cmd { 2050 __be32 op_to_viid; 2051 __be32 retval_len16; 2052 __be32 mtu_to_vlanexen; 2053 __be32 r4_lo; 2054 }; 2055 2056 #define FW_VI_RXMODE_CMD_VIID_S 0 2057 #define FW_VI_RXMODE_CMD_VIID_V(x) ((x) << FW_VI_RXMODE_CMD_VIID_S) 2058 2059 #define FW_VI_RXMODE_CMD_MTU_S 16 2060 #define FW_VI_RXMODE_CMD_MTU_M 0xffff 2061 #define FW_VI_RXMODE_CMD_MTU_V(x) ((x) << FW_VI_RXMODE_CMD_MTU_S) 2062 2063 #define FW_VI_RXMODE_CMD_PROMISCEN_S 14 2064 #define FW_VI_RXMODE_CMD_PROMISCEN_M 0x3 2065 #define FW_VI_RXMODE_CMD_PROMISCEN_V(x) ((x) << FW_VI_RXMODE_CMD_PROMISCEN_S) 2066 2067 #define FW_VI_RXMODE_CMD_ALLMULTIEN_S 12 2068 #define FW_VI_RXMODE_CMD_ALLMULTIEN_M 0x3 2069 #define FW_VI_RXMODE_CMD_ALLMULTIEN_V(x) \ 2070 ((x) << FW_VI_RXMODE_CMD_ALLMULTIEN_S) 2071 2072 #define FW_VI_RXMODE_CMD_BROADCASTEN_S 10 2073 #define FW_VI_RXMODE_CMD_BROADCASTEN_M 0x3 2074 #define FW_VI_RXMODE_CMD_BROADCASTEN_V(x) \ 2075 ((x) << FW_VI_RXMODE_CMD_BROADCASTEN_S) 2076 2077 #define FW_VI_RXMODE_CMD_VLANEXEN_S 8 2078 #define FW_VI_RXMODE_CMD_VLANEXEN_M 0x3 2079 #define FW_VI_RXMODE_CMD_VLANEXEN_V(x) ((x) << FW_VI_RXMODE_CMD_VLANEXEN_S) 2080 2081 struct fw_vi_enable_cmd { 2082 __be32 op_to_viid; 2083 __be32 ien_to_len16; 2084 __be16 blinkdur; 2085 __be16 r3; 2086 __be32 r4; 2087 }; 2088 2089 #define FW_VI_ENABLE_CMD_VIID_S 0 2090 #define FW_VI_ENABLE_CMD_VIID_V(x) ((x) << FW_VI_ENABLE_CMD_VIID_S) 2091 2092 #define FW_VI_ENABLE_CMD_IEN_S 31 2093 #define FW_VI_ENABLE_CMD_IEN_V(x) ((x) << FW_VI_ENABLE_CMD_IEN_S) 2094 2095 #define FW_VI_ENABLE_CMD_EEN_S 30 2096 #define FW_VI_ENABLE_CMD_EEN_V(x) ((x) << FW_VI_ENABLE_CMD_EEN_S) 2097 2098 #define FW_VI_ENABLE_CMD_LED_S 29 2099 #define FW_VI_ENABLE_CMD_LED_V(x) ((x) << FW_VI_ENABLE_CMD_LED_S) 2100 #define FW_VI_ENABLE_CMD_LED_F FW_VI_ENABLE_CMD_LED_V(1U) 2101 2102 #define FW_VI_ENABLE_CMD_DCB_INFO_S 28 2103 #define FW_VI_ENABLE_CMD_DCB_INFO_V(x) ((x) << FW_VI_ENABLE_CMD_DCB_INFO_S) 2104 2105 /* VI VF stats offset definitions */ 2106 #define VI_VF_NUM_STATS 16 2107 enum fw_vi_stats_vf_index { 2108 FW_VI_VF_STAT_TX_BCAST_BYTES_IX, 2109 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, 2110 FW_VI_VF_STAT_TX_MCAST_BYTES_IX, 2111 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, 2112 FW_VI_VF_STAT_TX_UCAST_BYTES_IX, 2113 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, 2114 FW_VI_VF_STAT_TX_DROP_FRAMES_IX, 2115 FW_VI_VF_STAT_TX_OFLD_BYTES_IX, 2116 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, 2117 FW_VI_VF_STAT_RX_BCAST_BYTES_IX, 2118 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, 2119 FW_VI_VF_STAT_RX_MCAST_BYTES_IX, 2120 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, 2121 FW_VI_VF_STAT_RX_UCAST_BYTES_IX, 2122 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, 2123 FW_VI_VF_STAT_RX_ERR_FRAMES_IX 2124 }; 2125 2126 /* VI PF stats offset definitions */ 2127 #define VI_PF_NUM_STATS 17 2128 enum fw_vi_stats_pf_index { 2129 FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 2130 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 2131 FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 2132 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 2133 FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 2134 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 2135 FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 2136 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 2137 FW_VI_PF_STAT_RX_BYTES_IX, 2138 FW_VI_PF_STAT_RX_FRAMES_IX, 2139 FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 2140 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 2141 FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 2142 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 2143 FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 2144 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 2145 FW_VI_PF_STAT_RX_ERR_FRAMES_IX 2146 }; 2147 2148 struct fw_vi_stats_cmd { 2149 __be32 op_to_viid; 2150 __be32 retval_len16; 2151 union fw_vi_stats { 2152 struct fw_vi_stats_ctl { 2153 __be16 nstats_ix; 2154 __be16 r6; 2155 __be32 r7; 2156 __be64 stat0; 2157 __be64 stat1; 2158 __be64 stat2; 2159 __be64 stat3; 2160 __be64 stat4; 2161 __be64 stat5; 2162 } ctl; 2163 struct fw_vi_stats_pf { 2164 __be64 tx_bcast_bytes; 2165 __be64 tx_bcast_frames; 2166 __be64 tx_mcast_bytes; 2167 __be64 tx_mcast_frames; 2168 __be64 tx_ucast_bytes; 2169 __be64 tx_ucast_frames; 2170 __be64 tx_offload_bytes; 2171 __be64 tx_offload_frames; 2172 __be64 rx_pf_bytes; 2173 __be64 rx_pf_frames; 2174 __be64 rx_bcast_bytes; 2175 __be64 rx_bcast_frames; 2176 __be64 rx_mcast_bytes; 2177 __be64 rx_mcast_frames; 2178 __be64 rx_ucast_bytes; 2179 __be64 rx_ucast_frames; 2180 __be64 rx_err_frames; 2181 } pf; 2182 struct fw_vi_stats_vf { 2183 __be64 tx_bcast_bytes; 2184 __be64 tx_bcast_frames; 2185 __be64 tx_mcast_bytes; 2186 __be64 tx_mcast_frames; 2187 __be64 tx_ucast_bytes; 2188 __be64 tx_ucast_frames; 2189 __be64 tx_drop_frames; 2190 __be64 tx_offload_bytes; 2191 __be64 tx_offload_frames; 2192 __be64 rx_bcast_bytes; 2193 __be64 rx_bcast_frames; 2194 __be64 rx_mcast_bytes; 2195 __be64 rx_mcast_frames; 2196 __be64 rx_ucast_bytes; 2197 __be64 rx_ucast_frames; 2198 __be64 rx_err_frames; 2199 } vf; 2200 } u; 2201 }; 2202 2203 #define FW_VI_STATS_CMD_VIID_S 0 2204 #define FW_VI_STATS_CMD_VIID_V(x) ((x) << FW_VI_STATS_CMD_VIID_S) 2205 2206 #define FW_VI_STATS_CMD_NSTATS_S 12 2207 #define FW_VI_STATS_CMD_NSTATS_V(x) ((x) << FW_VI_STATS_CMD_NSTATS_S) 2208 2209 #define FW_VI_STATS_CMD_IX_S 0 2210 #define FW_VI_STATS_CMD_IX_V(x) ((x) << FW_VI_STATS_CMD_IX_S) 2211 2212 struct fw_acl_mac_cmd { 2213 __be32 op_to_vfn; 2214 __be32 en_to_len16; 2215 u8 nmac; 2216 u8 r3[7]; 2217 __be16 r4; 2218 u8 macaddr0[6]; 2219 __be16 r5; 2220 u8 macaddr1[6]; 2221 __be16 r6; 2222 u8 macaddr2[6]; 2223 __be16 r7; 2224 u8 macaddr3[6]; 2225 }; 2226 2227 #define FW_ACL_MAC_CMD_PFN_S 8 2228 #define FW_ACL_MAC_CMD_PFN_V(x) ((x) << FW_ACL_MAC_CMD_PFN_S) 2229 2230 #define FW_ACL_MAC_CMD_VFN_S 0 2231 #define FW_ACL_MAC_CMD_VFN_V(x) ((x) << FW_ACL_MAC_CMD_VFN_S) 2232 2233 #define FW_ACL_MAC_CMD_EN_S 31 2234 #define FW_ACL_MAC_CMD_EN_V(x) ((x) << FW_ACL_MAC_CMD_EN_S) 2235 2236 struct fw_acl_vlan_cmd { 2237 __be32 op_to_vfn; 2238 __be32 en_to_len16; 2239 u8 nvlan; 2240 u8 dropnovlan_fm; 2241 u8 r3_lo[6]; 2242 __be16 vlanid[16]; 2243 }; 2244 2245 #define FW_ACL_VLAN_CMD_PFN_S 8 2246 #define FW_ACL_VLAN_CMD_PFN_V(x) ((x) << FW_ACL_VLAN_CMD_PFN_S) 2247 2248 #define FW_ACL_VLAN_CMD_VFN_S 0 2249 #define FW_ACL_VLAN_CMD_VFN_V(x) ((x) << FW_ACL_VLAN_CMD_VFN_S) 2250 2251 #define FW_ACL_VLAN_CMD_EN_S 31 2252 #define FW_ACL_VLAN_CMD_EN_V(x) ((x) << FW_ACL_VLAN_CMD_EN_S) 2253 2254 #define FW_ACL_VLAN_CMD_DROPNOVLAN_S 7 2255 #define FW_ACL_VLAN_CMD_DROPNOVLAN_V(x) ((x) << FW_ACL_VLAN_CMD_DROPNOVLAN_S) 2256 2257 #define FW_ACL_VLAN_CMD_FM_S 6 2258 #define FW_ACL_VLAN_CMD_FM_V(x) ((x) << FW_ACL_VLAN_CMD_FM_S) 2259 2260 /* old 16-bit port capabilities bitmap (fw_port_cap16_t) */ 2261 enum fw_port_cap { 2262 FW_PORT_CAP_SPEED_100M = 0x0001, 2263 FW_PORT_CAP_SPEED_1G = 0x0002, 2264 FW_PORT_CAP_SPEED_25G = 0x0004, 2265 FW_PORT_CAP_SPEED_10G = 0x0008, 2266 FW_PORT_CAP_SPEED_40G = 0x0010, 2267 FW_PORT_CAP_SPEED_100G = 0x0020, 2268 FW_PORT_CAP_FC_RX = 0x0040, 2269 FW_PORT_CAP_FC_TX = 0x0080, 2270 FW_PORT_CAP_ANEG = 0x0100, 2271 FW_PORT_CAP_MDIX = 0x0200, 2272 FW_PORT_CAP_MDIAUTO = 0x0400, 2273 FW_PORT_CAP_FEC_RS = 0x0800, 2274 FW_PORT_CAP_FEC_BASER_RS = 0x1000, 2275 FW_PORT_CAP_FEC_RESERVED = 0x2000, 2276 FW_PORT_CAP_802_3_PAUSE = 0x4000, 2277 FW_PORT_CAP_802_3_ASM_DIR = 0x8000, 2278 }; 2279 2280 #define FW_PORT_CAP_SPEED_S 0 2281 #define FW_PORT_CAP_SPEED_M 0x3f 2282 #define FW_PORT_CAP_SPEED_V(x) ((x) << FW_PORT_CAP_SPEED_S) 2283 #define FW_PORT_CAP_SPEED_G(x) \ 2284 (((x) >> FW_PORT_CAP_SPEED_S) & FW_PORT_CAP_SPEED_M) 2285 2286 enum fw_port_mdi { 2287 FW_PORT_CAP_MDI_UNCHANGED, 2288 FW_PORT_CAP_MDI_AUTO, 2289 FW_PORT_CAP_MDI_F_STRAIGHT, 2290 FW_PORT_CAP_MDI_F_CROSSOVER 2291 }; 2292 2293 #define FW_PORT_CAP_MDI_S 9 2294 #define FW_PORT_CAP_MDI_V(x) ((x) << FW_PORT_CAP_MDI_S) 2295 2296 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */ 2297 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL 2298 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL 2299 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL 2300 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL 2301 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL 2302 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL 2303 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL 2304 #define FW_PORT_CAP32_SPEED_200G 0x00000080UL 2305 #define FW_PORT_CAP32_SPEED_400G 0x00000100UL 2306 #define FW_PORT_CAP32_SPEED_RESERVED1 0x00000200UL 2307 #define FW_PORT_CAP32_SPEED_RESERVED2 0x00000400UL 2308 #define FW_PORT_CAP32_SPEED_RESERVED3 0x00000800UL 2309 #define FW_PORT_CAP32_RESERVED1 0x0000f000UL 2310 #define FW_PORT_CAP32_FC_RX 0x00010000UL 2311 #define FW_PORT_CAP32_FC_TX 0x00020000UL 2312 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL 2313 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL 2314 #define FW_PORT_CAP32_ANEG 0x00100000UL 2315 #define FW_PORT_CAP32_MDIX 0x00200000UL 2316 #define FW_PORT_CAP32_MDIAUTO 0x00400000UL 2317 #define FW_PORT_CAP32_FEC_RS 0x00800000UL 2318 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL 2319 #define FW_PORT_CAP32_FEC_RESERVED1 0x02000000UL 2320 #define FW_PORT_CAP32_FEC_RESERVED2 0x04000000UL 2321 #define FW_PORT_CAP32_FEC_RESERVED3 0x08000000UL 2322 #define FW_PORT_CAP32_RESERVED2 0xf0000000UL 2323 2324 #define FW_PORT_CAP32_SPEED_S 0 2325 #define FW_PORT_CAP32_SPEED_M 0xfff 2326 #define FW_PORT_CAP32_SPEED_V(x) ((x) << FW_PORT_CAP32_SPEED_S) 2327 #define FW_PORT_CAP32_SPEED_G(x) \ 2328 (((x) >> FW_PORT_CAP32_SPEED_S) & FW_PORT_CAP32_SPEED_M) 2329 2330 #define FW_PORT_CAP32_FC_S 16 2331 #define FW_PORT_CAP32_FC_M 0x3 2332 #define FW_PORT_CAP32_FC_V(x) ((x) << FW_PORT_CAP32_FC_S) 2333 #define FW_PORT_CAP32_FC_G(x) \ 2334 (((x) >> FW_PORT_CAP32_FC_S) & FW_PORT_CAP32_FC_M) 2335 2336 #define FW_PORT_CAP32_802_3_S 18 2337 #define FW_PORT_CAP32_802_3_M 0x3 2338 #define FW_PORT_CAP32_802_3_V(x) ((x) << FW_PORT_CAP32_802_3_S) 2339 #define FW_PORT_CAP32_802_3_G(x) \ 2340 (((x) >> FW_PORT_CAP32_802_3_S) & FW_PORT_CAP32_802_3_M) 2341 2342 #define FW_PORT_CAP32_ANEG_S 20 2343 #define FW_PORT_CAP32_ANEG_M 0x1 2344 #define FW_PORT_CAP32_ANEG_V(x) ((x) << FW_PORT_CAP32_ANEG_S) 2345 #define FW_PORT_CAP32_ANEG_G(x) \ 2346 (((x) >> FW_PORT_CAP32_ANEG_S) & FW_PORT_CAP32_ANEG_M) 2347 2348 enum fw_port_mdi32 { 2349 FW_PORT_CAP32_MDI_UNCHANGED, 2350 FW_PORT_CAP32_MDI_AUTO, 2351 FW_PORT_CAP32_MDI_F_STRAIGHT, 2352 FW_PORT_CAP32_MDI_F_CROSSOVER 2353 }; 2354 2355 #define FW_PORT_CAP32_MDI_S 21 2356 #define FW_PORT_CAP32_MDI_M 3 2357 #define FW_PORT_CAP32_MDI_V(x) ((x) << FW_PORT_CAP32_MDI_S) 2358 #define FW_PORT_CAP32_MDI_G(x) \ 2359 (((x) >> FW_PORT_CAP32_MDI_S) & FW_PORT_CAP32_MDI_M) 2360 2361 #define FW_PORT_CAP32_FEC_S 23 2362 #define FW_PORT_CAP32_FEC_M 0x1f 2363 #define FW_PORT_CAP32_FEC_V(x) ((x) << FW_PORT_CAP32_FEC_S) 2364 #define FW_PORT_CAP32_FEC_G(x) \ 2365 (((x) >> FW_PORT_CAP32_FEC_S) & FW_PORT_CAP32_FEC_M) 2366 2367 /* macros to isolate various 32-bit Port Capabilities sub-fields */ 2368 #define CAP32_SPEED(__cap32) \ 2369 (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) & __cap32) 2370 2371 #define CAP32_FEC(__cap32) \ 2372 (FW_PORT_CAP32_FEC_V(FW_PORT_CAP32_FEC_M) & __cap32) 2373 2374 enum fw_port_action { 2375 FW_PORT_ACTION_L1_CFG = 0x0001, 2376 FW_PORT_ACTION_L2_CFG = 0x0002, 2377 FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 2378 FW_PORT_ACTION_L2_PPP_CFG = 0x0004, 2379 FW_PORT_ACTION_L2_DCB_CFG = 0x0005, 2380 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006, 2381 FW_PORT_ACTION_DCB_READ_RECV = 0x0007, 2382 FW_PORT_ACTION_DCB_READ_DET = 0x0008, 2383 FW_PORT_ACTION_L1_CFG32 = 0x0009, 2384 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a, 2385 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, 2386 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, 2387 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, 2388 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, 2389 FW_PORT_ACTION_L1_LPBK = 0x0021, 2390 FW_PORT_ACTION_L1_PMA_LPBK = 0x0022, 2391 FW_PORT_ACTION_L1_PCS_LPBK = 0x0023, 2392 FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024, 2393 FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025, 2394 FW_PORT_ACTION_PHY_RESET = 0x0040, 2395 FW_PORT_ACTION_PMA_RESET = 0x0041, 2396 FW_PORT_ACTION_PCS_RESET = 0x0042, 2397 FW_PORT_ACTION_PHYXS_RESET = 0x0043, 2398 FW_PORT_ACTION_DTEXS_REEST = 0x0044, 2399 FW_PORT_ACTION_AN_RESET = 0x0045 2400 }; 2401 2402 enum fw_port_l2cfg_ctlbf { 2403 FW_PORT_L2_CTLBF_OVLAN0 = 0x01, 2404 FW_PORT_L2_CTLBF_OVLAN1 = 0x02, 2405 FW_PORT_L2_CTLBF_OVLAN2 = 0x04, 2406 FW_PORT_L2_CTLBF_OVLAN3 = 0x08, 2407 FW_PORT_L2_CTLBF_IVLAN = 0x10, 2408 FW_PORT_L2_CTLBF_TXIPG = 0x20 2409 }; 2410 2411 enum fw_port_dcb_versions { 2412 FW_PORT_DCB_VER_UNKNOWN, 2413 FW_PORT_DCB_VER_CEE1D0, 2414 FW_PORT_DCB_VER_CEE1D01, 2415 FW_PORT_DCB_VER_IEEE, 2416 FW_PORT_DCB_VER_AUTO = 7 2417 }; 2418 2419 enum fw_port_dcb_cfg { 2420 FW_PORT_DCB_CFG_PG = 0x01, 2421 FW_PORT_DCB_CFG_PFC = 0x02, 2422 FW_PORT_DCB_CFG_APPL = 0x04 2423 }; 2424 2425 enum fw_port_dcb_cfg_rc { 2426 FW_PORT_DCB_CFG_SUCCESS = 0x0, 2427 FW_PORT_DCB_CFG_ERROR = 0x1 2428 }; 2429 2430 enum fw_port_dcb_type { 2431 FW_PORT_DCB_TYPE_PGID = 0x00, 2432 FW_PORT_DCB_TYPE_PGRATE = 0x01, 2433 FW_PORT_DCB_TYPE_PRIORATE = 0x02, 2434 FW_PORT_DCB_TYPE_PFC = 0x03, 2435 FW_PORT_DCB_TYPE_APP_ID = 0x04, 2436 FW_PORT_DCB_TYPE_CONTROL = 0x05, 2437 }; 2438 2439 enum fw_port_dcb_feature_state { 2440 FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0, 2441 FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1, 2442 FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2, 2443 FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3, 2444 }; 2445 2446 struct fw_port_cmd { 2447 __be32 op_to_portid; 2448 __be32 action_to_len16; 2449 union fw_port { 2450 struct fw_port_l1cfg { 2451 __be32 rcap; 2452 __be32 r; 2453 } l1cfg; 2454 struct fw_port_l2cfg { 2455 __u8 ctlbf; 2456 __u8 ovlan3_to_ivlan0; 2457 __be16 ivlantype; 2458 __be16 txipg_force_pinfo; 2459 __be16 mtu; 2460 __be16 ovlan0mask; 2461 __be16 ovlan0type; 2462 __be16 ovlan1mask; 2463 __be16 ovlan1type; 2464 __be16 ovlan2mask; 2465 __be16 ovlan2type; 2466 __be16 ovlan3mask; 2467 __be16 ovlan3type; 2468 } l2cfg; 2469 struct fw_port_info { 2470 __be32 lstatus_to_modtype; 2471 __be16 pcap; 2472 __be16 acap; 2473 __be16 mtu; 2474 __u8 cbllen; 2475 __u8 auxlinfo; 2476 __u8 dcbxdis_pkd; 2477 __u8 r8_lo; 2478 __be16 lpacap; 2479 __be64 r9; 2480 } info; 2481 struct fw_port_diags { 2482 __u8 diagop; 2483 __u8 r[3]; 2484 __be32 diagval; 2485 } diags; 2486 union fw_port_dcb { 2487 struct fw_port_dcb_pgid { 2488 __u8 type; 2489 __u8 apply_pkd; 2490 __u8 r10_lo[2]; 2491 __be32 pgid; 2492 __be64 r11; 2493 } pgid; 2494 struct fw_port_dcb_pgrate { 2495 __u8 type; 2496 __u8 apply_pkd; 2497 __u8 r10_lo[5]; 2498 __u8 num_tcs_supported; 2499 __u8 pgrate[8]; 2500 __u8 tsa[8]; 2501 } pgrate; 2502 struct fw_port_dcb_priorate { 2503 __u8 type; 2504 __u8 apply_pkd; 2505 __u8 r10_lo[6]; 2506 __u8 strict_priorate[8]; 2507 } priorate; 2508 struct fw_port_dcb_pfc { 2509 __u8 type; 2510 __u8 pfcen; 2511 __u8 r10[5]; 2512 __u8 max_pfc_tcs; 2513 __be64 r11; 2514 } pfc; 2515 struct fw_port_app_priority { 2516 __u8 type; 2517 __u8 r10[2]; 2518 __u8 idx; 2519 __u8 user_prio_map; 2520 __u8 sel_field; 2521 __be16 protocolid; 2522 __be64 r12; 2523 } app_priority; 2524 struct fw_port_dcb_control { 2525 __u8 type; 2526 __u8 all_syncd_pkd; 2527 __be16 dcb_version_to_app_state; 2528 __be32 r11; 2529 __be64 r12; 2530 } control; 2531 } dcb; 2532 struct fw_port_l1cfg32 { 2533 __be32 rcap32; 2534 __be32 r; 2535 } l1cfg32; 2536 struct fw_port_info32 { 2537 __be32 lstatus32_to_cbllen32; 2538 __be32 auxlinfo32_mtu32; 2539 __be32 linkattr32; 2540 __be32 pcaps32; 2541 __be32 acaps32; 2542 __be32 lpacaps32; 2543 } info32; 2544 } u; 2545 }; 2546 2547 #define FW_PORT_CMD_READ_S 22 2548 #define FW_PORT_CMD_READ_V(x) ((x) << FW_PORT_CMD_READ_S) 2549 #define FW_PORT_CMD_READ_F FW_PORT_CMD_READ_V(1U) 2550 2551 #define FW_PORT_CMD_PORTID_S 0 2552 #define FW_PORT_CMD_PORTID_M 0xf 2553 #define FW_PORT_CMD_PORTID_V(x) ((x) << FW_PORT_CMD_PORTID_S) 2554 #define FW_PORT_CMD_PORTID_G(x) \ 2555 (((x) >> FW_PORT_CMD_PORTID_S) & FW_PORT_CMD_PORTID_M) 2556 2557 #define FW_PORT_CMD_ACTION_S 16 2558 #define FW_PORT_CMD_ACTION_M 0xffff 2559 #define FW_PORT_CMD_ACTION_V(x) ((x) << FW_PORT_CMD_ACTION_S) 2560 #define FW_PORT_CMD_ACTION_G(x) \ 2561 (((x) >> FW_PORT_CMD_ACTION_S) & FW_PORT_CMD_ACTION_M) 2562 2563 #define FW_PORT_CMD_OVLAN3_S 7 2564 #define FW_PORT_CMD_OVLAN3_V(x) ((x) << FW_PORT_CMD_OVLAN3_S) 2565 2566 #define FW_PORT_CMD_OVLAN2_S 6 2567 #define FW_PORT_CMD_OVLAN2_V(x) ((x) << FW_PORT_CMD_OVLAN2_S) 2568 2569 #define FW_PORT_CMD_OVLAN1_S 5 2570 #define FW_PORT_CMD_OVLAN1_V(x) ((x) << FW_PORT_CMD_OVLAN1_S) 2571 2572 #define FW_PORT_CMD_OVLAN0_S 4 2573 #define FW_PORT_CMD_OVLAN0_V(x) ((x) << FW_PORT_CMD_OVLAN0_S) 2574 2575 #define FW_PORT_CMD_IVLAN0_S 3 2576 #define FW_PORT_CMD_IVLAN0_V(x) ((x) << FW_PORT_CMD_IVLAN0_S) 2577 2578 #define FW_PORT_CMD_TXIPG_S 3 2579 #define FW_PORT_CMD_TXIPG_V(x) ((x) << FW_PORT_CMD_TXIPG_S) 2580 2581 #define FW_PORT_CMD_LSTATUS_S 31 2582 #define FW_PORT_CMD_LSTATUS_M 0x1 2583 #define FW_PORT_CMD_LSTATUS_V(x) ((x) << FW_PORT_CMD_LSTATUS_S) 2584 #define FW_PORT_CMD_LSTATUS_G(x) \ 2585 (((x) >> FW_PORT_CMD_LSTATUS_S) & FW_PORT_CMD_LSTATUS_M) 2586 #define FW_PORT_CMD_LSTATUS_F FW_PORT_CMD_LSTATUS_V(1U) 2587 2588 #define FW_PORT_CMD_LSPEED_S 24 2589 #define FW_PORT_CMD_LSPEED_M 0x3f 2590 #define FW_PORT_CMD_LSPEED_V(x) ((x) << FW_PORT_CMD_LSPEED_S) 2591 #define FW_PORT_CMD_LSPEED_G(x) \ 2592 (((x) >> FW_PORT_CMD_LSPEED_S) & FW_PORT_CMD_LSPEED_M) 2593 2594 #define FW_PORT_CMD_TXPAUSE_S 23 2595 #define FW_PORT_CMD_TXPAUSE_V(x) ((x) << FW_PORT_CMD_TXPAUSE_S) 2596 #define FW_PORT_CMD_TXPAUSE_F FW_PORT_CMD_TXPAUSE_V(1U) 2597 2598 #define FW_PORT_CMD_RXPAUSE_S 22 2599 #define FW_PORT_CMD_RXPAUSE_V(x) ((x) << FW_PORT_CMD_RXPAUSE_S) 2600 #define FW_PORT_CMD_RXPAUSE_F FW_PORT_CMD_RXPAUSE_V(1U) 2601 2602 #define FW_PORT_CMD_MDIOCAP_S 21 2603 #define FW_PORT_CMD_MDIOCAP_V(x) ((x) << FW_PORT_CMD_MDIOCAP_S) 2604 #define FW_PORT_CMD_MDIOCAP_F FW_PORT_CMD_MDIOCAP_V(1U) 2605 2606 #define FW_PORT_CMD_MDIOADDR_S 16 2607 #define FW_PORT_CMD_MDIOADDR_M 0x1f 2608 #define FW_PORT_CMD_MDIOADDR_G(x) \ 2609 (((x) >> FW_PORT_CMD_MDIOADDR_S) & FW_PORT_CMD_MDIOADDR_M) 2610 2611 #define FW_PORT_CMD_LPTXPAUSE_S 15 2612 #define FW_PORT_CMD_LPTXPAUSE_V(x) ((x) << FW_PORT_CMD_LPTXPAUSE_S) 2613 #define FW_PORT_CMD_LPTXPAUSE_F FW_PORT_CMD_LPTXPAUSE_V(1U) 2614 2615 #define FW_PORT_CMD_LPRXPAUSE_S 14 2616 #define FW_PORT_CMD_LPRXPAUSE_V(x) ((x) << FW_PORT_CMD_LPRXPAUSE_S) 2617 #define FW_PORT_CMD_LPRXPAUSE_F FW_PORT_CMD_LPRXPAUSE_V(1U) 2618 2619 #define FW_PORT_CMD_PTYPE_S 8 2620 #define FW_PORT_CMD_PTYPE_M 0x1f 2621 #define FW_PORT_CMD_PTYPE_G(x) \ 2622 (((x) >> FW_PORT_CMD_PTYPE_S) & FW_PORT_CMD_PTYPE_M) 2623 2624 #define FW_PORT_CMD_LINKDNRC_S 5 2625 #define FW_PORT_CMD_LINKDNRC_M 0x7 2626 #define FW_PORT_CMD_LINKDNRC_G(x) \ 2627 (((x) >> FW_PORT_CMD_LINKDNRC_S) & FW_PORT_CMD_LINKDNRC_M) 2628 2629 #define FW_PORT_CMD_MODTYPE_S 0 2630 #define FW_PORT_CMD_MODTYPE_M 0x1f 2631 #define FW_PORT_CMD_MODTYPE_V(x) ((x) << FW_PORT_CMD_MODTYPE_S) 2632 #define FW_PORT_CMD_MODTYPE_G(x) \ 2633 (((x) >> FW_PORT_CMD_MODTYPE_S) & FW_PORT_CMD_MODTYPE_M) 2634 2635 #define FW_PORT_CMD_DCBXDIS_S 7 2636 #define FW_PORT_CMD_DCBXDIS_V(x) ((x) << FW_PORT_CMD_DCBXDIS_S) 2637 #define FW_PORT_CMD_DCBXDIS_F FW_PORT_CMD_DCBXDIS_V(1U) 2638 2639 #define FW_PORT_CMD_APPLY_S 7 2640 #define FW_PORT_CMD_APPLY_V(x) ((x) << FW_PORT_CMD_APPLY_S) 2641 #define FW_PORT_CMD_APPLY_F FW_PORT_CMD_APPLY_V(1U) 2642 2643 #define FW_PORT_CMD_ALL_SYNCD_S 7 2644 #define FW_PORT_CMD_ALL_SYNCD_V(x) ((x) << FW_PORT_CMD_ALL_SYNCD_S) 2645 #define FW_PORT_CMD_ALL_SYNCD_F FW_PORT_CMD_ALL_SYNCD_V(1U) 2646 2647 #define FW_PORT_CMD_DCB_VERSION_S 12 2648 #define FW_PORT_CMD_DCB_VERSION_M 0x7 2649 #define FW_PORT_CMD_DCB_VERSION_G(x) \ 2650 (((x) >> FW_PORT_CMD_DCB_VERSION_S) & FW_PORT_CMD_DCB_VERSION_M) 2651 2652 #define FW_PORT_CMD_LSTATUS32_S 31 2653 #define FW_PORT_CMD_LSTATUS32_M 0x1 2654 #define FW_PORT_CMD_LSTATUS32_V(x) ((x) << FW_PORT_CMD_LSTATUS32_S) 2655 #define FW_PORT_CMD_LSTATUS32_G(x) \ 2656 (((x) >> FW_PORT_CMD_LSTATUS32_S) & FW_PORT_CMD_LSTATUS32_M) 2657 #define FW_PORT_CMD_LSTATUS32_F FW_PORT_CMD_LSTATUS32_V(1U) 2658 2659 #define FW_PORT_CMD_LINKDNRC32_S 28 2660 #define FW_PORT_CMD_LINKDNRC32_M 0x7 2661 #define FW_PORT_CMD_LINKDNRC32_V(x) ((x) << FW_PORT_CMD_LINKDNRC32_S) 2662 #define FW_PORT_CMD_LINKDNRC32_G(x) \ 2663 (((x) >> FW_PORT_CMD_LINKDNRC32_S) & FW_PORT_CMD_LINKDNRC32_M) 2664 2665 #define FW_PORT_CMD_DCBXDIS32_S 27 2666 #define FW_PORT_CMD_DCBXDIS32_M 0x1 2667 #define FW_PORT_CMD_DCBXDIS32_V(x) ((x) << FW_PORT_CMD_DCBXDIS32_S) 2668 #define FW_PORT_CMD_DCBXDIS32_G(x) \ 2669 (((x) >> FW_PORT_CMD_DCBXDIS32_S) & FW_PORT_CMD_DCBXDIS32_M) 2670 #define FW_PORT_CMD_DCBXDIS32_F FW_PORT_CMD_DCBXDIS32_V(1U) 2671 2672 #define FW_PORT_CMD_MDIOCAP32_S 26 2673 #define FW_PORT_CMD_MDIOCAP32_M 0x1 2674 #define FW_PORT_CMD_MDIOCAP32_V(x) ((x) << FW_PORT_CMD_MDIOCAP32_S) 2675 #define FW_PORT_CMD_MDIOCAP32_G(x) \ 2676 (((x) >> FW_PORT_CMD_MDIOCAP32_S) & FW_PORT_CMD_MDIOCAP32_M) 2677 #define FW_PORT_CMD_MDIOCAP32_F FW_PORT_CMD_MDIOCAP32_V(1U) 2678 2679 #define FW_PORT_CMD_MDIOADDR32_S 21 2680 #define FW_PORT_CMD_MDIOADDR32_M 0x1f 2681 #define FW_PORT_CMD_MDIOADDR32_V(x) ((x) << FW_PORT_CMD_MDIOADDR32_S) 2682 #define FW_PORT_CMD_MDIOADDR32_G(x) \ 2683 (((x) >> FW_PORT_CMD_MDIOADDR32_S) & FW_PORT_CMD_MDIOADDR32_M) 2684 2685 #define FW_PORT_CMD_PORTTYPE32_S 13 2686 #define FW_PORT_CMD_PORTTYPE32_M 0xff 2687 #define FW_PORT_CMD_PORTTYPE32_V(x) ((x) << FW_PORT_CMD_PORTTYPE32_S) 2688 #define FW_PORT_CMD_PORTTYPE32_G(x) \ 2689 (((x) >> FW_PORT_CMD_PORTTYPE32_S) & FW_PORT_CMD_PORTTYPE32_M) 2690 2691 #define FW_PORT_CMD_MODTYPE32_S 8 2692 #define FW_PORT_CMD_MODTYPE32_M 0x1f 2693 #define FW_PORT_CMD_MODTYPE32_V(x) ((x) << FW_PORT_CMD_MODTYPE32_S) 2694 #define FW_PORT_CMD_MODTYPE32_G(x) \ 2695 (((x) >> FW_PORT_CMD_MODTYPE32_S) & FW_PORT_CMD_MODTYPE32_M) 2696 2697 #define FW_PORT_CMD_CBLLEN32_S 0 2698 #define FW_PORT_CMD_CBLLEN32_M 0xff 2699 #define FW_PORT_CMD_CBLLEN32_V(x) ((x) << FW_PORT_CMD_CBLLEN32_S) 2700 #define FW_PORT_CMD_CBLLEN32_G(x) \ 2701 (((x) >> FW_PORT_CMD_CBLLEN32_S) & FW_PORT_CMD_CBLLEN32_M) 2702 2703 #define FW_PORT_CMD_AUXLINFO32_S 24 2704 #define FW_PORT_CMD_AUXLINFO32_M 0xff 2705 #define FW_PORT_CMD_AUXLINFO32_V(x) ((x) << FW_PORT_CMD_AUXLINFO32_S) 2706 #define FW_PORT_CMD_AUXLINFO32_G(x) \ 2707 (((x) >> FW_PORT_CMD_AUXLINFO32_S) & FW_PORT_CMD_AUXLINFO32_M) 2708 2709 #define FW_PORT_AUXLINFO32_KX4_S 2 2710 #define FW_PORT_AUXLINFO32_KX4_M 0x1 2711 #define FW_PORT_AUXLINFO32_KX4_V(x) \ 2712 ((x) << FW_PORT_AUXLINFO32_KX4_S) 2713 #define FW_PORT_AUXLINFO32_KX4_G(x) \ 2714 (((x) >> FW_PORT_AUXLINFO32_KX4_S) & FW_PORT_AUXLINFO32_KX4_M) 2715 #define FW_PORT_AUXLINFO32_KX4_F FW_PORT_AUXLINFO32_KX4_V(1U) 2716 2717 #define FW_PORT_AUXLINFO32_KR_S 1 2718 #define FW_PORT_AUXLINFO32_KR_M 0x1 2719 #define FW_PORT_AUXLINFO32_KR_V(x) \ 2720 ((x) << FW_PORT_AUXLINFO32_KR_S) 2721 #define FW_PORT_AUXLINFO32_KR_G(x) \ 2722 (((x) >> FW_PORT_AUXLINFO32_KR_S) & FW_PORT_AUXLINFO32_KR_M) 2723 #define FW_PORT_AUXLINFO32_KR_F FW_PORT_AUXLINFO32_KR_V(1U) 2724 2725 #define FW_PORT_CMD_MTU32_S 0 2726 #define FW_PORT_CMD_MTU32_M 0xffff 2727 #define FW_PORT_CMD_MTU32_V(x) ((x) << FW_PORT_CMD_MTU32_S) 2728 #define FW_PORT_CMD_MTU32_G(x) \ 2729 (((x) >> FW_PORT_CMD_MTU32_S) & FW_PORT_CMD_MTU32_M) 2730 2731 enum fw_port_type { 2732 FW_PORT_TYPE_FIBER_XFI, 2733 FW_PORT_TYPE_FIBER_XAUI, 2734 FW_PORT_TYPE_BT_SGMII, 2735 FW_PORT_TYPE_BT_XFI, 2736 FW_PORT_TYPE_BT_XAUI, 2737 FW_PORT_TYPE_KX4, 2738 FW_PORT_TYPE_CX4, 2739 FW_PORT_TYPE_KX, 2740 FW_PORT_TYPE_KR, 2741 FW_PORT_TYPE_SFP, 2742 FW_PORT_TYPE_BP_AP, 2743 FW_PORT_TYPE_BP4_AP, 2744 FW_PORT_TYPE_QSFP_10G, 2745 FW_PORT_TYPE_QSA, 2746 FW_PORT_TYPE_QSFP, 2747 FW_PORT_TYPE_BP40_BA, 2748 FW_PORT_TYPE_KR4_100G, 2749 FW_PORT_TYPE_CR4_QSFP, 2750 FW_PORT_TYPE_CR_QSFP, 2751 FW_PORT_TYPE_CR2_QSFP, 2752 FW_PORT_TYPE_SFP28, 2753 FW_PORT_TYPE_KR_SFP28, 2754 2755 FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_M 2756 }; 2757 2758 enum fw_port_module_type { 2759 FW_PORT_MOD_TYPE_NA, 2760 FW_PORT_MOD_TYPE_LR, 2761 FW_PORT_MOD_TYPE_SR, 2762 FW_PORT_MOD_TYPE_ER, 2763 FW_PORT_MOD_TYPE_TWINAX_PASSIVE, 2764 FW_PORT_MOD_TYPE_TWINAX_ACTIVE, 2765 FW_PORT_MOD_TYPE_LRM, 2766 FW_PORT_MOD_TYPE_ERROR = FW_PORT_CMD_MODTYPE_M - 3, 2767 FW_PORT_MOD_TYPE_UNKNOWN = FW_PORT_CMD_MODTYPE_M - 2, 2768 FW_PORT_MOD_TYPE_NOTSUPPORTED = FW_PORT_CMD_MODTYPE_M - 1, 2769 2770 FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_M 2771 }; 2772 2773 enum fw_port_mod_sub_type { 2774 FW_PORT_MOD_SUB_TYPE_NA, 2775 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1, 2776 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2, 2777 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3, 2778 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4, 2779 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5, 2780 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8, 2781 2782 /* The following will never been in the VPD. They are TWINAX cable 2783 * lengths decoded from SFP+ module i2c PROMs. These should 2784 * almost certainly go somewhere else ... 2785 */ 2786 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9, 2787 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA, 2788 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB, 2789 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC, 2790 }; 2791 2792 enum fw_port_stats_tx_index { 2793 FW_STAT_TX_PORT_BYTES_IX = 0, 2794 FW_STAT_TX_PORT_FRAMES_IX, 2795 FW_STAT_TX_PORT_BCAST_IX, 2796 FW_STAT_TX_PORT_MCAST_IX, 2797 FW_STAT_TX_PORT_UCAST_IX, 2798 FW_STAT_TX_PORT_ERROR_IX, 2799 FW_STAT_TX_PORT_64B_IX, 2800 FW_STAT_TX_PORT_65B_127B_IX, 2801 FW_STAT_TX_PORT_128B_255B_IX, 2802 FW_STAT_TX_PORT_256B_511B_IX, 2803 FW_STAT_TX_PORT_512B_1023B_IX, 2804 FW_STAT_TX_PORT_1024B_1518B_IX, 2805 FW_STAT_TX_PORT_1519B_MAX_IX, 2806 FW_STAT_TX_PORT_DROP_IX, 2807 FW_STAT_TX_PORT_PAUSE_IX, 2808 FW_STAT_TX_PORT_PPP0_IX, 2809 FW_STAT_TX_PORT_PPP1_IX, 2810 FW_STAT_TX_PORT_PPP2_IX, 2811 FW_STAT_TX_PORT_PPP3_IX, 2812 FW_STAT_TX_PORT_PPP4_IX, 2813 FW_STAT_TX_PORT_PPP5_IX, 2814 FW_STAT_TX_PORT_PPP6_IX, 2815 FW_STAT_TX_PORT_PPP7_IX, 2816 FW_NUM_PORT_TX_STATS 2817 }; 2818 2819 enum fw_port_stat_rx_index { 2820 FW_STAT_RX_PORT_BYTES_IX = 0, 2821 FW_STAT_RX_PORT_FRAMES_IX, 2822 FW_STAT_RX_PORT_BCAST_IX, 2823 FW_STAT_RX_PORT_MCAST_IX, 2824 FW_STAT_RX_PORT_UCAST_IX, 2825 FW_STAT_RX_PORT_MTU_ERROR_IX, 2826 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 2827 FW_STAT_RX_PORT_CRC_ERROR_IX, 2828 FW_STAT_RX_PORT_LEN_ERROR_IX, 2829 FW_STAT_RX_PORT_SYM_ERROR_IX, 2830 FW_STAT_RX_PORT_64B_IX, 2831 FW_STAT_RX_PORT_65B_127B_IX, 2832 FW_STAT_RX_PORT_128B_255B_IX, 2833 FW_STAT_RX_PORT_256B_511B_IX, 2834 FW_STAT_RX_PORT_512B_1023B_IX, 2835 FW_STAT_RX_PORT_1024B_1518B_IX, 2836 FW_STAT_RX_PORT_1519B_MAX_IX, 2837 FW_STAT_RX_PORT_PAUSE_IX, 2838 FW_STAT_RX_PORT_PPP0_IX, 2839 FW_STAT_RX_PORT_PPP1_IX, 2840 FW_STAT_RX_PORT_PPP2_IX, 2841 FW_STAT_RX_PORT_PPP3_IX, 2842 FW_STAT_RX_PORT_PPP4_IX, 2843 FW_STAT_RX_PORT_PPP5_IX, 2844 FW_STAT_RX_PORT_PPP6_IX, 2845 FW_STAT_RX_PORT_PPP7_IX, 2846 FW_STAT_RX_PORT_LESS_64B_IX, 2847 FW_STAT_RX_PORT_MAC_ERROR_IX, 2848 FW_NUM_PORT_RX_STATS 2849 }; 2850 2851 /* port stats */ 2852 #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + FW_NUM_PORT_RX_STATS) 2853 2854 struct fw_port_stats_cmd { 2855 __be32 op_to_portid; 2856 __be32 retval_len16; 2857 union fw_port_stats { 2858 struct fw_port_stats_ctl { 2859 u8 nstats_bg_bm; 2860 u8 tx_ix; 2861 __be16 r6; 2862 __be32 r7; 2863 __be64 stat0; 2864 __be64 stat1; 2865 __be64 stat2; 2866 __be64 stat3; 2867 __be64 stat4; 2868 __be64 stat5; 2869 } ctl; 2870 struct fw_port_stats_all { 2871 __be64 tx_bytes; 2872 __be64 tx_frames; 2873 __be64 tx_bcast; 2874 __be64 tx_mcast; 2875 __be64 tx_ucast; 2876 __be64 tx_error; 2877 __be64 tx_64b; 2878 __be64 tx_65b_127b; 2879 __be64 tx_128b_255b; 2880 __be64 tx_256b_511b; 2881 __be64 tx_512b_1023b; 2882 __be64 tx_1024b_1518b; 2883 __be64 tx_1519b_max; 2884 __be64 tx_drop; 2885 __be64 tx_pause; 2886 __be64 tx_ppp0; 2887 __be64 tx_ppp1; 2888 __be64 tx_ppp2; 2889 __be64 tx_ppp3; 2890 __be64 tx_ppp4; 2891 __be64 tx_ppp5; 2892 __be64 tx_ppp6; 2893 __be64 tx_ppp7; 2894 __be64 rx_bytes; 2895 __be64 rx_frames; 2896 __be64 rx_bcast; 2897 __be64 rx_mcast; 2898 __be64 rx_ucast; 2899 __be64 rx_mtu_error; 2900 __be64 rx_mtu_crc_error; 2901 __be64 rx_crc_error; 2902 __be64 rx_len_error; 2903 __be64 rx_sym_error; 2904 __be64 rx_64b; 2905 __be64 rx_65b_127b; 2906 __be64 rx_128b_255b; 2907 __be64 rx_256b_511b; 2908 __be64 rx_512b_1023b; 2909 __be64 rx_1024b_1518b; 2910 __be64 rx_1519b_max; 2911 __be64 rx_pause; 2912 __be64 rx_ppp0; 2913 __be64 rx_ppp1; 2914 __be64 rx_ppp2; 2915 __be64 rx_ppp3; 2916 __be64 rx_ppp4; 2917 __be64 rx_ppp5; 2918 __be64 rx_ppp6; 2919 __be64 rx_ppp7; 2920 __be64 rx_less_64b; 2921 __be64 rx_bg_drop; 2922 __be64 rx_bg_trunc; 2923 } all; 2924 } u; 2925 }; 2926 2927 /* port loopback stats */ 2928 #define FW_NUM_LB_STATS 16 2929 enum fw_port_lb_stats_index { 2930 FW_STAT_LB_PORT_BYTES_IX, 2931 FW_STAT_LB_PORT_FRAMES_IX, 2932 FW_STAT_LB_PORT_BCAST_IX, 2933 FW_STAT_LB_PORT_MCAST_IX, 2934 FW_STAT_LB_PORT_UCAST_IX, 2935 FW_STAT_LB_PORT_ERROR_IX, 2936 FW_STAT_LB_PORT_64B_IX, 2937 FW_STAT_LB_PORT_65B_127B_IX, 2938 FW_STAT_LB_PORT_128B_255B_IX, 2939 FW_STAT_LB_PORT_256B_511B_IX, 2940 FW_STAT_LB_PORT_512B_1023B_IX, 2941 FW_STAT_LB_PORT_1024B_1518B_IX, 2942 FW_STAT_LB_PORT_1519B_MAX_IX, 2943 FW_STAT_LB_PORT_DROP_FRAMES_IX 2944 }; 2945 2946 struct fw_port_lb_stats_cmd { 2947 __be32 op_to_lbport; 2948 __be32 retval_len16; 2949 union fw_port_lb_stats { 2950 struct fw_port_lb_stats_ctl { 2951 u8 nstats_bg_bm; 2952 u8 ix_pkd; 2953 __be16 r6; 2954 __be32 r7; 2955 __be64 stat0; 2956 __be64 stat1; 2957 __be64 stat2; 2958 __be64 stat3; 2959 __be64 stat4; 2960 __be64 stat5; 2961 } ctl; 2962 struct fw_port_lb_stats_all { 2963 __be64 tx_bytes; 2964 __be64 tx_frames; 2965 __be64 tx_bcast; 2966 __be64 tx_mcast; 2967 __be64 tx_ucast; 2968 __be64 tx_error; 2969 __be64 tx_64b; 2970 __be64 tx_65b_127b; 2971 __be64 tx_128b_255b; 2972 __be64 tx_256b_511b; 2973 __be64 tx_512b_1023b; 2974 __be64 tx_1024b_1518b; 2975 __be64 tx_1519b_max; 2976 __be64 rx_lb_drop; 2977 __be64 rx_lb_trunc; 2978 } all; 2979 } u; 2980 }; 2981 2982 enum fw_ptp_subop { 2983 /* none */ 2984 FW_PTP_SC_INIT_TIMER = 0x00, 2985 FW_PTP_SC_TX_TYPE = 0x01, 2986 /* init */ 2987 FW_PTP_SC_RXTIME_STAMP = 0x08, 2988 FW_PTP_SC_RDRX_TYPE = 0x09, 2989 /* ts */ 2990 FW_PTP_SC_ADJ_FREQ = 0x10, 2991 FW_PTP_SC_ADJ_TIME = 0x11, 2992 FW_PTP_SC_ADJ_FTIME = 0x12, 2993 FW_PTP_SC_WALL_CLOCK = 0x13, 2994 FW_PTP_SC_GET_TIME = 0x14, 2995 FW_PTP_SC_SET_TIME = 0x15, 2996 }; 2997 2998 struct fw_ptp_cmd { 2999 __be32 op_to_portid; 3000 __be32 retval_len16; 3001 union fw_ptp { 3002 struct fw_ptp_sc { 3003 __u8 sc; 3004 __u8 r3[7]; 3005 } scmd; 3006 struct fw_ptp_init { 3007 __u8 sc; 3008 __u8 txchan; 3009 __be16 absid; 3010 __be16 mode; 3011 __be16 r3; 3012 } init; 3013 struct fw_ptp_ts { 3014 __u8 sc; 3015 __u8 sign; 3016 __be16 r3; 3017 __be32 ppb; 3018 __be64 tm; 3019 } ts; 3020 } u; 3021 __be64 r3; 3022 }; 3023 3024 #define FW_PTP_CMD_PORTID_S 0 3025 #define FW_PTP_CMD_PORTID_M 0xf 3026 #define FW_PTP_CMD_PORTID_V(x) ((x) << FW_PTP_CMD_PORTID_S) 3027 #define FW_PTP_CMD_PORTID_G(x) \ 3028 (((x) >> FW_PTP_CMD_PORTID_S) & FW_PTP_CMD_PORTID_M) 3029 3030 struct fw_rss_ind_tbl_cmd { 3031 __be32 op_to_viid; 3032 __be32 retval_len16; 3033 __be16 niqid; 3034 __be16 startidx; 3035 __be32 r3; 3036 __be32 iq0_to_iq2; 3037 __be32 iq3_to_iq5; 3038 __be32 iq6_to_iq8; 3039 __be32 iq9_to_iq11; 3040 __be32 iq12_to_iq14; 3041 __be32 iq15_to_iq17; 3042 __be32 iq18_to_iq20; 3043 __be32 iq21_to_iq23; 3044 __be32 iq24_to_iq26; 3045 __be32 iq27_to_iq29; 3046 __be32 iq30_iq31; 3047 __be32 r15_lo; 3048 }; 3049 3050 #define FW_RSS_IND_TBL_CMD_VIID_S 0 3051 #define FW_RSS_IND_TBL_CMD_VIID_V(x) ((x) << FW_RSS_IND_TBL_CMD_VIID_S) 3052 3053 #define FW_RSS_IND_TBL_CMD_IQ0_S 20 3054 #define FW_RSS_IND_TBL_CMD_IQ0_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ0_S) 3055 3056 #define FW_RSS_IND_TBL_CMD_IQ1_S 10 3057 #define FW_RSS_IND_TBL_CMD_IQ1_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ1_S) 3058 3059 #define FW_RSS_IND_TBL_CMD_IQ2_S 0 3060 #define FW_RSS_IND_TBL_CMD_IQ2_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ2_S) 3061 3062 struct fw_rss_glb_config_cmd { 3063 __be32 op_to_write; 3064 __be32 retval_len16; 3065 union fw_rss_glb_config { 3066 struct fw_rss_glb_config_manual { 3067 __be32 mode_pkd; 3068 __be32 r3; 3069 __be64 r4; 3070 __be64 r5; 3071 } manual; 3072 struct fw_rss_glb_config_basicvirtual { 3073 __be32 mode_pkd; 3074 __be32 synmapen_to_hashtoeplitz; 3075 __be64 r8; 3076 __be64 r9; 3077 } basicvirtual; 3078 } u; 3079 }; 3080 3081 #define FW_RSS_GLB_CONFIG_CMD_MODE_S 28 3082 #define FW_RSS_GLB_CONFIG_CMD_MODE_M 0xf 3083 #define FW_RSS_GLB_CONFIG_CMD_MODE_V(x) ((x) << FW_RSS_GLB_CONFIG_CMD_MODE_S) 3084 #define FW_RSS_GLB_CONFIG_CMD_MODE_G(x) \ 3085 (((x) >> FW_RSS_GLB_CONFIG_CMD_MODE_S) & FW_RSS_GLB_CONFIG_CMD_MODE_M) 3086 3087 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 3088 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 3089 3090 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S 8 3091 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(x) \ 3092 ((x) << FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S) 3093 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_F \ 3094 FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(1U) 3095 3096 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S 7 3097 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(x) \ 3098 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S) 3099 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_F \ 3100 FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(1U) 3101 3102 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S 6 3103 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(x) \ 3104 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S) 3105 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_F \ 3106 FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(1U) 3107 3108 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S 5 3109 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(x) \ 3110 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S) 3111 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_F \ 3112 FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(1U) 3113 3114 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S 4 3115 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(x) \ 3116 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S) 3117 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_F \ 3118 FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(1U) 3119 3120 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S 3 3121 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(x) \ 3122 ((x) << FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S) 3123 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_F \ 3124 FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(1U) 3125 3126 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S 2 3127 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(x) \ 3128 ((x) << FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S) 3129 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F \ 3130 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(1U) 3131 3132 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S 1 3133 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(x) \ 3134 ((x) << FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S) 3135 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F \ 3136 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(1U) 3137 3138 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S 0 3139 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(x) \ 3140 ((x) << FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S) 3141 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F \ 3142 FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(1U) 3143 3144 struct fw_rss_vi_config_cmd { 3145 __be32 op_to_viid; 3146 #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0) 3147 __be32 retval_len16; 3148 union fw_rss_vi_config { 3149 struct fw_rss_vi_config_manual { 3150 __be64 r3; 3151 __be64 r4; 3152 __be64 r5; 3153 } manual; 3154 struct fw_rss_vi_config_basicvirtual { 3155 __be32 r6; 3156 __be32 defaultq_to_udpen; 3157 __be64 r9; 3158 __be64 r10; 3159 } basicvirtual; 3160 } u; 3161 }; 3162 3163 #define FW_RSS_VI_CONFIG_CMD_VIID_S 0 3164 #define FW_RSS_VI_CONFIG_CMD_VIID_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_VIID_S) 3165 3166 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S 16 3167 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M 0x3ff 3168 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(x) \ 3169 ((x) << FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) 3170 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_G(x) \ 3171 (((x) >> FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) & \ 3172 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M) 3173 3174 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S 4 3175 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(x) \ 3176 ((x) << FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S) 3177 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F \ 3178 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(1U) 3179 3180 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S 3 3181 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(x) \ 3182 ((x) << FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S) 3183 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F \ 3184 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(1U) 3185 3186 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S 2 3187 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(x) \ 3188 ((x) << FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S) 3189 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F \ 3190 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(1U) 3191 3192 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S 1 3193 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(x) \ 3194 ((x) << FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S) 3195 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F \ 3196 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(1U) 3197 3198 #define FW_RSS_VI_CONFIG_CMD_UDPEN_S 0 3199 #define FW_RSS_VI_CONFIG_CMD_UDPEN_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_UDPEN_S) 3200 #define FW_RSS_VI_CONFIG_CMD_UDPEN_F FW_RSS_VI_CONFIG_CMD_UDPEN_V(1U) 3201 3202 enum fw_sched_sc { 3203 FW_SCHED_SC_PARAMS = 1, 3204 }; 3205 3206 struct fw_sched_cmd { 3207 __be32 op_to_write; 3208 __be32 retval_len16; 3209 union fw_sched { 3210 struct fw_sched_config { 3211 __u8 sc; 3212 __u8 type; 3213 __u8 minmaxen; 3214 __u8 r3[5]; 3215 __u8 nclasses[4]; 3216 __be32 r4; 3217 } config; 3218 struct fw_sched_params { 3219 __u8 sc; 3220 __u8 type; 3221 __u8 level; 3222 __u8 mode; 3223 __u8 unit; 3224 __u8 rate; 3225 __u8 ch; 3226 __u8 cl; 3227 __be32 min; 3228 __be32 max; 3229 __be16 weight; 3230 __be16 pktsize; 3231 __be16 burstsize; 3232 __be16 r4; 3233 } params; 3234 } u; 3235 }; 3236 3237 struct fw_clip_cmd { 3238 __be32 op_to_write; 3239 __be32 alloc_to_len16; 3240 __be64 ip_hi; 3241 __be64 ip_lo; 3242 __be32 r4[2]; 3243 }; 3244 3245 #define FW_CLIP_CMD_ALLOC_S 31 3246 #define FW_CLIP_CMD_ALLOC_V(x) ((x) << FW_CLIP_CMD_ALLOC_S) 3247 #define FW_CLIP_CMD_ALLOC_F FW_CLIP_CMD_ALLOC_V(1U) 3248 3249 #define FW_CLIP_CMD_FREE_S 30 3250 #define FW_CLIP_CMD_FREE_V(x) ((x) << FW_CLIP_CMD_FREE_S) 3251 #define FW_CLIP_CMD_FREE_F FW_CLIP_CMD_FREE_V(1U) 3252 3253 enum fw_error_type { 3254 FW_ERROR_TYPE_EXCEPTION = 0x0, 3255 FW_ERROR_TYPE_HWMODULE = 0x1, 3256 FW_ERROR_TYPE_WR = 0x2, 3257 FW_ERROR_TYPE_ACL = 0x3, 3258 }; 3259 3260 struct fw_error_cmd { 3261 __be32 op_to_type; 3262 __be32 len16_pkd; 3263 union fw_error { 3264 struct fw_error_exception { 3265 __be32 info[6]; 3266 } exception; 3267 struct fw_error_hwmodule { 3268 __be32 regaddr; 3269 __be32 regval; 3270 } hwmodule; 3271 struct fw_error_wr { 3272 __be16 cidx; 3273 __be16 pfn_vfn; 3274 __be32 eqid; 3275 u8 wrhdr[16]; 3276 } wr; 3277 struct fw_error_acl { 3278 __be16 cidx; 3279 __be16 pfn_vfn; 3280 __be32 eqid; 3281 __be16 mv_pkd; 3282 u8 val[6]; 3283 __be64 r4; 3284 } acl; 3285 } u; 3286 }; 3287 3288 struct fw_debug_cmd { 3289 __be32 op_type; 3290 __be32 len16_pkd; 3291 union fw_debug { 3292 struct fw_debug_assert { 3293 __be32 fcid; 3294 __be32 line; 3295 __be32 x; 3296 __be32 y; 3297 u8 filename_0_7[8]; 3298 u8 filename_8_15[8]; 3299 __be64 r3; 3300 } assert; 3301 struct fw_debug_prt { 3302 __be16 dprtstridx; 3303 __be16 r3[3]; 3304 __be32 dprtstrparam0; 3305 __be32 dprtstrparam1; 3306 __be32 dprtstrparam2; 3307 __be32 dprtstrparam3; 3308 } prt; 3309 } u; 3310 }; 3311 3312 #define FW_DEBUG_CMD_TYPE_S 0 3313 #define FW_DEBUG_CMD_TYPE_M 0xff 3314 #define FW_DEBUG_CMD_TYPE_G(x) \ 3315 (((x) >> FW_DEBUG_CMD_TYPE_S) & FW_DEBUG_CMD_TYPE_M) 3316 3317 enum pcie_fw_eval { 3318 PCIE_FW_EVAL_CRASH = 0, 3319 }; 3320 3321 #define PCIE_FW_ERR_S 31 3322 #define PCIE_FW_ERR_V(x) ((x) << PCIE_FW_ERR_S) 3323 #define PCIE_FW_ERR_F PCIE_FW_ERR_V(1U) 3324 3325 #define PCIE_FW_INIT_S 30 3326 #define PCIE_FW_INIT_V(x) ((x) << PCIE_FW_INIT_S) 3327 #define PCIE_FW_INIT_F PCIE_FW_INIT_V(1U) 3328 3329 #define PCIE_FW_HALT_S 29 3330 #define PCIE_FW_HALT_V(x) ((x) << PCIE_FW_HALT_S) 3331 #define PCIE_FW_HALT_F PCIE_FW_HALT_V(1U) 3332 3333 #define PCIE_FW_EVAL_S 24 3334 #define PCIE_FW_EVAL_M 0x7 3335 #define PCIE_FW_EVAL_G(x) (((x) >> PCIE_FW_EVAL_S) & PCIE_FW_EVAL_M) 3336 3337 #define PCIE_FW_MASTER_VLD_S 15 3338 #define PCIE_FW_MASTER_VLD_V(x) ((x) << PCIE_FW_MASTER_VLD_S) 3339 #define PCIE_FW_MASTER_VLD_F PCIE_FW_MASTER_VLD_V(1U) 3340 3341 #define PCIE_FW_MASTER_S 12 3342 #define PCIE_FW_MASTER_M 0x7 3343 #define PCIE_FW_MASTER_V(x) ((x) << PCIE_FW_MASTER_S) 3344 #define PCIE_FW_MASTER_G(x) (((x) >> PCIE_FW_MASTER_S) & PCIE_FW_MASTER_M) 3345 3346 struct fw_hdr { 3347 u8 ver; 3348 u8 chip; /* terminator chip type */ 3349 __be16 len512; /* bin length in units of 512-bytes */ 3350 __be32 fw_ver; /* firmware version */ 3351 __be32 tp_microcode_ver; 3352 u8 intfver_nic; 3353 u8 intfver_vnic; 3354 u8 intfver_ofld; 3355 u8 intfver_ri; 3356 u8 intfver_iscsipdu; 3357 u8 intfver_iscsi; 3358 u8 intfver_fcoepdu; 3359 u8 intfver_fcoe; 3360 __u32 reserved2; 3361 __u32 reserved3; 3362 __u32 reserved4; 3363 __be32 flags; 3364 __be32 reserved6[23]; 3365 }; 3366 3367 enum fw_hdr_chip { 3368 FW_HDR_CHIP_T4, 3369 FW_HDR_CHIP_T5, 3370 FW_HDR_CHIP_T6 3371 }; 3372 3373 #define FW_HDR_FW_VER_MAJOR_S 24 3374 #define FW_HDR_FW_VER_MAJOR_M 0xff 3375 #define FW_HDR_FW_VER_MAJOR_V(x) \ 3376 ((x) << FW_HDR_FW_VER_MAJOR_S) 3377 #define FW_HDR_FW_VER_MAJOR_G(x) \ 3378 (((x) >> FW_HDR_FW_VER_MAJOR_S) & FW_HDR_FW_VER_MAJOR_M) 3379 3380 #define FW_HDR_FW_VER_MINOR_S 16 3381 #define FW_HDR_FW_VER_MINOR_M 0xff 3382 #define FW_HDR_FW_VER_MINOR_V(x) \ 3383 ((x) << FW_HDR_FW_VER_MINOR_S) 3384 #define FW_HDR_FW_VER_MINOR_G(x) \ 3385 (((x) >> FW_HDR_FW_VER_MINOR_S) & FW_HDR_FW_VER_MINOR_M) 3386 3387 #define FW_HDR_FW_VER_MICRO_S 8 3388 #define FW_HDR_FW_VER_MICRO_M 0xff 3389 #define FW_HDR_FW_VER_MICRO_V(x) \ 3390 ((x) << FW_HDR_FW_VER_MICRO_S) 3391 #define FW_HDR_FW_VER_MICRO_G(x) \ 3392 (((x) >> FW_HDR_FW_VER_MICRO_S) & FW_HDR_FW_VER_MICRO_M) 3393 3394 #define FW_HDR_FW_VER_BUILD_S 0 3395 #define FW_HDR_FW_VER_BUILD_M 0xff 3396 #define FW_HDR_FW_VER_BUILD_V(x) \ 3397 ((x) << FW_HDR_FW_VER_BUILD_S) 3398 #define FW_HDR_FW_VER_BUILD_G(x) \ 3399 (((x) >> FW_HDR_FW_VER_BUILD_S) & FW_HDR_FW_VER_BUILD_M) 3400 3401 enum fw_hdr_intfver { 3402 FW_HDR_INTFVER_NIC = 0x00, 3403 FW_HDR_INTFVER_VNIC = 0x00, 3404 FW_HDR_INTFVER_OFLD = 0x00, 3405 FW_HDR_INTFVER_RI = 0x00, 3406 FW_HDR_INTFVER_ISCSIPDU = 0x00, 3407 FW_HDR_INTFVER_ISCSI = 0x00, 3408 FW_HDR_INTFVER_FCOEPDU = 0x00, 3409 FW_HDR_INTFVER_FCOE = 0x00, 3410 }; 3411 3412 enum fw_hdr_flags { 3413 FW_HDR_FLAGS_RESET_HALT = 0x00000001, 3414 }; 3415 3416 /* length of the formatting string */ 3417 #define FW_DEVLOG_FMT_LEN 192 3418 3419 /* maximum number of the formatting string parameters */ 3420 #define FW_DEVLOG_FMT_PARAMS_NUM 8 3421 3422 /* priority levels */ 3423 enum fw_devlog_level { 3424 FW_DEVLOG_LEVEL_EMERG = 0x0, 3425 FW_DEVLOG_LEVEL_CRIT = 0x1, 3426 FW_DEVLOG_LEVEL_ERR = 0x2, 3427 FW_DEVLOG_LEVEL_NOTICE = 0x3, 3428 FW_DEVLOG_LEVEL_INFO = 0x4, 3429 FW_DEVLOG_LEVEL_DEBUG = 0x5, 3430 FW_DEVLOG_LEVEL_MAX = 0x5, 3431 }; 3432 3433 /* facilities that may send a log message */ 3434 enum fw_devlog_facility { 3435 FW_DEVLOG_FACILITY_CORE = 0x00, 3436 FW_DEVLOG_FACILITY_CF = 0x01, 3437 FW_DEVLOG_FACILITY_SCHED = 0x02, 3438 FW_DEVLOG_FACILITY_TIMER = 0x04, 3439 FW_DEVLOG_FACILITY_RES = 0x06, 3440 FW_DEVLOG_FACILITY_HW = 0x08, 3441 FW_DEVLOG_FACILITY_FLR = 0x10, 3442 FW_DEVLOG_FACILITY_DMAQ = 0x12, 3443 FW_DEVLOG_FACILITY_PHY = 0x14, 3444 FW_DEVLOG_FACILITY_MAC = 0x16, 3445 FW_DEVLOG_FACILITY_PORT = 0x18, 3446 FW_DEVLOG_FACILITY_VI = 0x1A, 3447 FW_DEVLOG_FACILITY_FILTER = 0x1C, 3448 FW_DEVLOG_FACILITY_ACL = 0x1E, 3449 FW_DEVLOG_FACILITY_TM = 0x20, 3450 FW_DEVLOG_FACILITY_QFC = 0x22, 3451 FW_DEVLOG_FACILITY_DCB = 0x24, 3452 FW_DEVLOG_FACILITY_ETH = 0x26, 3453 FW_DEVLOG_FACILITY_OFLD = 0x28, 3454 FW_DEVLOG_FACILITY_RI = 0x2A, 3455 FW_DEVLOG_FACILITY_ISCSI = 0x2C, 3456 FW_DEVLOG_FACILITY_FCOE = 0x2E, 3457 FW_DEVLOG_FACILITY_FOISCSI = 0x30, 3458 FW_DEVLOG_FACILITY_FOFCOE = 0x32, 3459 FW_DEVLOG_FACILITY_CHNET = 0x34, 3460 FW_DEVLOG_FACILITY_MAX = 0x34, 3461 }; 3462 3463 /* log message format */ 3464 struct fw_devlog_e { 3465 __be64 timestamp; 3466 __be32 seqno; 3467 __be16 reserved1; 3468 __u8 level; 3469 __u8 facility; 3470 __u8 fmt[FW_DEVLOG_FMT_LEN]; 3471 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM]; 3472 __be32 reserved3[4]; 3473 }; 3474 3475 struct fw_devlog_cmd { 3476 __be32 op_to_write; 3477 __be32 retval_len16; 3478 __u8 level; 3479 __u8 r2[7]; 3480 __be32 memtype_devlog_memaddr16_devlog; 3481 __be32 memsize_devlog; 3482 __be32 r3[2]; 3483 }; 3484 3485 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S 28 3486 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M 0xf 3487 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(x) \ 3488 (((x) >> FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S) & \ 3489 FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M) 3490 3491 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S 0 3492 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M 0xfffffff 3493 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(x) \ 3494 (((x) >> FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S) & \ 3495 FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M) 3496 3497 /* P C I E F W P F 7 R E G I S T E R */ 3498 3499 /* PF7 stores the Firmware Device Log parameters which allows Host Drivers to 3500 * access the "devlog" which needing to contact firmware. The encoding is 3501 * mostly the same as that returned by the DEVLOG command except for the size 3502 * which is encoded as the number of entries in multiples-1 of 128 here rather 3503 * than the memory size as is done in the DEVLOG command. Thus, 0 means 128 3504 * and 15 means 2048. This of course in turn constrains the allowed values 3505 * for the devlog size ... 3506 */ 3507 #define PCIE_FW_PF_DEVLOG 7 3508 3509 #define PCIE_FW_PF_DEVLOG_NENTRIES128_S 28 3510 #define PCIE_FW_PF_DEVLOG_NENTRIES128_M 0xf 3511 #define PCIE_FW_PF_DEVLOG_NENTRIES128_V(x) \ 3512 ((x) << PCIE_FW_PF_DEVLOG_NENTRIES128_S) 3513 #define PCIE_FW_PF_DEVLOG_NENTRIES128_G(x) \ 3514 (((x) >> PCIE_FW_PF_DEVLOG_NENTRIES128_S) & \ 3515 PCIE_FW_PF_DEVLOG_NENTRIES128_M) 3516 3517 #define PCIE_FW_PF_DEVLOG_ADDR16_S 4 3518 #define PCIE_FW_PF_DEVLOG_ADDR16_M 0xffffff 3519 #define PCIE_FW_PF_DEVLOG_ADDR16_V(x) ((x) << PCIE_FW_PF_DEVLOG_ADDR16_S) 3520 #define PCIE_FW_PF_DEVLOG_ADDR16_G(x) \ 3521 (((x) >> PCIE_FW_PF_DEVLOG_ADDR16_S) & PCIE_FW_PF_DEVLOG_ADDR16_M) 3522 3523 #define PCIE_FW_PF_DEVLOG_MEMTYPE_S 0 3524 #define PCIE_FW_PF_DEVLOG_MEMTYPE_M 0xf 3525 #define PCIE_FW_PF_DEVLOG_MEMTYPE_V(x) ((x) << PCIE_FW_PF_DEVLOG_MEMTYPE_S) 3526 #define PCIE_FW_PF_DEVLOG_MEMTYPE_G(x) \ 3527 (((x) >> PCIE_FW_PF_DEVLOG_MEMTYPE_S) & PCIE_FW_PF_DEVLOG_MEMTYPE_M) 3528 3529 #define MAX_IMM_OFLD_TX_DATA_WR_LEN (0xff + sizeof(struct fw_ofld_tx_data_wr)) 3530 3531 struct fw_crypto_lookaside_wr { 3532 __be32 op_to_cctx_size; 3533 __be32 len16_pkd; 3534 __be32 session_id; 3535 __be32 rx_chid_to_rx_q_id; 3536 __be32 key_addr; 3537 __be32 pld_size_hash_size; 3538 __be64 cookie; 3539 }; 3540 3541 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_S 24 3542 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_M 0xff 3543 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_V(x) \ 3544 ((x) << FW_CRYPTO_LOOKASIDE_WR_OPCODE_S) 3545 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_G(x) \ 3546 (((x) >> FW_CRYPTO_LOOKASIDE_WR_OPCODE_S) & \ 3547 FW_CRYPTO_LOOKASIDE_WR_OPCODE_M) 3548 3549 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_S 23 3550 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_M 0x1 3551 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_V(x) \ 3552 ((x) << FW_CRYPTO_LOOKASIDE_WR_COMPL_S) 3553 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_G(x) \ 3554 (((x) >> FW_CRYPTO_LOOKASIDE_WR_COMPL_S) & \ 3555 FW_CRYPTO_LOOKASIDE_WR_COMPL_M) 3556 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_F FW_CRYPTO_LOOKASIDE_WR_COMPL_V(1U) 3557 3558 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S 15 3559 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M 0xff 3560 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_V(x) \ 3561 ((x) << FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S) 3562 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_G(x) \ 3563 (((x) >> FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S) & \ 3564 FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M) 3565 3566 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S 5 3567 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M 0x3 3568 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_V(x) \ 3569 ((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S) 3570 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_G(x) \ 3571 (((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S) & \ 3572 FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M) 3573 3574 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S 0 3575 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M 0x1f 3576 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_V(x) \ 3577 ((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S) 3578 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_G(x) \ 3579 (((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S) & \ 3580 FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M) 3581 3582 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_S 0 3583 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_M 0xff 3584 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_V(x) \ 3585 ((x) << FW_CRYPTO_LOOKASIDE_WR_LEN16_S) 3586 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_G(x) \ 3587 (((x) >> FW_CRYPTO_LOOKASIDE_WR_LEN16_S) & \ 3588 FW_CRYPTO_LOOKASIDE_WR_LEN16_M) 3589 3590 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S 29 3591 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M 0x3 3592 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_V(x) \ 3593 ((x) << FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S) 3594 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_G(x) \ 3595 (((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S) & \ 3596 FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M) 3597 3598 #define FW_CRYPTO_LOOKASIDE_WR_LCB_S 27 3599 #define FW_CRYPTO_LOOKASIDE_WR_LCB_M 0x3 3600 #define FW_CRYPTO_LOOKASIDE_WR_LCB_V(x) \ 3601 ((x) << FW_CRYPTO_LOOKASIDE_WR_LCB_S) 3602 #define FW_CRYPTO_LOOKASIDE_WR_LCB_G(x) \ 3603 (((x) >> FW_CRYPTO_LOOKASIDE_WR_LCB_S) & FW_CRYPTO_LOOKASIDE_WR_LCB_M) 3604 3605 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_S 25 3606 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_M 0x3 3607 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_V(x) \ 3608 ((x) << FW_CRYPTO_LOOKASIDE_WR_PHASH_S) 3609 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_G(x) \ 3610 (((x) >> FW_CRYPTO_LOOKASIDE_WR_PHASH_S) & \ 3611 FW_CRYPTO_LOOKASIDE_WR_PHASH_M) 3612 3613 #define FW_CRYPTO_LOOKASIDE_WR_IV_S 23 3614 #define FW_CRYPTO_LOOKASIDE_WR_IV_M 0x3 3615 #define FW_CRYPTO_LOOKASIDE_WR_IV_V(x) \ 3616 ((x) << FW_CRYPTO_LOOKASIDE_WR_IV_S) 3617 #define FW_CRYPTO_LOOKASIDE_WR_IV_G(x) \ 3618 (((x) >> FW_CRYPTO_LOOKASIDE_WR_IV_S) & FW_CRYPTO_LOOKASIDE_WR_IV_M) 3619 3620 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_S 15 3621 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_M 0xff 3622 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_V(x) \ 3623 ((x) << FW_CRYPTO_LOOKASIDE_WR_FQIDX_S) 3624 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_G(x) \ 3625 (((x) >> FW_CRYPTO_LOOKASIDE_WR_FQIDX_S) & \ 3626 FW_CRYPTO_LOOKASIDE_WR_FQIDX_M) 3627 3628 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_S 10 3629 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_M 0x3 3630 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_V(x) \ 3631 ((x) << FW_CRYPTO_LOOKASIDE_WR_TX_CH_S) 3632 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_G(x) \ 3633 (((x) >> FW_CRYPTO_LOOKASIDE_WR_TX_CH_S) & \ 3634 FW_CRYPTO_LOOKASIDE_WR_TX_CH_M) 3635 3636 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S 0 3637 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M 0x3ff 3638 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_V(x) \ 3639 ((x) << FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S) 3640 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_G(x) \ 3641 (((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S) & \ 3642 FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M) 3643 3644 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S 24 3645 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M 0xff 3646 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_V(x) \ 3647 ((x) << FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S) 3648 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_G(x) \ 3649 (((x) >> FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S) & \ 3650 FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M) 3651 3652 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S 17 3653 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M 0x7f 3654 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_V(x) \ 3655 ((x) << FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S) 3656 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_G(x) \ 3657 (((x) >> FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S) & \ 3658 FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M) 3659 3660 #endif /* _T4FW_INTERFACE_H_ */ 3661