1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2009-2014 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef _T4FW_INTERFACE_H_ 36 #define _T4FW_INTERFACE_H_ 37 38 enum fw_retval { 39 FW_SUCCESS = 0, /* completed successfully */ 40 FW_EPERM = 1, /* operation not permitted */ 41 FW_ENOENT = 2, /* no such file or directory */ 42 FW_EIO = 5, /* input/output error; hw bad */ 43 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 44 FW_EAGAIN = 11, /* try again */ 45 FW_ENOMEM = 12, /* out of memory */ 46 FW_EFAULT = 14, /* bad address; fw bad */ 47 FW_EBUSY = 16, /* resource busy */ 48 FW_EEXIST = 17, /* file exists */ 49 FW_ENODEV = 19, /* no such device */ 50 FW_EINVAL = 22, /* invalid argument */ 51 FW_ENOSPC = 28, /* no space left on device */ 52 FW_ENOSYS = 38, /* functionality not implemented */ 53 FW_ENODATA = 61, /* no data available */ 54 FW_EPROTO = 71, /* protocol error */ 55 FW_EADDRINUSE = 98, /* address already in use */ 56 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 57 FW_ENETDOWN = 100, /* network is down */ 58 FW_ENETUNREACH = 101, /* network is unreachable */ 59 FW_ENOBUFS = 105, /* no buffer space available */ 60 FW_ETIMEDOUT = 110, /* timeout */ 61 FW_EINPROGRESS = 115, /* fw internal */ 62 FW_SCSI_ABORT_REQUESTED = 128, /* */ 63 FW_SCSI_ABORT_TIMEDOUT = 129, /* */ 64 FW_SCSI_ABORTED = 130, /* */ 65 FW_SCSI_CLOSE_REQUESTED = 131, /* */ 66 FW_ERR_LINK_DOWN = 132, /* */ 67 FW_RDEV_NOT_READY = 133, /* */ 68 FW_ERR_RDEV_LOST = 134, /* */ 69 FW_ERR_RDEV_LOGO = 135, /* */ 70 FW_FCOE_NO_XCHG = 136, /* */ 71 FW_SCSI_RSP_ERR = 137, /* */ 72 FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 73 FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 74 FW_SCSI_OVER_FLOW_ERR = 140, /* */ 75 FW_SCSI_DDP_ERR = 141, /* DDP error*/ 76 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 77 }; 78 79 #define FW_T4VF_SGE_BASE_ADDR 0x0000 80 #define FW_T4VF_MPS_BASE_ADDR 0x0100 81 #define FW_T4VF_PL_BASE_ADDR 0x0200 82 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240 83 #define FW_T4VF_CIM_BASE_ADDR 0x0300 84 85 enum fw_wr_opcodes { 86 FW_FILTER_WR = 0x02, 87 FW_ULPTX_WR = 0x04, 88 FW_TP_WR = 0x05, 89 FW_ETH_TX_PKT_WR = 0x08, 90 FW_OFLD_CONNECTION_WR = 0x2f, 91 FW_FLOWC_WR = 0x0a, 92 FW_OFLD_TX_DATA_WR = 0x0b, 93 FW_CMD_WR = 0x10, 94 FW_ETH_TX_PKT_VM_WR = 0x11, 95 FW_RI_RES_WR = 0x0c, 96 FW_RI_INIT_WR = 0x0d, 97 FW_RI_RDMA_WRITE_WR = 0x14, 98 FW_RI_SEND_WR = 0x15, 99 FW_RI_RDMA_READ_WR = 0x16, 100 FW_RI_RECV_WR = 0x17, 101 FW_RI_BIND_MW_WR = 0x18, 102 FW_RI_FR_NSMR_WR = 0x19, 103 FW_RI_INV_LSTAG_WR = 0x1a, 104 FW_LASTC2E_WR = 0x70 105 }; 106 107 struct fw_wr_hdr { 108 __be32 hi; 109 __be32 lo; 110 }; 111 112 /* work request opcode (hi) */ 113 #define FW_WR_OP_S 24 114 #define FW_WR_OP_M 0xff 115 #define FW_WR_OP_V(x) ((x) << FW_WR_OP_S) 116 #define FW_WR_OP_G(x) (((x) >> FW_WR_OP_S) & FW_WR_OP_M) 117 118 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */ 119 #define FW_WR_ATOMIC_S 23 120 #define FW_WR_ATOMIC_V(x) ((x) << FW_WR_ATOMIC_S) 121 122 /* flush flag (hi) - firmware flushes flushable work request buffered 123 * in the flow context. 124 */ 125 #define FW_WR_FLUSH_S 22 126 #define FW_WR_FLUSH_V(x) ((x) << FW_WR_FLUSH_S) 127 128 /* completion flag (hi) - firmware generates a cpl_fw6_ack */ 129 #define FW_WR_COMPL_S 21 130 #define FW_WR_COMPL_V(x) ((x) << FW_WR_COMPL_S) 131 #define FW_WR_COMPL_F FW_WR_COMPL_V(1U) 132 133 /* work request immediate data length (hi) */ 134 #define FW_WR_IMMDLEN_S 0 135 #define FW_WR_IMMDLEN_M 0xff 136 #define FW_WR_IMMDLEN_V(x) ((x) << FW_WR_IMMDLEN_S) 137 138 /* egress queue status update to associated ingress queue entry (lo) */ 139 #define FW_WR_EQUIQ_S 31 140 #define FW_WR_EQUIQ_V(x) ((x) << FW_WR_EQUIQ_S) 141 #define FW_WR_EQUIQ_F FW_WR_EQUIQ_V(1U) 142 143 /* egress queue status update to egress queue status entry (lo) */ 144 #define FW_WR_EQUEQ_S 30 145 #define FW_WR_EQUEQ_V(x) ((x) << FW_WR_EQUEQ_S) 146 #define FW_WR_EQUEQ_F FW_WR_EQUEQ_V(1U) 147 148 /* flow context identifier (lo) */ 149 #define FW_WR_FLOWID_S 8 150 #define FW_WR_FLOWID_V(x) ((x) << FW_WR_FLOWID_S) 151 152 /* length in units of 16-bytes (lo) */ 153 #define FW_WR_LEN16_S 0 154 #define FW_WR_LEN16_V(x) ((x) << FW_WR_LEN16_S) 155 156 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 157 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327 158 159 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 160 enum fw_filter_wr_cookie { 161 FW_FILTER_WR_SUCCESS, 162 FW_FILTER_WR_FLT_ADDED, 163 FW_FILTER_WR_FLT_DELETED, 164 FW_FILTER_WR_SMT_TBL_FULL, 165 FW_FILTER_WR_EINVAL, 166 }; 167 168 struct fw_filter_wr { 169 __be32 op_pkd; 170 __be32 len16_pkd; 171 __be64 r3; 172 __be32 tid_to_iq; 173 __be32 del_filter_to_l2tix; 174 __be16 ethtype; 175 __be16 ethtypem; 176 __u8 frag_to_ovlan_vldm; 177 __u8 smac_sel; 178 __be16 rx_chan_rx_rpl_iq; 179 __be32 maci_to_matchtypem; 180 __u8 ptcl; 181 __u8 ptclm; 182 __u8 ttyp; 183 __u8 ttypm; 184 __be16 ivlan; 185 __be16 ivlanm; 186 __be16 ovlan; 187 __be16 ovlanm; 188 __u8 lip[16]; 189 __u8 lipm[16]; 190 __u8 fip[16]; 191 __u8 fipm[16]; 192 __be16 lp; 193 __be16 lpm; 194 __be16 fp; 195 __be16 fpm; 196 __be16 r7; 197 __u8 sma[6]; 198 }; 199 200 #define FW_FILTER_WR_TID_S 12 201 #define FW_FILTER_WR_TID_M 0xfffff 202 #define FW_FILTER_WR_TID_V(x) ((x) << FW_FILTER_WR_TID_S) 203 #define FW_FILTER_WR_TID_G(x) \ 204 (((x) >> FW_FILTER_WR_TID_S) & FW_FILTER_WR_TID_M) 205 206 #define FW_FILTER_WR_RQTYPE_S 11 207 #define FW_FILTER_WR_RQTYPE_M 0x1 208 #define FW_FILTER_WR_RQTYPE_V(x) ((x) << FW_FILTER_WR_RQTYPE_S) 209 #define FW_FILTER_WR_RQTYPE_G(x) \ 210 (((x) >> FW_FILTER_WR_RQTYPE_S) & FW_FILTER_WR_RQTYPE_M) 211 #define FW_FILTER_WR_RQTYPE_F FW_FILTER_WR_RQTYPE_V(1U) 212 213 #define FW_FILTER_WR_NOREPLY_S 10 214 #define FW_FILTER_WR_NOREPLY_M 0x1 215 #define FW_FILTER_WR_NOREPLY_V(x) ((x) << FW_FILTER_WR_NOREPLY_S) 216 #define FW_FILTER_WR_NOREPLY_G(x) \ 217 (((x) >> FW_FILTER_WR_NOREPLY_S) & FW_FILTER_WR_NOREPLY_M) 218 #define FW_FILTER_WR_NOREPLY_F FW_FILTER_WR_NOREPLY_V(1U) 219 220 #define FW_FILTER_WR_IQ_S 0 221 #define FW_FILTER_WR_IQ_M 0x3ff 222 #define FW_FILTER_WR_IQ_V(x) ((x) << FW_FILTER_WR_IQ_S) 223 #define FW_FILTER_WR_IQ_G(x) \ 224 (((x) >> FW_FILTER_WR_IQ_S) & FW_FILTER_WR_IQ_M) 225 226 #define FW_FILTER_WR_DEL_FILTER_S 31 227 #define FW_FILTER_WR_DEL_FILTER_M 0x1 228 #define FW_FILTER_WR_DEL_FILTER_V(x) ((x) << FW_FILTER_WR_DEL_FILTER_S) 229 #define FW_FILTER_WR_DEL_FILTER_G(x) \ 230 (((x) >> FW_FILTER_WR_DEL_FILTER_S) & FW_FILTER_WR_DEL_FILTER_M) 231 #define FW_FILTER_WR_DEL_FILTER_F FW_FILTER_WR_DEL_FILTER_V(1U) 232 233 #define FW_FILTER_WR_RPTTID_S 25 234 #define FW_FILTER_WR_RPTTID_M 0x1 235 #define FW_FILTER_WR_RPTTID_V(x) ((x) << FW_FILTER_WR_RPTTID_S) 236 #define FW_FILTER_WR_RPTTID_G(x) \ 237 (((x) >> FW_FILTER_WR_RPTTID_S) & FW_FILTER_WR_RPTTID_M) 238 #define FW_FILTER_WR_RPTTID_F FW_FILTER_WR_RPTTID_V(1U) 239 240 #define FW_FILTER_WR_DROP_S 24 241 #define FW_FILTER_WR_DROP_M 0x1 242 #define FW_FILTER_WR_DROP_V(x) ((x) << FW_FILTER_WR_DROP_S) 243 #define FW_FILTER_WR_DROP_G(x) \ 244 (((x) >> FW_FILTER_WR_DROP_S) & FW_FILTER_WR_DROP_M) 245 #define FW_FILTER_WR_DROP_F FW_FILTER_WR_DROP_V(1U) 246 247 #define FW_FILTER_WR_DIRSTEER_S 23 248 #define FW_FILTER_WR_DIRSTEER_M 0x1 249 #define FW_FILTER_WR_DIRSTEER_V(x) ((x) << FW_FILTER_WR_DIRSTEER_S) 250 #define FW_FILTER_WR_DIRSTEER_G(x) \ 251 (((x) >> FW_FILTER_WR_DIRSTEER_S) & FW_FILTER_WR_DIRSTEER_M) 252 #define FW_FILTER_WR_DIRSTEER_F FW_FILTER_WR_DIRSTEER_V(1U) 253 254 #define FW_FILTER_WR_MASKHASH_S 22 255 #define FW_FILTER_WR_MASKHASH_M 0x1 256 #define FW_FILTER_WR_MASKHASH_V(x) ((x) << FW_FILTER_WR_MASKHASH_S) 257 #define FW_FILTER_WR_MASKHASH_G(x) \ 258 (((x) >> FW_FILTER_WR_MASKHASH_S) & FW_FILTER_WR_MASKHASH_M) 259 #define FW_FILTER_WR_MASKHASH_F FW_FILTER_WR_MASKHASH_V(1U) 260 261 #define FW_FILTER_WR_DIRSTEERHASH_S 21 262 #define FW_FILTER_WR_DIRSTEERHASH_M 0x1 263 #define FW_FILTER_WR_DIRSTEERHASH_V(x) ((x) << FW_FILTER_WR_DIRSTEERHASH_S) 264 #define FW_FILTER_WR_DIRSTEERHASH_G(x) \ 265 (((x) >> FW_FILTER_WR_DIRSTEERHASH_S) & FW_FILTER_WR_DIRSTEERHASH_M) 266 #define FW_FILTER_WR_DIRSTEERHASH_F FW_FILTER_WR_DIRSTEERHASH_V(1U) 267 268 #define FW_FILTER_WR_LPBK_S 20 269 #define FW_FILTER_WR_LPBK_M 0x1 270 #define FW_FILTER_WR_LPBK_V(x) ((x) << FW_FILTER_WR_LPBK_S) 271 #define FW_FILTER_WR_LPBK_G(x) \ 272 (((x) >> FW_FILTER_WR_LPBK_S) & FW_FILTER_WR_LPBK_M) 273 #define FW_FILTER_WR_LPBK_F FW_FILTER_WR_LPBK_V(1U) 274 275 #define FW_FILTER_WR_DMAC_S 19 276 #define FW_FILTER_WR_DMAC_M 0x1 277 #define FW_FILTER_WR_DMAC_V(x) ((x) << FW_FILTER_WR_DMAC_S) 278 #define FW_FILTER_WR_DMAC_G(x) \ 279 (((x) >> FW_FILTER_WR_DMAC_S) & FW_FILTER_WR_DMAC_M) 280 #define FW_FILTER_WR_DMAC_F FW_FILTER_WR_DMAC_V(1U) 281 282 #define FW_FILTER_WR_SMAC_S 18 283 #define FW_FILTER_WR_SMAC_M 0x1 284 #define FW_FILTER_WR_SMAC_V(x) ((x) << FW_FILTER_WR_SMAC_S) 285 #define FW_FILTER_WR_SMAC_G(x) \ 286 (((x) >> FW_FILTER_WR_SMAC_S) & FW_FILTER_WR_SMAC_M) 287 #define FW_FILTER_WR_SMAC_F FW_FILTER_WR_SMAC_V(1U) 288 289 #define FW_FILTER_WR_INSVLAN_S 17 290 #define FW_FILTER_WR_INSVLAN_M 0x1 291 #define FW_FILTER_WR_INSVLAN_V(x) ((x) << FW_FILTER_WR_INSVLAN_S) 292 #define FW_FILTER_WR_INSVLAN_G(x) \ 293 (((x) >> FW_FILTER_WR_INSVLAN_S) & FW_FILTER_WR_INSVLAN_M) 294 #define FW_FILTER_WR_INSVLAN_F FW_FILTER_WR_INSVLAN_V(1U) 295 296 #define FW_FILTER_WR_RMVLAN_S 16 297 #define FW_FILTER_WR_RMVLAN_M 0x1 298 #define FW_FILTER_WR_RMVLAN_V(x) ((x) << FW_FILTER_WR_RMVLAN_S) 299 #define FW_FILTER_WR_RMVLAN_G(x) \ 300 (((x) >> FW_FILTER_WR_RMVLAN_S) & FW_FILTER_WR_RMVLAN_M) 301 #define FW_FILTER_WR_RMVLAN_F FW_FILTER_WR_RMVLAN_V(1U) 302 303 #define FW_FILTER_WR_HITCNTS_S 15 304 #define FW_FILTER_WR_HITCNTS_M 0x1 305 #define FW_FILTER_WR_HITCNTS_V(x) ((x) << FW_FILTER_WR_HITCNTS_S) 306 #define FW_FILTER_WR_HITCNTS_G(x) \ 307 (((x) >> FW_FILTER_WR_HITCNTS_S) & FW_FILTER_WR_HITCNTS_M) 308 #define FW_FILTER_WR_HITCNTS_F FW_FILTER_WR_HITCNTS_V(1U) 309 310 #define FW_FILTER_WR_TXCHAN_S 13 311 #define FW_FILTER_WR_TXCHAN_M 0x3 312 #define FW_FILTER_WR_TXCHAN_V(x) ((x) << FW_FILTER_WR_TXCHAN_S) 313 #define FW_FILTER_WR_TXCHAN_G(x) \ 314 (((x) >> FW_FILTER_WR_TXCHAN_S) & FW_FILTER_WR_TXCHAN_M) 315 316 #define FW_FILTER_WR_PRIO_S 12 317 #define FW_FILTER_WR_PRIO_M 0x1 318 #define FW_FILTER_WR_PRIO_V(x) ((x) << FW_FILTER_WR_PRIO_S) 319 #define FW_FILTER_WR_PRIO_G(x) \ 320 (((x) >> FW_FILTER_WR_PRIO_S) & FW_FILTER_WR_PRIO_M) 321 #define FW_FILTER_WR_PRIO_F FW_FILTER_WR_PRIO_V(1U) 322 323 #define FW_FILTER_WR_L2TIX_S 0 324 #define FW_FILTER_WR_L2TIX_M 0xfff 325 #define FW_FILTER_WR_L2TIX_V(x) ((x) << FW_FILTER_WR_L2TIX_S) 326 #define FW_FILTER_WR_L2TIX_G(x) \ 327 (((x) >> FW_FILTER_WR_L2TIX_S) & FW_FILTER_WR_L2TIX_M) 328 329 #define FW_FILTER_WR_FRAG_S 7 330 #define FW_FILTER_WR_FRAG_M 0x1 331 #define FW_FILTER_WR_FRAG_V(x) ((x) << FW_FILTER_WR_FRAG_S) 332 #define FW_FILTER_WR_FRAG_G(x) \ 333 (((x) >> FW_FILTER_WR_FRAG_S) & FW_FILTER_WR_FRAG_M) 334 #define FW_FILTER_WR_FRAG_F FW_FILTER_WR_FRAG_V(1U) 335 336 #define FW_FILTER_WR_FRAGM_S 6 337 #define FW_FILTER_WR_FRAGM_M 0x1 338 #define FW_FILTER_WR_FRAGM_V(x) ((x) << FW_FILTER_WR_FRAGM_S) 339 #define FW_FILTER_WR_FRAGM_G(x) \ 340 (((x) >> FW_FILTER_WR_FRAGM_S) & FW_FILTER_WR_FRAGM_M) 341 #define FW_FILTER_WR_FRAGM_F FW_FILTER_WR_FRAGM_V(1U) 342 343 #define FW_FILTER_WR_IVLAN_VLD_S 5 344 #define FW_FILTER_WR_IVLAN_VLD_M 0x1 345 #define FW_FILTER_WR_IVLAN_VLD_V(x) ((x) << FW_FILTER_WR_IVLAN_VLD_S) 346 #define FW_FILTER_WR_IVLAN_VLD_G(x) \ 347 (((x) >> FW_FILTER_WR_IVLAN_VLD_S) & FW_FILTER_WR_IVLAN_VLD_M) 348 #define FW_FILTER_WR_IVLAN_VLD_F FW_FILTER_WR_IVLAN_VLD_V(1U) 349 350 #define FW_FILTER_WR_OVLAN_VLD_S 4 351 #define FW_FILTER_WR_OVLAN_VLD_M 0x1 352 #define FW_FILTER_WR_OVLAN_VLD_V(x) ((x) << FW_FILTER_WR_OVLAN_VLD_S) 353 #define FW_FILTER_WR_OVLAN_VLD_G(x) \ 354 (((x) >> FW_FILTER_WR_OVLAN_VLD_S) & FW_FILTER_WR_OVLAN_VLD_M) 355 #define FW_FILTER_WR_OVLAN_VLD_F FW_FILTER_WR_OVLAN_VLD_V(1U) 356 357 #define FW_FILTER_WR_IVLAN_VLDM_S 3 358 #define FW_FILTER_WR_IVLAN_VLDM_M 0x1 359 #define FW_FILTER_WR_IVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_IVLAN_VLDM_S) 360 #define FW_FILTER_WR_IVLAN_VLDM_G(x) \ 361 (((x) >> FW_FILTER_WR_IVLAN_VLDM_S) & FW_FILTER_WR_IVLAN_VLDM_M) 362 #define FW_FILTER_WR_IVLAN_VLDM_F FW_FILTER_WR_IVLAN_VLDM_V(1U) 363 364 #define FW_FILTER_WR_OVLAN_VLDM_S 2 365 #define FW_FILTER_WR_OVLAN_VLDM_M 0x1 366 #define FW_FILTER_WR_OVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_OVLAN_VLDM_S) 367 #define FW_FILTER_WR_OVLAN_VLDM_G(x) \ 368 (((x) >> FW_FILTER_WR_OVLAN_VLDM_S) & FW_FILTER_WR_OVLAN_VLDM_M) 369 #define FW_FILTER_WR_OVLAN_VLDM_F FW_FILTER_WR_OVLAN_VLDM_V(1U) 370 371 #define FW_FILTER_WR_RX_CHAN_S 15 372 #define FW_FILTER_WR_RX_CHAN_M 0x1 373 #define FW_FILTER_WR_RX_CHAN_V(x) ((x) << FW_FILTER_WR_RX_CHAN_S) 374 #define FW_FILTER_WR_RX_CHAN_G(x) \ 375 (((x) >> FW_FILTER_WR_RX_CHAN_S) & FW_FILTER_WR_RX_CHAN_M) 376 #define FW_FILTER_WR_RX_CHAN_F FW_FILTER_WR_RX_CHAN_V(1U) 377 378 #define FW_FILTER_WR_RX_RPL_IQ_S 0 379 #define FW_FILTER_WR_RX_RPL_IQ_M 0x3ff 380 #define FW_FILTER_WR_RX_RPL_IQ_V(x) ((x) << FW_FILTER_WR_RX_RPL_IQ_S) 381 #define FW_FILTER_WR_RX_RPL_IQ_G(x) \ 382 (((x) >> FW_FILTER_WR_RX_RPL_IQ_S) & FW_FILTER_WR_RX_RPL_IQ_M) 383 384 #define FW_FILTER_WR_MACI_S 23 385 #define FW_FILTER_WR_MACI_M 0x1ff 386 #define FW_FILTER_WR_MACI_V(x) ((x) << FW_FILTER_WR_MACI_S) 387 #define FW_FILTER_WR_MACI_G(x) \ 388 (((x) >> FW_FILTER_WR_MACI_S) & FW_FILTER_WR_MACI_M) 389 390 #define FW_FILTER_WR_MACIM_S 14 391 #define FW_FILTER_WR_MACIM_M 0x1ff 392 #define FW_FILTER_WR_MACIM_V(x) ((x) << FW_FILTER_WR_MACIM_S) 393 #define FW_FILTER_WR_MACIM_G(x) \ 394 (((x) >> FW_FILTER_WR_MACIM_S) & FW_FILTER_WR_MACIM_M) 395 396 #define FW_FILTER_WR_FCOE_S 13 397 #define FW_FILTER_WR_FCOE_M 0x1 398 #define FW_FILTER_WR_FCOE_V(x) ((x) << FW_FILTER_WR_FCOE_S) 399 #define FW_FILTER_WR_FCOE_G(x) \ 400 (((x) >> FW_FILTER_WR_FCOE_S) & FW_FILTER_WR_FCOE_M) 401 #define FW_FILTER_WR_FCOE_F FW_FILTER_WR_FCOE_V(1U) 402 403 #define FW_FILTER_WR_FCOEM_S 12 404 #define FW_FILTER_WR_FCOEM_M 0x1 405 #define FW_FILTER_WR_FCOEM_V(x) ((x) << FW_FILTER_WR_FCOEM_S) 406 #define FW_FILTER_WR_FCOEM_G(x) \ 407 (((x) >> FW_FILTER_WR_FCOEM_S) & FW_FILTER_WR_FCOEM_M) 408 #define FW_FILTER_WR_FCOEM_F FW_FILTER_WR_FCOEM_V(1U) 409 410 #define FW_FILTER_WR_PORT_S 9 411 #define FW_FILTER_WR_PORT_M 0x7 412 #define FW_FILTER_WR_PORT_V(x) ((x) << FW_FILTER_WR_PORT_S) 413 #define FW_FILTER_WR_PORT_G(x) \ 414 (((x) >> FW_FILTER_WR_PORT_S) & FW_FILTER_WR_PORT_M) 415 416 #define FW_FILTER_WR_PORTM_S 6 417 #define FW_FILTER_WR_PORTM_M 0x7 418 #define FW_FILTER_WR_PORTM_V(x) ((x) << FW_FILTER_WR_PORTM_S) 419 #define FW_FILTER_WR_PORTM_G(x) \ 420 (((x) >> FW_FILTER_WR_PORTM_S) & FW_FILTER_WR_PORTM_M) 421 422 #define FW_FILTER_WR_MATCHTYPE_S 3 423 #define FW_FILTER_WR_MATCHTYPE_M 0x7 424 #define FW_FILTER_WR_MATCHTYPE_V(x) ((x) << FW_FILTER_WR_MATCHTYPE_S) 425 #define FW_FILTER_WR_MATCHTYPE_G(x) \ 426 (((x) >> FW_FILTER_WR_MATCHTYPE_S) & FW_FILTER_WR_MATCHTYPE_M) 427 428 #define FW_FILTER_WR_MATCHTYPEM_S 0 429 #define FW_FILTER_WR_MATCHTYPEM_M 0x7 430 #define FW_FILTER_WR_MATCHTYPEM_V(x) ((x) << FW_FILTER_WR_MATCHTYPEM_S) 431 #define FW_FILTER_WR_MATCHTYPEM_G(x) \ 432 (((x) >> FW_FILTER_WR_MATCHTYPEM_S) & FW_FILTER_WR_MATCHTYPEM_M) 433 434 struct fw_ulptx_wr { 435 __be32 op_to_compl; 436 __be32 flowid_len16; 437 u64 cookie; 438 }; 439 440 struct fw_tp_wr { 441 __be32 op_to_immdlen; 442 __be32 flowid_len16; 443 u64 cookie; 444 }; 445 446 struct fw_eth_tx_pkt_wr { 447 __be32 op_immdlen; 448 __be32 equiq_to_len16; 449 __be64 r3; 450 }; 451 452 struct fw_ofld_connection_wr { 453 __be32 op_compl; 454 __be32 len16_pkd; 455 __u64 cookie; 456 __be64 r2; 457 __be64 r3; 458 struct fw_ofld_connection_le { 459 __be32 version_cpl; 460 __be32 filter; 461 __be32 r1; 462 __be16 lport; 463 __be16 pport; 464 union fw_ofld_connection_leip { 465 struct fw_ofld_connection_le_ipv4 { 466 __be32 pip; 467 __be32 lip; 468 __be64 r0; 469 __be64 r1; 470 __be64 r2; 471 } ipv4; 472 struct fw_ofld_connection_le_ipv6 { 473 __be64 pip_hi; 474 __be64 pip_lo; 475 __be64 lip_hi; 476 __be64 lip_lo; 477 } ipv6; 478 } u; 479 } le; 480 struct fw_ofld_connection_tcb { 481 __be32 t_state_to_astid; 482 __be16 cplrxdataack_cplpassacceptrpl; 483 __be16 rcv_adv; 484 __be32 rcv_nxt; 485 __be32 tx_max; 486 __be64 opt0; 487 __be32 opt2; 488 __be32 r1; 489 __be64 r2; 490 __be64 r3; 491 } tcb; 492 }; 493 494 #define FW_OFLD_CONNECTION_WR_VERSION_S 31 495 #define FW_OFLD_CONNECTION_WR_VERSION_M 0x1 496 #define FW_OFLD_CONNECTION_WR_VERSION_V(x) \ 497 ((x) << FW_OFLD_CONNECTION_WR_VERSION_S) 498 #define FW_OFLD_CONNECTION_WR_VERSION_G(x) \ 499 (((x) >> FW_OFLD_CONNECTION_WR_VERSION_S) & \ 500 FW_OFLD_CONNECTION_WR_VERSION_M) 501 #define FW_OFLD_CONNECTION_WR_VERSION_F \ 502 FW_OFLD_CONNECTION_WR_VERSION_V(1U) 503 504 #define FW_OFLD_CONNECTION_WR_CPL_S 30 505 #define FW_OFLD_CONNECTION_WR_CPL_M 0x1 506 #define FW_OFLD_CONNECTION_WR_CPL_V(x) ((x) << FW_OFLD_CONNECTION_WR_CPL_S) 507 #define FW_OFLD_CONNECTION_WR_CPL_G(x) \ 508 (((x) >> FW_OFLD_CONNECTION_WR_CPL_S) & FW_OFLD_CONNECTION_WR_CPL_M) 509 #define FW_OFLD_CONNECTION_WR_CPL_F FW_OFLD_CONNECTION_WR_CPL_V(1U) 510 511 #define FW_OFLD_CONNECTION_WR_T_STATE_S 28 512 #define FW_OFLD_CONNECTION_WR_T_STATE_M 0xf 513 #define FW_OFLD_CONNECTION_WR_T_STATE_V(x) \ 514 ((x) << FW_OFLD_CONNECTION_WR_T_STATE_S) 515 #define FW_OFLD_CONNECTION_WR_T_STATE_G(x) \ 516 (((x) >> FW_OFLD_CONNECTION_WR_T_STATE_S) & \ 517 FW_OFLD_CONNECTION_WR_T_STATE_M) 518 519 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_S 24 520 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_M 0xf 521 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_V(x) \ 522 ((x) << FW_OFLD_CONNECTION_WR_RCV_SCALE_S) 523 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_G(x) \ 524 (((x) >> FW_OFLD_CONNECTION_WR_RCV_SCALE_S) & \ 525 FW_OFLD_CONNECTION_WR_RCV_SCALE_M) 526 527 #define FW_OFLD_CONNECTION_WR_ASTID_S 0 528 #define FW_OFLD_CONNECTION_WR_ASTID_M 0xffffff 529 #define FW_OFLD_CONNECTION_WR_ASTID_V(x) \ 530 ((x) << FW_OFLD_CONNECTION_WR_ASTID_S) 531 #define FW_OFLD_CONNECTION_WR_ASTID_G(x) \ 532 (((x) >> FW_OFLD_CONNECTION_WR_ASTID_S) & FW_OFLD_CONNECTION_WR_ASTID_M) 533 534 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S 15 535 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M 0x1 536 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(x) \ 537 ((x) << FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) 538 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_G(x) \ 539 (((x) >> FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) & \ 540 FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M) 541 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_F \ 542 FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(1U) 543 544 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S 14 545 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M 0x1 546 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(x) \ 547 ((x) << FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) 548 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_G(x) \ 549 (((x) >> FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) & \ 550 FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M) 551 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_F \ 552 FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(1U) 553 554 enum fw_flowc_mnem { 555 FW_FLOWC_MNEM_PFNVFN, /* PFN [15:8] VFN [7:0] */ 556 FW_FLOWC_MNEM_CH, 557 FW_FLOWC_MNEM_PORT, 558 FW_FLOWC_MNEM_IQID, 559 FW_FLOWC_MNEM_SNDNXT, 560 FW_FLOWC_MNEM_RCVNXT, 561 FW_FLOWC_MNEM_SNDBUF, 562 FW_FLOWC_MNEM_MSS, 563 FW_FLOWC_MNEM_TXDATAPLEN_MAX, 564 }; 565 566 struct fw_flowc_mnemval { 567 u8 mnemonic; 568 u8 r4[3]; 569 __be32 val; 570 }; 571 572 struct fw_flowc_wr { 573 __be32 op_to_nparams; 574 __be32 flowid_len16; 575 struct fw_flowc_mnemval mnemval[0]; 576 }; 577 578 #define FW_FLOWC_WR_NPARAMS_S 0 579 #define FW_FLOWC_WR_NPARAMS_V(x) ((x) << FW_FLOWC_WR_NPARAMS_S) 580 581 struct fw_ofld_tx_data_wr { 582 __be32 op_to_immdlen; 583 __be32 flowid_len16; 584 __be32 plen; 585 __be32 tunnel_to_proxy; 586 }; 587 588 #define FW_OFLD_TX_DATA_WR_TUNNEL_S 19 589 #define FW_OFLD_TX_DATA_WR_TUNNEL_V(x) ((x) << FW_OFLD_TX_DATA_WR_TUNNEL_S) 590 591 #define FW_OFLD_TX_DATA_WR_SAVE_S 18 592 #define FW_OFLD_TX_DATA_WR_SAVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SAVE_S) 593 594 #define FW_OFLD_TX_DATA_WR_FLUSH_S 17 595 #define FW_OFLD_TX_DATA_WR_FLUSH_V(x) ((x) << FW_OFLD_TX_DATA_WR_FLUSH_S) 596 #define FW_OFLD_TX_DATA_WR_FLUSH_F FW_OFLD_TX_DATA_WR_FLUSH_V(1U) 597 598 #define FW_OFLD_TX_DATA_WR_URGENT_S 16 599 #define FW_OFLD_TX_DATA_WR_URGENT_V(x) ((x) << FW_OFLD_TX_DATA_WR_URGENT_S) 600 601 #define FW_OFLD_TX_DATA_WR_MORE_S 15 602 #define FW_OFLD_TX_DATA_WR_MORE_V(x) ((x) << FW_OFLD_TX_DATA_WR_MORE_S) 603 604 #define FW_OFLD_TX_DATA_WR_SHOVE_S 14 605 #define FW_OFLD_TX_DATA_WR_SHOVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SHOVE_S) 606 #define FW_OFLD_TX_DATA_WR_SHOVE_F FW_OFLD_TX_DATA_WR_SHOVE_V(1U) 607 608 #define FW_OFLD_TX_DATA_WR_ULPMODE_S 10 609 #define FW_OFLD_TX_DATA_WR_ULPMODE_V(x) ((x) << FW_OFLD_TX_DATA_WR_ULPMODE_S) 610 611 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_S 6 612 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_V(x) \ 613 ((x) << FW_OFLD_TX_DATA_WR_ULPSUBMODE_S) 614 615 struct fw_cmd_wr { 616 __be32 op_dma; 617 __be32 len16_pkd; 618 __be64 cookie_daddr; 619 }; 620 621 #define FW_CMD_WR_DMA_S 17 622 #define FW_CMD_WR_DMA_V(x) ((x) << FW_CMD_WR_DMA_S) 623 624 struct fw_eth_tx_pkt_vm_wr { 625 __be32 op_immdlen; 626 __be32 equiq_to_len16; 627 __be32 r3[2]; 628 u8 ethmacdst[6]; 629 u8 ethmacsrc[6]; 630 __be16 ethtype; 631 __be16 vlantci; 632 }; 633 634 #define FW_CMD_MAX_TIMEOUT 10000 635 636 /* 637 * If a host driver does a HELLO and discovers that there's already a MASTER 638 * selected, we may have to wait for that MASTER to finish issuing RESET, 639 * configuration and INITIALIZE commands. Also, there's a possibility that 640 * our own HELLO may get lost if it happens right as the MASTER is issuign a 641 * RESET command, so we need to be willing to make a few retries of our HELLO. 642 */ 643 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 644 #define FW_CMD_HELLO_RETRIES 3 645 646 647 enum fw_cmd_opcodes { 648 FW_LDST_CMD = 0x01, 649 FW_RESET_CMD = 0x03, 650 FW_HELLO_CMD = 0x04, 651 FW_BYE_CMD = 0x05, 652 FW_INITIALIZE_CMD = 0x06, 653 FW_CAPS_CONFIG_CMD = 0x07, 654 FW_PARAMS_CMD = 0x08, 655 FW_PFVF_CMD = 0x09, 656 FW_IQ_CMD = 0x10, 657 FW_EQ_MNGT_CMD = 0x11, 658 FW_EQ_ETH_CMD = 0x12, 659 FW_EQ_CTRL_CMD = 0x13, 660 FW_EQ_OFLD_CMD = 0x21, 661 FW_VI_CMD = 0x14, 662 FW_VI_MAC_CMD = 0x15, 663 FW_VI_RXMODE_CMD = 0x16, 664 FW_VI_ENABLE_CMD = 0x17, 665 FW_ACL_MAC_CMD = 0x18, 666 FW_ACL_VLAN_CMD = 0x19, 667 FW_VI_STATS_CMD = 0x1a, 668 FW_PORT_CMD = 0x1b, 669 FW_PORT_STATS_CMD = 0x1c, 670 FW_PORT_LB_STATS_CMD = 0x1d, 671 FW_PORT_TRACE_CMD = 0x1e, 672 FW_PORT_TRACE_MMAP_CMD = 0x1f, 673 FW_RSS_IND_TBL_CMD = 0x20, 674 FW_RSS_GLB_CONFIG_CMD = 0x22, 675 FW_RSS_VI_CONFIG_CMD = 0x23, 676 FW_DEVLOG_CMD = 0x25, 677 FW_CLIP_CMD = 0x28, 678 FW_LASTC2E_CMD = 0x40, 679 FW_ERROR_CMD = 0x80, 680 FW_DEBUG_CMD = 0x81, 681 }; 682 683 enum fw_cmd_cap { 684 FW_CMD_CAP_PF = 0x01, 685 FW_CMD_CAP_DMAQ = 0x02, 686 FW_CMD_CAP_PORT = 0x04, 687 FW_CMD_CAP_PORTPROMISC = 0x08, 688 FW_CMD_CAP_PORTSTATS = 0x10, 689 FW_CMD_CAP_VF = 0x80, 690 }; 691 692 /* 693 * Generic command header flit0 694 */ 695 struct fw_cmd_hdr { 696 __be32 hi; 697 __be32 lo; 698 }; 699 700 #define FW_CMD_OP_S 24 701 #define FW_CMD_OP_M 0xff 702 #define FW_CMD_OP_V(x) ((x) << FW_CMD_OP_S) 703 #define FW_CMD_OP_G(x) (((x) >> FW_CMD_OP_S) & FW_CMD_OP_M) 704 705 #define FW_CMD_REQUEST_S 23 706 #define FW_CMD_REQUEST_V(x) ((x) << FW_CMD_REQUEST_S) 707 #define FW_CMD_REQUEST_F FW_CMD_REQUEST_V(1U) 708 709 #define FW_CMD_READ_S 22 710 #define FW_CMD_READ_V(x) ((x) << FW_CMD_READ_S) 711 #define FW_CMD_READ_F FW_CMD_READ_V(1U) 712 713 #define FW_CMD_WRITE_S 21 714 #define FW_CMD_WRITE_V(x) ((x) << FW_CMD_WRITE_S) 715 #define FW_CMD_WRITE_F FW_CMD_WRITE_V(1U) 716 717 #define FW_CMD_EXEC_S 20 718 #define FW_CMD_EXEC_V(x) ((x) << FW_CMD_EXEC_S) 719 #define FW_CMD_EXEC_F FW_CMD_EXEC_V(1U) 720 721 #define FW_CMD_RAMASK_S 20 722 #define FW_CMD_RAMASK_V(x) ((x) << FW_CMD_RAMASK_S) 723 724 #define FW_CMD_RETVAL_S 8 725 #define FW_CMD_RETVAL_M 0xff 726 #define FW_CMD_RETVAL_V(x) ((x) << FW_CMD_RETVAL_S) 727 #define FW_CMD_RETVAL_G(x) (((x) >> FW_CMD_RETVAL_S) & FW_CMD_RETVAL_M) 728 729 #define FW_CMD_LEN16_S 0 730 #define FW_CMD_LEN16_V(x) ((x) << FW_CMD_LEN16_S) 731 732 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 733 734 enum fw_ldst_addrspc { 735 FW_LDST_ADDRSPC_FIRMWARE = 0x0001, 736 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, 737 FW_LDST_ADDRSPC_SGE_INGC = 0x0009, 738 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, 739 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 740 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 741 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 742 FW_LDST_ADDRSPC_TP_MIB = 0x0012, 743 FW_LDST_ADDRSPC_MDIO = 0x0018, 744 FW_LDST_ADDRSPC_MPS = 0x0020, 745 FW_LDST_ADDRSPC_FUNC = 0x0028, 746 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, 747 }; 748 749 enum fw_ldst_mps_fid { 750 FW_LDST_MPS_ATRB, 751 FW_LDST_MPS_RPLC 752 }; 753 754 enum fw_ldst_func_access_ctl { 755 FW_LDST_FUNC_ACC_CTL_VIID, 756 FW_LDST_FUNC_ACC_CTL_FID 757 }; 758 759 enum fw_ldst_func_mod_index { 760 FW_LDST_FUNC_MPS 761 }; 762 763 struct fw_ldst_cmd { 764 __be32 op_to_addrspace; 765 #define FW_LDST_CMD_ADDRSPACE_S 0 766 #define FW_LDST_CMD_ADDRSPACE_V(x) ((x) << FW_LDST_CMD_ADDRSPACE_S) 767 __be32 cycles_to_len16; 768 union fw_ldst { 769 struct fw_ldst_addrval { 770 __be32 addr; 771 __be32 val; 772 } addrval; 773 struct fw_ldst_idctxt { 774 __be32 physid; 775 __be32 msg_pkd; 776 __be32 ctxt_data7; 777 __be32 ctxt_data6; 778 __be32 ctxt_data5; 779 __be32 ctxt_data4; 780 __be32 ctxt_data3; 781 __be32 ctxt_data2; 782 __be32 ctxt_data1; 783 __be32 ctxt_data0; 784 } idctxt; 785 struct fw_ldst_mdio { 786 __be16 paddr_mmd; 787 __be16 raddr; 788 __be16 vctl; 789 __be16 rval; 790 } mdio; 791 struct fw_ldst_mps { 792 __be16 fid_ctl; 793 __be16 rplcpf_pkd; 794 __be32 rplc127_96; 795 __be32 rplc95_64; 796 __be32 rplc63_32; 797 __be32 rplc31_0; 798 __be32 atrb; 799 __be16 vlan[16]; 800 } mps; 801 struct fw_ldst_func { 802 u8 access_ctl; 803 u8 mod_index; 804 __be16 ctl_id; 805 __be32 offset; 806 __be64 data0; 807 __be64 data1; 808 } func; 809 struct fw_ldst_pcie { 810 u8 ctrl_to_fn; 811 u8 bnum; 812 u8 r; 813 u8 ext_r; 814 u8 select_naccess; 815 u8 pcie_fn; 816 __be16 nset_pkd; 817 __be32 data[12]; 818 } pcie; 819 } u; 820 }; 821 822 #define FW_LDST_CMD_MSG_S 31 823 #define FW_LDST_CMD_MSG_V(x) ((x) << FW_LDST_CMD_MSG_S) 824 825 #define FW_LDST_CMD_PADDR_S 8 826 #define FW_LDST_CMD_PADDR_V(x) ((x) << FW_LDST_CMD_PADDR_S) 827 828 #define FW_LDST_CMD_MMD_S 0 829 #define FW_LDST_CMD_MMD_V(x) ((x) << FW_LDST_CMD_MMD_S) 830 831 #define FW_LDST_CMD_FID_S 15 832 #define FW_LDST_CMD_FID_V(x) ((x) << FW_LDST_CMD_FID_S) 833 834 #define FW_LDST_CMD_CTL_S 0 835 #define FW_LDST_CMD_CTL_V(x) ((x) << FW_LDST_CMD_CTL_S) 836 837 #define FW_LDST_CMD_RPLCPF_S 0 838 #define FW_LDST_CMD_RPLCPF_V(x) ((x) << FW_LDST_CMD_RPLCPF_S) 839 840 #define FW_LDST_CMD_LC_S 4 841 #define FW_LDST_CMD_LC_V(x) ((x) << FW_LDST_CMD_LC_S) 842 #define FW_LDST_CMD_LC_F FW_LDST_CMD_LC_V(1U) 843 844 #define FW_LDST_CMD_FN_S 0 845 #define FW_LDST_CMD_FN_V(x) ((x) << FW_LDST_CMD_FN_S) 846 847 #define FW_LDST_CMD_NACCESS_S 0 848 #define FW_LDST_CMD_NACCESS_V(x) ((x) << FW_LDST_CMD_NACCESS_S) 849 850 struct fw_reset_cmd { 851 __be32 op_to_write; 852 __be32 retval_len16; 853 __be32 val; 854 __be32 halt_pkd; 855 }; 856 857 #define FW_RESET_CMD_HALT_S 31 858 #define FW_RESET_CMD_HALT_M 0x1 859 #define FW_RESET_CMD_HALT_V(x) ((x) << FW_RESET_CMD_HALT_S) 860 #define FW_RESET_CMD_HALT_G(x) \ 861 (((x) >> FW_RESET_CMD_HALT_S) & FW_RESET_CMD_HALT_M) 862 #define FW_RESET_CMD_HALT_F FW_RESET_CMD_HALT_V(1U) 863 864 enum fw_hellow_cmd { 865 fw_hello_cmd_stage_os = 0x0 866 }; 867 868 struct fw_hello_cmd { 869 __be32 op_to_write; 870 __be32 retval_len16; 871 __be32 err_to_clearinit; 872 __be32 fwrev; 873 }; 874 875 #define FW_HELLO_CMD_ERR_S 31 876 #define FW_HELLO_CMD_ERR_V(x) ((x) << FW_HELLO_CMD_ERR_S) 877 #define FW_HELLO_CMD_ERR_F FW_HELLO_CMD_ERR_V(1U) 878 879 #define FW_HELLO_CMD_INIT_S 30 880 #define FW_HELLO_CMD_INIT_V(x) ((x) << FW_HELLO_CMD_INIT_S) 881 #define FW_HELLO_CMD_INIT_F FW_HELLO_CMD_INIT_V(1U) 882 883 #define FW_HELLO_CMD_MASTERDIS_S 29 884 #define FW_HELLO_CMD_MASTERDIS_V(x) ((x) << FW_HELLO_CMD_MASTERDIS_S) 885 886 #define FW_HELLO_CMD_MASTERFORCE_S 28 887 #define FW_HELLO_CMD_MASTERFORCE_V(x) ((x) << FW_HELLO_CMD_MASTERFORCE_S) 888 889 #define FW_HELLO_CMD_MBMASTER_S 24 890 #define FW_HELLO_CMD_MBMASTER_M 0xfU 891 #define FW_HELLO_CMD_MBMASTER_V(x) ((x) << FW_HELLO_CMD_MBMASTER_S) 892 #define FW_HELLO_CMD_MBMASTER_G(x) \ 893 (((x) >> FW_HELLO_CMD_MBMASTER_S) & FW_HELLO_CMD_MBMASTER_M) 894 895 #define FW_HELLO_CMD_MBASYNCNOTINT_S 23 896 #define FW_HELLO_CMD_MBASYNCNOTINT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOTINT_S) 897 898 #define FW_HELLO_CMD_MBASYNCNOT_S 20 899 #define FW_HELLO_CMD_MBASYNCNOT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOT_S) 900 901 #define FW_HELLO_CMD_STAGE_S 17 902 #define FW_HELLO_CMD_STAGE_V(x) ((x) << FW_HELLO_CMD_STAGE_S) 903 904 #define FW_HELLO_CMD_CLEARINIT_S 16 905 #define FW_HELLO_CMD_CLEARINIT_V(x) ((x) << FW_HELLO_CMD_CLEARINIT_S) 906 #define FW_HELLO_CMD_CLEARINIT_F FW_HELLO_CMD_CLEARINIT_V(1U) 907 908 struct fw_bye_cmd { 909 __be32 op_to_write; 910 __be32 retval_len16; 911 __be64 r3; 912 }; 913 914 struct fw_initialize_cmd { 915 __be32 op_to_write; 916 __be32 retval_len16; 917 __be64 r3; 918 }; 919 920 enum fw_caps_config_hm { 921 FW_CAPS_CONFIG_HM_PCIE = 0x00000001, 922 FW_CAPS_CONFIG_HM_PL = 0x00000002, 923 FW_CAPS_CONFIG_HM_SGE = 0x00000004, 924 FW_CAPS_CONFIG_HM_CIM = 0x00000008, 925 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, 926 FW_CAPS_CONFIG_HM_TP = 0x00000020, 927 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, 928 FW_CAPS_CONFIG_HM_PMRX = 0x00000080, 929 FW_CAPS_CONFIG_HM_PMTX = 0x00000100, 930 FW_CAPS_CONFIG_HM_MC = 0x00000200, 931 FW_CAPS_CONFIG_HM_LE = 0x00000400, 932 FW_CAPS_CONFIG_HM_MPS = 0x00000800, 933 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, 934 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, 935 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, 936 FW_CAPS_CONFIG_HM_MI = 0x00008000, 937 FW_CAPS_CONFIG_HM_I2CM = 0x00010000, 938 FW_CAPS_CONFIG_HM_NCSI = 0x00020000, 939 FW_CAPS_CONFIG_HM_SMB = 0x00040000, 940 FW_CAPS_CONFIG_HM_MA = 0x00080000, 941 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, 942 FW_CAPS_CONFIG_HM_PMU = 0x00200000, 943 FW_CAPS_CONFIG_HM_UART = 0x00400000, 944 FW_CAPS_CONFIG_HM_SF = 0x00800000, 945 }; 946 947 enum fw_caps_config_nbm { 948 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, 949 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, 950 }; 951 952 enum fw_caps_config_link { 953 FW_CAPS_CONFIG_LINK_PPP = 0x00000001, 954 FW_CAPS_CONFIG_LINK_QFC = 0x00000002, 955 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, 956 }; 957 958 enum fw_caps_config_switch { 959 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, 960 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, 961 }; 962 963 enum fw_caps_config_nic { 964 FW_CAPS_CONFIG_NIC = 0x00000001, 965 FW_CAPS_CONFIG_NIC_VM = 0x00000002, 966 }; 967 968 enum fw_caps_config_ofld { 969 FW_CAPS_CONFIG_OFLD = 0x00000001, 970 }; 971 972 enum fw_caps_config_rdma { 973 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, 974 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, 975 }; 976 977 enum fw_caps_config_iscsi { 978 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, 979 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, 980 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, 981 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, 982 }; 983 984 enum fw_caps_config_fcoe { 985 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 986 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 987 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 988 }; 989 990 enum fw_memtype_cf { 991 FW_MEMTYPE_CF_EDC0 = 0x0, 992 FW_MEMTYPE_CF_EDC1 = 0x1, 993 FW_MEMTYPE_CF_EXTMEM = 0x2, 994 FW_MEMTYPE_CF_FLASH = 0x4, 995 FW_MEMTYPE_CF_INTERNAL = 0x5, 996 FW_MEMTYPE_CF_EXTMEM1 = 0x6, 997 }; 998 999 struct fw_caps_config_cmd { 1000 __be32 op_to_write; 1001 __be32 cfvalid_to_len16; 1002 __be32 r2; 1003 __be32 hwmbitmap; 1004 __be16 nbmcaps; 1005 __be16 linkcaps; 1006 __be16 switchcaps; 1007 __be16 r3; 1008 __be16 niccaps; 1009 __be16 ofldcaps; 1010 __be16 rdmacaps; 1011 __be16 r4; 1012 __be16 iscsicaps; 1013 __be16 fcoecaps; 1014 __be32 cfcsum; 1015 __be32 finiver; 1016 __be32 finicsum; 1017 }; 1018 1019 #define FW_CAPS_CONFIG_CMD_CFVALID_S 27 1020 #define FW_CAPS_CONFIG_CMD_CFVALID_V(x) ((x) << FW_CAPS_CONFIG_CMD_CFVALID_S) 1021 #define FW_CAPS_CONFIG_CMD_CFVALID_F FW_CAPS_CONFIG_CMD_CFVALID_V(1U) 1022 1023 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S 24 1024 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(x) \ 1025 ((x) << FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S) 1026 1027 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S 16 1028 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(x) \ 1029 ((x) << FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S) 1030 1031 /* 1032 * params command mnemonics 1033 */ 1034 enum fw_params_mnem { 1035 FW_PARAMS_MNEM_DEV = 1, /* device params */ 1036 FW_PARAMS_MNEM_PFVF = 2, /* function params */ 1037 FW_PARAMS_MNEM_REG = 3, /* limited register access */ 1038 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 1039 FW_PARAMS_MNEM_CHNET = 5, /* chnet params */ 1040 FW_PARAMS_MNEM_LAST 1041 }; 1042 1043 /* 1044 * device parameters 1045 */ 1046 enum fw_params_param_dev { 1047 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 1048 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 1049 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs 1050 * allocated by the device's 1051 * Lookup Engine 1052 */ 1053 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, 1054 FW_PARAMS_PARAM_DEV_INTVER_NIC = 0x04, 1055 FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05, 1056 FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06, 1057 FW_PARAMS_PARAM_DEV_INTVER_RI = 0x07, 1058 FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08, 1059 FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09, 1060 FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A, 1061 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, 1062 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, 1063 FW_PARAMS_PARAM_DEV_CF = 0x0D, 1064 FW_PARAMS_PARAM_DEV_DIAG = 0x11, 1065 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD */ 1066 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER = 0x14, /* max supported adap IRD */ 1067 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, 1068 FW_PARAMS_PARAM_DEV_FWCACHE = 0x18, 1069 }; 1070 1071 /* 1072 * physical and virtual function parameters 1073 */ 1074 enum fw_params_param_pfvf { 1075 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, 1076 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, 1077 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, 1078 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 1079 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 1080 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 1081 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 1082 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, 1083 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, 1084 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, 1085 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, 1086 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, 1087 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, 1088 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, 1089 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, 1090 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, 1091 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, 1092 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, 1093 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, 1094 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 1095 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 1096 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15, 1097 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16, 1098 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17, 1099 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18, 1100 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, 1101 FW_PARAMS_PARAM_PFVF_VIID = 0x24, 1102 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 1103 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 1104 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 1105 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 1106 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 1107 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 1108 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, 1109 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 1110 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 1111 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, 1112 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30, 1113 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31 1114 }; 1115 1116 /* 1117 * dma queue parameters 1118 */ 1119 enum fw_params_param_dmaq { 1120 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 1121 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 1122 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 1123 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 1124 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, 1125 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13, 1126 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20, 1127 }; 1128 1129 enum fw_params_param_dev_diag { 1130 FW_PARAM_DEV_DIAG_TMP = 0x00, 1131 FW_PARAM_DEV_DIAG_VDD = 0x01, 1132 }; 1133 1134 enum fw_params_param_dev_fwcache { 1135 FW_PARAM_DEV_FWCACHE_FLUSH = 0x00, 1136 FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01, 1137 }; 1138 1139 #define FW_PARAMS_MNEM_S 24 1140 #define FW_PARAMS_MNEM_V(x) ((x) << FW_PARAMS_MNEM_S) 1141 1142 #define FW_PARAMS_PARAM_X_S 16 1143 #define FW_PARAMS_PARAM_X_V(x) ((x) << FW_PARAMS_PARAM_X_S) 1144 1145 #define FW_PARAMS_PARAM_Y_S 8 1146 #define FW_PARAMS_PARAM_Y_M 0xffU 1147 #define FW_PARAMS_PARAM_Y_V(x) ((x) << FW_PARAMS_PARAM_Y_S) 1148 #define FW_PARAMS_PARAM_Y_G(x) (((x) >> FW_PARAMS_PARAM_Y_S) &\ 1149 FW_PARAMS_PARAM_Y_M) 1150 1151 #define FW_PARAMS_PARAM_Z_S 0 1152 #define FW_PARAMS_PARAM_Z_M 0xffu 1153 #define FW_PARAMS_PARAM_Z_V(x) ((x) << FW_PARAMS_PARAM_Z_S) 1154 #define FW_PARAMS_PARAM_Z_G(x) (((x) >> FW_PARAMS_PARAM_Z_S) &\ 1155 FW_PARAMS_PARAM_Z_M) 1156 1157 #define FW_PARAMS_PARAM_XYZ_S 0 1158 #define FW_PARAMS_PARAM_XYZ_V(x) ((x) << FW_PARAMS_PARAM_XYZ_S) 1159 1160 #define FW_PARAMS_PARAM_YZ_S 0 1161 #define FW_PARAMS_PARAM_YZ_V(x) ((x) << FW_PARAMS_PARAM_YZ_S) 1162 1163 struct fw_params_cmd { 1164 __be32 op_to_vfn; 1165 __be32 retval_len16; 1166 struct fw_params_param { 1167 __be32 mnem; 1168 __be32 val; 1169 } param[7]; 1170 }; 1171 1172 #define FW_PARAMS_CMD_PFN_S 8 1173 #define FW_PARAMS_CMD_PFN_V(x) ((x) << FW_PARAMS_CMD_PFN_S) 1174 1175 #define FW_PARAMS_CMD_VFN_S 0 1176 #define FW_PARAMS_CMD_VFN_V(x) ((x) << FW_PARAMS_CMD_VFN_S) 1177 1178 struct fw_pfvf_cmd { 1179 __be32 op_to_vfn; 1180 __be32 retval_len16; 1181 __be32 niqflint_niq; 1182 __be32 type_to_neq; 1183 __be32 tc_to_nexactf; 1184 __be32 r_caps_to_nethctrl; 1185 __be16 nricq; 1186 __be16 nriqp; 1187 __be32 r4; 1188 }; 1189 1190 #define FW_PFVF_CMD_PFN_S 8 1191 #define FW_PFVF_CMD_PFN_V(x) ((x) << FW_PFVF_CMD_PFN_S) 1192 1193 #define FW_PFVF_CMD_VFN_S 0 1194 #define FW_PFVF_CMD_VFN_V(x) ((x) << FW_PFVF_CMD_VFN_S) 1195 1196 #define FW_PFVF_CMD_NIQFLINT_S 20 1197 #define FW_PFVF_CMD_NIQFLINT_M 0xfff 1198 #define FW_PFVF_CMD_NIQFLINT_V(x) ((x) << FW_PFVF_CMD_NIQFLINT_S) 1199 #define FW_PFVF_CMD_NIQFLINT_G(x) \ 1200 (((x) >> FW_PFVF_CMD_NIQFLINT_S) & FW_PFVF_CMD_NIQFLINT_M) 1201 1202 #define FW_PFVF_CMD_NIQ_S 0 1203 #define FW_PFVF_CMD_NIQ_M 0xfffff 1204 #define FW_PFVF_CMD_NIQ_V(x) ((x) << FW_PFVF_CMD_NIQ_S) 1205 #define FW_PFVF_CMD_NIQ_G(x) \ 1206 (((x) >> FW_PFVF_CMD_NIQ_S) & FW_PFVF_CMD_NIQ_M) 1207 1208 #define FW_PFVF_CMD_TYPE_S 31 1209 #define FW_PFVF_CMD_TYPE_M 0x1 1210 #define FW_PFVF_CMD_TYPE_V(x) ((x) << FW_PFVF_CMD_TYPE_S) 1211 #define FW_PFVF_CMD_TYPE_G(x) \ 1212 (((x) >> FW_PFVF_CMD_TYPE_S) & FW_PFVF_CMD_TYPE_M) 1213 #define FW_PFVF_CMD_TYPE_F FW_PFVF_CMD_TYPE_V(1U) 1214 1215 #define FW_PFVF_CMD_CMASK_S 24 1216 #define FW_PFVF_CMD_CMASK_M 0xf 1217 #define FW_PFVF_CMD_CMASK_V(x) ((x) << FW_PFVF_CMD_CMASK_S) 1218 #define FW_PFVF_CMD_CMASK_G(x) \ 1219 (((x) >> FW_PFVF_CMD_CMASK_S) & FW_PFVF_CMD_CMASK_M) 1220 1221 #define FW_PFVF_CMD_PMASK_S 20 1222 #define FW_PFVF_CMD_PMASK_M 0xf 1223 #define FW_PFVF_CMD_PMASK_V(x) ((x) << FW_PFVF_CMD_PMASK_S) 1224 #define FW_PFVF_CMD_PMASK_G(x) \ 1225 (((x) >> FW_PFVF_CMD_PMASK_S) & FW_PFVF_CMD_PMASK_M) 1226 1227 #define FW_PFVF_CMD_NEQ_S 0 1228 #define FW_PFVF_CMD_NEQ_M 0xfffff 1229 #define FW_PFVF_CMD_NEQ_V(x) ((x) << FW_PFVF_CMD_NEQ_S) 1230 #define FW_PFVF_CMD_NEQ_G(x) \ 1231 (((x) >> FW_PFVF_CMD_NEQ_S) & FW_PFVF_CMD_NEQ_M) 1232 1233 #define FW_PFVF_CMD_TC_S 24 1234 #define FW_PFVF_CMD_TC_M 0xff 1235 #define FW_PFVF_CMD_TC_V(x) ((x) << FW_PFVF_CMD_TC_S) 1236 #define FW_PFVF_CMD_TC_G(x) (((x) >> FW_PFVF_CMD_TC_S) & FW_PFVF_CMD_TC_M) 1237 1238 #define FW_PFVF_CMD_NVI_S 16 1239 #define FW_PFVF_CMD_NVI_M 0xff 1240 #define FW_PFVF_CMD_NVI_V(x) ((x) << FW_PFVF_CMD_NVI_S) 1241 #define FW_PFVF_CMD_NVI_G(x) (((x) >> FW_PFVF_CMD_NVI_S) & FW_PFVF_CMD_NVI_M) 1242 1243 #define FW_PFVF_CMD_NEXACTF_S 0 1244 #define FW_PFVF_CMD_NEXACTF_M 0xffff 1245 #define FW_PFVF_CMD_NEXACTF_V(x) ((x) << FW_PFVF_CMD_NEXACTF_S) 1246 #define FW_PFVF_CMD_NEXACTF_G(x) \ 1247 (((x) >> FW_PFVF_CMD_NEXACTF_S) & FW_PFVF_CMD_NEXACTF_M) 1248 1249 #define FW_PFVF_CMD_R_CAPS_S 24 1250 #define FW_PFVF_CMD_R_CAPS_M 0xff 1251 #define FW_PFVF_CMD_R_CAPS_V(x) ((x) << FW_PFVF_CMD_R_CAPS_S) 1252 #define FW_PFVF_CMD_R_CAPS_G(x) \ 1253 (((x) >> FW_PFVF_CMD_R_CAPS_S) & FW_PFVF_CMD_R_CAPS_M) 1254 1255 #define FW_PFVF_CMD_WX_CAPS_S 16 1256 #define FW_PFVF_CMD_WX_CAPS_M 0xff 1257 #define FW_PFVF_CMD_WX_CAPS_V(x) ((x) << FW_PFVF_CMD_WX_CAPS_S) 1258 #define FW_PFVF_CMD_WX_CAPS_G(x) \ 1259 (((x) >> FW_PFVF_CMD_WX_CAPS_S) & FW_PFVF_CMD_WX_CAPS_M) 1260 1261 #define FW_PFVF_CMD_NETHCTRL_S 0 1262 #define FW_PFVF_CMD_NETHCTRL_M 0xffff 1263 #define FW_PFVF_CMD_NETHCTRL_V(x) ((x) << FW_PFVF_CMD_NETHCTRL_S) 1264 #define FW_PFVF_CMD_NETHCTRL_G(x) \ 1265 (((x) >> FW_PFVF_CMD_NETHCTRL_S) & FW_PFVF_CMD_NETHCTRL_M) 1266 1267 enum fw_iq_type { 1268 FW_IQ_TYPE_FL_INT_CAP, 1269 FW_IQ_TYPE_NO_FL_INT_CAP 1270 }; 1271 1272 struct fw_iq_cmd { 1273 __be32 op_to_vfn; 1274 __be32 alloc_to_len16; 1275 __be16 physiqid; 1276 __be16 iqid; 1277 __be16 fl0id; 1278 __be16 fl1id; 1279 __be32 type_to_iqandstindex; 1280 __be16 iqdroprss_to_iqesize; 1281 __be16 iqsize; 1282 __be64 iqaddr; 1283 __be32 iqns_to_fl0congen; 1284 __be16 fl0dcaen_to_fl0cidxfthresh; 1285 __be16 fl0size; 1286 __be64 fl0addr; 1287 __be32 fl1cngchmap_to_fl1congen; 1288 __be16 fl1dcaen_to_fl1cidxfthresh; 1289 __be16 fl1size; 1290 __be64 fl1addr; 1291 }; 1292 1293 #define FW_IQ_CMD_PFN_S 8 1294 #define FW_IQ_CMD_PFN_V(x) ((x) << FW_IQ_CMD_PFN_S) 1295 1296 #define FW_IQ_CMD_VFN_S 0 1297 #define FW_IQ_CMD_VFN_V(x) ((x) << FW_IQ_CMD_VFN_S) 1298 1299 #define FW_IQ_CMD_ALLOC_S 31 1300 #define FW_IQ_CMD_ALLOC_V(x) ((x) << FW_IQ_CMD_ALLOC_S) 1301 #define FW_IQ_CMD_ALLOC_F FW_IQ_CMD_ALLOC_V(1U) 1302 1303 #define FW_IQ_CMD_FREE_S 30 1304 #define FW_IQ_CMD_FREE_V(x) ((x) << FW_IQ_CMD_FREE_S) 1305 #define FW_IQ_CMD_FREE_F FW_IQ_CMD_FREE_V(1U) 1306 1307 #define FW_IQ_CMD_MODIFY_S 29 1308 #define FW_IQ_CMD_MODIFY_V(x) ((x) << FW_IQ_CMD_MODIFY_S) 1309 #define FW_IQ_CMD_MODIFY_F FW_IQ_CMD_MODIFY_V(1U) 1310 1311 #define FW_IQ_CMD_IQSTART_S 28 1312 #define FW_IQ_CMD_IQSTART_V(x) ((x) << FW_IQ_CMD_IQSTART_S) 1313 #define FW_IQ_CMD_IQSTART_F FW_IQ_CMD_IQSTART_V(1U) 1314 1315 #define FW_IQ_CMD_IQSTOP_S 27 1316 #define FW_IQ_CMD_IQSTOP_V(x) ((x) << FW_IQ_CMD_IQSTOP_S) 1317 #define FW_IQ_CMD_IQSTOP_F FW_IQ_CMD_IQSTOP_V(1U) 1318 1319 #define FW_IQ_CMD_TYPE_S 29 1320 #define FW_IQ_CMD_TYPE_V(x) ((x) << FW_IQ_CMD_TYPE_S) 1321 1322 #define FW_IQ_CMD_IQASYNCH_S 28 1323 #define FW_IQ_CMD_IQASYNCH_V(x) ((x) << FW_IQ_CMD_IQASYNCH_S) 1324 1325 #define FW_IQ_CMD_VIID_S 16 1326 #define FW_IQ_CMD_VIID_V(x) ((x) << FW_IQ_CMD_VIID_S) 1327 1328 #define FW_IQ_CMD_IQANDST_S 15 1329 #define FW_IQ_CMD_IQANDST_V(x) ((x) << FW_IQ_CMD_IQANDST_S) 1330 1331 #define FW_IQ_CMD_IQANUS_S 14 1332 #define FW_IQ_CMD_IQANUS_V(x) ((x) << FW_IQ_CMD_IQANUS_S) 1333 1334 #define FW_IQ_CMD_IQANUD_S 12 1335 #define FW_IQ_CMD_IQANUD_V(x) ((x) << FW_IQ_CMD_IQANUD_S) 1336 1337 #define FW_IQ_CMD_IQANDSTINDEX_S 0 1338 #define FW_IQ_CMD_IQANDSTINDEX_V(x) ((x) << FW_IQ_CMD_IQANDSTINDEX_S) 1339 1340 #define FW_IQ_CMD_IQDROPRSS_S 15 1341 #define FW_IQ_CMD_IQDROPRSS_V(x) ((x) << FW_IQ_CMD_IQDROPRSS_S) 1342 #define FW_IQ_CMD_IQDROPRSS_F FW_IQ_CMD_IQDROPRSS_V(1U) 1343 1344 #define FW_IQ_CMD_IQGTSMODE_S 14 1345 #define FW_IQ_CMD_IQGTSMODE_V(x) ((x) << FW_IQ_CMD_IQGTSMODE_S) 1346 #define FW_IQ_CMD_IQGTSMODE_F FW_IQ_CMD_IQGTSMODE_V(1U) 1347 1348 #define FW_IQ_CMD_IQPCIECH_S 12 1349 #define FW_IQ_CMD_IQPCIECH_V(x) ((x) << FW_IQ_CMD_IQPCIECH_S) 1350 1351 #define FW_IQ_CMD_IQDCAEN_S 11 1352 #define FW_IQ_CMD_IQDCAEN_V(x) ((x) << FW_IQ_CMD_IQDCAEN_S) 1353 1354 #define FW_IQ_CMD_IQDCACPU_S 6 1355 #define FW_IQ_CMD_IQDCACPU_V(x) ((x) << FW_IQ_CMD_IQDCACPU_S) 1356 1357 #define FW_IQ_CMD_IQINTCNTTHRESH_S 4 1358 #define FW_IQ_CMD_IQINTCNTTHRESH_V(x) ((x) << FW_IQ_CMD_IQINTCNTTHRESH_S) 1359 1360 #define FW_IQ_CMD_IQO_S 3 1361 #define FW_IQ_CMD_IQO_V(x) ((x) << FW_IQ_CMD_IQO_S) 1362 #define FW_IQ_CMD_IQO_F FW_IQ_CMD_IQO_V(1U) 1363 1364 #define FW_IQ_CMD_IQCPRIO_S 2 1365 #define FW_IQ_CMD_IQCPRIO_V(x) ((x) << FW_IQ_CMD_IQCPRIO_S) 1366 1367 #define FW_IQ_CMD_IQESIZE_S 0 1368 #define FW_IQ_CMD_IQESIZE_V(x) ((x) << FW_IQ_CMD_IQESIZE_S) 1369 1370 #define FW_IQ_CMD_IQNS_S 31 1371 #define FW_IQ_CMD_IQNS_V(x) ((x) << FW_IQ_CMD_IQNS_S) 1372 1373 #define FW_IQ_CMD_IQRO_S 30 1374 #define FW_IQ_CMD_IQRO_V(x) ((x) << FW_IQ_CMD_IQRO_S) 1375 1376 #define FW_IQ_CMD_IQFLINTIQHSEN_S 28 1377 #define FW_IQ_CMD_IQFLINTIQHSEN_V(x) ((x) << FW_IQ_CMD_IQFLINTIQHSEN_S) 1378 1379 #define FW_IQ_CMD_IQFLINTCONGEN_S 27 1380 #define FW_IQ_CMD_IQFLINTCONGEN_V(x) ((x) << FW_IQ_CMD_IQFLINTCONGEN_S) 1381 #define FW_IQ_CMD_IQFLINTCONGEN_F FW_IQ_CMD_IQFLINTCONGEN_V(1U) 1382 1383 #define FW_IQ_CMD_IQFLINTISCSIC_S 26 1384 #define FW_IQ_CMD_IQFLINTISCSIC_V(x) ((x) << FW_IQ_CMD_IQFLINTISCSIC_S) 1385 1386 #define FW_IQ_CMD_FL0CNGCHMAP_S 20 1387 #define FW_IQ_CMD_FL0CNGCHMAP_V(x) ((x) << FW_IQ_CMD_FL0CNGCHMAP_S) 1388 1389 #define FW_IQ_CMD_FL0CACHELOCK_S 15 1390 #define FW_IQ_CMD_FL0CACHELOCK_V(x) ((x) << FW_IQ_CMD_FL0CACHELOCK_S) 1391 1392 #define FW_IQ_CMD_FL0DBP_S 14 1393 #define FW_IQ_CMD_FL0DBP_V(x) ((x) << FW_IQ_CMD_FL0DBP_S) 1394 1395 #define FW_IQ_CMD_FL0DATANS_S 13 1396 #define FW_IQ_CMD_FL0DATANS_V(x) ((x) << FW_IQ_CMD_FL0DATANS_S) 1397 1398 #define FW_IQ_CMD_FL0DATARO_S 12 1399 #define FW_IQ_CMD_FL0DATARO_V(x) ((x) << FW_IQ_CMD_FL0DATARO_S) 1400 #define FW_IQ_CMD_FL0DATARO_F FW_IQ_CMD_FL0DATARO_V(1U) 1401 1402 #define FW_IQ_CMD_FL0CONGCIF_S 11 1403 #define FW_IQ_CMD_FL0CONGCIF_V(x) ((x) << FW_IQ_CMD_FL0CONGCIF_S) 1404 #define FW_IQ_CMD_FL0CONGCIF_F FW_IQ_CMD_FL0CONGCIF_V(1U) 1405 1406 #define FW_IQ_CMD_FL0ONCHIP_S 10 1407 #define FW_IQ_CMD_FL0ONCHIP_V(x) ((x) << FW_IQ_CMD_FL0ONCHIP_S) 1408 1409 #define FW_IQ_CMD_FL0STATUSPGNS_S 9 1410 #define FW_IQ_CMD_FL0STATUSPGNS_V(x) ((x) << FW_IQ_CMD_FL0STATUSPGNS_S) 1411 1412 #define FW_IQ_CMD_FL0STATUSPGRO_S 8 1413 #define FW_IQ_CMD_FL0STATUSPGRO_V(x) ((x) << FW_IQ_CMD_FL0STATUSPGRO_S) 1414 1415 #define FW_IQ_CMD_FL0FETCHNS_S 7 1416 #define FW_IQ_CMD_FL0FETCHNS_V(x) ((x) << FW_IQ_CMD_FL0FETCHNS_S) 1417 1418 #define FW_IQ_CMD_FL0FETCHRO_S 6 1419 #define FW_IQ_CMD_FL0FETCHRO_V(x) ((x) << FW_IQ_CMD_FL0FETCHRO_S) 1420 #define FW_IQ_CMD_FL0FETCHRO_F FW_IQ_CMD_FL0FETCHRO_V(1U) 1421 1422 #define FW_IQ_CMD_FL0HOSTFCMODE_S 4 1423 #define FW_IQ_CMD_FL0HOSTFCMODE_V(x) ((x) << FW_IQ_CMD_FL0HOSTFCMODE_S) 1424 1425 #define FW_IQ_CMD_FL0CPRIO_S 3 1426 #define FW_IQ_CMD_FL0CPRIO_V(x) ((x) << FW_IQ_CMD_FL0CPRIO_S) 1427 1428 #define FW_IQ_CMD_FL0PADEN_S 2 1429 #define FW_IQ_CMD_FL0PADEN_V(x) ((x) << FW_IQ_CMD_FL0PADEN_S) 1430 #define FW_IQ_CMD_FL0PADEN_F FW_IQ_CMD_FL0PADEN_V(1U) 1431 1432 #define FW_IQ_CMD_FL0PACKEN_S 1 1433 #define FW_IQ_CMD_FL0PACKEN_V(x) ((x) << FW_IQ_CMD_FL0PACKEN_S) 1434 #define FW_IQ_CMD_FL0PACKEN_F FW_IQ_CMD_FL0PACKEN_V(1U) 1435 1436 #define FW_IQ_CMD_FL0CONGEN_S 0 1437 #define FW_IQ_CMD_FL0CONGEN_V(x) ((x) << FW_IQ_CMD_FL0CONGEN_S) 1438 #define FW_IQ_CMD_FL0CONGEN_F FW_IQ_CMD_FL0CONGEN_V(1U) 1439 1440 #define FW_IQ_CMD_FL0DCAEN_S 15 1441 #define FW_IQ_CMD_FL0DCAEN_V(x) ((x) << FW_IQ_CMD_FL0DCAEN_S) 1442 1443 #define FW_IQ_CMD_FL0DCACPU_S 10 1444 #define FW_IQ_CMD_FL0DCACPU_V(x) ((x) << FW_IQ_CMD_FL0DCACPU_S) 1445 1446 #define FW_IQ_CMD_FL0FBMIN_S 7 1447 #define FW_IQ_CMD_FL0FBMIN_V(x) ((x) << FW_IQ_CMD_FL0FBMIN_S) 1448 1449 #define FW_IQ_CMD_FL0FBMAX_S 4 1450 #define FW_IQ_CMD_FL0FBMAX_V(x) ((x) << FW_IQ_CMD_FL0FBMAX_S) 1451 1452 #define FW_IQ_CMD_FL0CIDXFTHRESHO_S 3 1453 #define FW_IQ_CMD_FL0CIDXFTHRESHO_V(x) ((x) << FW_IQ_CMD_FL0CIDXFTHRESHO_S) 1454 #define FW_IQ_CMD_FL0CIDXFTHRESHO_F FW_IQ_CMD_FL0CIDXFTHRESHO_V(1U) 1455 1456 #define FW_IQ_CMD_FL0CIDXFTHRESH_S 0 1457 #define FW_IQ_CMD_FL0CIDXFTHRESH_V(x) ((x) << FW_IQ_CMD_FL0CIDXFTHRESH_S) 1458 1459 #define FW_IQ_CMD_FL1CNGCHMAP_S 20 1460 #define FW_IQ_CMD_FL1CNGCHMAP_V(x) ((x) << FW_IQ_CMD_FL1CNGCHMAP_S) 1461 1462 #define FW_IQ_CMD_FL1CACHELOCK_S 15 1463 #define FW_IQ_CMD_FL1CACHELOCK_V(x) ((x) << FW_IQ_CMD_FL1CACHELOCK_S) 1464 1465 #define FW_IQ_CMD_FL1DBP_S 14 1466 #define FW_IQ_CMD_FL1DBP_V(x) ((x) << FW_IQ_CMD_FL1DBP_S) 1467 1468 #define FW_IQ_CMD_FL1DATANS_S 13 1469 #define FW_IQ_CMD_FL1DATANS_V(x) ((x) << FW_IQ_CMD_FL1DATANS_S) 1470 1471 #define FW_IQ_CMD_FL1DATARO_S 12 1472 #define FW_IQ_CMD_FL1DATARO_V(x) ((x) << FW_IQ_CMD_FL1DATARO_S) 1473 1474 #define FW_IQ_CMD_FL1CONGCIF_S 11 1475 #define FW_IQ_CMD_FL1CONGCIF_V(x) ((x) << FW_IQ_CMD_FL1CONGCIF_S) 1476 1477 #define FW_IQ_CMD_FL1ONCHIP_S 10 1478 #define FW_IQ_CMD_FL1ONCHIP_V(x) ((x) << FW_IQ_CMD_FL1ONCHIP_S) 1479 1480 #define FW_IQ_CMD_FL1STATUSPGNS_S 9 1481 #define FW_IQ_CMD_FL1STATUSPGNS_V(x) ((x) << FW_IQ_CMD_FL1STATUSPGNS_S) 1482 1483 #define FW_IQ_CMD_FL1STATUSPGRO_S 8 1484 #define FW_IQ_CMD_FL1STATUSPGRO_V(x) ((x) << FW_IQ_CMD_FL1STATUSPGRO_S) 1485 1486 #define FW_IQ_CMD_FL1FETCHNS_S 7 1487 #define FW_IQ_CMD_FL1FETCHNS_V(x) ((x) << FW_IQ_CMD_FL1FETCHNS_S) 1488 1489 #define FW_IQ_CMD_FL1FETCHRO_S 6 1490 #define FW_IQ_CMD_FL1FETCHRO_V(x) ((x) << FW_IQ_CMD_FL1FETCHRO_S) 1491 1492 #define FW_IQ_CMD_FL1HOSTFCMODE_S 4 1493 #define FW_IQ_CMD_FL1HOSTFCMODE_V(x) ((x) << FW_IQ_CMD_FL1HOSTFCMODE_S) 1494 1495 #define FW_IQ_CMD_FL1CPRIO_S 3 1496 #define FW_IQ_CMD_FL1CPRIO_V(x) ((x) << FW_IQ_CMD_FL1CPRIO_S) 1497 1498 #define FW_IQ_CMD_FL1PADEN_S 2 1499 #define FW_IQ_CMD_FL1PADEN_V(x) ((x) << FW_IQ_CMD_FL1PADEN_S) 1500 #define FW_IQ_CMD_FL1PADEN_F FW_IQ_CMD_FL1PADEN_V(1U) 1501 1502 #define FW_IQ_CMD_FL1PACKEN_S 1 1503 #define FW_IQ_CMD_FL1PACKEN_V(x) ((x) << FW_IQ_CMD_FL1PACKEN_S) 1504 #define FW_IQ_CMD_FL1PACKEN_F FW_IQ_CMD_FL1PACKEN_V(1U) 1505 1506 #define FW_IQ_CMD_FL1CONGEN_S 0 1507 #define FW_IQ_CMD_FL1CONGEN_V(x) ((x) << FW_IQ_CMD_FL1CONGEN_S) 1508 #define FW_IQ_CMD_FL1CONGEN_F FW_IQ_CMD_FL1CONGEN_V(1U) 1509 1510 #define FW_IQ_CMD_FL1DCAEN_S 15 1511 #define FW_IQ_CMD_FL1DCAEN_V(x) ((x) << FW_IQ_CMD_FL1DCAEN_S) 1512 1513 #define FW_IQ_CMD_FL1DCACPU_S 10 1514 #define FW_IQ_CMD_FL1DCACPU_V(x) ((x) << FW_IQ_CMD_FL1DCACPU_S) 1515 1516 #define FW_IQ_CMD_FL1FBMIN_S 7 1517 #define FW_IQ_CMD_FL1FBMIN_V(x) ((x) << FW_IQ_CMD_FL1FBMIN_S) 1518 1519 #define FW_IQ_CMD_FL1FBMAX_S 4 1520 #define FW_IQ_CMD_FL1FBMAX_V(x) ((x) << FW_IQ_CMD_FL1FBMAX_S) 1521 1522 #define FW_IQ_CMD_FL1CIDXFTHRESHO_S 3 1523 #define FW_IQ_CMD_FL1CIDXFTHRESHO_V(x) ((x) << FW_IQ_CMD_FL1CIDXFTHRESHO_S) 1524 #define FW_IQ_CMD_FL1CIDXFTHRESHO_F FW_IQ_CMD_FL1CIDXFTHRESHO_V(1U) 1525 1526 #define FW_IQ_CMD_FL1CIDXFTHRESH_S 0 1527 #define FW_IQ_CMD_FL1CIDXFTHRESH_V(x) ((x) << FW_IQ_CMD_FL1CIDXFTHRESH_S) 1528 1529 struct fw_eq_eth_cmd { 1530 __be32 op_to_vfn; 1531 __be32 alloc_to_len16; 1532 __be32 eqid_pkd; 1533 __be32 physeqid_pkd; 1534 __be32 fetchszm_to_iqid; 1535 __be32 dcaen_to_eqsize; 1536 __be64 eqaddr; 1537 __be32 viid_pkd; 1538 __be32 r8_lo; 1539 __be64 r9; 1540 }; 1541 1542 #define FW_EQ_ETH_CMD_PFN_S 8 1543 #define FW_EQ_ETH_CMD_PFN_V(x) ((x) << FW_EQ_ETH_CMD_PFN_S) 1544 1545 #define FW_EQ_ETH_CMD_VFN_S 0 1546 #define FW_EQ_ETH_CMD_VFN_V(x) ((x) << FW_EQ_ETH_CMD_VFN_S) 1547 1548 #define FW_EQ_ETH_CMD_ALLOC_S 31 1549 #define FW_EQ_ETH_CMD_ALLOC_V(x) ((x) << FW_EQ_ETH_CMD_ALLOC_S) 1550 #define FW_EQ_ETH_CMD_ALLOC_F FW_EQ_ETH_CMD_ALLOC_V(1U) 1551 1552 #define FW_EQ_ETH_CMD_FREE_S 30 1553 #define FW_EQ_ETH_CMD_FREE_V(x) ((x) << FW_EQ_ETH_CMD_FREE_S) 1554 #define FW_EQ_ETH_CMD_FREE_F FW_EQ_ETH_CMD_FREE_V(1U) 1555 1556 #define FW_EQ_ETH_CMD_MODIFY_S 29 1557 #define FW_EQ_ETH_CMD_MODIFY_V(x) ((x) << FW_EQ_ETH_CMD_MODIFY_S) 1558 #define FW_EQ_ETH_CMD_MODIFY_F FW_EQ_ETH_CMD_MODIFY_V(1U) 1559 1560 #define FW_EQ_ETH_CMD_EQSTART_S 28 1561 #define FW_EQ_ETH_CMD_EQSTART_V(x) ((x) << FW_EQ_ETH_CMD_EQSTART_S) 1562 #define FW_EQ_ETH_CMD_EQSTART_F FW_EQ_ETH_CMD_EQSTART_V(1U) 1563 1564 #define FW_EQ_ETH_CMD_EQSTOP_S 27 1565 #define FW_EQ_ETH_CMD_EQSTOP_V(x) ((x) << FW_EQ_ETH_CMD_EQSTOP_S) 1566 #define FW_EQ_ETH_CMD_EQSTOP_F FW_EQ_ETH_CMD_EQSTOP_V(1U) 1567 1568 #define FW_EQ_ETH_CMD_EQID_S 0 1569 #define FW_EQ_ETH_CMD_EQID_M 0xfffff 1570 #define FW_EQ_ETH_CMD_EQID_V(x) ((x) << FW_EQ_ETH_CMD_EQID_S) 1571 #define FW_EQ_ETH_CMD_EQID_G(x) \ 1572 (((x) >> FW_EQ_ETH_CMD_EQID_S) & FW_EQ_ETH_CMD_EQID_M) 1573 1574 #define FW_EQ_ETH_CMD_PHYSEQID_S 0 1575 #define FW_EQ_ETH_CMD_PHYSEQID_M 0xfffff 1576 #define FW_EQ_ETH_CMD_PHYSEQID_V(x) ((x) << FW_EQ_ETH_CMD_PHYSEQID_S) 1577 #define FW_EQ_ETH_CMD_PHYSEQID_G(x) \ 1578 (((x) >> FW_EQ_ETH_CMD_PHYSEQID_S) & FW_EQ_ETH_CMD_PHYSEQID_M) 1579 1580 #define FW_EQ_ETH_CMD_FETCHSZM_S 26 1581 #define FW_EQ_ETH_CMD_FETCHSZM_V(x) ((x) << FW_EQ_ETH_CMD_FETCHSZM_S) 1582 #define FW_EQ_ETH_CMD_FETCHSZM_F FW_EQ_ETH_CMD_FETCHSZM_V(1U) 1583 1584 #define FW_EQ_ETH_CMD_STATUSPGNS_S 25 1585 #define FW_EQ_ETH_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_ETH_CMD_STATUSPGNS_S) 1586 1587 #define FW_EQ_ETH_CMD_STATUSPGRO_S 24 1588 #define FW_EQ_ETH_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_ETH_CMD_STATUSPGRO_S) 1589 1590 #define FW_EQ_ETH_CMD_FETCHNS_S 23 1591 #define FW_EQ_ETH_CMD_FETCHNS_V(x) ((x) << FW_EQ_ETH_CMD_FETCHNS_S) 1592 1593 #define FW_EQ_ETH_CMD_FETCHRO_S 22 1594 #define FW_EQ_ETH_CMD_FETCHRO_V(x) ((x) << FW_EQ_ETH_CMD_FETCHRO_S) 1595 #define FW_EQ_ETH_CMD_FETCHRO_F FW_EQ_ETH_CMD_FETCHRO_V(1U) 1596 1597 #define FW_EQ_ETH_CMD_HOSTFCMODE_S 20 1598 #define FW_EQ_ETH_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_ETH_CMD_HOSTFCMODE_S) 1599 1600 #define FW_EQ_ETH_CMD_CPRIO_S 19 1601 #define FW_EQ_ETH_CMD_CPRIO_V(x) ((x) << FW_EQ_ETH_CMD_CPRIO_S) 1602 1603 #define FW_EQ_ETH_CMD_ONCHIP_S 18 1604 #define FW_EQ_ETH_CMD_ONCHIP_V(x) ((x) << FW_EQ_ETH_CMD_ONCHIP_S) 1605 1606 #define FW_EQ_ETH_CMD_PCIECHN_S 16 1607 #define FW_EQ_ETH_CMD_PCIECHN_V(x) ((x) << FW_EQ_ETH_CMD_PCIECHN_S) 1608 1609 #define FW_EQ_ETH_CMD_IQID_S 0 1610 #define FW_EQ_ETH_CMD_IQID_V(x) ((x) << FW_EQ_ETH_CMD_IQID_S) 1611 1612 #define FW_EQ_ETH_CMD_DCAEN_S 31 1613 #define FW_EQ_ETH_CMD_DCAEN_V(x) ((x) << FW_EQ_ETH_CMD_DCAEN_S) 1614 1615 #define FW_EQ_ETH_CMD_DCACPU_S 26 1616 #define FW_EQ_ETH_CMD_DCACPU_V(x) ((x) << FW_EQ_ETH_CMD_DCACPU_S) 1617 1618 #define FW_EQ_ETH_CMD_FBMIN_S 23 1619 #define FW_EQ_ETH_CMD_FBMIN_V(x) ((x) << FW_EQ_ETH_CMD_FBMIN_S) 1620 1621 #define FW_EQ_ETH_CMD_FBMAX_S 20 1622 #define FW_EQ_ETH_CMD_FBMAX_V(x) ((x) << FW_EQ_ETH_CMD_FBMAX_S) 1623 1624 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_S 19 1625 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESHO_S) 1626 1627 #define FW_EQ_ETH_CMD_CIDXFTHRESH_S 16 1628 #define FW_EQ_ETH_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESH_S) 1629 1630 #define FW_EQ_ETH_CMD_EQSIZE_S 0 1631 #define FW_EQ_ETH_CMD_EQSIZE_V(x) ((x) << FW_EQ_ETH_CMD_EQSIZE_S) 1632 1633 #define FW_EQ_ETH_CMD_AUTOEQUEQE_S 30 1634 #define FW_EQ_ETH_CMD_AUTOEQUEQE_V(x) ((x) << FW_EQ_ETH_CMD_AUTOEQUEQE_S) 1635 #define FW_EQ_ETH_CMD_AUTOEQUEQE_F FW_EQ_ETH_CMD_AUTOEQUEQE_V(1U) 1636 1637 #define FW_EQ_ETH_CMD_VIID_S 16 1638 #define FW_EQ_ETH_CMD_VIID_V(x) ((x) << FW_EQ_ETH_CMD_VIID_S) 1639 1640 struct fw_eq_ctrl_cmd { 1641 __be32 op_to_vfn; 1642 __be32 alloc_to_len16; 1643 __be32 cmpliqid_eqid; 1644 __be32 physeqid_pkd; 1645 __be32 fetchszm_to_iqid; 1646 __be32 dcaen_to_eqsize; 1647 __be64 eqaddr; 1648 }; 1649 1650 #define FW_EQ_CTRL_CMD_PFN_S 8 1651 #define FW_EQ_CTRL_CMD_PFN_V(x) ((x) << FW_EQ_CTRL_CMD_PFN_S) 1652 1653 #define FW_EQ_CTRL_CMD_VFN_S 0 1654 #define FW_EQ_CTRL_CMD_VFN_V(x) ((x) << FW_EQ_CTRL_CMD_VFN_S) 1655 1656 #define FW_EQ_CTRL_CMD_ALLOC_S 31 1657 #define FW_EQ_CTRL_CMD_ALLOC_V(x) ((x) << FW_EQ_CTRL_CMD_ALLOC_S) 1658 #define FW_EQ_CTRL_CMD_ALLOC_F FW_EQ_CTRL_CMD_ALLOC_V(1U) 1659 1660 #define FW_EQ_CTRL_CMD_FREE_S 30 1661 #define FW_EQ_CTRL_CMD_FREE_V(x) ((x) << FW_EQ_CTRL_CMD_FREE_S) 1662 #define FW_EQ_CTRL_CMD_FREE_F FW_EQ_CTRL_CMD_FREE_V(1U) 1663 1664 #define FW_EQ_CTRL_CMD_MODIFY_S 29 1665 #define FW_EQ_CTRL_CMD_MODIFY_V(x) ((x) << FW_EQ_CTRL_CMD_MODIFY_S) 1666 #define FW_EQ_CTRL_CMD_MODIFY_F FW_EQ_CTRL_CMD_MODIFY_V(1U) 1667 1668 #define FW_EQ_CTRL_CMD_EQSTART_S 28 1669 #define FW_EQ_CTRL_CMD_EQSTART_V(x) ((x) << FW_EQ_CTRL_CMD_EQSTART_S) 1670 #define FW_EQ_CTRL_CMD_EQSTART_F FW_EQ_CTRL_CMD_EQSTART_V(1U) 1671 1672 #define FW_EQ_CTRL_CMD_EQSTOP_S 27 1673 #define FW_EQ_CTRL_CMD_EQSTOP_V(x) ((x) << FW_EQ_CTRL_CMD_EQSTOP_S) 1674 #define FW_EQ_CTRL_CMD_EQSTOP_F FW_EQ_CTRL_CMD_EQSTOP_V(1U) 1675 1676 #define FW_EQ_CTRL_CMD_CMPLIQID_S 20 1677 #define FW_EQ_CTRL_CMD_CMPLIQID_V(x) ((x) << FW_EQ_CTRL_CMD_CMPLIQID_S) 1678 1679 #define FW_EQ_CTRL_CMD_EQID_S 0 1680 #define FW_EQ_CTRL_CMD_EQID_M 0xfffff 1681 #define FW_EQ_CTRL_CMD_EQID_V(x) ((x) << FW_EQ_CTRL_CMD_EQID_S) 1682 #define FW_EQ_CTRL_CMD_EQID_G(x) \ 1683 (((x) >> FW_EQ_CTRL_CMD_EQID_S) & FW_EQ_CTRL_CMD_EQID_M) 1684 1685 #define FW_EQ_CTRL_CMD_PHYSEQID_S 0 1686 #define FW_EQ_CTRL_CMD_PHYSEQID_M 0xfffff 1687 #define FW_EQ_CTRL_CMD_PHYSEQID_G(x) \ 1688 (((x) >> FW_EQ_CTRL_CMD_PHYSEQID_S) & FW_EQ_CTRL_CMD_PHYSEQID_M) 1689 1690 #define FW_EQ_CTRL_CMD_FETCHSZM_S 26 1691 #define FW_EQ_CTRL_CMD_FETCHSZM_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHSZM_S) 1692 #define FW_EQ_CTRL_CMD_FETCHSZM_F FW_EQ_CTRL_CMD_FETCHSZM_V(1U) 1693 1694 #define FW_EQ_CTRL_CMD_STATUSPGNS_S 25 1695 #define FW_EQ_CTRL_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_CTRL_CMD_STATUSPGNS_S) 1696 #define FW_EQ_CTRL_CMD_STATUSPGNS_F FW_EQ_CTRL_CMD_STATUSPGNS_V(1U) 1697 1698 #define FW_EQ_CTRL_CMD_STATUSPGRO_S 24 1699 #define FW_EQ_CTRL_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_CTRL_CMD_STATUSPGRO_S) 1700 #define FW_EQ_CTRL_CMD_STATUSPGRO_F FW_EQ_CTRL_CMD_STATUSPGRO_V(1U) 1701 1702 #define FW_EQ_CTRL_CMD_FETCHNS_S 23 1703 #define FW_EQ_CTRL_CMD_FETCHNS_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHNS_S) 1704 #define FW_EQ_CTRL_CMD_FETCHNS_F FW_EQ_CTRL_CMD_FETCHNS_V(1U) 1705 1706 #define FW_EQ_CTRL_CMD_FETCHRO_S 22 1707 #define FW_EQ_CTRL_CMD_FETCHRO_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHRO_S) 1708 #define FW_EQ_CTRL_CMD_FETCHRO_F FW_EQ_CTRL_CMD_FETCHRO_V(1U) 1709 1710 #define FW_EQ_CTRL_CMD_HOSTFCMODE_S 20 1711 #define FW_EQ_CTRL_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_CTRL_CMD_HOSTFCMODE_S) 1712 1713 #define FW_EQ_CTRL_CMD_CPRIO_S 19 1714 #define FW_EQ_CTRL_CMD_CPRIO_V(x) ((x) << FW_EQ_CTRL_CMD_CPRIO_S) 1715 1716 #define FW_EQ_CTRL_CMD_ONCHIP_S 18 1717 #define FW_EQ_CTRL_CMD_ONCHIP_V(x) ((x) << FW_EQ_CTRL_CMD_ONCHIP_S) 1718 1719 #define FW_EQ_CTRL_CMD_PCIECHN_S 16 1720 #define FW_EQ_CTRL_CMD_PCIECHN_V(x) ((x) << FW_EQ_CTRL_CMD_PCIECHN_S) 1721 1722 #define FW_EQ_CTRL_CMD_IQID_S 0 1723 #define FW_EQ_CTRL_CMD_IQID_V(x) ((x) << FW_EQ_CTRL_CMD_IQID_S) 1724 1725 #define FW_EQ_CTRL_CMD_DCAEN_S 31 1726 #define FW_EQ_CTRL_CMD_DCAEN_V(x) ((x) << FW_EQ_CTRL_CMD_DCAEN_S) 1727 1728 #define FW_EQ_CTRL_CMD_DCACPU_S 26 1729 #define FW_EQ_CTRL_CMD_DCACPU_V(x) ((x) << FW_EQ_CTRL_CMD_DCACPU_S) 1730 1731 #define FW_EQ_CTRL_CMD_FBMIN_S 23 1732 #define FW_EQ_CTRL_CMD_FBMIN_V(x) ((x) << FW_EQ_CTRL_CMD_FBMIN_S) 1733 1734 #define FW_EQ_CTRL_CMD_FBMAX_S 20 1735 #define FW_EQ_CTRL_CMD_FBMAX_V(x) ((x) << FW_EQ_CTRL_CMD_FBMAX_S) 1736 1737 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_S 19 1738 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_V(x) \ 1739 ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESHO_S) 1740 1741 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_S 16 1742 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESH_S) 1743 1744 #define FW_EQ_CTRL_CMD_EQSIZE_S 0 1745 #define FW_EQ_CTRL_CMD_EQSIZE_V(x) ((x) << FW_EQ_CTRL_CMD_EQSIZE_S) 1746 1747 struct fw_eq_ofld_cmd { 1748 __be32 op_to_vfn; 1749 __be32 alloc_to_len16; 1750 __be32 eqid_pkd; 1751 __be32 physeqid_pkd; 1752 __be32 fetchszm_to_iqid; 1753 __be32 dcaen_to_eqsize; 1754 __be64 eqaddr; 1755 }; 1756 1757 #define FW_EQ_OFLD_CMD_PFN_S 8 1758 #define FW_EQ_OFLD_CMD_PFN_V(x) ((x) << FW_EQ_OFLD_CMD_PFN_S) 1759 1760 #define FW_EQ_OFLD_CMD_VFN_S 0 1761 #define FW_EQ_OFLD_CMD_VFN_V(x) ((x) << FW_EQ_OFLD_CMD_VFN_S) 1762 1763 #define FW_EQ_OFLD_CMD_ALLOC_S 31 1764 #define FW_EQ_OFLD_CMD_ALLOC_V(x) ((x) << FW_EQ_OFLD_CMD_ALLOC_S) 1765 #define FW_EQ_OFLD_CMD_ALLOC_F FW_EQ_OFLD_CMD_ALLOC_V(1U) 1766 1767 #define FW_EQ_OFLD_CMD_FREE_S 30 1768 #define FW_EQ_OFLD_CMD_FREE_V(x) ((x) << FW_EQ_OFLD_CMD_FREE_S) 1769 #define FW_EQ_OFLD_CMD_FREE_F FW_EQ_OFLD_CMD_FREE_V(1U) 1770 1771 #define FW_EQ_OFLD_CMD_MODIFY_S 29 1772 #define FW_EQ_OFLD_CMD_MODIFY_V(x) ((x) << FW_EQ_OFLD_CMD_MODIFY_S) 1773 #define FW_EQ_OFLD_CMD_MODIFY_F FW_EQ_OFLD_CMD_MODIFY_V(1U) 1774 1775 #define FW_EQ_OFLD_CMD_EQSTART_S 28 1776 #define FW_EQ_OFLD_CMD_EQSTART_V(x) ((x) << FW_EQ_OFLD_CMD_EQSTART_S) 1777 #define FW_EQ_OFLD_CMD_EQSTART_F FW_EQ_OFLD_CMD_EQSTART_V(1U) 1778 1779 #define FW_EQ_OFLD_CMD_EQSTOP_S 27 1780 #define FW_EQ_OFLD_CMD_EQSTOP_V(x) ((x) << FW_EQ_OFLD_CMD_EQSTOP_S) 1781 #define FW_EQ_OFLD_CMD_EQSTOP_F FW_EQ_OFLD_CMD_EQSTOP_V(1U) 1782 1783 #define FW_EQ_OFLD_CMD_EQID_S 0 1784 #define FW_EQ_OFLD_CMD_EQID_M 0xfffff 1785 #define FW_EQ_OFLD_CMD_EQID_V(x) ((x) << FW_EQ_OFLD_CMD_EQID_S) 1786 #define FW_EQ_OFLD_CMD_EQID_G(x) \ 1787 (((x) >> FW_EQ_OFLD_CMD_EQID_S) & FW_EQ_OFLD_CMD_EQID_M) 1788 1789 #define FW_EQ_OFLD_CMD_PHYSEQID_S 0 1790 #define FW_EQ_OFLD_CMD_PHYSEQID_M 0xfffff 1791 #define FW_EQ_OFLD_CMD_PHYSEQID_G(x) \ 1792 (((x) >> FW_EQ_OFLD_CMD_PHYSEQID_S) & FW_EQ_OFLD_CMD_PHYSEQID_M) 1793 1794 #define FW_EQ_OFLD_CMD_FETCHSZM_S 26 1795 #define FW_EQ_OFLD_CMD_FETCHSZM_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHSZM_S) 1796 1797 #define FW_EQ_OFLD_CMD_STATUSPGNS_S 25 1798 #define FW_EQ_OFLD_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_OFLD_CMD_STATUSPGNS_S) 1799 1800 #define FW_EQ_OFLD_CMD_STATUSPGRO_S 24 1801 #define FW_EQ_OFLD_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_OFLD_CMD_STATUSPGRO_S) 1802 1803 #define FW_EQ_OFLD_CMD_FETCHNS_S 23 1804 #define FW_EQ_OFLD_CMD_FETCHNS_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHNS_S) 1805 1806 #define FW_EQ_OFLD_CMD_FETCHRO_S 22 1807 #define FW_EQ_OFLD_CMD_FETCHRO_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHRO_S) 1808 #define FW_EQ_OFLD_CMD_FETCHRO_F FW_EQ_OFLD_CMD_FETCHRO_V(1U) 1809 1810 #define FW_EQ_OFLD_CMD_HOSTFCMODE_S 20 1811 #define FW_EQ_OFLD_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_OFLD_CMD_HOSTFCMODE_S) 1812 1813 #define FW_EQ_OFLD_CMD_CPRIO_S 19 1814 #define FW_EQ_OFLD_CMD_CPRIO_V(x) ((x) << FW_EQ_OFLD_CMD_CPRIO_S) 1815 1816 #define FW_EQ_OFLD_CMD_ONCHIP_S 18 1817 #define FW_EQ_OFLD_CMD_ONCHIP_V(x) ((x) << FW_EQ_OFLD_CMD_ONCHIP_S) 1818 1819 #define FW_EQ_OFLD_CMD_PCIECHN_S 16 1820 #define FW_EQ_OFLD_CMD_PCIECHN_V(x) ((x) << FW_EQ_OFLD_CMD_PCIECHN_S) 1821 1822 #define FW_EQ_OFLD_CMD_IQID_S 0 1823 #define FW_EQ_OFLD_CMD_IQID_V(x) ((x) << FW_EQ_OFLD_CMD_IQID_S) 1824 1825 #define FW_EQ_OFLD_CMD_DCAEN_S 31 1826 #define FW_EQ_OFLD_CMD_DCAEN_V(x) ((x) << FW_EQ_OFLD_CMD_DCAEN_S) 1827 1828 #define FW_EQ_OFLD_CMD_DCACPU_S 26 1829 #define FW_EQ_OFLD_CMD_DCACPU_V(x) ((x) << FW_EQ_OFLD_CMD_DCACPU_S) 1830 1831 #define FW_EQ_OFLD_CMD_FBMIN_S 23 1832 #define FW_EQ_OFLD_CMD_FBMIN_V(x) ((x) << FW_EQ_OFLD_CMD_FBMIN_S) 1833 1834 #define FW_EQ_OFLD_CMD_FBMAX_S 20 1835 #define FW_EQ_OFLD_CMD_FBMAX_V(x) ((x) << FW_EQ_OFLD_CMD_FBMAX_S) 1836 1837 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_S 19 1838 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_V(x) \ 1839 ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESHO_S) 1840 1841 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_S 16 1842 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESH_S) 1843 1844 #define FW_EQ_OFLD_CMD_EQSIZE_S 0 1845 #define FW_EQ_OFLD_CMD_EQSIZE_V(x) ((x) << FW_EQ_OFLD_CMD_EQSIZE_S) 1846 1847 /* 1848 * Macros for VIID parsing: 1849 * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number 1850 */ 1851 1852 #define FW_VIID_PFN_S 8 1853 #define FW_VIID_PFN_M 0x7 1854 #define FW_VIID_PFN_G(x) (((x) >> FW_VIID_PFN_S) & FW_VIID_PFN_M) 1855 1856 #define FW_VIID_VIVLD_S 7 1857 #define FW_VIID_VIVLD_M 0x1 1858 #define FW_VIID_VIVLD_G(x) (((x) >> FW_VIID_VIVLD_S) & FW_VIID_VIVLD_M) 1859 1860 #define FW_VIID_VIN_S 0 1861 #define FW_VIID_VIN_M 0x7F 1862 #define FW_VIID_VIN_G(x) (((x) >> FW_VIID_VIN_S) & FW_VIID_VIN_M) 1863 1864 struct fw_vi_cmd { 1865 __be32 op_to_vfn; 1866 __be32 alloc_to_len16; 1867 __be16 type_viid; 1868 u8 mac[6]; 1869 u8 portid_pkd; 1870 u8 nmac; 1871 u8 nmac0[6]; 1872 __be16 rsssize_pkd; 1873 u8 nmac1[6]; 1874 __be16 idsiiq_pkd; 1875 u8 nmac2[6]; 1876 __be16 idseiq_pkd; 1877 u8 nmac3[6]; 1878 __be64 r9; 1879 __be64 r10; 1880 }; 1881 1882 #define FW_VI_CMD_PFN_S 8 1883 #define FW_VI_CMD_PFN_V(x) ((x) << FW_VI_CMD_PFN_S) 1884 1885 #define FW_VI_CMD_VFN_S 0 1886 #define FW_VI_CMD_VFN_V(x) ((x) << FW_VI_CMD_VFN_S) 1887 1888 #define FW_VI_CMD_ALLOC_S 31 1889 #define FW_VI_CMD_ALLOC_V(x) ((x) << FW_VI_CMD_ALLOC_S) 1890 #define FW_VI_CMD_ALLOC_F FW_VI_CMD_ALLOC_V(1U) 1891 1892 #define FW_VI_CMD_FREE_S 30 1893 #define FW_VI_CMD_FREE_V(x) ((x) << FW_VI_CMD_FREE_S) 1894 #define FW_VI_CMD_FREE_F FW_VI_CMD_FREE_V(1U) 1895 1896 #define FW_VI_CMD_VIID_S 0 1897 #define FW_VI_CMD_VIID_M 0xfff 1898 #define FW_VI_CMD_VIID_V(x) ((x) << FW_VI_CMD_VIID_S) 1899 #define FW_VI_CMD_VIID_G(x) (((x) >> FW_VI_CMD_VIID_S) & FW_VI_CMD_VIID_M) 1900 1901 #define FW_VI_CMD_PORTID_S 4 1902 #define FW_VI_CMD_PORTID_M 0xf 1903 #define FW_VI_CMD_PORTID_V(x) ((x) << FW_VI_CMD_PORTID_S) 1904 #define FW_VI_CMD_PORTID_G(x) \ 1905 (((x) >> FW_VI_CMD_PORTID_S) & FW_VI_CMD_PORTID_M) 1906 1907 #define FW_VI_CMD_RSSSIZE_S 0 1908 #define FW_VI_CMD_RSSSIZE_M 0x7ff 1909 #define FW_VI_CMD_RSSSIZE_G(x) \ 1910 (((x) >> FW_VI_CMD_RSSSIZE_S) & FW_VI_CMD_RSSSIZE_M) 1911 1912 /* Special VI_MAC command index ids */ 1913 #define FW_VI_MAC_ADD_MAC 0x3FF 1914 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 1915 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD 1916 #define FW_CLS_TCAM_NUM_ENTRIES 336 1917 1918 enum fw_vi_mac_smac { 1919 FW_VI_MAC_MPS_TCAM_ENTRY, 1920 FW_VI_MAC_MPS_TCAM_ONLY, 1921 FW_VI_MAC_SMT_ONLY, 1922 FW_VI_MAC_SMT_AND_MPSTCAM 1923 }; 1924 1925 enum fw_vi_mac_result { 1926 FW_VI_MAC_R_SUCCESS, 1927 FW_VI_MAC_R_F_NONEXISTENT_NOMEM, 1928 FW_VI_MAC_R_SMAC_FAIL, 1929 FW_VI_MAC_R_F_ACL_CHECK 1930 }; 1931 1932 struct fw_vi_mac_cmd { 1933 __be32 op_to_viid; 1934 __be32 freemacs_to_len16; 1935 union fw_vi_mac { 1936 struct fw_vi_mac_exact { 1937 __be16 valid_to_idx; 1938 u8 macaddr[6]; 1939 } exact[7]; 1940 struct fw_vi_mac_hash { 1941 __be64 hashvec; 1942 } hash; 1943 } u; 1944 }; 1945 1946 #define FW_VI_MAC_CMD_VIID_S 0 1947 #define FW_VI_MAC_CMD_VIID_V(x) ((x) << FW_VI_MAC_CMD_VIID_S) 1948 1949 #define FW_VI_MAC_CMD_FREEMACS_S 31 1950 #define FW_VI_MAC_CMD_FREEMACS_V(x) ((x) << FW_VI_MAC_CMD_FREEMACS_S) 1951 1952 #define FW_VI_MAC_CMD_HASHVECEN_S 23 1953 #define FW_VI_MAC_CMD_HASHVECEN_V(x) ((x) << FW_VI_MAC_CMD_HASHVECEN_S) 1954 #define FW_VI_MAC_CMD_HASHVECEN_F FW_VI_MAC_CMD_HASHVECEN_V(1U) 1955 1956 #define FW_VI_MAC_CMD_HASHUNIEN_S 22 1957 #define FW_VI_MAC_CMD_HASHUNIEN_V(x) ((x) << FW_VI_MAC_CMD_HASHUNIEN_S) 1958 1959 #define FW_VI_MAC_CMD_VALID_S 15 1960 #define FW_VI_MAC_CMD_VALID_V(x) ((x) << FW_VI_MAC_CMD_VALID_S) 1961 #define FW_VI_MAC_CMD_VALID_F FW_VI_MAC_CMD_VALID_V(1U) 1962 1963 #define FW_VI_MAC_CMD_PRIO_S 12 1964 #define FW_VI_MAC_CMD_PRIO_V(x) ((x) << FW_VI_MAC_CMD_PRIO_S) 1965 1966 #define FW_VI_MAC_CMD_SMAC_RESULT_S 10 1967 #define FW_VI_MAC_CMD_SMAC_RESULT_M 0x3 1968 #define FW_VI_MAC_CMD_SMAC_RESULT_V(x) ((x) << FW_VI_MAC_CMD_SMAC_RESULT_S) 1969 #define FW_VI_MAC_CMD_SMAC_RESULT_G(x) \ 1970 (((x) >> FW_VI_MAC_CMD_SMAC_RESULT_S) & FW_VI_MAC_CMD_SMAC_RESULT_M) 1971 1972 #define FW_VI_MAC_CMD_IDX_S 0 1973 #define FW_VI_MAC_CMD_IDX_M 0x3ff 1974 #define FW_VI_MAC_CMD_IDX_V(x) ((x) << FW_VI_MAC_CMD_IDX_S) 1975 #define FW_VI_MAC_CMD_IDX_G(x) \ 1976 (((x) >> FW_VI_MAC_CMD_IDX_S) & FW_VI_MAC_CMD_IDX_M) 1977 1978 #define FW_RXMODE_MTU_NO_CHG 65535 1979 1980 struct fw_vi_rxmode_cmd { 1981 __be32 op_to_viid; 1982 __be32 retval_len16; 1983 __be32 mtu_to_vlanexen; 1984 __be32 r4_lo; 1985 }; 1986 1987 #define FW_VI_RXMODE_CMD_VIID_S 0 1988 #define FW_VI_RXMODE_CMD_VIID_V(x) ((x) << FW_VI_RXMODE_CMD_VIID_S) 1989 1990 #define FW_VI_RXMODE_CMD_MTU_S 16 1991 #define FW_VI_RXMODE_CMD_MTU_M 0xffff 1992 #define FW_VI_RXMODE_CMD_MTU_V(x) ((x) << FW_VI_RXMODE_CMD_MTU_S) 1993 1994 #define FW_VI_RXMODE_CMD_PROMISCEN_S 14 1995 #define FW_VI_RXMODE_CMD_PROMISCEN_M 0x3 1996 #define FW_VI_RXMODE_CMD_PROMISCEN_V(x) ((x) << FW_VI_RXMODE_CMD_PROMISCEN_S) 1997 1998 #define FW_VI_RXMODE_CMD_ALLMULTIEN_S 12 1999 #define FW_VI_RXMODE_CMD_ALLMULTIEN_M 0x3 2000 #define FW_VI_RXMODE_CMD_ALLMULTIEN_V(x) \ 2001 ((x) << FW_VI_RXMODE_CMD_ALLMULTIEN_S) 2002 2003 #define FW_VI_RXMODE_CMD_BROADCASTEN_S 10 2004 #define FW_VI_RXMODE_CMD_BROADCASTEN_M 0x3 2005 #define FW_VI_RXMODE_CMD_BROADCASTEN_V(x) \ 2006 ((x) << FW_VI_RXMODE_CMD_BROADCASTEN_S) 2007 2008 #define FW_VI_RXMODE_CMD_VLANEXEN_S 8 2009 #define FW_VI_RXMODE_CMD_VLANEXEN_M 0x3 2010 #define FW_VI_RXMODE_CMD_VLANEXEN_V(x) ((x) << FW_VI_RXMODE_CMD_VLANEXEN_S) 2011 2012 struct fw_vi_enable_cmd { 2013 __be32 op_to_viid; 2014 __be32 ien_to_len16; 2015 __be16 blinkdur; 2016 __be16 r3; 2017 __be32 r4; 2018 }; 2019 2020 #define FW_VI_ENABLE_CMD_VIID_S 0 2021 #define FW_VI_ENABLE_CMD_VIID_V(x) ((x) << FW_VI_ENABLE_CMD_VIID_S) 2022 2023 #define FW_VI_ENABLE_CMD_IEN_S 31 2024 #define FW_VI_ENABLE_CMD_IEN_V(x) ((x) << FW_VI_ENABLE_CMD_IEN_S) 2025 2026 #define FW_VI_ENABLE_CMD_EEN_S 30 2027 #define FW_VI_ENABLE_CMD_EEN_V(x) ((x) << FW_VI_ENABLE_CMD_EEN_S) 2028 2029 #define FW_VI_ENABLE_CMD_LED_S 29 2030 #define FW_VI_ENABLE_CMD_LED_V(x) ((x) << FW_VI_ENABLE_CMD_LED_S) 2031 #define FW_VI_ENABLE_CMD_LED_F FW_VI_ENABLE_CMD_LED_V(1U) 2032 2033 #define FW_VI_ENABLE_CMD_DCB_INFO_S 28 2034 #define FW_VI_ENABLE_CMD_DCB_INFO_V(x) ((x) << FW_VI_ENABLE_CMD_DCB_INFO_S) 2035 2036 /* VI VF stats offset definitions */ 2037 #define VI_VF_NUM_STATS 16 2038 enum fw_vi_stats_vf_index { 2039 FW_VI_VF_STAT_TX_BCAST_BYTES_IX, 2040 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, 2041 FW_VI_VF_STAT_TX_MCAST_BYTES_IX, 2042 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, 2043 FW_VI_VF_STAT_TX_UCAST_BYTES_IX, 2044 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, 2045 FW_VI_VF_STAT_TX_DROP_FRAMES_IX, 2046 FW_VI_VF_STAT_TX_OFLD_BYTES_IX, 2047 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, 2048 FW_VI_VF_STAT_RX_BCAST_BYTES_IX, 2049 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, 2050 FW_VI_VF_STAT_RX_MCAST_BYTES_IX, 2051 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, 2052 FW_VI_VF_STAT_RX_UCAST_BYTES_IX, 2053 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, 2054 FW_VI_VF_STAT_RX_ERR_FRAMES_IX 2055 }; 2056 2057 /* VI PF stats offset definitions */ 2058 #define VI_PF_NUM_STATS 17 2059 enum fw_vi_stats_pf_index { 2060 FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 2061 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 2062 FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 2063 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 2064 FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 2065 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 2066 FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 2067 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 2068 FW_VI_PF_STAT_RX_BYTES_IX, 2069 FW_VI_PF_STAT_RX_FRAMES_IX, 2070 FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 2071 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 2072 FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 2073 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 2074 FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 2075 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 2076 FW_VI_PF_STAT_RX_ERR_FRAMES_IX 2077 }; 2078 2079 struct fw_vi_stats_cmd { 2080 __be32 op_to_viid; 2081 __be32 retval_len16; 2082 union fw_vi_stats { 2083 struct fw_vi_stats_ctl { 2084 __be16 nstats_ix; 2085 __be16 r6; 2086 __be32 r7; 2087 __be64 stat0; 2088 __be64 stat1; 2089 __be64 stat2; 2090 __be64 stat3; 2091 __be64 stat4; 2092 __be64 stat5; 2093 } ctl; 2094 struct fw_vi_stats_pf { 2095 __be64 tx_bcast_bytes; 2096 __be64 tx_bcast_frames; 2097 __be64 tx_mcast_bytes; 2098 __be64 tx_mcast_frames; 2099 __be64 tx_ucast_bytes; 2100 __be64 tx_ucast_frames; 2101 __be64 tx_offload_bytes; 2102 __be64 tx_offload_frames; 2103 __be64 rx_pf_bytes; 2104 __be64 rx_pf_frames; 2105 __be64 rx_bcast_bytes; 2106 __be64 rx_bcast_frames; 2107 __be64 rx_mcast_bytes; 2108 __be64 rx_mcast_frames; 2109 __be64 rx_ucast_bytes; 2110 __be64 rx_ucast_frames; 2111 __be64 rx_err_frames; 2112 } pf; 2113 struct fw_vi_stats_vf { 2114 __be64 tx_bcast_bytes; 2115 __be64 tx_bcast_frames; 2116 __be64 tx_mcast_bytes; 2117 __be64 tx_mcast_frames; 2118 __be64 tx_ucast_bytes; 2119 __be64 tx_ucast_frames; 2120 __be64 tx_drop_frames; 2121 __be64 tx_offload_bytes; 2122 __be64 tx_offload_frames; 2123 __be64 rx_bcast_bytes; 2124 __be64 rx_bcast_frames; 2125 __be64 rx_mcast_bytes; 2126 __be64 rx_mcast_frames; 2127 __be64 rx_ucast_bytes; 2128 __be64 rx_ucast_frames; 2129 __be64 rx_err_frames; 2130 } vf; 2131 } u; 2132 }; 2133 2134 #define FW_VI_STATS_CMD_VIID_S 0 2135 #define FW_VI_STATS_CMD_VIID_V(x) ((x) << FW_VI_STATS_CMD_VIID_S) 2136 2137 #define FW_VI_STATS_CMD_NSTATS_S 12 2138 #define FW_VI_STATS_CMD_NSTATS_V(x) ((x) << FW_VI_STATS_CMD_NSTATS_S) 2139 2140 #define FW_VI_STATS_CMD_IX_S 0 2141 #define FW_VI_STATS_CMD_IX_V(x) ((x) << FW_VI_STATS_CMD_IX_S) 2142 2143 struct fw_acl_mac_cmd { 2144 __be32 op_to_vfn; 2145 __be32 en_to_len16; 2146 u8 nmac; 2147 u8 r3[7]; 2148 __be16 r4; 2149 u8 macaddr0[6]; 2150 __be16 r5; 2151 u8 macaddr1[6]; 2152 __be16 r6; 2153 u8 macaddr2[6]; 2154 __be16 r7; 2155 u8 macaddr3[6]; 2156 }; 2157 2158 #define FW_ACL_MAC_CMD_PFN_S 8 2159 #define FW_ACL_MAC_CMD_PFN_V(x) ((x) << FW_ACL_MAC_CMD_PFN_S) 2160 2161 #define FW_ACL_MAC_CMD_VFN_S 0 2162 #define FW_ACL_MAC_CMD_VFN_V(x) ((x) << FW_ACL_MAC_CMD_VFN_S) 2163 2164 #define FW_ACL_MAC_CMD_EN_S 31 2165 #define FW_ACL_MAC_CMD_EN_V(x) ((x) << FW_ACL_MAC_CMD_EN_S) 2166 2167 struct fw_acl_vlan_cmd { 2168 __be32 op_to_vfn; 2169 __be32 en_to_len16; 2170 u8 nvlan; 2171 u8 dropnovlan_fm; 2172 u8 r3_lo[6]; 2173 __be16 vlanid[16]; 2174 }; 2175 2176 #define FW_ACL_VLAN_CMD_PFN_S 8 2177 #define FW_ACL_VLAN_CMD_PFN_V(x) ((x) << FW_ACL_VLAN_CMD_PFN_S) 2178 2179 #define FW_ACL_VLAN_CMD_VFN_S 0 2180 #define FW_ACL_VLAN_CMD_VFN_V(x) ((x) << FW_ACL_VLAN_CMD_VFN_S) 2181 2182 #define FW_ACL_VLAN_CMD_EN_S 31 2183 #define FW_ACL_VLAN_CMD_EN_V(x) ((x) << FW_ACL_VLAN_CMD_EN_S) 2184 2185 #define FW_ACL_VLAN_CMD_DROPNOVLAN_S 7 2186 #define FW_ACL_VLAN_CMD_DROPNOVLAN_V(x) ((x) << FW_ACL_VLAN_CMD_DROPNOVLAN_S) 2187 2188 #define FW_ACL_VLAN_CMD_FM_S 6 2189 #define FW_ACL_VLAN_CMD_FM_V(x) ((x) << FW_ACL_VLAN_CMD_FM_S) 2190 2191 enum fw_port_cap { 2192 FW_PORT_CAP_SPEED_100M = 0x0001, 2193 FW_PORT_CAP_SPEED_1G = 0x0002, 2194 FW_PORT_CAP_SPEED_2_5G = 0x0004, 2195 FW_PORT_CAP_SPEED_10G = 0x0008, 2196 FW_PORT_CAP_SPEED_40G = 0x0010, 2197 FW_PORT_CAP_SPEED_100G = 0x0020, 2198 FW_PORT_CAP_FC_RX = 0x0040, 2199 FW_PORT_CAP_FC_TX = 0x0080, 2200 FW_PORT_CAP_ANEG = 0x0100, 2201 FW_PORT_CAP_MDI_0 = 0x0200, 2202 FW_PORT_CAP_MDI_1 = 0x0400, 2203 FW_PORT_CAP_BEAN = 0x0800, 2204 FW_PORT_CAP_PMA_LPBK = 0x1000, 2205 FW_PORT_CAP_PCS_LPBK = 0x2000, 2206 FW_PORT_CAP_PHYXS_LPBK = 0x4000, 2207 FW_PORT_CAP_FAR_END_LPBK = 0x8000, 2208 }; 2209 2210 enum fw_port_mdi { 2211 FW_PORT_CAP_MDI_UNCHANGED, 2212 FW_PORT_CAP_MDI_AUTO, 2213 FW_PORT_CAP_MDI_F_STRAIGHT, 2214 FW_PORT_CAP_MDI_F_CROSSOVER 2215 }; 2216 2217 #define FW_PORT_CAP_MDI_S 9 2218 #define FW_PORT_CAP_MDI_V(x) ((x) << FW_PORT_CAP_MDI_S) 2219 2220 enum fw_port_action { 2221 FW_PORT_ACTION_L1_CFG = 0x0001, 2222 FW_PORT_ACTION_L2_CFG = 0x0002, 2223 FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 2224 FW_PORT_ACTION_L2_PPP_CFG = 0x0004, 2225 FW_PORT_ACTION_L2_DCB_CFG = 0x0005, 2226 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006, 2227 FW_PORT_ACTION_DCB_READ_RECV = 0x0007, 2228 FW_PORT_ACTION_DCB_READ_DET = 0x0008, 2229 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, 2230 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, 2231 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, 2232 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, 2233 FW_PORT_ACTION_L1_LPBK = 0x0021, 2234 FW_PORT_ACTION_L1_PMA_LPBK = 0x0022, 2235 FW_PORT_ACTION_L1_PCS_LPBK = 0x0023, 2236 FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024, 2237 FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025, 2238 FW_PORT_ACTION_PHY_RESET = 0x0040, 2239 FW_PORT_ACTION_PMA_RESET = 0x0041, 2240 FW_PORT_ACTION_PCS_RESET = 0x0042, 2241 FW_PORT_ACTION_PHYXS_RESET = 0x0043, 2242 FW_PORT_ACTION_DTEXS_REEST = 0x0044, 2243 FW_PORT_ACTION_AN_RESET = 0x0045 2244 }; 2245 2246 enum fw_port_l2cfg_ctlbf { 2247 FW_PORT_L2_CTLBF_OVLAN0 = 0x01, 2248 FW_PORT_L2_CTLBF_OVLAN1 = 0x02, 2249 FW_PORT_L2_CTLBF_OVLAN2 = 0x04, 2250 FW_PORT_L2_CTLBF_OVLAN3 = 0x08, 2251 FW_PORT_L2_CTLBF_IVLAN = 0x10, 2252 FW_PORT_L2_CTLBF_TXIPG = 0x20 2253 }; 2254 2255 enum fw_port_dcb_versions { 2256 FW_PORT_DCB_VER_UNKNOWN, 2257 FW_PORT_DCB_VER_CEE1D0, 2258 FW_PORT_DCB_VER_CEE1D01, 2259 FW_PORT_DCB_VER_IEEE, 2260 FW_PORT_DCB_VER_AUTO = 7 2261 }; 2262 2263 enum fw_port_dcb_cfg { 2264 FW_PORT_DCB_CFG_PG = 0x01, 2265 FW_PORT_DCB_CFG_PFC = 0x02, 2266 FW_PORT_DCB_CFG_APPL = 0x04 2267 }; 2268 2269 enum fw_port_dcb_cfg_rc { 2270 FW_PORT_DCB_CFG_SUCCESS = 0x0, 2271 FW_PORT_DCB_CFG_ERROR = 0x1 2272 }; 2273 2274 enum fw_port_dcb_type { 2275 FW_PORT_DCB_TYPE_PGID = 0x00, 2276 FW_PORT_DCB_TYPE_PGRATE = 0x01, 2277 FW_PORT_DCB_TYPE_PRIORATE = 0x02, 2278 FW_PORT_DCB_TYPE_PFC = 0x03, 2279 FW_PORT_DCB_TYPE_APP_ID = 0x04, 2280 FW_PORT_DCB_TYPE_CONTROL = 0x05, 2281 }; 2282 2283 enum fw_port_dcb_feature_state { 2284 FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0, 2285 FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1, 2286 FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2, 2287 FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3, 2288 }; 2289 2290 struct fw_port_cmd { 2291 __be32 op_to_portid; 2292 __be32 action_to_len16; 2293 union fw_port { 2294 struct fw_port_l1cfg { 2295 __be32 rcap; 2296 __be32 r; 2297 } l1cfg; 2298 struct fw_port_l2cfg { 2299 __u8 ctlbf; 2300 __u8 ovlan3_to_ivlan0; 2301 __be16 ivlantype; 2302 __be16 txipg_force_pinfo; 2303 __be16 mtu; 2304 __be16 ovlan0mask; 2305 __be16 ovlan0type; 2306 __be16 ovlan1mask; 2307 __be16 ovlan1type; 2308 __be16 ovlan2mask; 2309 __be16 ovlan2type; 2310 __be16 ovlan3mask; 2311 __be16 ovlan3type; 2312 } l2cfg; 2313 struct fw_port_info { 2314 __be32 lstatus_to_modtype; 2315 __be16 pcap; 2316 __be16 acap; 2317 __be16 mtu; 2318 __u8 cbllen; 2319 __u8 auxlinfo; 2320 __u8 dcbxdis_pkd; 2321 __u8 r8_lo[3]; 2322 __be64 r9; 2323 } info; 2324 struct fw_port_diags { 2325 __u8 diagop; 2326 __u8 r[3]; 2327 __be32 diagval; 2328 } diags; 2329 union fw_port_dcb { 2330 struct fw_port_dcb_pgid { 2331 __u8 type; 2332 __u8 apply_pkd; 2333 __u8 r10_lo[2]; 2334 __be32 pgid; 2335 __be64 r11; 2336 } pgid; 2337 struct fw_port_dcb_pgrate { 2338 __u8 type; 2339 __u8 apply_pkd; 2340 __u8 r10_lo[5]; 2341 __u8 num_tcs_supported; 2342 __u8 pgrate[8]; 2343 __u8 tsa[8]; 2344 } pgrate; 2345 struct fw_port_dcb_priorate { 2346 __u8 type; 2347 __u8 apply_pkd; 2348 __u8 r10_lo[6]; 2349 __u8 strict_priorate[8]; 2350 } priorate; 2351 struct fw_port_dcb_pfc { 2352 __u8 type; 2353 __u8 pfcen; 2354 __u8 r10[5]; 2355 __u8 max_pfc_tcs; 2356 __be64 r11; 2357 } pfc; 2358 struct fw_port_app_priority { 2359 __u8 type; 2360 __u8 r10[2]; 2361 __u8 idx; 2362 __u8 user_prio_map; 2363 __u8 sel_field; 2364 __be16 protocolid; 2365 __be64 r12; 2366 } app_priority; 2367 struct fw_port_dcb_control { 2368 __u8 type; 2369 __u8 all_syncd_pkd; 2370 __be16 dcb_version_to_app_state; 2371 __be32 r11; 2372 __be64 r12; 2373 } control; 2374 } dcb; 2375 } u; 2376 }; 2377 2378 #define FW_PORT_CMD_READ_S 22 2379 #define FW_PORT_CMD_READ_V(x) ((x) << FW_PORT_CMD_READ_S) 2380 #define FW_PORT_CMD_READ_F FW_PORT_CMD_READ_V(1U) 2381 2382 #define FW_PORT_CMD_PORTID_S 0 2383 #define FW_PORT_CMD_PORTID_M 0xf 2384 #define FW_PORT_CMD_PORTID_V(x) ((x) << FW_PORT_CMD_PORTID_S) 2385 #define FW_PORT_CMD_PORTID_G(x) \ 2386 (((x) >> FW_PORT_CMD_PORTID_S) & FW_PORT_CMD_PORTID_M) 2387 2388 #define FW_PORT_CMD_ACTION_S 16 2389 #define FW_PORT_CMD_ACTION_M 0xffff 2390 #define FW_PORT_CMD_ACTION_V(x) ((x) << FW_PORT_CMD_ACTION_S) 2391 #define FW_PORT_CMD_ACTION_G(x) \ 2392 (((x) >> FW_PORT_CMD_ACTION_S) & FW_PORT_CMD_ACTION_M) 2393 2394 #define FW_PORT_CMD_OVLAN3_S 7 2395 #define FW_PORT_CMD_OVLAN3_V(x) ((x) << FW_PORT_CMD_OVLAN3_S) 2396 2397 #define FW_PORT_CMD_OVLAN2_S 6 2398 #define FW_PORT_CMD_OVLAN2_V(x) ((x) << FW_PORT_CMD_OVLAN2_S) 2399 2400 #define FW_PORT_CMD_OVLAN1_S 5 2401 #define FW_PORT_CMD_OVLAN1_V(x) ((x) << FW_PORT_CMD_OVLAN1_S) 2402 2403 #define FW_PORT_CMD_OVLAN0_S 4 2404 #define FW_PORT_CMD_OVLAN0_V(x) ((x) << FW_PORT_CMD_OVLAN0_S) 2405 2406 #define FW_PORT_CMD_IVLAN0_S 3 2407 #define FW_PORT_CMD_IVLAN0_V(x) ((x) << FW_PORT_CMD_IVLAN0_S) 2408 2409 #define FW_PORT_CMD_TXIPG_S 3 2410 #define FW_PORT_CMD_TXIPG_V(x) ((x) << FW_PORT_CMD_TXIPG_S) 2411 2412 #define FW_PORT_CMD_LSTATUS_S 31 2413 #define FW_PORT_CMD_LSTATUS_M 0x1 2414 #define FW_PORT_CMD_LSTATUS_V(x) ((x) << FW_PORT_CMD_LSTATUS_S) 2415 #define FW_PORT_CMD_LSTATUS_G(x) \ 2416 (((x) >> FW_PORT_CMD_LSTATUS_S) & FW_PORT_CMD_LSTATUS_M) 2417 #define FW_PORT_CMD_LSTATUS_F FW_PORT_CMD_LSTATUS_V(1U) 2418 2419 #define FW_PORT_CMD_LSPEED_S 24 2420 #define FW_PORT_CMD_LSPEED_M 0x3f 2421 #define FW_PORT_CMD_LSPEED_V(x) ((x) << FW_PORT_CMD_LSPEED_S) 2422 #define FW_PORT_CMD_LSPEED_G(x) \ 2423 (((x) >> FW_PORT_CMD_LSPEED_S) & FW_PORT_CMD_LSPEED_M) 2424 2425 #define FW_PORT_CMD_TXPAUSE_S 23 2426 #define FW_PORT_CMD_TXPAUSE_V(x) ((x) << FW_PORT_CMD_TXPAUSE_S) 2427 #define FW_PORT_CMD_TXPAUSE_F FW_PORT_CMD_TXPAUSE_V(1U) 2428 2429 #define FW_PORT_CMD_RXPAUSE_S 22 2430 #define FW_PORT_CMD_RXPAUSE_V(x) ((x) << FW_PORT_CMD_RXPAUSE_S) 2431 #define FW_PORT_CMD_RXPAUSE_F FW_PORT_CMD_RXPAUSE_V(1U) 2432 2433 #define FW_PORT_CMD_MDIOCAP_S 21 2434 #define FW_PORT_CMD_MDIOCAP_V(x) ((x) << FW_PORT_CMD_MDIOCAP_S) 2435 #define FW_PORT_CMD_MDIOCAP_F FW_PORT_CMD_MDIOCAP_V(1U) 2436 2437 #define FW_PORT_CMD_MDIOADDR_S 16 2438 #define FW_PORT_CMD_MDIOADDR_M 0x1f 2439 #define FW_PORT_CMD_MDIOADDR_G(x) \ 2440 (((x) >> FW_PORT_CMD_MDIOADDR_S) & FW_PORT_CMD_MDIOADDR_M) 2441 2442 #define FW_PORT_CMD_LPTXPAUSE_S 15 2443 #define FW_PORT_CMD_LPTXPAUSE_V(x) ((x) << FW_PORT_CMD_LPTXPAUSE_S) 2444 #define FW_PORT_CMD_LPTXPAUSE_F FW_PORT_CMD_LPTXPAUSE_V(1U) 2445 2446 #define FW_PORT_CMD_LPRXPAUSE_S 14 2447 #define FW_PORT_CMD_LPRXPAUSE_V(x) ((x) << FW_PORT_CMD_LPRXPAUSE_S) 2448 #define FW_PORT_CMD_LPRXPAUSE_F FW_PORT_CMD_LPRXPAUSE_V(1U) 2449 2450 #define FW_PORT_CMD_PTYPE_S 8 2451 #define FW_PORT_CMD_PTYPE_M 0x1f 2452 #define FW_PORT_CMD_PTYPE_G(x) \ 2453 (((x) >> FW_PORT_CMD_PTYPE_S) & FW_PORT_CMD_PTYPE_M) 2454 2455 #define FW_PORT_CMD_MODTYPE_S 0 2456 #define FW_PORT_CMD_MODTYPE_M 0x1f 2457 #define FW_PORT_CMD_MODTYPE_V(x) ((x) << FW_PORT_CMD_MODTYPE_S) 2458 #define FW_PORT_CMD_MODTYPE_G(x) \ 2459 (((x) >> FW_PORT_CMD_MODTYPE_S) & FW_PORT_CMD_MODTYPE_M) 2460 2461 #define FW_PORT_CMD_DCBXDIS_S 7 2462 #define FW_PORT_CMD_DCBXDIS_V(x) ((x) << FW_PORT_CMD_DCBXDIS_S) 2463 #define FW_PORT_CMD_DCBXDIS_F FW_PORT_CMD_DCBXDIS_V(1U) 2464 2465 #define FW_PORT_CMD_APPLY_S 7 2466 #define FW_PORT_CMD_APPLY_V(x) ((x) << FW_PORT_CMD_APPLY_S) 2467 #define FW_PORT_CMD_APPLY_F FW_PORT_CMD_APPLY_V(1U) 2468 2469 #define FW_PORT_CMD_ALL_SYNCD_S 7 2470 #define FW_PORT_CMD_ALL_SYNCD_V(x) ((x) << FW_PORT_CMD_ALL_SYNCD_S) 2471 #define FW_PORT_CMD_ALL_SYNCD_F FW_PORT_CMD_ALL_SYNCD_V(1U) 2472 2473 #define FW_PORT_CMD_DCB_VERSION_S 12 2474 #define FW_PORT_CMD_DCB_VERSION_M 0x7 2475 #define FW_PORT_CMD_DCB_VERSION_G(x) \ 2476 (((x) >> FW_PORT_CMD_DCB_VERSION_S) & FW_PORT_CMD_DCB_VERSION_M) 2477 2478 enum fw_port_type { 2479 FW_PORT_TYPE_FIBER_XFI, 2480 FW_PORT_TYPE_FIBER_XAUI, 2481 FW_PORT_TYPE_BT_SGMII, 2482 FW_PORT_TYPE_BT_XFI, 2483 FW_PORT_TYPE_BT_XAUI, 2484 FW_PORT_TYPE_KX4, 2485 FW_PORT_TYPE_CX4, 2486 FW_PORT_TYPE_KX, 2487 FW_PORT_TYPE_KR, 2488 FW_PORT_TYPE_SFP, 2489 FW_PORT_TYPE_BP_AP, 2490 FW_PORT_TYPE_BP4_AP, 2491 FW_PORT_TYPE_QSFP_10G, 2492 FW_PORT_TYPE_QSA, 2493 FW_PORT_TYPE_QSFP, 2494 FW_PORT_TYPE_BP40_BA, 2495 2496 FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_M 2497 }; 2498 2499 enum fw_port_module_type { 2500 FW_PORT_MOD_TYPE_NA, 2501 FW_PORT_MOD_TYPE_LR, 2502 FW_PORT_MOD_TYPE_SR, 2503 FW_PORT_MOD_TYPE_ER, 2504 FW_PORT_MOD_TYPE_TWINAX_PASSIVE, 2505 FW_PORT_MOD_TYPE_TWINAX_ACTIVE, 2506 FW_PORT_MOD_TYPE_LRM, 2507 FW_PORT_MOD_TYPE_ERROR = FW_PORT_CMD_MODTYPE_M - 3, 2508 FW_PORT_MOD_TYPE_UNKNOWN = FW_PORT_CMD_MODTYPE_M - 2, 2509 FW_PORT_MOD_TYPE_NOTSUPPORTED = FW_PORT_CMD_MODTYPE_M - 1, 2510 2511 FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_M 2512 }; 2513 2514 enum fw_port_mod_sub_type { 2515 FW_PORT_MOD_SUB_TYPE_NA, 2516 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1, 2517 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2, 2518 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3, 2519 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4, 2520 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5, 2521 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8, 2522 2523 /* The following will never been in the VPD. They are TWINAX cable 2524 * lengths decoded from SFP+ module i2c PROMs. These should 2525 * almost certainly go somewhere else ... 2526 */ 2527 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9, 2528 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA, 2529 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB, 2530 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC, 2531 }; 2532 2533 /* port stats */ 2534 #define FW_NUM_PORT_STATS 50 2535 #define FW_NUM_PORT_TX_STATS 23 2536 #define FW_NUM_PORT_RX_STATS 27 2537 2538 enum fw_port_stats_tx_index { 2539 FW_STAT_TX_PORT_BYTES_IX, 2540 FW_STAT_TX_PORT_FRAMES_IX, 2541 FW_STAT_TX_PORT_BCAST_IX, 2542 FW_STAT_TX_PORT_MCAST_IX, 2543 FW_STAT_TX_PORT_UCAST_IX, 2544 FW_STAT_TX_PORT_ERROR_IX, 2545 FW_STAT_TX_PORT_64B_IX, 2546 FW_STAT_TX_PORT_65B_127B_IX, 2547 FW_STAT_TX_PORT_128B_255B_IX, 2548 FW_STAT_TX_PORT_256B_511B_IX, 2549 FW_STAT_TX_PORT_512B_1023B_IX, 2550 FW_STAT_TX_PORT_1024B_1518B_IX, 2551 FW_STAT_TX_PORT_1519B_MAX_IX, 2552 FW_STAT_TX_PORT_DROP_IX, 2553 FW_STAT_TX_PORT_PAUSE_IX, 2554 FW_STAT_TX_PORT_PPP0_IX, 2555 FW_STAT_TX_PORT_PPP1_IX, 2556 FW_STAT_TX_PORT_PPP2_IX, 2557 FW_STAT_TX_PORT_PPP3_IX, 2558 FW_STAT_TX_PORT_PPP4_IX, 2559 FW_STAT_TX_PORT_PPP5_IX, 2560 FW_STAT_TX_PORT_PPP6_IX, 2561 FW_STAT_TX_PORT_PPP7_IX 2562 }; 2563 2564 enum fw_port_stat_rx_index { 2565 FW_STAT_RX_PORT_BYTES_IX, 2566 FW_STAT_RX_PORT_FRAMES_IX, 2567 FW_STAT_RX_PORT_BCAST_IX, 2568 FW_STAT_RX_PORT_MCAST_IX, 2569 FW_STAT_RX_PORT_UCAST_IX, 2570 FW_STAT_RX_PORT_MTU_ERROR_IX, 2571 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 2572 FW_STAT_RX_PORT_CRC_ERROR_IX, 2573 FW_STAT_RX_PORT_LEN_ERROR_IX, 2574 FW_STAT_RX_PORT_SYM_ERROR_IX, 2575 FW_STAT_RX_PORT_64B_IX, 2576 FW_STAT_RX_PORT_65B_127B_IX, 2577 FW_STAT_RX_PORT_128B_255B_IX, 2578 FW_STAT_RX_PORT_256B_511B_IX, 2579 FW_STAT_RX_PORT_512B_1023B_IX, 2580 FW_STAT_RX_PORT_1024B_1518B_IX, 2581 FW_STAT_RX_PORT_1519B_MAX_IX, 2582 FW_STAT_RX_PORT_PAUSE_IX, 2583 FW_STAT_RX_PORT_PPP0_IX, 2584 FW_STAT_RX_PORT_PPP1_IX, 2585 FW_STAT_RX_PORT_PPP2_IX, 2586 FW_STAT_RX_PORT_PPP3_IX, 2587 FW_STAT_RX_PORT_PPP4_IX, 2588 FW_STAT_RX_PORT_PPP5_IX, 2589 FW_STAT_RX_PORT_PPP6_IX, 2590 FW_STAT_RX_PORT_PPP7_IX, 2591 FW_STAT_RX_PORT_LESS_64B_IX 2592 }; 2593 2594 struct fw_port_stats_cmd { 2595 __be32 op_to_portid; 2596 __be32 retval_len16; 2597 union fw_port_stats { 2598 struct fw_port_stats_ctl { 2599 u8 nstats_bg_bm; 2600 u8 tx_ix; 2601 __be16 r6; 2602 __be32 r7; 2603 __be64 stat0; 2604 __be64 stat1; 2605 __be64 stat2; 2606 __be64 stat3; 2607 __be64 stat4; 2608 __be64 stat5; 2609 } ctl; 2610 struct fw_port_stats_all { 2611 __be64 tx_bytes; 2612 __be64 tx_frames; 2613 __be64 tx_bcast; 2614 __be64 tx_mcast; 2615 __be64 tx_ucast; 2616 __be64 tx_error; 2617 __be64 tx_64b; 2618 __be64 tx_65b_127b; 2619 __be64 tx_128b_255b; 2620 __be64 tx_256b_511b; 2621 __be64 tx_512b_1023b; 2622 __be64 tx_1024b_1518b; 2623 __be64 tx_1519b_max; 2624 __be64 tx_drop; 2625 __be64 tx_pause; 2626 __be64 tx_ppp0; 2627 __be64 tx_ppp1; 2628 __be64 tx_ppp2; 2629 __be64 tx_ppp3; 2630 __be64 tx_ppp4; 2631 __be64 tx_ppp5; 2632 __be64 tx_ppp6; 2633 __be64 tx_ppp7; 2634 __be64 rx_bytes; 2635 __be64 rx_frames; 2636 __be64 rx_bcast; 2637 __be64 rx_mcast; 2638 __be64 rx_ucast; 2639 __be64 rx_mtu_error; 2640 __be64 rx_mtu_crc_error; 2641 __be64 rx_crc_error; 2642 __be64 rx_len_error; 2643 __be64 rx_sym_error; 2644 __be64 rx_64b; 2645 __be64 rx_65b_127b; 2646 __be64 rx_128b_255b; 2647 __be64 rx_256b_511b; 2648 __be64 rx_512b_1023b; 2649 __be64 rx_1024b_1518b; 2650 __be64 rx_1519b_max; 2651 __be64 rx_pause; 2652 __be64 rx_ppp0; 2653 __be64 rx_ppp1; 2654 __be64 rx_ppp2; 2655 __be64 rx_ppp3; 2656 __be64 rx_ppp4; 2657 __be64 rx_ppp5; 2658 __be64 rx_ppp6; 2659 __be64 rx_ppp7; 2660 __be64 rx_less_64b; 2661 __be64 rx_bg_drop; 2662 __be64 rx_bg_trunc; 2663 } all; 2664 } u; 2665 }; 2666 2667 /* port loopback stats */ 2668 #define FW_NUM_LB_STATS 16 2669 enum fw_port_lb_stats_index { 2670 FW_STAT_LB_PORT_BYTES_IX, 2671 FW_STAT_LB_PORT_FRAMES_IX, 2672 FW_STAT_LB_PORT_BCAST_IX, 2673 FW_STAT_LB_PORT_MCAST_IX, 2674 FW_STAT_LB_PORT_UCAST_IX, 2675 FW_STAT_LB_PORT_ERROR_IX, 2676 FW_STAT_LB_PORT_64B_IX, 2677 FW_STAT_LB_PORT_65B_127B_IX, 2678 FW_STAT_LB_PORT_128B_255B_IX, 2679 FW_STAT_LB_PORT_256B_511B_IX, 2680 FW_STAT_LB_PORT_512B_1023B_IX, 2681 FW_STAT_LB_PORT_1024B_1518B_IX, 2682 FW_STAT_LB_PORT_1519B_MAX_IX, 2683 FW_STAT_LB_PORT_DROP_FRAMES_IX 2684 }; 2685 2686 struct fw_port_lb_stats_cmd { 2687 __be32 op_to_lbport; 2688 __be32 retval_len16; 2689 union fw_port_lb_stats { 2690 struct fw_port_lb_stats_ctl { 2691 u8 nstats_bg_bm; 2692 u8 ix_pkd; 2693 __be16 r6; 2694 __be32 r7; 2695 __be64 stat0; 2696 __be64 stat1; 2697 __be64 stat2; 2698 __be64 stat3; 2699 __be64 stat4; 2700 __be64 stat5; 2701 } ctl; 2702 struct fw_port_lb_stats_all { 2703 __be64 tx_bytes; 2704 __be64 tx_frames; 2705 __be64 tx_bcast; 2706 __be64 tx_mcast; 2707 __be64 tx_ucast; 2708 __be64 tx_error; 2709 __be64 tx_64b; 2710 __be64 tx_65b_127b; 2711 __be64 tx_128b_255b; 2712 __be64 tx_256b_511b; 2713 __be64 tx_512b_1023b; 2714 __be64 tx_1024b_1518b; 2715 __be64 tx_1519b_max; 2716 __be64 rx_lb_drop; 2717 __be64 rx_lb_trunc; 2718 } all; 2719 } u; 2720 }; 2721 2722 struct fw_rss_ind_tbl_cmd { 2723 __be32 op_to_viid; 2724 __be32 retval_len16; 2725 __be16 niqid; 2726 __be16 startidx; 2727 __be32 r3; 2728 __be32 iq0_to_iq2; 2729 __be32 iq3_to_iq5; 2730 __be32 iq6_to_iq8; 2731 __be32 iq9_to_iq11; 2732 __be32 iq12_to_iq14; 2733 __be32 iq15_to_iq17; 2734 __be32 iq18_to_iq20; 2735 __be32 iq21_to_iq23; 2736 __be32 iq24_to_iq26; 2737 __be32 iq27_to_iq29; 2738 __be32 iq30_iq31; 2739 __be32 r15_lo; 2740 }; 2741 2742 #define FW_RSS_IND_TBL_CMD_VIID_S 0 2743 #define FW_RSS_IND_TBL_CMD_VIID_V(x) ((x) << FW_RSS_IND_TBL_CMD_VIID_S) 2744 2745 #define FW_RSS_IND_TBL_CMD_IQ0_S 20 2746 #define FW_RSS_IND_TBL_CMD_IQ0_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ0_S) 2747 2748 #define FW_RSS_IND_TBL_CMD_IQ1_S 10 2749 #define FW_RSS_IND_TBL_CMD_IQ1_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ1_S) 2750 2751 #define FW_RSS_IND_TBL_CMD_IQ2_S 0 2752 #define FW_RSS_IND_TBL_CMD_IQ2_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ2_S) 2753 2754 struct fw_rss_glb_config_cmd { 2755 __be32 op_to_write; 2756 __be32 retval_len16; 2757 union fw_rss_glb_config { 2758 struct fw_rss_glb_config_manual { 2759 __be32 mode_pkd; 2760 __be32 r3; 2761 __be64 r4; 2762 __be64 r5; 2763 } manual; 2764 struct fw_rss_glb_config_basicvirtual { 2765 __be32 mode_pkd; 2766 __be32 synmapen_to_hashtoeplitz; 2767 __be64 r8; 2768 __be64 r9; 2769 } basicvirtual; 2770 } u; 2771 }; 2772 2773 #define FW_RSS_GLB_CONFIG_CMD_MODE_S 28 2774 #define FW_RSS_GLB_CONFIG_CMD_MODE_M 0xf 2775 #define FW_RSS_GLB_CONFIG_CMD_MODE_V(x) ((x) << FW_RSS_GLB_CONFIG_CMD_MODE_S) 2776 #define FW_RSS_GLB_CONFIG_CMD_MODE_G(x) \ 2777 (((x) >> FW_RSS_GLB_CONFIG_CMD_MODE_S) & FW_RSS_GLB_CONFIG_CMD_MODE_M) 2778 2779 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 2780 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 2781 2782 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S 8 2783 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(x) \ 2784 ((x) << FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S) 2785 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_F \ 2786 FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(1U) 2787 2788 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S 7 2789 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(x) \ 2790 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S) 2791 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_F \ 2792 FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(1U) 2793 2794 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S 6 2795 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(x) \ 2796 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S) 2797 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_F \ 2798 FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(1U) 2799 2800 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S 5 2801 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(x) \ 2802 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S) 2803 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_F \ 2804 FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(1U) 2805 2806 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S 4 2807 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(x) \ 2808 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S) 2809 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_F \ 2810 FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(1U) 2811 2812 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S 3 2813 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(x) \ 2814 ((x) << FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S) 2815 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_F \ 2816 FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(1U) 2817 2818 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S 2 2819 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(x) \ 2820 ((x) << FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S) 2821 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F \ 2822 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(1U) 2823 2824 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S 1 2825 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(x) \ 2826 ((x) << FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S) 2827 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F \ 2828 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(1U) 2829 2830 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S 0 2831 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(x) \ 2832 ((x) << FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S) 2833 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F \ 2834 FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(1U) 2835 2836 struct fw_rss_vi_config_cmd { 2837 __be32 op_to_viid; 2838 #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0) 2839 __be32 retval_len16; 2840 union fw_rss_vi_config { 2841 struct fw_rss_vi_config_manual { 2842 __be64 r3; 2843 __be64 r4; 2844 __be64 r5; 2845 } manual; 2846 struct fw_rss_vi_config_basicvirtual { 2847 __be32 r6; 2848 __be32 defaultq_to_udpen; 2849 __be64 r9; 2850 __be64 r10; 2851 } basicvirtual; 2852 } u; 2853 }; 2854 2855 #define FW_RSS_VI_CONFIG_CMD_VIID_S 0 2856 #define FW_RSS_VI_CONFIG_CMD_VIID_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_VIID_S) 2857 2858 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S 16 2859 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M 0x3ff 2860 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(x) \ 2861 ((x) << FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) 2862 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_G(x) \ 2863 (((x) >> FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) & \ 2864 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M) 2865 2866 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S 4 2867 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(x) \ 2868 ((x) << FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S) 2869 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F \ 2870 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(1U) 2871 2872 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S 3 2873 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(x) \ 2874 ((x) << FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S) 2875 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F \ 2876 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(1U) 2877 2878 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S 2 2879 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(x) \ 2880 ((x) << FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S) 2881 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F \ 2882 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(1U) 2883 2884 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S 1 2885 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(x) \ 2886 ((x) << FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S) 2887 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F \ 2888 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(1U) 2889 2890 #define FW_RSS_VI_CONFIG_CMD_UDPEN_S 0 2891 #define FW_RSS_VI_CONFIG_CMD_UDPEN_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_UDPEN_S) 2892 #define FW_RSS_VI_CONFIG_CMD_UDPEN_F FW_RSS_VI_CONFIG_CMD_UDPEN_V(1U) 2893 2894 struct fw_clip_cmd { 2895 __be32 op_to_write; 2896 __be32 alloc_to_len16; 2897 __be64 ip_hi; 2898 __be64 ip_lo; 2899 __be32 r4[2]; 2900 }; 2901 2902 #define FW_CLIP_CMD_ALLOC_S 31 2903 #define FW_CLIP_CMD_ALLOC_V(x) ((x) << FW_CLIP_CMD_ALLOC_S) 2904 #define FW_CLIP_CMD_ALLOC_F FW_CLIP_CMD_ALLOC_V(1U) 2905 2906 #define FW_CLIP_CMD_FREE_S 30 2907 #define FW_CLIP_CMD_FREE_V(x) ((x) << FW_CLIP_CMD_FREE_S) 2908 #define FW_CLIP_CMD_FREE_F FW_CLIP_CMD_FREE_V(1U) 2909 2910 enum fw_error_type { 2911 FW_ERROR_TYPE_EXCEPTION = 0x0, 2912 FW_ERROR_TYPE_HWMODULE = 0x1, 2913 FW_ERROR_TYPE_WR = 0x2, 2914 FW_ERROR_TYPE_ACL = 0x3, 2915 }; 2916 2917 struct fw_error_cmd { 2918 __be32 op_to_type; 2919 __be32 len16_pkd; 2920 union fw_error { 2921 struct fw_error_exception { 2922 __be32 info[6]; 2923 } exception; 2924 struct fw_error_hwmodule { 2925 __be32 regaddr; 2926 __be32 regval; 2927 } hwmodule; 2928 struct fw_error_wr { 2929 __be16 cidx; 2930 __be16 pfn_vfn; 2931 __be32 eqid; 2932 u8 wrhdr[16]; 2933 } wr; 2934 struct fw_error_acl { 2935 __be16 cidx; 2936 __be16 pfn_vfn; 2937 __be32 eqid; 2938 __be16 mv_pkd; 2939 u8 val[6]; 2940 __be64 r4; 2941 } acl; 2942 } u; 2943 }; 2944 2945 struct fw_debug_cmd { 2946 __be32 op_type; 2947 __be32 len16_pkd; 2948 union fw_debug { 2949 struct fw_debug_assert { 2950 __be32 fcid; 2951 __be32 line; 2952 __be32 x; 2953 __be32 y; 2954 u8 filename_0_7[8]; 2955 u8 filename_8_15[8]; 2956 __be64 r3; 2957 } assert; 2958 struct fw_debug_prt { 2959 __be16 dprtstridx; 2960 __be16 r3[3]; 2961 __be32 dprtstrparam0; 2962 __be32 dprtstrparam1; 2963 __be32 dprtstrparam2; 2964 __be32 dprtstrparam3; 2965 } prt; 2966 } u; 2967 }; 2968 2969 #define FW_DEBUG_CMD_TYPE_S 0 2970 #define FW_DEBUG_CMD_TYPE_M 0xff 2971 #define FW_DEBUG_CMD_TYPE_G(x) \ 2972 (((x) >> FW_DEBUG_CMD_TYPE_S) & FW_DEBUG_CMD_TYPE_M) 2973 2974 #define PCIE_FW_ERR_S 31 2975 #define PCIE_FW_ERR_V(x) ((x) << PCIE_FW_ERR_S) 2976 #define PCIE_FW_ERR_F PCIE_FW_ERR_V(1U) 2977 2978 #define PCIE_FW_INIT_S 30 2979 #define PCIE_FW_INIT_V(x) ((x) << PCIE_FW_INIT_S) 2980 #define PCIE_FW_INIT_F PCIE_FW_INIT_V(1U) 2981 2982 #define PCIE_FW_HALT_S 29 2983 #define PCIE_FW_HALT_V(x) ((x) << PCIE_FW_HALT_S) 2984 #define PCIE_FW_HALT_F PCIE_FW_HALT_V(1U) 2985 2986 #define PCIE_FW_EVAL_S 24 2987 #define PCIE_FW_EVAL_M 0x7 2988 #define PCIE_FW_EVAL_G(x) (((x) >> PCIE_FW_EVAL_S) & PCIE_FW_EVAL_M) 2989 2990 #define PCIE_FW_MASTER_VLD_S 15 2991 #define PCIE_FW_MASTER_VLD_V(x) ((x) << PCIE_FW_MASTER_VLD_S) 2992 #define PCIE_FW_MASTER_VLD_F PCIE_FW_MASTER_VLD_V(1U) 2993 2994 #define PCIE_FW_MASTER_S 12 2995 #define PCIE_FW_MASTER_M 0x7 2996 #define PCIE_FW_MASTER_V(x) ((x) << PCIE_FW_MASTER_S) 2997 #define PCIE_FW_MASTER_G(x) (((x) >> PCIE_FW_MASTER_S) & PCIE_FW_MASTER_M) 2998 2999 struct fw_hdr { 3000 u8 ver; 3001 u8 chip; /* terminator chip type */ 3002 __be16 len512; /* bin length in units of 512-bytes */ 3003 __be32 fw_ver; /* firmware version */ 3004 __be32 tp_microcode_ver; 3005 u8 intfver_nic; 3006 u8 intfver_vnic; 3007 u8 intfver_ofld; 3008 u8 intfver_ri; 3009 u8 intfver_iscsipdu; 3010 u8 intfver_iscsi; 3011 u8 intfver_fcoepdu; 3012 u8 intfver_fcoe; 3013 __u32 reserved2; 3014 __u32 reserved3; 3015 __u32 reserved4; 3016 __be32 flags; 3017 __be32 reserved6[23]; 3018 }; 3019 3020 enum fw_hdr_chip { 3021 FW_HDR_CHIP_T4, 3022 FW_HDR_CHIP_T5 3023 }; 3024 3025 #define FW_HDR_FW_VER_MAJOR_S 24 3026 #define FW_HDR_FW_VER_MAJOR_M 0xff 3027 #define FW_HDR_FW_VER_MAJOR_V(x) \ 3028 ((x) << FW_HDR_FW_VER_MAJOR_S) 3029 #define FW_HDR_FW_VER_MAJOR_G(x) \ 3030 (((x) >> FW_HDR_FW_VER_MAJOR_S) & FW_HDR_FW_VER_MAJOR_M) 3031 3032 #define FW_HDR_FW_VER_MINOR_S 16 3033 #define FW_HDR_FW_VER_MINOR_M 0xff 3034 #define FW_HDR_FW_VER_MINOR_V(x) \ 3035 ((x) << FW_HDR_FW_VER_MINOR_S) 3036 #define FW_HDR_FW_VER_MINOR_G(x) \ 3037 (((x) >> FW_HDR_FW_VER_MINOR_S) & FW_HDR_FW_VER_MINOR_M) 3038 3039 #define FW_HDR_FW_VER_MICRO_S 8 3040 #define FW_HDR_FW_VER_MICRO_M 0xff 3041 #define FW_HDR_FW_VER_MICRO_V(x) \ 3042 ((x) << FW_HDR_FW_VER_MICRO_S) 3043 #define FW_HDR_FW_VER_MICRO_G(x) \ 3044 (((x) >> FW_HDR_FW_VER_MICRO_S) & FW_HDR_FW_VER_MICRO_M) 3045 3046 #define FW_HDR_FW_VER_BUILD_S 0 3047 #define FW_HDR_FW_VER_BUILD_M 0xff 3048 #define FW_HDR_FW_VER_BUILD_V(x) \ 3049 ((x) << FW_HDR_FW_VER_BUILD_S) 3050 #define FW_HDR_FW_VER_BUILD_G(x) \ 3051 (((x) >> FW_HDR_FW_VER_BUILD_S) & FW_HDR_FW_VER_BUILD_M) 3052 3053 enum fw_hdr_intfver { 3054 FW_HDR_INTFVER_NIC = 0x00, 3055 FW_HDR_INTFVER_VNIC = 0x00, 3056 FW_HDR_INTFVER_OFLD = 0x00, 3057 FW_HDR_INTFVER_RI = 0x00, 3058 FW_HDR_INTFVER_ISCSIPDU = 0x00, 3059 FW_HDR_INTFVER_ISCSI = 0x00, 3060 FW_HDR_INTFVER_FCOEPDU = 0x00, 3061 FW_HDR_INTFVER_FCOE = 0x00, 3062 }; 3063 3064 enum fw_hdr_flags { 3065 FW_HDR_FLAGS_RESET_HALT = 0x00000001, 3066 }; 3067 3068 /* length of the formatting string */ 3069 #define FW_DEVLOG_FMT_LEN 192 3070 3071 /* maximum number of the formatting string parameters */ 3072 #define FW_DEVLOG_FMT_PARAMS_NUM 8 3073 3074 /* priority levels */ 3075 enum fw_devlog_level { 3076 FW_DEVLOG_LEVEL_EMERG = 0x0, 3077 FW_DEVLOG_LEVEL_CRIT = 0x1, 3078 FW_DEVLOG_LEVEL_ERR = 0x2, 3079 FW_DEVLOG_LEVEL_NOTICE = 0x3, 3080 FW_DEVLOG_LEVEL_INFO = 0x4, 3081 FW_DEVLOG_LEVEL_DEBUG = 0x5, 3082 FW_DEVLOG_LEVEL_MAX = 0x5, 3083 }; 3084 3085 /* facilities that may send a log message */ 3086 enum fw_devlog_facility { 3087 FW_DEVLOG_FACILITY_CORE = 0x00, 3088 FW_DEVLOG_FACILITY_CF = 0x01, 3089 FW_DEVLOG_FACILITY_SCHED = 0x02, 3090 FW_DEVLOG_FACILITY_TIMER = 0x04, 3091 FW_DEVLOG_FACILITY_RES = 0x06, 3092 FW_DEVLOG_FACILITY_HW = 0x08, 3093 FW_DEVLOG_FACILITY_FLR = 0x10, 3094 FW_DEVLOG_FACILITY_DMAQ = 0x12, 3095 FW_DEVLOG_FACILITY_PHY = 0x14, 3096 FW_DEVLOG_FACILITY_MAC = 0x16, 3097 FW_DEVLOG_FACILITY_PORT = 0x18, 3098 FW_DEVLOG_FACILITY_VI = 0x1A, 3099 FW_DEVLOG_FACILITY_FILTER = 0x1C, 3100 FW_DEVLOG_FACILITY_ACL = 0x1E, 3101 FW_DEVLOG_FACILITY_TM = 0x20, 3102 FW_DEVLOG_FACILITY_QFC = 0x22, 3103 FW_DEVLOG_FACILITY_DCB = 0x24, 3104 FW_DEVLOG_FACILITY_ETH = 0x26, 3105 FW_DEVLOG_FACILITY_OFLD = 0x28, 3106 FW_DEVLOG_FACILITY_RI = 0x2A, 3107 FW_DEVLOG_FACILITY_ISCSI = 0x2C, 3108 FW_DEVLOG_FACILITY_FCOE = 0x2E, 3109 FW_DEVLOG_FACILITY_FOISCSI = 0x30, 3110 FW_DEVLOG_FACILITY_FOFCOE = 0x32, 3111 FW_DEVLOG_FACILITY_CHNET = 0x34, 3112 FW_DEVLOG_FACILITY_MAX = 0x34, 3113 }; 3114 3115 /* log message format */ 3116 struct fw_devlog_e { 3117 __be64 timestamp; 3118 __be32 seqno; 3119 __be16 reserved1; 3120 __u8 level; 3121 __u8 facility; 3122 __u8 fmt[FW_DEVLOG_FMT_LEN]; 3123 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM]; 3124 __be32 reserved3[4]; 3125 }; 3126 3127 struct fw_devlog_cmd { 3128 __be32 op_to_write; 3129 __be32 retval_len16; 3130 __u8 level; 3131 __u8 r2[7]; 3132 __be32 memtype_devlog_memaddr16_devlog; 3133 __be32 memsize_devlog; 3134 __be32 r3[2]; 3135 }; 3136 3137 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S 28 3138 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M 0xf 3139 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(x) \ 3140 (((x) >> FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S) & \ 3141 FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M) 3142 3143 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S 0 3144 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M 0xfffffff 3145 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(x) \ 3146 (((x) >> FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S) & \ 3147 FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M) 3148 3149 /* P C I E F W P F 7 R E G I S T E R */ 3150 3151 /* PF7 stores the Firmware Device Log parameters which allows Host Drivers to 3152 * access the "devlog" which needing to contact firmware. The encoding is 3153 * mostly the same as that returned by the DEVLOG command except for the size 3154 * which is encoded as the number of entries in multiples-1 of 128 here rather 3155 * than the memory size as is done in the DEVLOG command. Thus, 0 means 128 3156 * and 15 means 2048. This of course in turn constrains the allowed values 3157 * for the devlog size ... 3158 */ 3159 #define PCIE_FW_PF_DEVLOG 7 3160 3161 #define PCIE_FW_PF_DEVLOG_NENTRIES128_S 28 3162 #define PCIE_FW_PF_DEVLOG_NENTRIES128_M 0xf 3163 #define PCIE_FW_PF_DEVLOG_NENTRIES128_V(x) \ 3164 ((x) << PCIE_FW_PF_DEVLOG_NENTRIES128_S) 3165 #define PCIE_FW_PF_DEVLOG_NENTRIES128_G(x) \ 3166 (((x) >> PCIE_FW_PF_DEVLOG_NENTRIES128_S) & \ 3167 PCIE_FW_PF_DEVLOG_NENTRIES128_M) 3168 3169 #define PCIE_FW_PF_DEVLOG_ADDR16_S 4 3170 #define PCIE_FW_PF_DEVLOG_ADDR16_M 0xffffff 3171 #define PCIE_FW_PF_DEVLOG_ADDR16_V(x) ((x) << PCIE_FW_PF_DEVLOG_ADDR16_S) 3172 #define PCIE_FW_PF_DEVLOG_ADDR16_G(x) \ 3173 (((x) >> PCIE_FW_PF_DEVLOG_ADDR16_S) & PCIE_FW_PF_DEVLOG_ADDR16_M) 3174 3175 #define PCIE_FW_PF_DEVLOG_MEMTYPE_S 0 3176 #define PCIE_FW_PF_DEVLOG_MEMTYPE_M 0xf 3177 #define PCIE_FW_PF_DEVLOG_MEMTYPE_V(x) ((x) << PCIE_FW_PF_DEVLOG_MEMTYPE_S) 3178 #define PCIE_FW_PF_DEVLOG_MEMTYPE_G(x) \ 3179 (((x) >> PCIE_FW_PF_DEVLOG_MEMTYPE_S) & PCIE_FW_PF_DEVLOG_MEMTYPE_M) 3180 3181 #endif /* _T4FW_INTERFACE_H_ */ 3182