1 /*
2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
3  *
4  * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
5  *
6  * This software is available to you under a choice of one of two
7  * licenses.  You may choose to be licensed under the terms of the GNU
8  * General Public License (GPL) Version 2, available from the file
9  * COPYING in the main directory of this source tree, or the
10  * OpenIB.org BSD license below:
11  *
12  *     Redistribution and use in source and binary forms, with or
13  *     without modification, are permitted provided that the following
14  *     conditions are met:
15  *
16  *      - Redistributions of source code must retain the above
17  *        copyright notice, this list of conditions and the following
18  *        disclaimer.
19  *
20  *      - Redistributions in binary form must reproduce the above
21  *        copyright notice, this list of conditions and the following
22  *        disclaimer in the documentation and/or other materials
23  *        provided with the distribution.
24  *
25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32  * SOFTWARE.
33  */
34 
35 #ifndef _T4FW_INTERFACE_H_
36 #define _T4FW_INTERFACE_H_
37 
38 enum fw_retval {
39 	FW_SUCCESS		= 0,	/* completed sucessfully */
40 	FW_EPERM		= 1,	/* operation not permitted */
41 	FW_ENOENT		= 2,	/* no such file or directory */
42 	FW_EIO			= 5,	/* input/output error; hw bad */
43 	FW_ENOEXEC		= 8,	/* exec format error; inv microcode */
44 	FW_EAGAIN		= 11,	/* try again */
45 	FW_ENOMEM		= 12,	/* out of memory */
46 	FW_EFAULT		= 14,	/* bad address; fw bad */
47 	FW_EBUSY		= 16,	/* resource busy */
48 	FW_EEXIST		= 17,	/* file exists */
49 	FW_EINVAL		= 22,	/* invalid argument */
50 	FW_ENOSPC		= 28,	/* no space left on device */
51 	FW_ENOSYS		= 38,	/* functionality not implemented */
52 	FW_EPROTO		= 71,	/* protocol error */
53 	FW_EADDRINUSE		= 98,	/* address already in use */
54 	FW_EADDRNOTAVAIL	= 99,	/* cannot assigned requested address */
55 	FW_ENETDOWN		= 100,	/* network is down */
56 	FW_ENETUNREACH		= 101,	/* network is unreachable */
57 	FW_ENOBUFS		= 105,	/* no buffer space available */
58 	FW_ETIMEDOUT		= 110,	/* timeout */
59 	FW_EINPROGRESS		= 115,	/* fw internal */
60 	FW_SCSI_ABORT_REQUESTED	= 128,	/* */
61 	FW_SCSI_ABORT_TIMEDOUT	= 129,	/* */
62 	FW_SCSI_ABORTED		= 130,	/* */
63 	FW_SCSI_CLOSE_REQUESTED	= 131,	/* */
64 	FW_ERR_LINK_DOWN	= 132,	/* */
65 	FW_RDEV_NOT_READY	= 133,	/* */
66 	FW_ERR_RDEV_LOST	= 134,	/* */
67 	FW_ERR_RDEV_LOGO	= 135,	/* */
68 	FW_FCOE_NO_XCHG		= 136,	/* */
69 	FW_SCSI_RSP_ERR		= 137,	/* */
70 	FW_ERR_RDEV_IMPL_LOGO	= 138,	/* */
71 	FW_SCSI_UNDER_FLOW_ERR  = 139,	/* */
72 	FW_SCSI_OVER_FLOW_ERR   = 140,	/* */
73 	FW_SCSI_DDP_ERR		= 141,	/* DDP error*/
74 	FW_SCSI_TASK_ERR	= 142,	/* No SCSI tasks available */
75 };
76 
77 #define FW_T4VF_SGE_BASE_ADDR      0x0000
78 #define FW_T4VF_MPS_BASE_ADDR      0x0100
79 #define FW_T4VF_PL_BASE_ADDR       0x0200
80 #define FW_T4VF_MBDATA_BASE_ADDR   0x0240
81 #define FW_T4VF_CIM_BASE_ADDR      0x0300
82 
83 enum fw_wr_opcodes {
84 	FW_FILTER_WR                   = 0x02,
85 	FW_ULPTX_WR                    = 0x04,
86 	FW_TP_WR                       = 0x05,
87 	FW_ETH_TX_PKT_WR               = 0x08,
88 	FW_OFLD_CONNECTION_WR          = 0x2f,
89 	FW_FLOWC_WR                    = 0x0a,
90 	FW_OFLD_TX_DATA_WR             = 0x0b,
91 	FW_CMD_WR                      = 0x10,
92 	FW_ETH_TX_PKT_VM_WR            = 0x11,
93 	FW_RI_RES_WR                   = 0x0c,
94 	FW_RI_INIT_WR                  = 0x0d,
95 	FW_RI_RDMA_WRITE_WR            = 0x14,
96 	FW_RI_SEND_WR                  = 0x15,
97 	FW_RI_RDMA_READ_WR             = 0x16,
98 	FW_RI_RECV_WR                  = 0x17,
99 	FW_RI_BIND_MW_WR               = 0x18,
100 	FW_RI_FR_NSMR_WR               = 0x19,
101 	FW_RI_INV_LSTAG_WR             = 0x1a,
102 	FW_LASTC2E_WR                  = 0x40
103 };
104 
105 struct fw_wr_hdr {
106 	__be32 hi;
107 	__be32 lo;
108 };
109 
110 #define FW_WR_OP(x)	 ((x) << 24)
111 #define FW_WR_OP_GET(x)	 (((x) >> 24) & 0xff)
112 #define FW_WR_ATOMIC(x)	 ((x) << 23)
113 #define FW_WR_FLUSH(x)   ((x) << 22)
114 #define FW_WR_COMPL(x)   ((x) << 21)
115 #define FW_WR_IMMDLEN_MASK 0xff
116 #define FW_WR_IMMDLEN(x) ((x) << 0)
117 
118 #define FW_WR_EQUIQ	(1U << 31)
119 #define FW_WR_EQUEQ	(1U << 30)
120 #define FW_WR_FLOWID(x)	((x) << 8)
121 #define FW_WR_LEN16(x)	((x) << 0)
122 
123 #define HW_TPL_FR_MT_PR_IV_P_FC         0X32B
124 #define HW_TPL_FR_MT_PR_OV_P_FC         0X327
125 
126 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
127 enum fw_filter_wr_cookie {
128 	FW_FILTER_WR_SUCCESS,
129 	FW_FILTER_WR_FLT_ADDED,
130 	FW_FILTER_WR_FLT_DELETED,
131 	FW_FILTER_WR_SMT_TBL_FULL,
132 	FW_FILTER_WR_EINVAL,
133 };
134 
135 struct fw_filter_wr {
136 	__be32 op_pkd;
137 	__be32 len16_pkd;
138 	__be64 r3;
139 	__be32 tid_to_iq;
140 	__be32 del_filter_to_l2tix;
141 	__be16 ethtype;
142 	__be16 ethtypem;
143 	__u8   frag_to_ovlan_vldm;
144 	__u8   smac_sel;
145 	__be16 rx_chan_rx_rpl_iq;
146 	__be32 maci_to_matchtypem;
147 	__u8   ptcl;
148 	__u8   ptclm;
149 	__u8   ttyp;
150 	__u8   ttypm;
151 	__be16 ivlan;
152 	__be16 ivlanm;
153 	__be16 ovlan;
154 	__be16 ovlanm;
155 	__u8   lip[16];
156 	__u8   lipm[16];
157 	__u8   fip[16];
158 	__u8   fipm[16];
159 	__be16 lp;
160 	__be16 lpm;
161 	__be16 fp;
162 	__be16 fpm;
163 	__be16 r7;
164 	__u8   sma[6];
165 };
166 
167 #define S_FW_FILTER_WR_TID      12
168 #define M_FW_FILTER_WR_TID      0xfffff
169 #define V_FW_FILTER_WR_TID(x)   ((x) << S_FW_FILTER_WR_TID)
170 #define G_FW_FILTER_WR_TID(x)   \
171 	(((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID)
172 
173 #define S_FW_FILTER_WR_RQTYPE           11
174 #define M_FW_FILTER_WR_RQTYPE           0x1
175 #define V_FW_FILTER_WR_RQTYPE(x)        ((x) << S_FW_FILTER_WR_RQTYPE)
176 #define G_FW_FILTER_WR_RQTYPE(x)        \
177 	(((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE)
178 #define F_FW_FILTER_WR_RQTYPE   V_FW_FILTER_WR_RQTYPE(1U)
179 
180 #define S_FW_FILTER_WR_NOREPLY          10
181 #define M_FW_FILTER_WR_NOREPLY          0x1
182 #define V_FW_FILTER_WR_NOREPLY(x)       ((x) << S_FW_FILTER_WR_NOREPLY)
183 #define G_FW_FILTER_WR_NOREPLY(x)       \
184 	(((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY)
185 #define F_FW_FILTER_WR_NOREPLY  V_FW_FILTER_WR_NOREPLY(1U)
186 
187 #define S_FW_FILTER_WR_IQ       0
188 #define M_FW_FILTER_WR_IQ       0x3ff
189 #define V_FW_FILTER_WR_IQ(x)    ((x) << S_FW_FILTER_WR_IQ)
190 #define G_FW_FILTER_WR_IQ(x)    \
191 	(((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ)
192 
193 #define S_FW_FILTER_WR_DEL_FILTER       31
194 #define M_FW_FILTER_WR_DEL_FILTER       0x1
195 #define V_FW_FILTER_WR_DEL_FILTER(x)    ((x) << S_FW_FILTER_WR_DEL_FILTER)
196 #define G_FW_FILTER_WR_DEL_FILTER(x)    \
197 	(((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER)
198 #define F_FW_FILTER_WR_DEL_FILTER       V_FW_FILTER_WR_DEL_FILTER(1U)
199 
200 #define S_FW_FILTER_WR_RPTTID           25
201 #define M_FW_FILTER_WR_RPTTID           0x1
202 #define V_FW_FILTER_WR_RPTTID(x)        ((x) << S_FW_FILTER_WR_RPTTID)
203 #define G_FW_FILTER_WR_RPTTID(x)        \
204 	(((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID)
205 #define F_FW_FILTER_WR_RPTTID   V_FW_FILTER_WR_RPTTID(1U)
206 
207 #define S_FW_FILTER_WR_DROP     24
208 #define M_FW_FILTER_WR_DROP     0x1
209 #define V_FW_FILTER_WR_DROP(x)  ((x) << S_FW_FILTER_WR_DROP)
210 #define G_FW_FILTER_WR_DROP(x)  \
211 	(((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP)
212 #define F_FW_FILTER_WR_DROP     V_FW_FILTER_WR_DROP(1U)
213 
214 #define S_FW_FILTER_WR_DIRSTEER         23
215 #define M_FW_FILTER_WR_DIRSTEER         0x1
216 #define V_FW_FILTER_WR_DIRSTEER(x)      ((x) << S_FW_FILTER_WR_DIRSTEER)
217 #define G_FW_FILTER_WR_DIRSTEER(x)      \
218 	(((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER)
219 #define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U)
220 
221 #define S_FW_FILTER_WR_MASKHASH         22
222 #define M_FW_FILTER_WR_MASKHASH         0x1
223 #define V_FW_FILTER_WR_MASKHASH(x)      ((x) << S_FW_FILTER_WR_MASKHASH)
224 #define G_FW_FILTER_WR_MASKHASH(x)      \
225 	(((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH)
226 #define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U)
227 
228 #define S_FW_FILTER_WR_DIRSTEERHASH     21
229 #define M_FW_FILTER_WR_DIRSTEERHASH     0x1
230 #define V_FW_FILTER_WR_DIRSTEERHASH(x)  ((x) << S_FW_FILTER_WR_DIRSTEERHASH)
231 #define G_FW_FILTER_WR_DIRSTEERHASH(x)  \
232 	(((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH)
233 #define F_FW_FILTER_WR_DIRSTEERHASH     V_FW_FILTER_WR_DIRSTEERHASH(1U)
234 
235 #define S_FW_FILTER_WR_LPBK     20
236 #define M_FW_FILTER_WR_LPBK     0x1
237 #define V_FW_FILTER_WR_LPBK(x)  ((x) << S_FW_FILTER_WR_LPBK)
238 #define G_FW_FILTER_WR_LPBK(x)  \
239 	(((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK)
240 #define F_FW_FILTER_WR_LPBK     V_FW_FILTER_WR_LPBK(1U)
241 
242 #define S_FW_FILTER_WR_DMAC     19
243 #define M_FW_FILTER_WR_DMAC     0x1
244 #define V_FW_FILTER_WR_DMAC(x)  ((x) << S_FW_FILTER_WR_DMAC)
245 #define G_FW_FILTER_WR_DMAC(x)  \
246 	(((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC)
247 #define F_FW_FILTER_WR_DMAC     V_FW_FILTER_WR_DMAC(1U)
248 
249 #define S_FW_FILTER_WR_SMAC     18
250 #define M_FW_FILTER_WR_SMAC     0x1
251 #define V_FW_FILTER_WR_SMAC(x)  ((x) << S_FW_FILTER_WR_SMAC)
252 #define G_FW_FILTER_WR_SMAC(x)  \
253 	(((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC)
254 #define F_FW_FILTER_WR_SMAC     V_FW_FILTER_WR_SMAC(1U)
255 
256 #define S_FW_FILTER_WR_INSVLAN          17
257 #define M_FW_FILTER_WR_INSVLAN          0x1
258 #define V_FW_FILTER_WR_INSVLAN(x)       ((x) << S_FW_FILTER_WR_INSVLAN)
259 #define G_FW_FILTER_WR_INSVLAN(x)       \
260 	(((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN)
261 #define F_FW_FILTER_WR_INSVLAN  V_FW_FILTER_WR_INSVLAN(1U)
262 
263 #define S_FW_FILTER_WR_RMVLAN           16
264 #define M_FW_FILTER_WR_RMVLAN           0x1
265 #define V_FW_FILTER_WR_RMVLAN(x)        ((x) << S_FW_FILTER_WR_RMVLAN)
266 #define G_FW_FILTER_WR_RMVLAN(x)        \
267 	(((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN)
268 #define F_FW_FILTER_WR_RMVLAN   V_FW_FILTER_WR_RMVLAN(1U)
269 
270 #define S_FW_FILTER_WR_HITCNTS          15
271 #define M_FW_FILTER_WR_HITCNTS          0x1
272 #define V_FW_FILTER_WR_HITCNTS(x)       ((x) << S_FW_FILTER_WR_HITCNTS)
273 #define G_FW_FILTER_WR_HITCNTS(x)       \
274 	(((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS)
275 #define F_FW_FILTER_WR_HITCNTS  V_FW_FILTER_WR_HITCNTS(1U)
276 
277 #define S_FW_FILTER_WR_TXCHAN           13
278 #define M_FW_FILTER_WR_TXCHAN           0x3
279 #define V_FW_FILTER_WR_TXCHAN(x)        ((x) << S_FW_FILTER_WR_TXCHAN)
280 #define G_FW_FILTER_WR_TXCHAN(x)        \
281 	(((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN)
282 
283 #define S_FW_FILTER_WR_PRIO     12
284 #define M_FW_FILTER_WR_PRIO     0x1
285 #define V_FW_FILTER_WR_PRIO(x)  ((x) << S_FW_FILTER_WR_PRIO)
286 #define G_FW_FILTER_WR_PRIO(x)  \
287 	(((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO)
288 #define F_FW_FILTER_WR_PRIO     V_FW_FILTER_WR_PRIO(1U)
289 
290 #define S_FW_FILTER_WR_L2TIX    0
291 #define M_FW_FILTER_WR_L2TIX    0xfff
292 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX)
293 #define G_FW_FILTER_WR_L2TIX(x) \
294 	(((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX)
295 
296 #define S_FW_FILTER_WR_FRAG     7
297 #define M_FW_FILTER_WR_FRAG     0x1
298 #define V_FW_FILTER_WR_FRAG(x)  ((x) << S_FW_FILTER_WR_FRAG)
299 #define G_FW_FILTER_WR_FRAG(x)  \
300 	(((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG)
301 #define F_FW_FILTER_WR_FRAG     V_FW_FILTER_WR_FRAG(1U)
302 
303 #define S_FW_FILTER_WR_FRAGM    6
304 #define M_FW_FILTER_WR_FRAGM    0x1
305 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM)
306 #define G_FW_FILTER_WR_FRAGM(x) \
307 	(((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM)
308 #define F_FW_FILTER_WR_FRAGM    V_FW_FILTER_WR_FRAGM(1U)
309 
310 #define S_FW_FILTER_WR_IVLAN_VLD        5
311 #define M_FW_FILTER_WR_IVLAN_VLD        0x1
312 #define V_FW_FILTER_WR_IVLAN_VLD(x)     ((x) << S_FW_FILTER_WR_IVLAN_VLD)
313 #define G_FW_FILTER_WR_IVLAN_VLD(x)     \
314 	(((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD)
315 #define F_FW_FILTER_WR_IVLAN_VLD        V_FW_FILTER_WR_IVLAN_VLD(1U)
316 
317 #define S_FW_FILTER_WR_OVLAN_VLD        4
318 #define M_FW_FILTER_WR_OVLAN_VLD        0x1
319 #define V_FW_FILTER_WR_OVLAN_VLD(x)     ((x) << S_FW_FILTER_WR_OVLAN_VLD)
320 #define G_FW_FILTER_WR_OVLAN_VLD(x)     \
321 	(((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD)
322 #define F_FW_FILTER_WR_OVLAN_VLD        V_FW_FILTER_WR_OVLAN_VLD(1U)
323 
324 #define S_FW_FILTER_WR_IVLAN_VLDM       3
325 #define M_FW_FILTER_WR_IVLAN_VLDM       0x1
326 #define V_FW_FILTER_WR_IVLAN_VLDM(x)    ((x) << S_FW_FILTER_WR_IVLAN_VLDM)
327 #define G_FW_FILTER_WR_IVLAN_VLDM(x)    \
328 	(((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM)
329 #define F_FW_FILTER_WR_IVLAN_VLDM       V_FW_FILTER_WR_IVLAN_VLDM(1U)
330 
331 #define S_FW_FILTER_WR_OVLAN_VLDM       2
332 #define M_FW_FILTER_WR_OVLAN_VLDM       0x1
333 #define V_FW_FILTER_WR_OVLAN_VLDM(x)    ((x) << S_FW_FILTER_WR_OVLAN_VLDM)
334 #define G_FW_FILTER_WR_OVLAN_VLDM(x)    \
335 	(((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM)
336 #define F_FW_FILTER_WR_OVLAN_VLDM       V_FW_FILTER_WR_OVLAN_VLDM(1U)
337 
338 #define S_FW_FILTER_WR_RX_CHAN          15
339 #define M_FW_FILTER_WR_RX_CHAN          0x1
340 #define V_FW_FILTER_WR_RX_CHAN(x)       ((x) << S_FW_FILTER_WR_RX_CHAN)
341 #define G_FW_FILTER_WR_RX_CHAN(x)       \
342 	(((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN)
343 #define F_FW_FILTER_WR_RX_CHAN  V_FW_FILTER_WR_RX_CHAN(1U)
344 
345 #define S_FW_FILTER_WR_RX_RPL_IQ        0
346 #define M_FW_FILTER_WR_RX_RPL_IQ        0x3ff
347 #define V_FW_FILTER_WR_RX_RPL_IQ(x)     ((x) << S_FW_FILTER_WR_RX_RPL_IQ)
348 #define G_FW_FILTER_WR_RX_RPL_IQ(x)     \
349 	(((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ)
350 
351 #define S_FW_FILTER_WR_MACI     23
352 #define M_FW_FILTER_WR_MACI     0x1ff
353 #define V_FW_FILTER_WR_MACI(x)  ((x) << S_FW_FILTER_WR_MACI)
354 #define G_FW_FILTER_WR_MACI(x)  \
355 	(((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI)
356 
357 #define S_FW_FILTER_WR_MACIM    14
358 #define M_FW_FILTER_WR_MACIM    0x1ff
359 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM)
360 #define G_FW_FILTER_WR_MACIM(x) \
361 	(((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM)
362 
363 #define S_FW_FILTER_WR_FCOE     13
364 #define M_FW_FILTER_WR_FCOE     0x1
365 #define V_FW_FILTER_WR_FCOE(x)  ((x) << S_FW_FILTER_WR_FCOE)
366 #define G_FW_FILTER_WR_FCOE(x)  \
367 	(((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE)
368 #define F_FW_FILTER_WR_FCOE     V_FW_FILTER_WR_FCOE(1U)
369 
370 #define S_FW_FILTER_WR_FCOEM    12
371 #define M_FW_FILTER_WR_FCOEM    0x1
372 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM)
373 #define G_FW_FILTER_WR_FCOEM(x) \
374 	(((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM)
375 #define F_FW_FILTER_WR_FCOEM    V_FW_FILTER_WR_FCOEM(1U)
376 
377 #define S_FW_FILTER_WR_PORT     9
378 #define M_FW_FILTER_WR_PORT     0x7
379 #define V_FW_FILTER_WR_PORT(x)  ((x) << S_FW_FILTER_WR_PORT)
380 #define G_FW_FILTER_WR_PORT(x)  \
381 	(((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT)
382 
383 #define S_FW_FILTER_WR_PORTM    6
384 #define M_FW_FILTER_WR_PORTM    0x7
385 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM)
386 #define G_FW_FILTER_WR_PORTM(x) \
387 	(((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM)
388 
389 #define S_FW_FILTER_WR_MATCHTYPE        3
390 #define M_FW_FILTER_WR_MATCHTYPE        0x7
391 #define V_FW_FILTER_WR_MATCHTYPE(x)     ((x) << S_FW_FILTER_WR_MATCHTYPE)
392 #define G_FW_FILTER_WR_MATCHTYPE(x)     \
393 	(((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE)
394 
395 #define S_FW_FILTER_WR_MATCHTYPEM       0
396 #define M_FW_FILTER_WR_MATCHTYPEM       0x7
397 #define V_FW_FILTER_WR_MATCHTYPEM(x)    ((x) << S_FW_FILTER_WR_MATCHTYPEM)
398 #define G_FW_FILTER_WR_MATCHTYPEM(x)    \
399 	(((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM)
400 
401 struct fw_ulptx_wr {
402 	__be32 op_to_compl;
403 	__be32 flowid_len16;
404 	u64 cookie;
405 };
406 
407 struct fw_tp_wr {
408 	__be32 op_to_immdlen;
409 	__be32 flowid_len16;
410 	u64 cookie;
411 };
412 
413 struct fw_eth_tx_pkt_wr {
414 	__be32 op_immdlen;
415 	__be32 equiq_to_len16;
416 	__be64 r3;
417 };
418 
419 struct fw_ofld_connection_wr {
420 	__be32 op_compl;
421 	__be32 len16_pkd;
422 	__u64  cookie;
423 	__be64 r2;
424 	__be64 r3;
425 	struct fw_ofld_connection_le {
426 		__be32 version_cpl;
427 		__be32 filter;
428 		__be32 r1;
429 		__be16 lport;
430 		__be16 pport;
431 		union fw_ofld_connection_leip {
432 			struct fw_ofld_connection_le_ipv4 {
433 				__be32 pip;
434 				__be32 lip;
435 				__be64 r0;
436 				__be64 r1;
437 				__be64 r2;
438 			} ipv4;
439 			struct fw_ofld_connection_le_ipv6 {
440 				__be64 pip_hi;
441 				__be64 pip_lo;
442 				__be64 lip_hi;
443 				__be64 lip_lo;
444 			} ipv6;
445 		} u;
446 	} le;
447 	struct fw_ofld_connection_tcb {
448 		__be32 t_state_to_astid;
449 		__be16 cplrxdataack_cplpassacceptrpl;
450 		__be16 rcv_adv;
451 		__be32 rcv_nxt;
452 		__be32 tx_max;
453 		__be64 opt0;
454 		__be32 opt2;
455 		__be32 r1;
456 		__be64 r2;
457 		__be64 r3;
458 	} tcb;
459 };
460 
461 #define S_FW_OFLD_CONNECTION_WR_VERSION                31
462 #define M_FW_OFLD_CONNECTION_WR_VERSION                0x1
463 #define V_FW_OFLD_CONNECTION_WR_VERSION(x)     \
464 	((x) << S_FW_OFLD_CONNECTION_WR_VERSION)
465 #define G_FW_OFLD_CONNECTION_WR_VERSION(x)     \
466 	(((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \
467 	M_FW_OFLD_CONNECTION_WR_VERSION)
468 #define F_FW_OFLD_CONNECTION_WR_VERSION        \
469 	V_FW_OFLD_CONNECTION_WR_VERSION(1U)
470 
471 #define S_FW_OFLD_CONNECTION_WR_CPL    30
472 #define M_FW_OFLD_CONNECTION_WR_CPL    0x1
473 #define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL)
474 #define G_FW_OFLD_CONNECTION_WR_CPL(x) \
475 	(((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL)
476 #define F_FW_OFLD_CONNECTION_WR_CPL    V_FW_OFLD_CONNECTION_WR_CPL(1U)
477 
478 #define S_FW_OFLD_CONNECTION_WR_T_STATE                28
479 #define M_FW_OFLD_CONNECTION_WR_T_STATE                0xf
480 #define V_FW_OFLD_CONNECTION_WR_T_STATE(x)     \
481 	((x) << S_FW_OFLD_CONNECTION_WR_T_STATE)
482 #define G_FW_OFLD_CONNECTION_WR_T_STATE(x)     \
483 	(((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \
484 	M_FW_OFLD_CONNECTION_WR_T_STATE)
485 
486 #define S_FW_OFLD_CONNECTION_WR_RCV_SCALE      24
487 #define M_FW_OFLD_CONNECTION_WR_RCV_SCALE      0xf
488 #define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x)   \
489 	((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE)
490 #define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x)   \
491 	(((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \
492 	M_FW_OFLD_CONNECTION_WR_RCV_SCALE)
493 
494 #define S_FW_OFLD_CONNECTION_WR_ASTID          0
495 #define M_FW_OFLD_CONNECTION_WR_ASTID          0xffffff
496 #define V_FW_OFLD_CONNECTION_WR_ASTID(x)       \
497 	((x) << S_FW_OFLD_CONNECTION_WR_ASTID)
498 #define G_FW_OFLD_CONNECTION_WR_ASTID(x)       \
499 	(((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID)
500 
501 #define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK   15
502 #define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK   0x1
503 #define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x)        \
504 	((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)
505 #define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x)        \
506 	(((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \
507 	M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)
508 #define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK   \
509 	V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U)
510 
511 #define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL       14
512 #define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL       0x1
513 #define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x)    \
514 	((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL)
515 #define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x)    \
516 	(((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \
517 	M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL)
518 #define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL       \
519 	V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U)
520 
521 enum fw_flowc_mnem {
522 	FW_FLOWC_MNEM_PFNVFN,		/* PFN [15:8] VFN [7:0] */
523 	FW_FLOWC_MNEM_CH,
524 	FW_FLOWC_MNEM_PORT,
525 	FW_FLOWC_MNEM_IQID,
526 	FW_FLOWC_MNEM_SNDNXT,
527 	FW_FLOWC_MNEM_RCVNXT,
528 	FW_FLOWC_MNEM_SNDBUF,
529 	FW_FLOWC_MNEM_MSS,
530 };
531 
532 struct fw_flowc_mnemval {
533 	u8 mnemonic;
534 	u8 r4[3];
535 	__be32 val;
536 };
537 
538 struct fw_flowc_wr {
539 	__be32 op_to_nparams;
540 #define FW_FLOWC_WR_NPARAMS(x)	((x) << 0)
541 	__be32 flowid_len16;
542 	struct fw_flowc_mnemval mnemval[0];
543 };
544 
545 struct fw_ofld_tx_data_wr {
546 	__be32 op_to_immdlen;
547 	__be32 flowid_len16;
548 	__be32 plen;
549 	__be32 tunnel_to_proxy;
550 #define FW_OFLD_TX_DATA_WR_TUNNEL(x)	 ((x) << 19)
551 #define FW_OFLD_TX_DATA_WR_SAVE(x)	 ((x) << 18)
552 #define FW_OFLD_TX_DATA_WR_FLUSH(x)	 ((x) << 17)
553 #define FW_OFLD_TX_DATA_WR_URGENT(x)	 ((x) << 16)
554 #define FW_OFLD_TX_DATA_WR_MORE(x)	 ((x) << 15)
555 #define FW_OFLD_TX_DATA_WR_SHOVE(x)	 ((x) << 14)
556 #define FW_OFLD_TX_DATA_WR_ULPMODE(x)	 ((x) << 10)
557 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) ((x) << 6)
558 };
559 
560 struct fw_cmd_wr {
561 	__be32 op_dma;
562 #define FW_CMD_WR_DMA (1U << 17)
563 	__be32 len16_pkd;
564 	__be64 cookie_daddr;
565 };
566 
567 struct fw_eth_tx_pkt_vm_wr {
568 	__be32 op_immdlen;
569 	__be32 equiq_to_len16;
570 	__be32 r3[2];
571 	u8 ethmacdst[6];
572 	u8 ethmacsrc[6];
573 	__be16 ethtype;
574 	__be16 vlantci;
575 };
576 
577 #define FW_CMD_MAX_TIMEOUT 10000
578 
579 /*
580  * If a host driver does a HELLO and discovers that there's already a MASTER
581  * selected, we may have to wait for that MASTER to finish issuing RESET,
582  * configuration and INITIALIZE commands.  Also, there's a possibility that
583  * our own HELLO may get lost if it happens right as the MASTER is issuign a
584  * RESET command, so we need to be willing to make a few retries of our HELLO.
585  */
586 #define FW_CMD_HELLO_TIMEOUT	(3 * FW_CMD_MAX_TIMEOUT)
587 #define FW_CMD_HELLO_RETRIES	3
588 
589 
590 enum fw_cmd_opcodes {
591 	FW_LDST_CMD                    = 0x01,
592 	FW_RESET_CMD                   = 0x03,
593 	FW_HELLO_CMD                   = 0x04,
594 	FW_BYE_CMD                     = 0x05,
595 	FW_INITIALIZE_CMD              = 0x06,
596 	FW_CAPS_CONFIG_CMD             = 0x07,
597 	FW_PARAMS_CMD                  = 0x08,
598 	FW_PFVF_CMD                    = 0x09,
599 	FW_IQ_CMD                      = 0x10,
600 	FW_EQ_MNGT_CMD                 = 0x11,
601 	FW_EQ_ETH_CMD                  = 0x12,
602 	FW_EQ_CTRL_CMD                 = 0x13,
603 	FW_EQ_OFLD_CMD                 = 0x21,
604 	FW_VI_CMD                      = 0x14,
605 	FW_VI_MAC_CMD                  = 0x15,
606 	FW_VI_RXMODE_CMD               = 0x16,
607 	FW_VI_ENABLE_CMD               = 0x17,
608 	FW_ACL_MAC_CMD                 = 0x18,
609 	FW_ACL_VLAN_CMD                = 0x19,
610 	FW_VI_STATS_CMD                = 0x1a,
611 	FW_PORT_CMD                    = 0x1b,
612 	FW_PORT_STATS_CMD              = 0x1c,
613 	FW_PORT_LB_STATS_CMD           = 0x1d,
614 	FW_PORT_TRACE_CMD              = 0x1e,
615 	FW_PORT_TRACE_MMAP_CMD         = 0x1f,
616 	FW_RSS_IND_TBL_CMD             = 0x20,
617 	FW_RSS_GLB_CONFIG_CMD          = 0x22,
618 	FW_RSS_VI_CONFIG_CMD           = 0x23,
619 	FW_CLIP_CMD                    = 0x28,
620 	FW_LASTC2E_CMD                 = 0x40,
621 	FW_ERROR_CMD                   = 0x80,
622 	FW_DEBUG_CMD                   = 0x81,
623 };
624 
625 enum fw_cmd_cap {
626 	FW_CMD_CAP_PF                  = 0x01,
627 	FW_CMD_CAP_DMAQ                = 0x02,
628 	FW_CMD_CAP_PORT                = 0x04,
629 	FW_CMD_CAP_PORTPROMISC         = 0x08,
630 	FW_CMD_CAP_PORTSTATS           = 0x10,
631 	FW_CMD_CAP_VF                  = 0x80,
632 };
633 
634 /*
635  * Generic command header flit0
636  */
637 struct fw_cmd_hdr {
638 	__be32 hi;
639 	__be32 lo;
640 };
641 
642 #define FW_CMD_OP(x)		((x) << 24)
643 #define FW_CMD_OP_GET(x)        (((x) >> 24) & 0xff)
644 #define FW_CMD_REQUEST          (1U << 23)
645 #define FW_CMD_REQUEST_GET(x)   (((x) >> 23) & 0x1)
646 #define FW_CMD_READ		(1U << 22)
647 #define FW_CMD_WRITE		(1U << 21)
648 #define FW_CMD_EXEC		(1U << 20)
649 #define FW_CMD_RAMASK(x)	((x) << 20)
650 #define FW_CMD_RETVAL(x)	((x) << 8)
651 #define FW_CMD_RETVAL_GET(x)	(((x) >> 8) & 0xff)
652 #define FW_CMD_LEN16(x)         ((x) << 0)
653 #define FW_LEN16(fw_struct)	FW_CMD_LEN16(sizeof(fw_struct) / 16)
654 
655 enum fw_ldst_addrspc {
656 	FW_LDST_ADDRSPC_FIRMWARE  = 0x0001,
657 	FW_LDST_ADDRSPC_SGE_EGRC  = 0x0008,
658 	FW_LDST_ADDRSPC_SGE_INGC  = 0x0009,
659 	FW_LDST_ADDRSPC_SGE_FLMC  = 0x000a,
660 	FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
661 	FW_LDST_ADDRSPC_TP_PIO    = 0x0010,
662 	FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
663 	FW_LDST_ADDRSPC_TP_MIB    = 0x0012,
664 	FW_LDST_ADDRSPC_MDIO      = 0x0018,
665 	FW_LDST_ADDRSPC_MPS       = 0x0020,
666 	FW_LDST_ADDRSPC_FUNC      = 0x0028,
667 	FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
668 };
669 
670 enum fw_ldst_mps_fid {
671 	FW_LDST_MPS_ATRB,
672 	FW_LDST_MPS_RPLC
673 };
674 
675 enum fw_ldst_func_access_ctl {
676 	FW_LDST_FUNC_ACC_CTL_VIID,
677 	FW_LDST_FUNC_ACC_CTL_FID
678 };
679 
680 enum fw_ldst_func_mod_index {
681 	FW_LDST_FUNC_MPS
682 };
683 
684 struct fw_ldst_cmd {
685 	__be32 op_to_addrspace;
686 #define FW_LDST_CMD_ADDRSPACE(x) ((x) << 0)
687 	__be32 cycles_to_len16;
688 	union fw_ldst {
689 		struct fw_ldst_addrval {
690 			__be32 addr;
691 			__be32 val;
692 		} addrval;
693 		struct fw_ldst_idctxt {
694 			__be32 physid;
695 			__be32 msg_pkd;
696 			__be32 ctxt_data7;
697 			__be32 ctxt_data6;
698 			__be32 ctxt_data5;
699 			__be32 ctxt_data4;
700 			__be32 ctxt_data3;
701 			__be32 ctxt_data2;
702 			__be32 ctxt_data1;
703 			__be32 ctxt_data0;
704 		} idctxt;
705 		struct fw_ldst_mdio {
706 			__be16 paddr_mmd;
707 			__be16 raddr;
708 			__be16 vctl;
709 			__be16 rval;
710 		} mdio;
711 		struct fw_ldst_mps {
712 			__be16 fid_ctl;
713 			__be16 rplcpf_pkd;
714 			__be32 rplc127_96;
715 			__be32 rplc95_64;
716 			__be32 rplc63_32;
717 			__be32 rplc31_0;
718 			__be32 atrb;
719 			__be16 vlan[16];
720 		} mps;
721 		struct fw_ldst_func {
722 			u8 access_ctl;
723 			u8 mod_index;
724 			__be16 ctl_id;
725 			__be32 offset;
726 			__be64 data0;
727 			__be64 data1;
728 		} func;
729 		struct fw_ldst_pcie {
730 			u8 ctrl_to_fn;
731 			u8 bnum;
732 			u8 r;
733 			u8 ext_r;
734 			u8 select_naccess;
735 			u8 pcie_fn;
736 			__be16 nset_pkd;
737 			__be32 data[12];
738 		} pcie;
739 	} u;
740 };
741 
742 #define FW_LDST_CMD_MSG(x)	((x) << 31)
743 #define FW_LDST_CMD_PADDR(x)	((x) << 8)
744 #define FW_LDST_CMD_MMD(x)	((x) << 0)
745 #define FW_LDST_CMD_FID(x)	((x) << 15)
746 #define FW_LDST_CMD_CTL(x)	((x) << 0)
747 #define FW_LDST_CMD_RPLCPF(x)	((x) << 0)
748 #define FW_LDST_CMD_LC		(1U << 4)
749 #define FW_LDST_CMD_NACCESS(x)	((x) << 0)
750 #define FW_LDST_CMD_FN(x)	((x) << 0)
751 
752 struct fw_reset_cmd {
753 	__be32 op_to_write;
754 	__be32 retval_len16;
755 	__be32 val;
756 	__be32 halt_pkd;
757 };
758 
759 #define FW_RESET_CMD_HALT_SHIFT    31
760 #define FW_RESET_CMD_HALT_MASK     0x1
761 #define FW_RESET_CMD_HALT(x)       ((x) << FW_RESET_CMD_HALT_SHIFT)
762 #define FW_RESET_CMD_HALT_GET(x)  \
763 	(((x) >> FW_RESET_CMD_HALT_SHIFT) & FW_RESET_CMD_HALT_MASK)
764 
765 enum fw_hellow_cmd {
766 	fw_hello_cmd_stage_os		= 0x0
767 };
768 
769 struct fw_hello_cmd {
770 	__be32 op_to_write;
771 	__be32 retval_len16;
772 	__be32 err_to_clearinit;
773 #define FW_HELLO_CMD_ERR	    (1U << 31)
774 #define FW_HELLO_CMD_INIT	    (1U << 30)
775 #define FW_HELLO_CMD_MASTERDIS(x)   ((x) << 29)
776 #define FW_HELLO_CMD_MASTERFORCE(x) ((x) << 28)
777 #define FW_HELLO_CMD_MBMASTER_MASK   0xfU
778 #define FW_HELLO_CMD_MBMASTER_SHIFT  24
779 #define FW_HELLO_CMD_MBMASTER(x)     ((x) << FW_HELLO_CMD_MBMASTER_SHIFT)
780 #define FW_HELLO_CMD_MBMASTER_GET(x) \
781 	(((x) >> FW_HELLO_CMD_MBMASTER_SHIFT) & FW_HELLO_CMD_MBMASTER_MASK)
782 #define FW_HELLO_CMD_MBASYNCNOTINT(x)	((x) << 23)
783 #define FW_HELLO_CMD_MBASYNCNOT(x)  ((x) << 20)
784 #define FW_HELLO_CMD_STAGE(x)       ((x) << 17)
785 #define FW_HELLO_CMD_CLEARINIT      (1U << 16)
786 	__be32 fwrev;
787 };
788 
789 struct fw_bye_cmd {
790 	__be32 op_to_write;
791 	__be32 retval_len16;
792 	__be64 r3;
793 };
794 
795 struct fw_initialize_cmd {
796 	__be32 op_to_write;
797 	__be32 retval_len16;
798 	__be64 r3;
799 };
800 
801 enum fw_caps_config_hm {
802 	FW_CAPS_CONFIG_HM_PCIE		= 0x00000001,
803 	FW_CAPS_CONFIG_HM_PL		= 0x00000002,
804 	FW_CAPS_CONFIG_HM_SGE		= 0x00000004,
805 	FW_CAPS_CONFIG_HM_CIM		= 0x00000008,
806 	FW_CAPS_CONFIG_HM_ULPTX		= 0x00000010,
807 	FW_CAPS_CONFIG_HM_TP		= 0x00000020,
808 	FW_CAPS_CONFIG_HM_ULPRX		= 0x00000040,
809 	FW_CAPS_CONFIG_HM_PMRX		= 0x00000080,
810 	FW_CAPS_CONFIG_HM_PMTX		= 0x00000100,
811 	FW_CAPS_CONFIG_HM_MC		= 0x00000200,
812 	FW_CAPS_CONFIG_HM_LE		= 0x00000400,
813 	FW_CAPS_CONFIG_HM_MPS		= 0x00000800,
814 	FW_CAPS_CONFIG_HM_XGMAC		= 0x00001000,
815 	FW_CAPS_CONFIG_HM_CPLSWITCH	= 0x00002000,
816 	FW_CAPS_CONFIG_HM_T4DBG		= 0x00004000,
817 	FW_CAPS_CONFIG_HM_MI		= 0x00008000,
818 	FW_CAPS_CONFIG_HM_I2CM		= 0x00010000,
819 	FW_CAPS_CONFIG_HM_NCSI		= 0x00020000,
820 	FW_CAPS_CONFIG_HM_SMB		= 0x00040000,
821 	FW_CAPS_CONFIG_HM_MA		= 0x00080000,
822 	FW_CAPS_CONFIG_HM_EDRAM		= 0x00100000,
823 	FW_CAPS_CONFIG_HM_PMU		= 0x00200000,
824 	FW_CAPS_CONFIG_HM_UART		= 0x00400000,
825 	FW_CAPS_CONFIG_HM_SF		= 0x00800000,
826 };
827 
828 enum fw_caps_config_nbm {
829 	FW_CAPS_CONFIG_NBM_IPMI		= 0x00000001,
830 	FW_CAPS_CONFIG_NBM_NCSI		= 0x00000002,
831 };
832 
833 enum fw_caps_config_link {
834 	FW_CAPS_CONFIG_LINK_PPP		= 0x00000001,
835 	FW_CAPS_CONFIG_LINK_QFC		= 0x00000002,
836 	FW_CAPS_CONFIG_LINK_DCBX	= 0x00000004,
837 };
838 
839 enum fw_caps_config_switch {
840 	FW_CAPS_CONFIG_SWITCH_INGRESS	= 0x00000001,
841 	FW_CAPS_CONFIG_SWITCH_EGRESS	= 0x00000002,
842 };
843 
844 enum fw_caps_config_nic {
845 	FW_CAPS_CONFIG_NIC		= 0x00000001,
846 	FW_CAPS_CONFIG_NIC_VM		= 0x00000002,
847 };
848 
849 enum fw_caps_config_ofld {
850 	FW_CAPS_CONFIG_OFLD		= 0x00000001,
851 };
852 
853 enum fw_caps_config_rdma {
854 	FW_CAPS_CONFIG_RDMA_RDDP	= 0x00000001,
855 	FW_CAPS_CONFIG_RDMA_RDMAC	= 0x00000002,
856 };
857 
858 enum fw_caps_config_iscsi {
859 	FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
860 	FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
861 	FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
862 	FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
863 };
864 
865 enum fw_caps_config_fcoe {
866 	FW_CAPS_CONFIG_FCOE_INITIATOR	= 0x00000001,
867 	FW_CAPS_CONFIG_FCOE_TARGET	= 0x00000002,
868 	FW_CAPS_CONFIG_FCOE_CTRL_OFLD	= 0x00000004,
869 };
870 
871 enum fw_memtype_cf {
872 	FW_MEMTYPE_CF_EDC0		= 0x0,
873 	FW_MEMTYPE_CF_EDC1		= 0x1,
874 	FW_MEMTYPE_CF_EXTMEM		= 0x2,
875 	FW_MEMTYPE_CF_FLASH		= 0x4,
876 	FW_MEMTYPE_CF_INTERNAL		= 0x5,
877 };
878 
879 struct fw_caps_config_cmd {
880 	__be32 op_to_write;
881 	__be32 cfvalid_to_len16;
882 	__be32 r2;
883 	__be32 hwmbitmap;
884 	__be16 nbmcaps;
885 	__be16 linkcaps;
886 	__be16 switchcaps;
887 	__be16 r3;
888 	__be16 niccaps;
889 	__be16 ofldcaps;
890 	__be16 rdmacaps;
891 	__be16 r4;
892 	__be16 iscsicaps;
893 	__be16 fcoecaps;
894 	__be32 cfcsum;
895 	__be32 finiver;
896 	__be32 finicsum;
897 };
898 
899 #define FW_CAPS_CONFIG_CMD_CFVALID          (1U << 27)
900 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x)    ((x) << 24)
901 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) ((x) << 16)
902 
903 /*
904  * params command mnemonics
905  */
906 enum fw_params_mnem {
907 	FW_PARAMS_MNEM_DEV		= 1,	/* device params */
908 	FW_PARAMS_MNEM_PFVF		= 2,	/* function params */
909 	FW_PARAMS_MNEM_REG		= 3,	/* limited register access */
910 	FW_PARAMS_MNEM_DMAQ		= 4,	/* dma queue params */
911 	FW_PARAMS_MNEM_LAST
912 };
913 
914 /*
915  * device parameters
916  */
917 enum fw_params_param_dev {
918 	FW_PARAMS_PARAM_DEV_CCLK	= 0x00, /* chip core clock in khz */
919 	FW_PARAMS_PARAM_DEV_PORTVEC	= 0x01, /* the port vector */
920 	FW_PARAMS_PARAM_DEV_NTID	= 0x02, /* reads the number of TIDs
921 						 * allocated by the device's
922 						 * Lookup Engine
923 						 */
924 	FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
925 	FW_PARAMS_PARAM_DEV_INTVER_NIC	= 0x04,
926 	FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05,
927 	FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06,
928 	FW_PARAMS_PARAM_DEV_INTVER_RI	= 0x07,
929 	FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08,
930 	FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09,
931 	FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A,
932 	FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
933 	FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
934 	FW_PARAMS_PARAM_DEV_CF = 0x0D,
935 };
936 
937 /*
938  * physical and virtual function parameters
939  */
940 enum fw_params_param_pfvf {
941 	FW_PARAMS_PARAM_PFVF_RWXCAPS	= 0x00,
942 	FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
943 	FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
944 	FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
945 	FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
946 	FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
947 	FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
948 	FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
949 	FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
950 	FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
951 	FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
952 	FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
953 	FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
954 	FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
955 	FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
956 	FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
957 	FW_PARAMS_PARAM_PFVF_RQ_END	= 0x10,
958 	FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
959 	FW_PARAMS_PARAM_PFVF_PBL_END	= 0x12,
960 	FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
961 	FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
962 	FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,
963 	FW_PARAMS_PARAM_PFVF_SQRQ_END	= 0x16,
964 	FW_PARAMS_PARAM_PFVF_CQ_START	= 0x17,
965 	FW_PARAMS_PARAM_PFVF_CQ_END	= 0x18,
966 	FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
967 	FW_PARAMS_PARAM_PFVF_VIID       = 0x24,
968 	FW_PARAMS_PARAM_PFVF_CPMASK     = 0x25,
969 	FW_PARAMS_PARAM_PFVF_OCQ_START  = 0x26,
970 	FW_PARAMS_PARAM_PFVF_OCQ_END    = 0x27,
971 	FW_PARAMS_PARAM_PFVF_CONM_MAP   = 0x28,
972 	FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29,
973 	FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A,
974 	FW_PARAMS_PARAM_PFVF_EQ_START	= 0x2B,
975 	FW_PARAMS_PARAM_PFVF_EQ_END	= 0x2C,
976 	FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
977 	FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,
978 	FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,
979 	FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31
980 };
981 
982 /*
983  * dma queue parameters
984  */
985 enum fw_params_param_dmaq {
986 	FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
987 	FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
988 	FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
989 	FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
990 	FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
991 };
992 
993 #define FW_PARAMS_MNEM(x)      ((x) << 24)
994 #define FW_PARAMS_PARAM_X(x)   ((x) << 16)
995 #define FW_PARAMS_PARAM_Y_SHIFT  8
996 #define FW_PARAMS_PARAM_Y_MASK   0xffU
997 #define FW_PARAMS_PARAM_Y(x)     ((x) << FW_PARAMS_PARAM_Y_SHIFT)
998 #define FW_PARAMS_PARAM_Y_GET(x) (((x) >> FW_PARAMS_PARAM_Y_SHIFT) &\
999 		FW_PARAMS_PARAM_Y_MASK)
1000 #define FW_PARAMS_PARAM_Z_SHIFT  0
1001 #define FW_PARAMS_PARAM_Z_MASK   0xffu
1002 #define FW_PARAMS_PARAM_Z(x)     ((x) << FW_PARAMS_PARAM_Z_SHIFT)
1003 #define FW_PARAMS_PARAM_Z_GET(x) (((x) >> FW_PARAMS_PARAM_Z_SHIFT) &\
1004 		FW_PARAMS_PARAM_Z_MASK)
1005 #define FW_PARAMS_PARAM_XYZ(x) ((x) << 0)
1006 #define FW_PARAMS_PARAM_YZ(x)  ((x) << 0)
1007 
1008 struct fw_params_cmd {
1009 	__be32 op_to_vfn;
1010 	__be32 retval_len16;
1011 	struct fw_params_param {
1012 		__be32 mnem;
1013 		__be32 val;
1014 	} param[7];
1015 };
1016 
1017 #define FW_PARAMS_CMD_PFN(x) ((x) << 8)
1018 #define FW_PARAMS_CMD_VFN(x) ((x) << 0)
1019 
1020 struct fw_pfvf_cmd {
1021 	__be32 op_to_vfn;
1022 	__be32 retval_len16;
1023 	__be32 niqflint_niq;
1024 	__be32 type_to_neq;
1025 	__be32 tc_to_nexactf;
1026 	__be32 r_caps_to_nethctrl;
1027 	__be16 nricq;
1028 	__be16 nriqp;
1029 	__be32 r4;
1030 };
1031 
1032 #define FW_PFVF_CMD_PFN(x) ((x) << 8)
1033 #define FW_PFVF_CMD_VFN(x) ((x) << 0)
1034 
1035 #define FW_PFVF_CMD_NIQFLINT(x) ((x) << 20)
1036 #define FW_PFVF_CMD_NIQFLINT_GET(x) (((x) >> 20) & 0xfff)
1037 
1038 #define FW_PFVF_CMD_NIQ(x) ((x) << 0)
1039 #define FW_PFVF_CMD_NIQ_GET(x) (((x) >> 0) & 0xfffff)
1040 
1041 #define FW_PFVF_CMD_TYPE (1 << 31)
1042 #define FW_PFVF_CMD_TYPE_GET(x) (((x) >> 31) & 0x1)
1043 
1044 #define FW_PFVF_CMD_CMASK(x) ((x) << 24)
1045 #define FW_PFVF_CMD_CMASK_MASK 0xf
1046 #define FW_PFVF_CMD_CMASK_GET(x) (((x) >> 24) & FW_PFVF_CMD_CMASK_MASK)
1047 
1048 #define FW_PFVF_CMD_PMASK(x) ((x) << 20)
1049 #define FW_PFVF_CMD_PMASK_MASK 0xf
1050 #define FW_PFVF_CMD_PMASK_GET(x) (((x) >> 20) & FW_PFVF_CMD_PMASK_MASK)
1051 
1052 #define FW_PFVF_CMD_NEQ(x) ((x) << 0)
1053 #define FW_PFVF_CMD_NEQ_GET(x) (((x) >> 0) & 0xfffff)
1054 
1055 #define FW_PFVF_CMD_TC(x) ((x) << 24)
1056 #define FW_PFVF_CMD_TC_GET(x) (((x) >> 24) & 0xff)
1057 
1058 #define FW_PFVF_CMD_NVI(x) ((x) << 16)
1059 #define FW_PFVF_CMD_NVI_GET(x) (((x) >> 16) & 0xff)
1060 
1061 #define FW_PFVF_CMD_NEXACTF(x) ((x) << 0)
1062 #define FW_PFVF_CMD_NEXACTF_GET(x) (((x) >> 0) & 0xffff)
1063 
1064 #define FW_PFVF_CMD_R_CAPS(x) ((x) << 24)
1065 #define FW_PFVF_CMD_R_CAPS_GET(x) (((x) >> 24) & 0xff)
1066 
1067 #define FW_PFVF_CMD_WX_CAPS(x) ((x) << 16)
1068 #define FW_PFVF_CMD_WX_CAPS_GET(x) (((x) >> 16) & 0xff)
1069 
1070 #define FW_PFVF_CMD_NETHCTRL(x) ((x) << 0)
1071 #define FW_PFVF_CMD_NETHCTRL_GET(x) (((x) >> 0) & 0xffff)
1072 
1073 enum fw_iq_type {
1074 	FW_IQ_TYPE_FL_INT_CAP,
1075 	FW_IQ_TYPE_NO_FL_INT_CAP
1076 };
1077 
1078 struct fw_iq_cmd {
1079 	__be32 op_to_vfn;
1080 	__be32 alloc_to_len16;
1081 	__be16 physiqid;
1082 	__be16 iqid;
1083 	__be16 fl0id;
1084 	__be16 fl1id;
1085 	__be32 type_to_iqandstindex;
1086 	__be16 iqdroprss_to_iqesize;
1087 	__be16 iqsize;
1088 	__be64 iqaddr;
1089 	__be32 iqns_to_fl0congen;
1090 	__be16 fl0dcaen_to_fl0cidxfthresh;
1091 	__be16 fl0size;
1092 	__be64 fl0addr;
1093 	__be32 fl1cngchmap_to_fl1congen;
1094 	__be16 fl1dcaen_to_fl1cidxfthresh;
1095 	__be16 fl1size;
1096 	__be64 fl1addr;
1097 };
1098 
1099 #define FW_IQ_CMD_PFN(x) ((x) << 8)
1100 #define FW_IQ_CMD_VFN(x) ((x) << 0)
1101 
1102 #define FW_IQ_CMD_ALLOC (1U << 31)
1103 #define FW_IQ_CMD_FREE (1U << 30)
1104 #define FW_IQ_CMD_MODIFY (1U << 29)
1105 #define FW_IQ_CMD_IQSTART(x) ((x) << 28)
1106 #define FW_IQ_CMD_IQSTOP(x) ((x) << 27)
1107 
1108 #define FW_IQ_CMD_TYPE(x) ((x) << 29)
1109 #define FW_IQ_CMD_IQASYNCH(x) ((x) << 28)
1110 #define FW_IQ_CMD_VIID(x) ((x) << 16)
1111 #define FW_IQ_CMD_IQANDST(x) ((x) << 15)
1112 #define FW_IQ_CMD_IQANUS(x) ((x) << 14)
1113 #define FW_IQ_CMD_IQANUD(x) ((x) << 12)
1114 #define FW_IQ_CMD_IQANDSTINDEX(x) ((x) << 0)
1115 
1116 #define FW_IQ_CMD_IQDROPRSS (1U << 15)
1117 #define FW_IQ_CMD_IQGTSMODE (1U << 14)
1118 #define FW_IQ_CMD_IQPCIECH(x) ((x) << 12)
1119 #define FW_IQ_CMD_IQDCAEN(x) ((x) << 11)
1120 #define FW_IQ_CMD_IQDCACPU(x) ((x) << 6)
1121 #define FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << 4)
1122 #define FW_IQ_CMD_IQO (1U << 3)
1123 #define FW_IQ_CMD_IQCPRIO(x) ((x) << 2)
1124 #define FW_IQ_CMD_IQESIZE(x) ((x) << 0)
1125 
1126 #define FW_IQ_CMD_IQNS(x) ((x) << 31)
1127 #define FW_IQ_CMD_IQRO(x) ((x) << 30)
1128 #define FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << 28)
1129 #define FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << 27)
1130 #define FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << 26)
1131 #define FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << 20)
1132 #define FW_IQ_CMD_FL0CACHELOCK(x) ((x) << 15)
1133 #define FW_IQ_CMD_FL0DBP(x) ((x) << 14)
1134 #define FW_IQ_CMD_FL0DATANS(x) ((x) << 13)
1135 #define FW_IQ_CMD_FL0DATARO(x) ((x) << 12)
1136 #define FW_IQ_CMD_FL0CONGCIF(x) ((x) << 11)
1137 #define FW_IQ_CMD_FL0ONCHIP(x) ((x) << 10)
1138 #define FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << 9)
1139 #define FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << 8)
1140 #define FW_IQ_CMD_FL0FETCHNS(x) ((x) << 7)
1141 #define FW_IQ_CMD_FL0FETCHRO(x) ((x) << 6)
1142 #define FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << 4)
1143 #define FW_IQ_CMD_FL0CPRIO(x) ((x) << 3)
1144 #define FW_IQ_CMD_FL0PADEN(x) ((x) << 2)
1145 #define FW_IQ_CMD_FL0PACKEN(x) ((x) << 1)
1146 #define FW_IQ_CMD_FL0CONGEN (1U << 0)
1147 
1148 #define FW_IQ_CMD_FL0DCAEN(x) ((x) << 15)
1149 #define FW_IQ_CMD_FL0DCACPU(x) ((x) << 10)
1150 #define FW_IQ_CMD_FL0FBMIN(x) ((x) << 7)
1151 #define FW_IQ_CMD_FL0FBMAX(x) ((x) << 4)
1152 #define FW_IQ_CMD_FL0CIDXFTHRESHO (1U << 3)
1153 #define FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << 0)
1154 
1155 #define FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << 20)
1156 #define FW_IQ_CMD_FL1CACHELOCK(x) ((x) << 15)
1157 #define FW_IQ_CMD_FL1DBP(x) ((x) << 14)
1158 #define FW_IQ_CMD_FL1DATANS(x) ((x) << 13)
1159 #define FW_IQ_CMD_FL1DATARO(x) ((x) << 12)
1160 #define FW_IQ_CMD_FL1CONGCIF(x) ((x) << 11)
1161 #define FW_IQ_CMD_FL1ONCHIP(x) ((x) << 10)
1162 #define FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << 9)
1163 #define FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << 8)
1164 #define FW_IQ_CMD_FL1FETCHNS(x) ((x) << 7)
1165 #define FW_IQ_CMD_FL1FETCHRO(x) ((x) << 6)
1166 #define FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << 4)
1167 #define FW_IQ_CMD_FL1CPRIO(x) ((x) << 3)
1168 #define FW_IQ_CMD_FL1PADEN (1U << 2)
1169 #define FW_IQ_CMD_FL1PACKEN (1U << 1)
1170 #define FW_IQ_CMD_FL1CONGEN (1U << 0)
1171 
1172 #define FW_IQ_CMD_FL1DCAEN(x) ((x) << 15)
1173 #define FW_IQ_CMD_FL1DCACPU(x) ((x) << 10)
1174 #define FW_IQ_CMD_FL1FBMIN(x) ((x) << 7)
1175 #define FW_IQ_CMD_FL1FBMAX(x) ((x) << 4)
1176 #define FW_IQ_CMD_FL1CIDXFTHRESHO (1U << 3)
1177 #define FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << 0)
1178 
1179 struct fw_eq_eth_cmd {
1180 	__be32 op_to_vfn;
1181 	__be32 alloc_to_len16;
1182 	__be32 eqid_pkd;
1183 	__be32 physeqid_pkd;
1184 	__be32 fetchszm_to_iqid;
1185 	__be32 dcaen_to_eqsize;
1186 	__be64 eqaddr;
1187 	__be32 viid_pkd;
1188 	__be32 r8_lo;
1189 	__be64 r9;
1190 };
1191 
1192 #define FW_EQ_ETH_CMD_PFN(x) ((x) << 8)
1193 #define FW_EQ_ETH_CMD_VFN(x) ((x) << 0)
1194 #define FW_EQ_ETH_CMD_ALLOC (1U << 31)
1195 #define FW_EQ_ETH_CMD_FREE (1U << 30)
1196 #define FW_EQ_ETH_CMD_MODIFY (1U << 29)
1197 #define FW_EQ_ETH_CMD_EQSTART (1U << 28)
1198 #define FW_EQ_ETH_CMD_EQSTOP (1U << 27)
1199 
1200 #define FW_EQ_ETH_CMD_EQID(x) ((x) << 0)
1201 #define FW_EQ_ETH_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff)
1202 #define FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << 0)
1203 #define FW_EQ_ETH_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff)
1204 
1205 #define FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << 26)
1206 #define FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << 25)
1207 #define FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << 24)
1208 #define FW_EQ_ETH_CMD_FETCHNS(x) ((x) << 23)
1209 #define FW_EQ_ETH_CMD_FETCHRO(x) ((x) << 22)
1210 #define FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << 20)
1211 #define FW_EQ_ETH_CMD_CPRIO(x) ((x) << 19)
1212 #define FW_EQ_ETH_CMD_ONCHIP(x) ((x) << 18)
1213 #define FW_EQ_ETH_CMD_PCIECHN(x) ((x) << 16)
1214 #define FW_EQ_ETH_CMD_IQID(x) ((x) << 0)
1215 
1216 #define FW_EQ_ETH_CMD_DCAEN(x) ((x) << 31)
1217 #define FW_EQ_ETH_CMD_DCACPU(x) ((x) << 26)
1218 #define FW_EQ_ETH_CMD_FBMIN(x) ((x) << 23)
1219 #define FW_EQ_ETH_CMD_FBMAX(x) ((x) << 20)
1220 #define FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << 19)
1221 #define FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << 16)
1222 #define FW_EQ_ETH_CMD_EQSIZE(x) ((x) << 0)
1223 
1224 #define FW_EQ_ETH_CMD_VIID(x) ((x) << 16)
1225 
1226 struct fw_eq_ctrl_cmd {
1227 	__be32 op_to_vfn;
1228 	__be32 alloc_to_len16;
1229 	__be32 cmpliqid_eqid;
1230 	__be32 physeqid_pkd;
1231 	__be32 fetchszm_to_iqid;
1232 	__be32 dcaen_to_eqsize;
1233 	__be64 eqaddr;
1234 };
1235 
1236 #define FW_EQ_CTRL_CMD_PFN(x) ((x) << 8)
1237 #define FW_EQ_CTRL_CMD_VFN(x) ((x) << 0)
1238 
1239 #define FW_EQ_CTRL_CMD_ALLOC (1U << 31)
1240 #define FW_EQ_CTRL_CMD_FREE (1U << 30)
1241 #define FW_EQ_CTRL_CMD_MODIFY (1U << 29)
1242 #define FW_EQ_CTRL_CMD_EQSTART (1U << 28)
1243 #define FW_EQ_CTRL_CMD_EQSTOP (1U << 27)
1244 
1245 #define FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << 20)
1246 #define FW_EQ_CTRL_CMD_EQID(x) ((x) << 0)
1247 #define FW_EQ_CTRL_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff)
1248 #define FW_EQ_CTRL_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff)
1249 
1250 #define FW_EQ_CTRL_CMD_FETCHSZM (1U << 26)
1251 #define FW_EQ_CTRL_CMD_STATUSPGNS (1U << 25)
1252 #define FW_EQ_CTRL_CMD_STATUSPGRO (1U << 24)
1253 #define FW_EQ_CTRL_CMD_FETCHNS (1U << 23)
1254 #define FW_EQ_CTRL_CMD_FETCHRO (1U << 22)
1255 #define FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << 20)
1256 #define FW_EQ_CTRL_CMD_CPRIO(x) ((x) << 19)
1257 #define FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << 18)
1258 #define FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << 16)
1259 #define FW_EQ_CTRL_CMD_IQID(x) ((x) << 0)
1260 
1261 #define FW_EQ_CTRL_CMD_DCAEN(x) ((x) << 31)
1262 #define FW_EQ_CTRL_CMD_DCACPU(x) ((x) << 26)
1263 #define FW_EQ_CTRL_CMD_FBMIN(x) ((x) << 23)
1264 #define FW_EQ_CTRL_CMD_FBMAX(x) ((x) << 20)
1265 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) ((x) << 19)
1266 #define FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << 16)
1267 #define FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << 0)
1268 
1269 struct fw_eq_ofld_cmd {
1270 	__be32 op_to_vfn;
1271 	__be32 alloc_to_len16;
1272 	__be32 eqid_pkd;
1273 	__be32 physeqid_pkd;
1274 	__be32 fetchszm_to_iqid;
1275 	__be32 dcaen_to_eqsize;
1276 	__be64 eqaddr;
1277 };
1278 
1279 #define FW_EQ_OFLD_CMD_PFN(x) ((x) << 8)
1280 #define FW_EQ_OFLD_CMD_VFN(x) ((x) << 0)
1281 
1282 #define FW_EQ_OFLD_CMD_ALLOC (1U << 31)
1283 #define FW_EQ_OFLD_CMD_FREE (1U << 30)
1284 #define FW_EQ_OFLD_CMD_MODIFY (1U << 29)
1285 #define FW_EQ_OFLD_CMD_EQSTART (1U << 28)
1286 #define FW_EQ_OFLD_CMD_EQSTOP (1U << 27)
1287 
1288 #define FW_EQ_OFLD_CMD_EQID(x) ((x) << 0)
1289 #define FW_EQ_OFLD_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff)
1290 #define FW_EQ_OFLD_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff)
1291 
1292 #define FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << 26)
1293 #define FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << 25)
1294 #define FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << 24)
1295 #define FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << 23)
1296 #define FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << 22)
1297 #define FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << 20)
1298 #define FW_EQ_OFLD_CMD_CPRIO(x) ((x) << 19)
1299 #define FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << 18)
1300 #define FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << 16)
1301 #define FW_EQ_OFLD_CMD_IQID(x) ((x) << 0)
1302 
1303 #define FW_EQ_OFLD_CMD_DCAEN(x) ((x) << 31)
1304 #define FW_EQ_OFLD_CMD_DCACPU(x) ((x) << 26)
1305 #define FW_EQ_OFLD_CMD_FBMIN(x) ((x) << 23)
1306 #define FW_EQ_OFLD_CMD_FBMAX(x) ((x) << 20)
1307 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) ((x) << 19)
1308 #define FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << 16)
1309 #define FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << 0)
1310 
1311 /*
1312  * Macros for VIID parsing:
1313  * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number
1314  */
1315 #define FW_VIID_PFN_GET(x) (((x) >> 8) & 0x7)
1316 #define FW_VIID_VIVLD_GET(x) (((x) >> 7) & 0x1)
1317 #define FW_VIID_VIN_GET(x) (((x) >> 0) & 0x7F)
1318 
1319 struct fw_vi_cmd {
1320 	__be32 op_to_vfn;
1321 	__be32 alloc_to_len16;
1322 	__be16 type_viid;
1323 	u8 mac[6];
1324 	u8 portid_pkd;
1325 	u8 nmac;
1326 	u8 nmac0[6];
1327 	__be16 rsssize_pkd;
1328 	u8 nmac1[6];
1329 	__be16 idsiiq_pkd;
1330 	u8 nmac2[6];
1331 	__be16 idseiq_pkd;
1332 	u8 nmac3[6];
1333 	__be64 r9;
1334 	__be64 r10;
1335 };
1336 
1337 #define FW_VI_CMD_PFN(x) ((x) << 8)
1338 #define FW_VI_CMD_VFN(x) ((x) << 0)
1339 #define FW_VI_CMD_ALLOC (1U << 31)
1340 #define FW_VI_CMD_FREE (1U << 30)
1341 #define FW_VI_CMD_VIID(x) ((x) << 0)
1342 #define FW_VI_CMD_VIID_GET(x) ((x) & 0xfff)
1343 #define FW_VI_CMD_PORTID(x) ((x) << 4)
1344 #define FW_VI_CMD_PORTID_GET(x) (((x) >> 4) & 0xf)
1345 #define FW_VI_CMD_RSSSIZE_GET(x) (((x) >> 0) & 0x7ff)
1346 
1347 /* Special VI_MAC command index ids */
1348 #define FW_VI_MAC_ADD_MAC		0x3FF
1349 #define FW_VI_MAC_ADD_PERSIST_MAC	0x3FE
1350 #define FW_VI_MAC_MAC_BASED_FREE	0x3FD
1351 #define FW_CLS_TCAM_NUM_ENTRIES		336
1352 
1353 enum fw_vi_mac_smac {
1354 	FW_VI_MAC_MPS_TCAM_ENTRY,
1355 	FW_VI_MAC_MPS_TCAM_ONLY,
1356 	FW_VI_MAC_SMT_ONLY,
1357 	FW_VI_MAC_SMT_AND_MPSTCAM
1358 };
1359 
1360 enum fw_vi_mac_result {
1361 	FW_VI_MAC_R_SUCCESS,
1362 	FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
1363 	FW_VI_MAC_R_SMAC_FAIL,
1364 	FW_VI_MAC_R_F_ACL_CHECK
1365 };
1366 
1367 struct fw_vi_mac_cmd {
1368 	__be32 op_to_viid;
1369 	__be32 freemacs_to_len16;
1370 	union fw_vi_mac {
1371 		struct fw_vi_mac_exact {
1372 			__be16 valid_to_idx;
1373 			u8 macaddr[6];
1374 		} exact[7];
1375 		struct fw_vi_mac_hash {
1376 			__be64 hashvec;
1377 		} hash;
1378 	} u;
1379 };
1380 
1381 #define FW_VI_MAC_CMD_VIID(x) ((x) << 0)
1382 #define FW_VI_MAC_CMD_FREEMACS(x) ((x) << 31)
1383 #define FW_VI_MAC_CMD_HASHVECEN (1U << 23)
1384 #define FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << 22)
1385 #define FW_VI_MAC_CMD_VALID (1U << 15)
1386 #define FW_VI_MAC_CMD_PRIO(x) ((x) << 12)
1387 #define FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << 10)
1388 #define FW_VI_MAC_CMD_SMAC_RESULT_GET(x) (((x) >> 10) & 0x3)
1389 #define FW_VI_MAC_CMD_IDX(x) ((x) << 0)
1390 #define FW_VI_MAC_CMD_IDX_GET(x) (((x) >> 0) & 0x3ff)
1391 
1392 #define FW_RXMODE_MTU_NO_CHG	65535
1393 
1394 struct fw_vi_rxmode_cmd {
1395 	__be32 op_to_viid;
1396 	__be32 retval_len16;
1397 	__be32 mtu_to_vlanexen;
1398 	__be32 r4_lo;
1399 };
1400 
1401 #define FW_VI_RXMODE_CMD_VIID(x) ((x) << 0)
1402 #define FW_VI_RXMODE_CMD_MTU_MASK 0xffff
1403 #define FW_VI_RXMODE_CMD_MTU(x) ((x) << 16)
1404 #define FW_VI_RXMODE_CMD_PROMISCEN_MASK 0x3
1405 #define FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << 14)
1406 #define FW_VI_RXMODE_CMD_ALLMULTIEN_MASK 0x3
1407 #define FW_VI_RXMODE_CMD_ALLMULTIEN(x) ((x) << 12)
1408 #define FW_VI_RXMODE_CMD_BROADCASTEN_MASK 0x3
1409 #define FW_VI_RXMODE_CMD_BROADCASTEN(x) ((x) << 10)
1410 #define FW_VI_RXMODE_CMD_VLANEXEN_MASK 0x3
1411 #define FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << 8)
1412 
1413 struct fw_vi_enable_cmd {
1414 	__be32 op_to_viid;
1415 	__be32 ien_to_len16;
1416 	__be16 blinkdur;
1417 	__be16 r3;
1418 	__be32 r4;
1419 };
1420 
1421 #define FW_VI_ENABLE_CMD_VIID(x) ((x) << 0)
1422 #define FW_VI_ENABLE_CMD_IEN(x) ((x) << 31)
1423 #define FW_VI_ENABLE_CMD_EEN(x) ((x) << 30)
1424 #define FW_VI_ENABLE_CMD_LED (1U << 29)
1425 
1426 /* VI VF stats offset definitions */
1427 #define VI_VF_NUM_STATS	16
1428 enum fw_vi_stats_vf_index {
1429 	FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
1430 	FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
1431 	FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
1432 	FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
1433 	FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
1434 	FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
1435 	FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
1436 	FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
1437 	FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
1438 	FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
1439 	FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
1440 	FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
1441 	FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
1442 	FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
1443 	FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
1444 	FW_VI_VF_STAT_RX_ERR_FRAMES_IX
1445 };
1446 
1447 /* VI PF stats offset definitions */
1448 #define VI_PF_NUM_STATS	17
1449 enum fw_vi_stats_pf_index {
1450 	FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
1451 	FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
1452 	FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
1453 	FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
1454 	FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
1455 	FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
1456 	FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
1457 	FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
1458 	FW_VI_PF_STAT_RX_BYTES_IX,
1459 	FW_VI_PF_STAT_RX_FRAMES_IX,
1460 	FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
1461 	FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
1462 	FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
1463 	FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
1464 	FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
1465 	FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
1466 	FW_VI_PF_STAT_RX_ERR_FRAMES_IX
1467 };
1468 
1469 struct fw_vi_stats_cmd {
1470 	__be32 op_to_viid;
1471 	__be32 retval_len16;
1472 	union fw_vi_stats {
1473 		struct fw_vi_stats_ctl {
1474 			__be16 nstats_ix;
1475 			__be16 r6;
1476 			__be32 r7;
1477 			__be64 stat0;
1478 			__be64 stat1;
1479 			__be64 stat2;
1480 			__be64 stat3;
1481 			__be64 stat4;
1482 			__be64 stat5;
1483 		} ctl;
1484 		struct fw_vi_stats_pf {
1485 			__be64 tx_bcast_bytes;
1486 			__be64 tx_bcast_frames;
1487 			__be64 tx_mcast_bytes;
1488 			__be64 tx_mcast_frames;
1489 			__be64 tx_ucast_bytes;
1490 			__be64 tx_ucast_frames;
1491 			__be64 tx_offload_bytes;
1492 			__be64 tx_offload_frames;
1493 			__be64 rx_pf_bytes;
1494 			__be64 rx_pf_frames;
1495 			__be64 rx_bcast_bytes;
1496 			__be64 rx_bcast_frames;
1497 			__be64 rx_mcast_bytes;
1498 			__be64 rx_mcast_frames;
1499 			__be64 rx_ucast_bytes;
1500 			__be64 rx_ucast_frames;
1501 			__be64 rx_err_frames;
1502 		} pf;
1503 		struct fw_vi_stats_vf {
1504 			__be64 tx_bcast_bytes;
1505 			__be64 tx_bcast_frames;
1506 			__be64 tx_mcast_bytes;
1507 			__be64 tx_mcast_frames;
1508 			__be64 tx_ucast_bytes;
1509 			__be64 tx_ucast_frames;
1510 			__be64 tx_drop_frames;
1511 			__be64 tx_offload_bytes;
1512 			__be64 tx_offload_frames;
1513 			__be64 rx_bcast_bytes;
1514 			__be64 rx_bcast_frames;
1515 			__be64 rx_mcast_bytes;
1516 			__be64 rx_mcast_frames;
1517 			__be64 rx_ucast_bytes;
1518 			__be64 rx_ucast_frames;
1519 			__be64 rx_err_frames;
1520 		} vf;
1521 	} u;
1522 };
1523 
1524 #define FW_VI_STATS_CMD_VIID(x) ((x) << 0)
1525 #define FW_VI_STATS_CMD_NSTATS(x) ((x) << 12)
1526 #define FW_VI_STATS_CMD_IX(x) ((x) << 0)
1527 
1528 struct fw_acl_mac_cmd {
1529 	__be32 op_to_vfn;
1530 	__be32 en_to_len16;
1531 	u8 nmac;
1532 	u8 r3[7];
1533 	__be16 r4;
1534 	u8 macaddr0[6];
1535 	__be16 r5;
1536 	u8 macaddr1[6];
1537 	__be16 r6;
1538 	u8 macaddr2[6];
1539 	__be16 r7;
1540 	u8 macaddr3[6];
1541 };
1542 
1543 #define FW_ACL_MAC_CMD_PFN(x) ((x) << 8)
1544 #define FW_ACL_MAC_CMD_VFN(x) ((x) << 0)
1545 #define FW_ACL_MAC_CMD_EN(x) ((x) << 31)
1546 
1547 struct fw_acl_vlan_cmd {
1548 	__be32 op_to_vfn;
1549 	__be32 en_to_len16;
1550 	u8 nvlan;
1551 	u8 dropnovlan_fm;
1552 	u8 r3_lo[6];
1553 	__be16 vlanid[16];
1554 };
1555 
1556 #define FW_ACL_VLAN_CMD_PFN(x) ((x) << 8)
1557 #define FW_ACL_VLAN_CMD_VFN(x) ((x) << 0)
1558 #define FW_ACL_VLAN_CMD_EN(x) ((x) << 31)
1559 #define FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << 7)
1560 #define FW_ACL_VLAN_CMD_FM(x) ((x) << 6)
1561 
1562 enum fw_port_cap {
1563 	FW_PORT_CAP_SPEED_100M		= 0x0001,
1564 	FW_PORT_CAP_SPEED_1G		= 0x0002,
1565 	FW_PORT_CAP_SPEED_2_5G		= 0x0004,
1566 	FW_PORT_CAP_SPEED_10G		= 0x0008,
1567 	FW_PORT_CAP_SPEED_40G		= 0x0010,
1568 	FW_PORT_CAP_SPEED_100G		= 0x0020,
1569 	FW_PORT_CAP_FC_RX		= 0x0040,
1570 	FW_PORT_CAP_FC_TX		= 0x0080,
1571 	FW_PORT_CAP_ANEG		= 0x0100,
1572 	FW_PORT_CAP_MDI_0		= 0x0200,
1573 	FW_PORT_CAP_MDI_1		= 0x0400,
1574 	FW_PORT_CAP_BEAN		= 0x0800,
1575 	FW_PORT_CAP_PMA_LPBK		= 0x1000,
1576 	FW_PORT_CAP_PCS_LPBK		= 0x2000,
1577 	FW_PORT_CAP_PHYXS_LPBK		= 0x4000,
1578 	FW_PORT_CAP_FAR_END_LPBK	= 0x8000,
1579 };
1580 
1581 enum fw_port_mdi {
1582 	FW_PORT_MDI_UNCHANGED,
1583 	FW_PORT_MDI_AUTO,
1584 	FW_PORT_MDI_F_STRAIGHT,
1585 	FW_PORT_MDI_F_CROSSOVER
1586 };
1587 
1588 #define FW_PORT_MDI(x) ((x) << 9)
1589 
1590 enum fw_port_action {
1591 	FW_PORT_ACTION_L1_CFG		= 0x0001,
1592 	FW_PORT_ACTION_L2_CFG		= 0x0002,
1593 	FW_PORT_ACTION_GET_PORT_INFO	= 0x0003,
1594 	FW_PORT_ACTION_L2_PPP_CFG	= 0x0004,
1595 	FW_PORT_ACTION_L2_DCB_CFG	= 0x0005,
1596 	FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
1597 	FW_PORT_ACTION_L1_LOW_PWR_EN	= 0x0011,
1598 	FW_PORT_ACTION_L2_WOL_MODE_EN	= 0x0012,
1599 	FW_PORT_ACTION_LPBK_TO_NORMAL	= 0x0020,
1600 	FW_PORT_ACTION_L1_LPBK		= 0x0021,
1601 	FW_PORT_ACTION_L1_PMA_LPBK	= 0x0022,
1602 	FW_PORT_ACTION_L1_PCS_LPBK	= 0x0023,
1603 	FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024,
1604 	FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025,
1605 	FW_PORT_ACTION_PHY_RESET	= 0x0040,
1606 	FW_PORT_ACTION_PMA_RESET	= 0x0041,
1607 	FW_PORT_ACTION_PCS_RESET	= 0x0042,
1608 	FW_PORT_ACTION_PHYXS_RESET	= 0x0043,
1609 	FW_PORT_ACTION_DTEXS_REEST	= 0x0044,
1610 	FW_PORT_ACTION_AN_RESET		= 0x0045
1611 };
1612 
1613 enum fw_port_l2cfg_ctlbf {
1614 	FW_PORT_L2_CTLBF_OVLAN0	= 0x01,
1615 	FW_PORT_L2_CTLBF_OVLAN1	= 0x02,
1616 	FW_PORT_L2_CTLBF_OVLAN2	= 0x04,
1617 	FW_PORT_L2_CTLBF_OVLAN3	= 0x08,
1618 	FW_PORT_L2_CTLBF_IVLAN	= 0x10,
1619 	FW_PORT_L2_CTLBF_TXIPG	= 0x20
1620 };
1621 
1622 enum fw_port_dcb_cfg {
1623 	FW_PORT_DCB_CFG_PG	= 0x01,
1624 	FW_PORT_DCB_CFG_PFC	= 0x02,
1625 	FW_PORT_DCB_CFG_APPL	= 0x04
1626 };
1627 
1628 enum fw_port_dcb_cfg_rc {
1629 	FW_PORT_DCB_CFG_SUCCESS	= 0x0,
1630 	FW_PORT_DCB_CFG_ERROR	= 0x1
1631 };
1632 
1633 enum fw_port_dcb_type {
1634 	FW_PORT_DCB_TYPE_PGID		= 0x00,
1635 	FW_PORT_DCB_TYPE_PGRATE		= 0x01,
1636 	FW_PORT_DCB_TYPE_PRIORATE	= 0x02,
1637 	FW_PORT_DCB_TYPE_PFC		= 0x03,
1638 	FW_PORT_DCB_TYPE_APP_ID		= 0x04,
1639 };
1640 
1641 struct fw_port_cmd {
1642 	__be32 op_to_portid;
1643 	__be32 action_to_len16;
1644 	union fw_port {
1645 		struct fw_port_l1cfg {
1646 			__be32 rcap;
1647 			__be32 r;
1648 		} l1cfg;
1649 		struct fw_port_l2cfg {
1650 			__be16 ctlbf_to_ivlan0;
1651 			__be16 ivlantype;
1652 			__be32 txipg_pkd;
1653 			__be16 ovlan0mask;
1654 			__be16 ovlan0type;
1655 			__be16 ovlan1mask;
1656 			__be16 ovlan1type;
1657 			__be16 ovlan2mask;
1658 			__be16 ovlan2type;
1659 			__be16 ovlan3mask;
1660 			__be16 ovlan3type;
1661 		} l2cfg;
1662 		struct fw_port_info {
1663 			__be32 lstatus_to_modtype;
1664 			__be16 pcap;
1665 			__be16 acap;
1666 			__be16 mtu;
1667 			__u8   cbllen;
1668 			__u8   r9;
1669 			__be32 r10;
1670 			__be64 r11;
1671 		} info;
1672 		struct fw_port_ppp {
1673 			__be32 pppen_to_ncsich;
1674 			__be32 r11;
1675 		} ppp;
1676 		struct fw_port_dcb {
1677 			__be16 cfg;
1678 			u8 up_map;
1679 			u8 sf_cfgrc;
1680 			__be16 prot_ix;
1681 			u8 pe7_to_pe0;
1682 			u8 numTCPFCs;
1683 			__be32 pgid0_to_pgid7;
1684 			__be32 numTCs_oui;
1685 			u8 pgpc[8];
1686 		} dcb;
1687 	} u;
1688 };
1689 
1690 #define FW_PORT_CMD_READ (1U << 22)
1691 
1692 #define FW_PORT_CMD_PORTID(x) ((x) << 0)
1693 #define FW_PORT_CMD_PORTID_GET(x) (((x) >> 0) & 0xf)
1694 
1695 #define FW_PORT_CMD_ACTION(x) ((x) << 16)
1696 #define FW_PORT_CMD_ACTION_GET(x) (((x) >> 16) & 0xffff)
1697 
1698 #define FW_PORT_CMD_CTLBF(x) ((x) << 10)
1699 #define FW_PORT_CMD_OVLAN3(x) ((x) << 7)
1700 #define FW_PORT_CMD_OVLAN2(x) ((x) << 6)
1701 #define FW_PORT_CMD_OVLAN1(x) ((x) << 5)
1702 #define FW_PORT_CMD_OVLAN0(x) ((x) << 4)
1703 #define FW_PORT_CMD_IVLAN0(x) ((x) << 3)
1704 
1705 #define FW_PORT_CMD_TXIPG(x) ((x) << 19)
1706 
1707 #define FW_PORT_CMD_LSTATUS (1U << 31)
1708 #define FW_PORT_CMD_LSTATUS_GET(x) (((x) >> 31) & 0x1)
1709 #define FW_PORT_CMD_LSPEED(x) ((x) << 24)
1710 #define FW_PORT_CMD_LSPEED_GET(x) (((x) >> 24) & 0x3f)
1711 #define FW_PORT_CMD_TXPAUSE (1U << 23)
1712 #define FW_PORT_CMD_RXPAUSE (1U << 22)
1713 #define FW_PORT_CMD_MDIOCAP (1U << 21)
1714 #define FW_PORT_CMD_MDIOADDR_GET(x) (((x) >> 16) & 0x1f)
1715 #define FW_PORT_CMD_LPTXPAUSE (1U << 15)
1716 #define FW_PORT_CMD_LPRXPAUSE (1U << 14)
1717 #define FW_PORT_CMD_PTYPE_MASK 0x1f
1718 #define FW_PORT_CMD_PTYPE_GET(x) (((x) >> 8) & FW_PORT_CMD_PTYPE_MASK)
1719 #define FW_PORT_CMD_MODTYPE_MASK 0x1f
1720 #define FW_PORT_CMD_MODTYPE_GET(x) (((x) >> 0) & FW_PORT_CMD_MODTYPE_MASK)
1721 
1722 #define FW_PORT_CMD_PPPEN(x) ((x) << 31)
1723 #define FW_PORT_CMD_TPSRC(x) ((x) << 28)
1724 #define FW_PORT_CMD_NCSISRC(x) ((x) << 24)
1725 
1726 #define FW_PORT_CMD_CH0(x) ((x) << 20)
1727 #define FW_PORT_CMD_CH1(x) ((x) << 16)
1728 #define FW_PORT_CMD_CH2(x) ((x) << 12)
1729 #define FW_PORT_CMD_CH3(x) ((x) << 8)
1730 #define FW_PORT_CMD_NCSICH(x) ((x) << 4)
1731 
1732 enum fw_port_type {
1733 	FW_PORT_TYPE_FIBER_XFI,
1734 	FW_PORT_TYPE_FIBER_XAUI,
1735 	FW_PORT_TYPE_BT_SGMII,
1736 	FW_PORT_TYPE_BT_XFI,
1737 	FW_PORT_TYPE_BT_XAUI,
1738 	FW_PORT_TYPE_KX4,
1739 	FW_PORT_TYPE_CX4,
1740 	FW_PORT_TYPE_KX,
1741 	FW_PORT_TYPE_KR,
1742 	FW_PORT_TYPE_SFP,
1743 	FW_PORT_TYPE_BP_AP,
1744 	FW_PORT_TYPE_BP4_AP,
1745 
1746 	FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_MASK
1747 };
1748 
1749 enum fw_port_module_type {
1750 	FW_PORT_MOD_TYPE_NA,
1751 	FW_PORT_MOD_TYPE_LR,
1752 	FW_PORT_MOD_TYPE_SR,
1753 	FW_PORT_MOD_TYPE_ER,
1754 	FW_PORT_MOD_TYPE_TWINAX_PASSIVE,
1755 	FW_PORT_MOD_TYPE_TWINAX_ACTIVE,
1756 	FW_PORT_MOD_TYPE_LRM,
1757 	FW_PORT_MOD_TYPE_ERROR		= FW_PORT_CMD_MODTYPE_MASK - 3,
1758 	FW_PORT_MOD_TYPE_UNKNOWN	= FW_PORT_CMD_MODTYPE_MASK - 2,
1759 	FW_PORT_MOD_TYPE_NOTSUPPORTED	= FW_PORT_CMD_MODTYPE_MASK - 1,
1760 
1761 	FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_MASK
1762 };
1763 
1764 enum fw_port_mod_sub_type {
1765 	FW_PORT_MOD_SUB_TYPE_NA,
1766 	FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
1767 	FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
1768 	FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
1769 	FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
1770 	FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
1771 	FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
1772 
1773 	/* The following will never been in the VPD.  They are TWINAX cable
1774 	 * lengths decoded from SFP+ module i2c PROMs.  These should
1775 	 * almost certainly go somewhere else ...
1776 	 */
1777 	FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
1778 	FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
1779 	FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
1780 	FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
1781 };
1782 
1783 /* port stats */
1784 #define FW_NUM_PORT_STATS 50
1785 #define FW_NUM_PORT_TX_STATS 23
1786 #define FW_NUM_PORT_RX_STATS 27
1787 
1788 enum fw_port_stats_tx_index {
1789 	FW_STAT_TX_PORT_BYTES_IX,
1790 	FW_STAT_TX_PORT_FRAMES_IX,
1791 	FW_STAT_TX_PORT_BCAST_IX,
1792 	FW_STAT_TX_PORT_MCAST_IX,
1793 	FW_STAT_TX_PORT_UCAST_IX,
1794 	FW_STAT_TX_PORT_ERROR_IX,
1795 	FW_STAT_TX_PORT_64B_IX,
1796 	FW_STAT_TX_PORT_65B_127B_IX,
1797 	FW_STAT_TX_PORT_128B_255B_IX,
1798 	FW_STAT_TX_PORT_256B_511B_IX,
1799 	FW_STAT_TX_PORT_512B_1023B_IX,
1800 	FW_STAT_TX_PORT_1024B_1518B_IX,
1801 	FW_STAT_TX_PORT_1519B_MAX_IX,
1802 	FW_STAT_TX_PORT_DROP_IX,
1803 	FW_STAT_TX_PORT_PAUSE_IX,
1804 	FW_STAT_TX_PORT_PPP0_IX,
1805 	FW_STAT_TX_PORT_PPP1_IX,
1806 	FW_STAT_TX_PORT_PPP2_IX,
1807 	FW_STAT_TX_PORT_PPP3_IX,
1808 	FW_STAT_TX_PORT_PPP4_IX,
1809 	FW_STAT_TX_PORT_PPP5_IX,
1810 	FW_STAT_TX_PORT_PPP6_IX,
1811 	FW_STAT_TX_PORT_PPP7_IX
1812 };
1813 
1814 enum fw_port_stat_rx_index {
1815 	FW_STAT_RX_PORT_BYTES_IX,
1816 	FW_STAT_RX_PORT_FRAMES_IX,
1817 	FW_STAT_RX_PORT_BCAST_IX,
1818 	FW_STAT_RX_PORT_MCAST_IX,
1819 	FW_STAT_RX_PORT_UCAST_IX,
1820 	FW_STAT_RX_PORT_MTU_ERROR_IX,
1821 	FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
1822 	FW_STAT_RX_PORT_CRC_ERROR_IX,
1823 	FW_STAT_RX_PORT_LEN_ERROR_IX,
1824 	FW_STAT_RX_PORT_SYM_ERROR_IX,
1825 	FW_STAT_RX_PORT_64B_IX,
1826 	FW_STAT_RX_PORT_65B_127B_IX,
1827 	FW_STAT_RX_PORT_128B_255B_IX,
1828 	FW_STAT_RX_PORT_256B_511B_IX,
1829 	FW_STAT_RX_PORT_512B_1023B_IX,
1830 	FW_STAT_RX_PORT_1024B_1518B_IX,
1831 	FW_STAT_RX_PORT_1519B_MAX_IX,
1832 	FW_STAT_RX_PORT_PAUSE_IX,
1833 	FW_STAT_RX_PORT_PPP0_IX,
1834 	FW_STAT_RX_PORT_PPP1_IX,
1835 	FW_STAT_RX_PORT_PPP2_IX,
1836 	FW_STAT_RX_PORT_PPP3_IX,
1837 	FW_STAT_RX_PORT_PPP4_IX,
1838 	FW_STAT_RX_PORT_PPP5_IX,
1839 	FW_STAT_RX_PORT_PPP6_IX,
1840 	FW_STAT_RX_PORT_PPP7_IX,
1841 	FW_STAT_RX_PORT_LESS_64B_IX
1842 };
1843 
1844 struct fw_port_stats_cmd {
1845 	__be32 op_to_portid;
1846 	__be32 retval_len16;
1847 	union fw_port_stats {
1848 		struct fw_port_stats_ctl {
1849 			u8 nstats_bg_bm;
1850 			u8 tx_ix;
1851 			__be16 r6;
1852 			__be32 r7;
1853 			__be64 stat0;
1854 			__be64 stat1;
1855 			__be64 stat2;
1856 			__be64 stat3;
1857 			__be64 stat4;
1858 			__be64 stat5;
1859 		} ctl;
1860 		struct fw_port_stats_all {
1861 			__be64 tx_bytes;
1862 			__be64 tx_frames;
1863 			__be64 tx_bcast;
1864 			__be64 tx_mcast;
1865 			__be64 tx_ucast;
1866 			__be64 tx_error;
1867 			__be64 tx_64b;
1868 			__be64 tx_65b_127b;
1869 			__be64 tx_128b_255b;
1870 			__be64 tx_256b_511b;
1871 			__be64 tx_512b_1023b;
1872 			__be64 tx_1024b_1518b;
1873 			__be64 tx_1519b_max;
1874 			__be64 tx_drop;
1875 			__be64 tx_pause;
1876 			__be64 tx_ppp0;
1877 			__be64 tx_ppp1;
1878 			__be64 tx_ppp2;
1879 			__be64 tx_ppp3;
1880 			__be64 tx_ppp4;
1881 			__be64 tx_ppp5;
1882 			__be64 tx_ppp6;
1883 			__be64 tx_ppp7;
1884 			__be64 rx_bytes;
1885 			__be64 rx_frames;
1886 			__be64 rx_bcast;
1887 			__be64 rx_mcast;
1888 			__be64 rx_ucast;
1889 			__be64 rx_mtu_error;
1890 			__be64 rx_mtu_crc_error;
1891 			__be64 rx_crc_error;
1892 			__be64 rx_len_error;
1893 			__be64 rx_sym_error;
1894 			__be64 rx_64b;
1895 			__be64 rx_65b_127b;
1896 			__be64 rx_128b_255b;
1897 			__be64 rx_256b_511b;
1898 			__be64 rx_512b_1023b;
1899 			__be64 rx_1024b_1518b;
1900 			__be64 rx_1519b_max;
1901 			__be64 rx_pause;
1902 			__be64 rx_ppp0;
1903 			__be64 rx_ppp1;
1904 			__be64 rx_ppp2;
1905 			__be64 rx_ppp3;
1906 			__be64 rx_ppp4;
1907 			__be64 rx_ppp5;
1908 			__be64 rx_ppp6;
1909 			__be64 rx_ppp7;
1910 			__be64 rx_less_64b;
1911 			__be64 rx_bg_drop;
1912 			__be64 rx_bg_trunc;
1913 		} all;
1914 	} u;
1915 };
1916 
1917 #define FW_PORT_STATS_CMD_NSTATS(x) ((x) << 4)
1918 #define FW_PORT_STATS_CMD_BG_BM(x) ((x) << 0)
1919 #define FW_PORT_STATS_CMD_TX(x) ((x) << 7)
1920 #define FW_PORT_STATS_CMD_IX(x) ((x) << 0)
1921 
1922 /* port loopback stats */
1923 #define FW_NUM_LB_STATS 16
1924 enum fw_port_lb_stats_index {
1925 	FW_STAT_LB_PORT_BYTES_IX,
1926 	FW_STAT_LB_PORT_FRAMES_IX,
1927 	FW_STAT_LB_PORT_BCAST_IX,
1928 	FW_STAT_LB_PORT_MCAST_IX,
1929 	FW_STAT_LB_PORT_UCAST_IX,
1930 	FW_STAT_LB_PORT_ERROR_IX,
1931 	FW_STAT_LB_PORT_64B_IX,
1932 	FW_STAT_LB_PORT_65B_127B_IX,
1933 	FW_STAT_LB_PORT_128B_255B_IX,
1934 	FW_STAT_LB_PORT_256B_511B_IX,
1935 	FW_STAT_LB_PORT_512B_1023B_IX,
1936 	FW_STAT_LB_PORT_1024B_1518B_IX,
1937 	FW_STAT_LB_PORT_1519B_MAX_IX,
1938 	FW_STAT_LB_PORT_DROP_FRAMES_IX
1939 };
1940 
1941 struct fw_port_lb_stats_cmd {
1942 	__be32 op_to_lbport;
1943 	__be32 retval_len16;
1944 	union fw_port_lb_stats {
1945 		struct fw_port_lb_stats_ctl {
1946 			u8 nstats_bg_bm;
1947 			u8 ix_pkd;
1948 			__be16 r6;
1949 			__be32 r7;
1950 			__be64 stat0;
1951 			__be64 stat1;
1952 			__be64 stat2;
1953 			__be64 stat3;
1954 			__be64 stat4;
1955 			__be64 stat5;
1956 		} ctl;
1957 		struct fw_port_lb_stats_all {
1958 			__be64 tx_bytes;
1959 			__be64 tx_frames;
1960 			__be64 tx_bcast;
1961 			__be64 tx_mcast;
1962 			__be64 tx_ucast;
1963 			__be64 tx_error;
1964 			__be64 tx_64b;
1965 			__be64 tx_65b_127b;
1966 			__be64 tx_128b_255b;
1967 			__be64 tx_256b_511b;
1968 			__be64 tx_512b_1023b;
1969 			__be64 tx_1024b_1518b;
1970 			__be64 tx_1519b_max;
1971 			__be64 rx_lb_drop;
1972 			__be64 rx_lb_trunc;
1973 		} all;
1974 	} u;
1975 };
1976 
1977 #define FW_PORT_LB_STATS_CMD_LBPORT(x) ((x) << 0)
1978 #define FW_PORT_LB_STATS_CMD_NSTATS(x) ((x) << 4)
1979 #define FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << 0)
1980 #define FW_PORT_LB_STATS_CMD_IX(x) ((x) << 0)
1981 
1982 struct fw_rss_ind_tbl_cmd {
1983 	__be32 op_to_viid;
1984 #define FW_RSS_IND_TBL_CMD_VIID(x) ((x) << 0)
1985 	__be32 retval_len16;
1986 	__be16 niqid;
1987 	__be16 startidx;
1988 	__be32 r3;
1989 	__be32 iq0_to_iq2;
1990 #define FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << 20)
1991 #define FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << 10)
1992 #define FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << 0)
1993 	__be32 iq3_to_iq5;
1994 	__be32 iq6_to_iq8;
1995 	__be32 iq9_to_iq11;
1996 	__be32 iq12_to_iq14;
1997 	__be32 iq15_to_iq17;
1998 	__be32 iq18_to_iq20;
1999 	__be32 iq21_to_iq23;
2000 	__be32 iq24_to_iq26;
2001 	__be32 iq27_to_iq29;
2002 	__be32 iq30_iq31;
2003 	__be32 r15_lo;
2004 };
2005 
2006 struct fw_rss_glb_config_cmd {
2007 	__be32 op_to_write;
2008 	__be32 retval_len16;
2009 	union fw_rss_glb_config {
2010 		struct fw_rss_glb_config_manual {
2011 			__be32 mode_pkd;
2012 			__be32 r3;
2013 			__be64 r4;
2014 			__be64 r5;
2015 		} manual;
2016 		struct fw_rss_glb_config_basicvirtual {
2017 			__be32 mode_pkd;
2018 			__be32 synmapen_to_hashtoeplitz;
2019 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN      (1U << 8)
2020 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 (1U << 7)
2021 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 (1U << 6)
2022 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 (1U << 5)
2023 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 (1U << 4)
2024 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN      (1U << 3)
2025 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN      (1U << 2)
2026 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP     (1U << 1)
2027 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ  (1U << 0)
2028 			__be64 r8;
2029 			__be64 r9;
2030 		} basicvirtual;
2031 	} u;
2032 };
2033 
2034 #define FW_RSS_GLB_CONFIG_CMD_MODE(x)	((x) << 28)
2035 #define FW_RSS_GLB_CONFIG_CMD_MODE_GET(x) (((x) >> 28) & 0xf)
2036 
2037 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL	0
2038 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL	1
2039 
2040 struct fw_rss_vi_config_cmd {
2041 	__be32 op_to_viid;
2042 #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0)
2043 	__be32 retval_len16;
2044 	union fw_rss_vi_config {
2045 		struct fw_rss_vi_config_manual {
2046 			__be64 r3;
2047 			__be64 r4;
2048 			__be64 r5;
2049 		} manual;
2050 		struct fw_rss_vi_config_basicvirtual {
2051 			__be32 r6;
2052 			__be32 defaultq_to_udpen;
2053 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x)  ((x) << 16)
2054 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_GET(x) (((x) >> 16) & 0x3ff)
2055 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN (1U << 4)
2056 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN  (1U << 3)
2057 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN (1U << 2)
2058 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN  (1U << 1)
2059 #define FW_RSS_VI_CONFIG_CMD_UDPEN        (1U << 0)
2060 			__be64 r9;
2061 			__be64 r10;
2062 		} basicvirtual;
2063 	} u;
2064 };
2065 
2066 struct fw_clip_cmd {
2067 	__be32 op_to_write;
2068 	__be32 alloc_to_len16;
2069 	__be64 ip_hi;
2070 	__be64 ip_lo;
2071 	__be32 r4[2];
2072 };
2073 
2074 #define S_FW_CLIP_CMD_ALLOC     31
2075 #define M_FW_CLIP_CMD_ALLOC     0x1
2076 #define V_FW_CLIP_CMD_ALLOC(x)  ((x) << S_FW_CLIP_CMD_ALLOC)
2077 #define G_FW_CLIP_CMD_ALLOC(x)  \
2078 	(((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC)
2079 #define F_FW_CLIP_CMD_ALLOC     V_FW_CLIP_CMD_ALLOC(1U)
2080 
2081 #define S_FW_CLIP_CMD_FREE      30
2082 #define M_FW_CLIP_CMD_FREE      0x1
2083 #define V_FW_CLIP_CMD_FREE(x)   ((x) << S_FW_CLIP_CMD_FREE)
2084 #define G_FW_CLIP_CMD_FREE(x)   \
2085 	(((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE)
2086 #define F_FW_CLIP_CMD_FREE      V_FW_CLIP_CMD_FREE(1U)
2087 
2088 enum fw_error_type {
2089 	FW_ERROR_TYPE_EXCEPTION		= 0x0,
2090 	FW_ERROR_TYPE_HWMODULE		= 0x1,
2091 	FW_ERROR_TYPE_WR		= 0x2,
2092 	FW_ERROR_TYPE_ACL		= 0x3,
2093 };
2094 
2095 struct fw_error_cmd {
2096 	__be32 op_to_type;
2097 	__be32 len16_pkd;
2098 	union fw_error {
2099 		struct fw_error_exception {
2100 			__be32 info[6];
2101 		} exception;
2102 		struct fw_error_hwmodule {
2103 			__be32 regaddr;
2104 			__be32 regval;
2105 		} hwmodule;
2106 		struct fw_error_wr {
2107 			__be16 cidx;
2108 			__be16 pfn_vfn;
2109 			__be32 eqid;
2110 			u8 wrhdr[16];
2111 		} wr;
2112 		struct fw_error_acl {
2113 			__be16 cidx;
2114 			__be16 pfn_vfn;
2115 			__be32 eqid;
2116 			__be16 mv_pkd;
2117 			u8 val[6];
2118 			__be64 r4;
2119 		} acl;
2120 	} u;
2121 };
2122 
2123 struct fw_debug_cmd {
2124 	__be32 op_type;
2125 #define FW_DEBUG_CMD_TYPE_GET(x) ((x) & 0xff)
2126 	__be32 len16_pkd;
2127 	union fw_debug {
2128 		struct fw_debug_assert {
2129 			__be32 fcid;
2130 			__be32 line;
2131 			__be32 x;
2132 			__be32 y;
2133 			u8 filename_0_7[8];
2134 			u8 filename_8_15[8];
2135 			__be64 r3;
2136 		} assert;
2137 		struct fw_debug_prt {
2138 			__be16 dprtstridx;
2139 			__be16 r3[3];
2140 			__be32 dprtstrparam0;
2141 			__be32 dprtstrparam1;
2142 			__be32 dprtstrparam2;
2143 			__be32 dprtstrparam3;
2144 		} prt;
2145 	} u;
2146 };
2147 
2148 #define FW_PCIE_FW_ERR           (1U << 31)
2149 #define FW_PCIE_FW_INIT          (1U << 30)
2150 #define FW_PCIE_FW_HALT          (1U << 29)
2151 #define FW_PCIE_FW_MASTER_VLD    (1U << 15)
2152 #define FW_PCIE_FW_MASTER_MASK   0x7
2153 #define FW_PCIE_FW_MASTER_SHIFT  12
2154 #define FW_PCIE_FW_MASTER(x)     ((x) << FW_PCIE_FW_MASTER_SHIFT)
2155 #define FW_PCIE_FW_MASTER_GET(x) (((x) >> FW_PCIE_FW_MASTER_SHIFT) & \
2156 				 FW_PCIE_FW_MASTER_MASK)
2157 
2158 struct fw_hdr {
2159 	u8 ver;
2160 	u8 chip;			/* terminator chip type */
2161 	__be16	len512;			/* bin length in units of 512-bytes */
2162 	__be32	fw_ver;			/* firmware version */
2163 	__be32	tp_microcode_ver;
2164 	u8 intfver_nic;
2165 	u8 intfver_vnic;
2166 	u8 intfver_ofld;
2167 	u8 intfver_ri;
2168 	u8 intfver_iscsipdu;
2169 	u8 intfver_iscsi;
2170 	u8 intfver_fcoepdu;
2171 	u8 intfver_fcoe;
2172 	__u32   reserved2;
2173 	__u32   reserved3;
2174 	__u32   reserved4;
2175 	__be32  flags;
2176 	__be32  reserved6[23];
2177 };
2178 
2179 enum fw_hdr_chip {
2180 	FW_HDR_CHIP_T4,
2181 	FW_HDR_CHIP_T5
2182 };
2183 
2184 #define FW_HDR_FW_VER_MAJOR_GET(x) (((x) >> 24) & 0xff)
2185 #define FW_HDR_FW_VER_MINOR_GET(x) (((x) >> 16) & 0xff)
2186 #define FW_HDR_FW_VER_MICRO_GET(x) (((x) >> 8) & 0xff)
2187 #define FW_HDR_FW_VER_BUILD_GET(x) (((x) >> 0) & 0xff)
2188 
2189 enum fw_hdr_intfver {
2190 	FW_HDR_INTFVER_NIC      = 0x00,
2191 	FW_HDR_INTFVER_VNIC     = 0x00,
2192 	FW_HDR_INTFVER_OFLD     = 0x00,
2193 	FW_HDR_INTFVER_RI       = 0x00,
2194 	FW_HDR_INTFVER_ISCSIPDU = 0x00,
2195 	FW_HDR_INTFVER_ISCSI    = 0x00,
2196 	FW_HDR_INTFVER_FCOEPDU  = 0x00,
2197 	FW_HDR_INTFVER_FCOE     = 0x00,
2198 };
2199 
2200 enum fw_hdr_flags {
2201 	FW_HDR_FLAGS_RESET_HALT = 0x00000001,
2202 };
2203 
2204 #endif /* _T4FW_INTERFACE_H_ */
2205