1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef _T4FW_INTERFACE_H_ 36 #define _T4FW_INTERFACE_H_ 37 38 #define FW_T4VF_SGE_BASE_ADDR 0x0000 39 #define FW_T4VF_MPS_BASE_ADDR 0x0100 40 #define FW_T4VF_PL_BASE_ADDR 0x0200 41 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240 42 #define FW_T4VF_CIM_BASE_ADDR 0x0300 43 44 enum fw_wr_opcodes { 45 FW_FILTER_WR = 0x02, 46 FW_ULPTX_WR = 0x04, 47 FW_TP_WR = 0x05, 48 FW_ETH_TX_PKT_WR = 0x08, 49 FW_FLOWC_WR = 0x0a, 50 FW_OFLD_TX_DATA_WR = 0x0b, 51 FW_CMD_WR = 0x10, 52 FW_ETH_TX_PKT_VM_WR = 0x11, 53 FW_RI_RES_WR = 0x0c, 54 FW_RI_INIT_WR = 0x0d, 55 FW_RI_RDMA_WRITE_WR = 0x14, 56 FW_RI_SEND_WR = 0x15, 57 FW_RI_RDMA_READ_WR = 0x16, 58 FW_RI_RECV_WR = 0x17, 59 FW_RI_BIND_MW_WR = 0x18, 60 FW_RI_FR_NSMR_WR = 0x19, 61 FW_RI_INV_LSTAG_WR = 0x1a, 62 FW_LASTC2E_WR = 0x40 63 }; 64 65 struct fw_wr_hdr { 66 __be32 hi; 67 __be32 lo; 68 }; 69 70 #define FW_WR_OP(x) ((x) << 24) 71 #define FW_WR_ATOMIC(x) ((x) << 23) 72 #define FW_WR_FLUSH(x) ((x) << 22) 73 #define FW_WR_COMPL(x) ((x) << 21) 74 #define FW_WR_IMMDLEN_MASK 0xff 75 #define FW_WR_IMMDLEN(x) ((x) << 0) 76 77 #define FW_WR_EQUIQ (1U << 31) 78 #define FW_WR_EQUEQ (1U << 30) 79 #define FW_WR_FLOWID(x) ((x) << 8) 80 #define FW_WR_LEN16(x) ((x) << 0) 81 82 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 83 84 struct fw_ulptx_wr { 85 __be32 op_to_compl; 86 __be32 flowid_len16; 87 u64 cookie; 88 }; 89 90 struct fw_tp_wr { 91 __be32 op_to_immdlen; 92 __be32 flowid_len16; 93 u64 cookie; 94 }; 95 96 struct fw_eth_tx_pkt_wr { 97 __be32 op_immdlen; 98 __be32 equiq_to_len16; 99 __be64 r3; 100 }; 101 102 enum fw_flowc_mnem { 103 FW_FLOWC_MNEM_PFNVFN, /* PFN [15:8] VFN [7:0] */ 104 FW_FLOWC_MNEM_CH, 105 FW_FLOWC_MNEM_PORT, 106 FW_FLOWC_MNEM_IQID, 107 FW_FLOWC_MNEM_SNDNXT, 108 FW_FLOWC_MNEM_RCVNXT, 109 FW_FLOWC_MNEM_SNDBUF, 110 FW_FLOWC_MNEM_MSS, 111 }; 112 113 struct fw_flowc_mnemval { 114 u8 mnemonic; 115 u8 r4[3]; 116 __be32 val; 117 }; 118 119 struct fw_flowc_wr { 120 __be32 op_to_nparams; 121 #define FW_FLOWC_WR_NPARAMS(x) ((x) << 0) 122 __be32 flowid_len16; 123 struct fw_flowc_mnemval mnemval[0]; 124 }; 125 126 struct fw_ofld_tx_data_wr { 127 __be32 op_to_immdlen; 128 __be32 flowid_len16; 129 __be32 plen; 130 __be32 tunnel_to_proxy; 131 #define FW_OFLD_TX_DATA_WR_TUNNEL(x) ((x) << 19) 132 #define FW_OFLD_TX_DATA_WR_SAVE(x) ((x) << 18) 133 #define FW_OFLD_TX_DATA_WR_FLUSH(x) ((x) << 17) 134 #define FW_OFLD_TX_DATA_WR_URGENT(x) ((x) << 16) 135 #define FW_OFLD_TX_DATA_WR_MORE(x) ((x) << 15) 136 #define FW_OFLD_TX_DATA_WR_SHOVE(x) ((x) << 14) 137 #define FW_OFLD_TX_DATA_WR_ULPMODE(x) ((x) << 10) 138 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) ((x) << 6) 139 }; 140 141 struct fw_cmd_wr { 142 __be32 op_dma; 143 #define FW_CMD_WR_DMA (1U << 17) 144 __be32 len16_pkd; 145 __be64 cookie_daddr; 146 }; 147 148 struct fw_eth_tx_pkt_vm_wr { 149 __be32 op_immdlen; 150 __be32 equiq_to_len16; 151 __be32 r3[2]; 152 u8 ethmacdst[6]; 153 u8 ethmacsrc[6]; 154 __be16 ethtype; 155 __be16 vlantci; 156 }; 157 158 #define FW_CMD_MAX_TIMEOUT 3000 159 160 /* 161 * If a host driver does a HELLO and discovers that there's already a MASTER 162 * selected, we may have to wait for that MASTER to finish issuing RESET, 163 * configuration and INITIALIZE commands. Also, there's a possibility that 164 * our own HELLO may get lost if it happens right as the MASTER is issuign a 165 * RESET command, so we need to be willing to make a few retries of our HELLO. 166 */ 167 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 168 #define FW_CMD_HELLO_RETRIES 3 169 170 171 enum fw_cmd_opcodes { 172 FW_LDST_CMD = 0x01, 173 FW_RESET_CMD = 0x03, 174 FW_HELLO_CMD = 0x04, 175 FW_BYE_CMD = 0x05, 176 FW_INITIALIZE_CMD = 0x06, 177 FW_CAPS_CONFIG_CMD = 0x07, 178 FW_PARAMS_CMD = 0x08, 179 FW_PFVF_CMD = 0x09, 180 FW_IQ_CMD = 0x10, 181 FW_EQ_MNGT_CMD = 0x11, 182 FW_EQ_ETH_CMD = 0x12, 183 FW_EQ_CTRL_CMD = 0x13, 184 FW_EQ_OFLD_CMD = 0x21, 185 FW_VI_CMD = 0x14, 186 FW_VI_MAC_CMD = 0x15, 187 FW_VI_RXMODE_CMD = 0x16, 188 FW_VI_ENABLE_CMD = 0x17, 189 FW_ACL_MAC_CMD = 0x18, 190 FW_ACL_VLAN_CMD = 0x19, 191 FW_VI_STATS_CMD = 0x1a, 192 FW_PORT_CMD = 0x1b, 193 FW_PORT_STATS_CMD = 0x1c, 194 FW_PORT_LB_STATS_CMD = 0x1d, 195 FW_PORT_TRACE_CMD = 0x1e, 196 FW_PORT_TRACE_MMAP_CMD = 0x1f, 197 FW_RSS_IND_TBL_CMD = 0x20, 198 FW_RSS_GLB_CONFIG_CMD = 0x22, 199 FW_RSS_VI_CONFIG_CMD = 0x23, 200 FW_LASTC2E_CMD = 0x40, 201 FW_ERROR_CMD = 0x80, 202 FW_DEBUG_CMD = 0x81, 203 }; 204 205 enum fw_cmd_cap { 206 FW_CMD_CAP_PF = 0x01, 207 FW_CMD_CAP_DMAQ = 0x02, 208 FW_CMD_CAP_PORT = 0x04, 209 FW_CMD_CAP_PORTPROMISC = 0x08, 210 FW_CMD_CAP_PORTSTATS = 0x10, 211 FW_CMD_CAP_VF = 0x80, 212 }; 213 214 /* 215 * Generic command header flit0 216 */ 217 struct fw_cmd_hdr { 218 __be32 hi; 219 __be32 lo; 220 }; 221 222 #define FW_CMD_OP(x) ((x) << 24) 223 #define FW_CMD_OP_GET(x) (((x) >> 24) & 0xff) 224 #define FW_CMD_REQUEST (1U << 23) 225 #define FW_CMD_READ (1U << 22) 226 #define FW_CMD_WRITE (1U << 21) 227 #define FW_CMD_EXEC (1U << 20) 228 #define FW_CMD_RAMASK(x) ((x) << 20) 229 #define FW_CMD_RETVAL(x) ((x) << 8) 230 #define FW_CMD_RETVAL_GET(x) (((x) >> 8) & 0xff) 231 #define FW_CMD_LEN16(x) ((x) << 0) 232 233 enum fw_ldst_addrspc { 234 FW_LDST_ADDRSPC_FIRMWARE = 0x0001, 235 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, 236 FW_LDST_ADDRSPC_SGE_INGC = 0x0009, 237 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, 238 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 239 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 240 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 241 FW_LDST_ADDRSPC_TP_MIB = 0x0012, 242 FW_LDST_ADDRSPC_MDIO = 0x0018, 243 FW_LDST_ADDRSPC_MPS = 0x0020, 244 FW_LDST_ADDRSPC_FUNC = 0x0028 245 }; 246 247 enum fw_ldst_mps_fid { 248 FW_LDST_MPS_ATRB, 249 FW_LDST_MPS_RPLC 250 }; 251 252 enum fw_ldst_func_access_ctl { 253 FW_LDST_FUNC_ACC_CTL_VIID, 254 FW_LDST_FUNC_ACC_CTL_FID 255 }; 256 257 enum fw_ldst_func_mod_index { 258 FW_LDST_FUNC_MPS 259 }; 260 261 struct fw_ldst_cmd { 262 __be32 op_to_addrspace; 263 #define FW_LDST_CMD_ADDRSPACE(x) ((x) << 0) 264 __be32 cycles_to_len16; 265 union fw_ldst { 266 struct fw_ldst_addrval { 267 __be32 addr; 268 __be32 val; 269 } addrval; 270 struct fw_ldst_idctxt { 271 __be32 physid; 272 __be32 msg_pkd; 273 __be32 ctxt_data7; 274 __be32 ctxt_data6; 275 __be32 ctxt_data5; 276 __be32 ctxt_data4; 277 __be32 ctxt_data3; 278 __be32 ctxt_data2; 279 __be32 ctxt_data1; 280 __be32 ctxt_data0; 281 } idctxt; 282 struct fw_ldst_mdio { 283 __be16 paddr_mmd; 284 __be16 raddr; 285 __be16 vctl; 286 __be16 rval; 287 } mdio; 288 struct fw_ldst_mps { 289 __be16 fid_ctl; 290 __be16 rplcpf_pkd; 291 __be32 rplc127_96; 292 __be32 rplc95_64; 293 __be32 rplc63_32; 294 __be32 rplc31_0; 295 __be32 atrb; 296 __be16 vlan[16]; 297 } mps; 298 struct fw_ldst_func { 299 u8 access_ctl; 300 u8 mod_index; 301 __be16 ctl_id; 302 __be32 offset; 303 __be64 data0; 304 __be64 data1; 305 } func; 306 } u; 307 }; 308 309 #define FW_LDST_CMD_MSG(x) ((x) << 31) 310 #define FW_LDST_CMD_PADDR(x) ((x) << 8) 311 #define FW_LDST_CMD_MMD(x) ((x) << 0) 312 #define FW_LDST_CMD_FID(x) ((x) << 15) 313 #define FW_LDST_CMD_CTL(x) ((x) << 0) 314 #define FW_LDST_CMD_RPLCPF(x) ((x) << 0) 315 316 struct fw_reset_cmd { 317 __be32 op_to_write; 318 __be32 retval_len16; 319 __be32 val; 320 __be32 halt_pkd; 321 }; 322 323 #define FW_RESET_CMD_HALT_SHIFT 31 324 #define FW_RESET_CMD_HALT_MASK 0x1 325 #define FW_RESET_CMD_HALT(x) ((x) << FW_RESET_CMD_HALT_SHIFT) 326 #define FW_RESET_CMD_HALT_GET(x) \ 327 (((x) >> FW_RESET_CMD_HALT_SHIFT) & FW_RESET_CMD_HALT_MASK) 328 329 enum fw_hellow_cmd { 330 fw_hello_cmd_stage_os = 0x0 331 }; 332 333 struct fw_hello_cmd { 334 __be32 op_to_write; 335 __be32 retval_len16; 336 __be32 err_to_mbasyncnot; 337 #define FW_HELLO_CMD_ERR (1U << 31) 338 #define FW_HELLO_CMD_INIT (1U << 30) 339 #define FW_HELLO_CMD_MASTERDIS(x) ((x) << 29) 340 #define FW_HELLO_CMD_MASTERFORCE(x) ((x) << 28) 341 #define FW_HELLO_CMD_MBMASTER_MASK 0xfU 342 #define FW_HELLO_CMD_MBMASTER_SHIFT 24 343 #define FW_HELLO_CMD_MBMASTER(x) ((x) << FW_HELLO_CMD_MBMASTER_SHIFT) 344 #define FW_HELLO_CMD_MBMASTER_GET(x) \ 345 (((x) >> FW_HELLO_CMD_MBMASTER_SHIFT) & FW_HELLO_CMD_MBMASTER_MASK) 346 #define FW_HELLO_CMD_MBASYNCNOT(x) ((x) << 20) 347 #define FW_HELLO_CMD_STAGE(x) ((x) << 17) 348 #define FW_HELLO_CMD_CLEARINIT (1U << 16) 349 __be32 fwrev; 350 }; 351 352 struct fw_bye_cmd { 353 __be32 op_to_write; 354 __be32 retval_len16; 355 __be64 r3; 356 }; 357 358 struct fw_initialize_cmd { 359 __be32 op_to_write; 360 __be32 retval_len16; 361 __be64 r3; 362 }; 363 364 enum fw_caps_config_hm { 365 FW_CAPS_CONFIG_HM_PCIE = 0x00000001, 366 FW_CAPS_CONFIG_HM_PL = 0x00000002, 367 FW_CAPS_CONFIG_HM_SGE = 0x00000004, 368 FW_CAPS_CONFIG_HM_CIM = 0x00000008, 369 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, 370 FW_CAPS_CONFIG_HM_TP = 0x00000020, 371 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, 372 FW_CAPS_CONFIG_HM_PMRX = 0x00000080, 373 FW_CAPS_CONFIG_HM_PMTX = 0x00000100, 374 FW_CAPS_CONFIG_HM_MC = 0x00000200, 375 FW_CAPS_CONFIG_HM_LE = 0x00000400, 376 FW_CAPS_CONFIG_HM_MPS = 0x00000800, 377 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, 378 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, 379 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, 380 FW_CAPS_CONFIG_HM_MI = 0x00008000, 381 FW_CAPS_CONFIG_HM_I2CM = 0x00010000, 382 FW_CAPS_CONFIG_HM_NCSI = 0x00020000, 383 FW_CAPS_CONFIG_HM_SMB = 0x00040000, 384 FW_CAPS_CONFIG_HM_MA = 0x00080000, 385 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, 386 FW_CAPS_CONFIG_HM_PMU = 0x00200000, 387 FW_CAPS_CONFIG_HM_UART = 0x00400000, 388 FW_CAPS_CONFIG_HM_SF = 0x00800000, 389 }; 390 391 enum fw_caps_config_nbm { 392 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, 393 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, 394 }; 395 396 enum fw_caps_config_link { 397 FW_CAPS_CONFIG_LINK_PPP = 0x00000001, 398 FW_CAPS_CONFIG_LINK_QFC = 0x00000002, 399 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, 400 }; 401 402 enum fw_caps_config_switch { 403 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, 404 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, 405 }; 406 407 enum fw_caps_config_nic { 408 FW_CAPS_CONFIG_NIC = 0x00000001, 409 FW_CAPS_CONFIG_NIC_VM = 0x00000002, 410 }; 411 412 enum fw_caps_config_ofld { 413 FW_CAPS_CONFIG_OFLD = 0x00000001, 414 }; 415 416 enum fw_caps_config_rdma { 417 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, 418 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, 419 }; 420 421 enum fw_caps_config_iscsi { 422 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, 423 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, 424 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, 425 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, 426 }; 427 428 enum fw_caps_config_fcoe { 429 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 430 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 431 }; 432 433 enum fw_memtype_cf { 434 FW_MEMTYPE_CF_EDC0 = 0x0, 435 FW_MEMTYPE_CF_EDC1 = 0x1, 436 FW_MEMTYPE_CF_EXTMEM = 0x2, 437 FW_MEMTYPE_CF_FLASH = 0x4, 438 FW_MEMTYPE_CF_INTERNAL = 0x5, 439 }; 440 441 struct fw_caps_config_cmd { 442 __be32 op_to_write; 443 __be32 retval_len16; 444 __be32 r2; 445 __be32 hwmbitmap; 446 __be16 nbmcaps; 447 __be16 linkcaps; 448 __be16 switchcaps; 449 __be16 r3; 450 __be16 niccaps; 451 __be16 ofldcaps; 452 __be16 rdmacaps; 453 __be16 r4; 454 __be16 iscsicaps; 455 __be16 fcoecaps; 456 __be32 cfcsum; 457 __be32 finiver; 458 __be32 finicsum; 459 }; 460 461 #define FW_CAPS_CONFIG_CMD_CFVALID (1U << 27) 462 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) ((x) << 24) 463 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) ((x) << 16) 464 465 /* 466 * params command mnemonics 467 */ 468 enum fw_params_mnem { 469 FW_PARAMS_MNEM_DEV = 1, /* device params */ 470 FW_PARAMS_MNEM_PFVF = 2, /* function params */ 471 FW_PARAMS_MNEM_REG = 3, /* limited register access */ 472 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 473 FW_PARAMS_MNEM_LAST 474 }; 475 476 /* 477 * device parameters 478 */ 479 enum fw_params_param_dev { 480 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 481 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 482 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs 483 * allocated by the device's 484 * Lookup Engine 485 */ 486 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, 487 FW_PARAMS_PARAM_DEV_INTVER_NIC = 0x04, 488 FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05, 489 FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06, 490 FW_PARAMS_PARAM_DEV_INTVER_RI = 0x07, 491 FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08, 492 FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09, 493 FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A, 494 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, 495 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, 496 FW_PARAMS_PARAM_DEV_CF = 0x0D, 497 }; 498 499 /* 500 * physical and virtual function parameters 501 */ 502 enum fw_params_param_pfvf { 503 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, 504 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, 505 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, 506 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 507 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 508 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 509 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 510 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, 511 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, 512 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, 513 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, 514 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, 515 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, 516 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, 517 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, 518 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, 519 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, 520 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, 521 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, 522 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 523 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 524 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15, 525 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16, 526 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17, 527 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18, 528 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, 529 FW_PARAMS_PARAM_PFVF_VIID = 0x24, 530 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 531 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 532 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 533 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 534 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 535 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 536 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, 537 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 538 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 539 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E 540 }; 541 542 /* 543 * dma queue parameters 544 */ 545 enum fw_params_param_dmaq { 546 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 547 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 548 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 549 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 550 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, 551 }; 552 553 #define FW_PARAMS_MNEM(x) ((x) << 24) 554 #define FW_PARAMS_PARAM_X(x) ((x) << 16) 555 #define FW_PARAMS_PARAM_Y_SHIFT 8 556 #define FW_PARAMS_PARAM_Y_MASK 0xffU 557 #define FW_PARAMS_PARAM_Y(x) ((x) << FW_PARAMS_PARAM_Y_SHIFT) 558 #define FW_PARAMS_PARAM_Y_GET(x) (((x) >> FW_PARAMS_PARAM_Y_SHIFT) &\ 559 FW_PARAMS_PARAM_Y_MASK) 560 #define FW_PARAMS_PARAM_Z_SHIFT 0 561 #define FW_PARAMS_PARAM_Z_MASK 0xffu 562 #define FW_PARAMS_PARAM_Z(x) ((x) << FW_PARAMS_PARAM_Z_SHIFT) 563 #define FW_PARAMS_PARAM_Z_GET(x) (((x) >> FW_PARAMS_PARAM_Z_SHIFT) &\ 564 FW_PARAMS_PARAM_Z_MASK) 565 #define FW_PARAMS_PARAM_XYZ(x) ((x) << 0) 566 #define FW_PARAMS_PARAM_YZ(x) ((x) << 0) 567 568 struct fw_params_cmd { 569 __be32 op_to_vfn; 570 __be32 retval_len16; 571 struct fw_params_param { 572 __be32 mnem; 573 __be32 val; 574 } param[7]; 575 }; 576 577 #define FW_PARAMS_CMD_PFN(x) ((x) << 8) 578 #define FW_PARAMS_CMD_VFN(x) ((x) << 0) 579 580 struct fw_pfvf_cmd { 581 __be32 op_to_vfn; 582 __be32 retval_len16; 583 __be32 niqflint_niq; 584 __be32 type_to_neq; 585 __be32 tc_to_nexactf; 586 __be32 r_caps_to_nethctrl; 587 __be16 nricq; 588 __be16 nriqp; 589 __be32 r4; 590 }; 591 592 #define FW_PFVF_CMD_PFN(x) ((x) << 8) 593 #define FW_PFVF_CMD_VFN(x) ((x) << 0) 594 595 #define FW_PFVF_CMD_NIQFLINT(x) ((x) << 20) 596 #define FW_PFVF_CMD_NIQFLINT_GET(x) (((x) >> 20) & 0xfff) 597 598 #define FW_PFVF_CMD_NIQ(x) ((x) << 0) 599 #define FW_PFVF_CMD_NIQ_GET(x) (((x) >> 0) & 0xfffff) 600 601 #define FW_PFVF_CMD_TYPE (1 << 31) 602 #define FW_PFVF_CMD_TYPE_GET(x) (((x) >> 31) & 0x1) 603 604 #define FW_PFVF_CMD_CMASK(x) ((x) << 24) 605 #define FW_PFVF_CMD_CMASK_MASK 0xf 606 #define FW_PFVF_CMD_CMASK_GET(x) (((x) >> 24) & FW_PFVF_CMD_CMASK_MASK) 607 608 #define FW_PFVF_CMD_PMASK(x) ((x) << 20) 609 #define FW_PFVF_CMD_PMASK_MASK 0xf 610 #define FW_PFVF_CMD_PMASK_GET(x) (((x) >> 20) & FW_PFVF_CMD_PMASK_MASK) 611 612 #define FW_PFVF_CMD_NEQ(x) ((x) << 0) 613 #define FW_PFVF_CMD_NEQ_GET(x) (((x) >> 0) & 0xfffff) 614 615 #define FW_PFVF_CMD_TC(x) ((x) << 24) 616 #define FW_PFVF_CMD_TC_GET(x) (((x) >> 24) & 0xff) 617 618 #define FW_PFVF_CMD_NVI(x) ((x) << 16) 619 #define FW_PFVF_CMD_NVI_GET(x) (((x) >> 16) & 0xff) 620 621 #define FW_PFVF_CMD_NEXACTF(x) ((x) << 0) 622 #define FW_PFVF_CMD_NEXACTF_GET(x) (((x) >> 0) & 0xffff) 623 624 #define FW_PFVF_CMD_R_CAPS(x) ((x) << 24) 625 #define FW_PFVF_CMD_R_CAPS_GET(x) (((x) >> 24) & 0xff) 626 627 #define FW_PFVF_CMD_WX_CAPS(x) ((x) << 16) 628 #define FW_PFVF_CMD_WX_CAPS_GET(x) (((x) >> 16) & 0xff) 629 630 #define FW_PFVF_CMD_NETHCTRL(x) ((x) << 0) 631 #define FW_PFVF_CMD_NETHCTRL_GET(x) (((x) >> 0) & 0xffff) 632 633 enum fw_iq_type { 634 FW_IQ_TYPE_FL_INT_CAP, 635 FW_IQ_TYPE_NO_FL_INT_CAP 636 }; 637 638 struct fw_iq_cmd { 639 __be32 op_to_vfn; 640 __be32 alloc_to_len16; 641 __be16 physiqid; 642 __be16 iqid; 643 __be16 fl0id; 644 __be16 fl1id; 645 __be32 type_to_iqandstindex; 646 __be16 iqdroprss_to_iqesize; 647 __be16 iqsize; 648 __be64 iqaddr; 649 __be32 iqns_to_fl0congen; 650 __be16 fl0dcaen_to_fl0cidxfthresh; 651 __be16 fl0size; 652 __be64 fl0addr; 653 __be32 fl1cngchmap_to_fl1congen; 654 __be16 fl1dcaen_to_fl1cidxfthresh; 655 __be16 fl1size; 656 __be64 fl1addr; 657 }; 658 659 #define FW_IQ_CMD_PFN(x) ((x) << 8) 660 #define FW_IQ_CMD_VFN(x) ((x) << 0) 661 662 #define FW_IQ_CMD_ALLOC (1U << 31) 663 #define FW_IQ_CMD_FREE (1U << 30) 664 #define FW_IQ_CMD_MODIFY (1U << 29) 665 #define FW_IQ_CMD_IQSTART(x) ((x) << 28) 666 #define FW_IQ_CMD_IQSTOP(x) ((x) << 27) 667 668 #define FW_IQ_CMD_TYPE(x) ((x) << 29) 669 #define FW_IQ_CMD_IQASYNCH(x) ((x) << 28) 670 #define FW_IQ_CMD_VIID(x) ((x) << 16) 671 #define FW_IQ_CMD_IQANDST(x) ((x) << 15) 672 #define FW_IQ_CMD_IQANUS(x) ((x) << 14) 673 #define FW_IQ_CMD_IQANUD(x) ((x) << 12) 674 #define FW_IQ_CMD_IQANDSTINDEX(x) ((x) << 0) 675 676 #define FW_IQ_CMD_IQDROPRSS (1U << 15) 677 #define FW_IQ_CMD_IQGTSMODE (1U << 14) 678 #define FW_IQ_CMD_IQPCIECH(x) ((x) << 12) 679 #define FW_IQ_CMD_IQDCAEN(x) ((x) << 11) 680 #define FW_IQ_CMD_IQDCACPU(x) ((x) << 6) 681 #define FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << 4) 682 #define FW_IQ_CMD_IQO (1U << 3) 683 #define FW_IQ_CMD_IQCPRIO(x) ((x) << 2) 684 #define FW_IQ_CMD_IQESIZE(x) ((x) << 0) 685 686 #define FW_IQ_CMD_IQNS(x) ((x) << 31) 687 #define FW_IQ_CMD_IQRO(x) ((x) << 30) 688 #define FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << 28) 689 #define FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << 27) 690 #define FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << 26) 691 #define FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << 20) 692 #define FW_IQ_CMD_FL0CACHELOCK(x) ((x) << 15) 693 #define FW_IQ_CMD_FL0DBP(x) ((x) << 14) 694 #define FW_IQ_CMD_FL0DATANS(x) ((x) << 13) 695 #define FW_IQ_CMD_FL0DATARO(x) ((x) << 12) 696 #define FW_IQ_CMD_FL0CONGCIF(x) ((x) << 11) 697 #define FW_IQ_CMD_FL0ONCHIP(x) ((x) << 10) 698 #define FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << 9) 699 #define FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << 8) 700 #define FW_IQ_CMD_FL0FETCHNS(x) ((x) << 7) 701 #define FW_IQ_CMD_FL0FETCHRO(x) ((x) << 6) 702 #define FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << 4) 703 #define FW_IQ_CMD_FL0CPRIO(x) ((x) << 3) 704 #define FW_IQ_CMD_FL0PADEN (1U << 2) 705 #define FW_IQ_CMD_FL0PACKEN (1U << 1) 706 #define FW_IQ_CMD_FL0CONGEN (1U << 0) 707 708 #define FW_IQ_CMD_FL0DCAEN(x) ((x) << 15) 709 #define FW_IQ_CMD_FL0DCACPU(x) ((x) << 10) 710 #define FW_IQ_CMD_FL0FBMIN(x) ((x) << 7) 711 #define FW_IQ_CMD_FL0FBMAX(x) ((x) << 4) 712 #define FW_IQ_CMD_FL0CIDXFTHRESHO (1U << 3) 713 #define FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << 0) 714 715 #define FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << 20) 716 #define FW_IQ_CMD_FL1CACHELOCK(x) ((x) << 15) 717 #define FW_IQ_CMD_FL1DBP(x) ((x) << 14) 718 #define FW_IQ_CMD_FL1DATANS(x) ((x) << 13) 719 #define FW_IQ_CMD_FL1DATARO(x) ((x) << 12) 720 #define FW_IQ_CMD_FL1CONGCIF(x) ((x) << 11) 721 #define FW_IQ_CMD_FL1ONCHIP(x) ((x) << 10) 722 #define FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << 9) 723 #define FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << 8) 724 #define FW_IQ_CMD_FL1FETCHNS(x) ((x) << 7) 725 #define FW_IQ_CMD_FL1FETCHRO(x) ((x) << 6) 726 #define FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << 4) 727 #define FW_IQ_CMD_FL1CPRIO(x) ((x) << 3) 728 #define FW_IQ_CMD_FL1PADEN (1U << 2) 729 #define FW_IQ_CMD_FL1PACKEN (1U << 1) 730 #define FW_IQ_CMD_FL1CONGEN (1U << 0) 731 732 #define FW_IQ_CMD_FL1DCAEN(x) ((x) << 15) 733 #define FW_IQ_CMD_FL1DCACPU(x) ((x) << 10) 734 #define FW_IQ_CMD_FL1FBMIN(x) ((x) << 7) 735 #define FW_IQ_CMD_FL1FBMAX(x) ((x) << 4) 736 #define FW_IQ_CMD_FL1CIDXFTHRESHO (1U << 3) 737 #define FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << 0) 738 739 struct fw_eq_eth_cmd { 740 __be32 op_to_vfn; 741 __be32 alloc_to_len16; 742 __be32 eqid_pkd; 743 __be32 physeqid_pkd; 744 __be32 fetchszm_to_iqid; 745 __be32 dcaen_to_eqsize; 746 __be64 eqaddr; 747 __be32 viid_pkd; 748 __be32 r8_lo; 749 __be64 r9; 750 }; 751 752 #define FW_EQ_ETH_CMD_PFN(x) ((x) << 8) 753 #define FW_EQ_ETH_CMD_VFN(x) ((x) << 0) 754 #define FW_EQ_ETH_CMD_ALLOC (1U << 31) 755 #define FW_EQ_ETH_CMD_FREE (1U << 30) 756 #define FW_EQ_ETH_CMD_MODIFY (1U << 29) 757 #define FW_EQ_ETH_CMD_EQSTART (1U << 28) 758 #define FW_EQ_ETH_CMD_EQSTOP (1U << 27) 759 760 #define FW_EQ_ETH_CMD_EQID(x) ((x) << 0) 761 #define FW_EQ_ETH_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff) 762 #define FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << 0) 763 #define FW_EQ_ETH_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff) 764 765 #define FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << 26) 766 #define FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << 25) 767 #define FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << 24) 768 #define FW_EQ_ETH_CMD_FETCHNS(x) ((x) << 23) 769 #define FW_EQ_ETH_CMD_FETCHRO(x) ((x) << 22) 770 #define FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << 20) 771 #define FW_EQ_ETH_CMD_CPRIO(x) ((x) << 19) 772 #define FW_EQ_ETH_CMD_ONCHIP(x) ((x) << 18) 773 #define FW_EQ_ETH_CMD_PCIECHN(x) ((x) << 16) 774 #define FW_EQ_ETH_CMD_IQID(x) ((x) << 0) 775 776 #define FW_EQ_ETH_CMD_DCAEN(x) ((x) << 31) 777 #define FW_EQ_ETH_CMD_DCACPU(x) ((x) << 26) 778 #define FW_EQ_ETH_CMD_FBMIN(x) ((x) << 23) 779 #define FW_EQ_ETH_CMD_FBMAX(x) ((x) << 20) 780 #define FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << 19) 781 #define FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << 16) 782 #define FW_EQ_ETH_CMD_EQSIZE(x) ((x) << 0) 783 784 #define FW_EQ_ETH_CMD_VIID(x) ((x) << 16) 785 786 struct fw_eq_ctrl_cmd { 787 __be32 op_to_vfn; 788 __be32 alloc_to_len16; 789 __be32 cmpliqid_eqid; 790 __be32 physeqid_pkd; 791 __be32 fetchszm_to_iqid; 792 __be32 dcaen_to_eqsize; 793 __be64 eqaddr; 794 }; 795 796 #define FW_EQ_CTRL_CMD_PFN(x) ((x) << 8) 797 #define FW_EQ_CTRL_CMD_VFN(x) ((x) << 0) 798 799 #define FW_EQ_CTRL_CMD_ALLOC (1U << 31) 800 #define FW_EQ_CTRL_CMD_FREE (1U << 30) 801 #define FW_EQ_CTRL_CMD_MODIFY (1U << 29) 802 #define FW_EQ_CTRL_CMD_EQSTART (1U << 28) 803 #define FW_EQ_CTRL_CMD_EQSTOP (1U << 27) 804 805 #define FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << 20) 806 #define FW_EQ_CTRL_CMD_EQID(x) ((x) << 0) 807 #define FW_EQ_CTRL_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff) 808 #define FW_EQ_CTRL_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff) 809 810 #define FW_EQ_CTRL_CMD_FETCHSZM (1U << 26) 811 #define FW_EQ_CTRL_CMD_STATUSPGNS (1U << 25) 812 #define FW_EQ_CTRL_CMD_STATUSPGRO (1U << 24) 813 #define FW_EQ_CTRL_CMD_FETCHNS (1U << 23) 814 #define FW_EQ_CTRL_CMD_FETCHRO (1U << 22) 815 #define FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << 20) 816 #define FW_EQ_CTRL_CMD_CPRIO(x) ((x) << 19) 817 #define FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << 18) 818 #define FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << 16) 819 #define FW_EQ_CTRL_CMD_IQID(x) ((x) << 0) 820 821 #define FW_EQ_CTRL_CMD_DCAEN(x) ((x) << 31) 822 #define FW_EQ_CTRL_CMD_DCACPU(x) ((x) << 26) 823 #define FW_EQ_CTRL_CMD_FBMIN(x) ((x) << 23) 824 #define FW_EQ_CTRL_CMD_FBMAX(x) ((x) << 20) 825 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) ((x) << 19) 826 #define FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << 16) 827 #define FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << 0) 828 829 struct fw_eq_ofld_cmd { 830 __be32 op_to_vfn; 831 __be32 alloc_to_len16; 832 __be32 eqid_pkd; 833 __be32 physeqid_pkd; 834 __be32 fetchszm_to_iqid; 835 __be32 dcaen_to_eqsize; 836 __be64 eqaddr; 837 }; 838 839 #define FW_EQ_OFLD_CMD_PFN(x) ((x) << 8) 840 #define FW_EQ_OFLD_CMD_VFN(x) ((x) << 0) 841 842 #define FW_EQ_OFLD_CMD_ALLOC (1U << 31) 843 #define FW_EQ_OFLD_CMD_FREE (1U << 30) 844 #define FW_EQ_OFLD_CMD_MODIFY (1U << 29) 845 #define FW_EQ_OFLD_CMD_EQSTART (1U << 28) 846 #define FW_EQ_OFLD_CMD_EQSTOP (1U << 27) 847 848 #define FW_EQ_OFLD_CMD_EQID(x) ((x) << 0) 849 #define FW_EQ_OFLD_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff) 850 #define FW_EQ_OFLD_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff) 851 852 #define FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << 26) 853 #define FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << 25) 854 #define FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << 24) 855 #define FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << 23) 856 #define FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << 22) 857 #define FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << 20) 858 #define FW_EQ_OFLD_CMD_CPRIO(x) ((x) << 19) 859 #define FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << 18) 860 #define FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << 16) 861 #define FW_EQ_OFLD_CMD_IQID(x) ((x) << 0) 862 863 #define FW_EQ_OFLD_CMD_DCAEN(x) ((x) << 31) 864 #define FW_EQ_OFLD_CMD_DCACPU(x) ((x) << 26) 865 #define FW_EQ_OFLD_CMD_FBMIN(x) ((x) << 23) 866 #define FW_EQ_OFLD_CMD_FBMAX(x) ((x) << 20) 867 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) ((x) << 19) 868 #define FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << 16) 869 #define FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << 0) 870 871 /* 872 * Macros for VIID parsing: 873 * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number 874 */ 875 #define FW_VIID_PFN_GET(x) (((x) >> 8) & 0x7) 876 #define FW_VIID_VIVLD_GET(x) (((x) >> 7) & 0x1) 877 #define FW_VIID_VIN_GET(x) (((x) >> 0) & 0x7F) 878 879 struct fw_vi_cmd { 880 __be32 op_to_vfn; 881 __be32 alloc_to_len16; 882 __be16 type_viid; 883 u8 mac[6]; 884 u8 portid_pkd; 885 u8 nmac; 886 u8 nmac0[6]; 887 __be16 rsssize_pkd; 888 u8 nmac1[6]; 889 __be16 idsiiq_pkd; 890 u8 nmac2[6]; 891 __be16 idseiq_pkd; 892 u8 nmac3[6]; 893 __be64 r9; 894 __be64 r10; 895 }; 896 897 #define FW_VI_CMD_PFN(x) ((x) << 8) 898 #define FW_VI_CMD_VFN(x) ((x) << 0) 899 #define FW_VI_CMD_ALLOC (1U << 31) 900 #define FW_VI_CMD_FREE (1U << 30) 901 #define FW_VI_CMD_VIID(x) ((x) << 0) 902 #define FW_VI_CMD_VIID_GET(x) ((x) & 0xfff) 903 #define FW_VI_CMD_PORTID(x) ((x) << 4) 904 #define FW_VI_CMD_PORTID_GET(x) (((x) >> 4) & 0xf) 905 #define FW_VI_CMD_RSSSIZE_GET(x) (((x) >> 0) & 0x7ff) 906 907 /* Special VI_MAC command index ids */ 908 #define FW_VI_MAC_ADD_MAC 0x3FF 909 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 910 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD 911 #define FW_CLS_TCAM_NUM_ENTRIES 336 912 913 enum fw_vi_mac_smac { 914 FW_VI_MAC_MPS_TCAM_ENTRY, 915 FW_VI_MAC_MPS_TCAM_ONLY, 916 FW_VI_MAC_SMT_ONLY, 917 FW_VI_MAC_SMT_AND_MPSTCAM 918 }; 919 920 enum fw_vi_mac_result { 921 FW_VI_MAC_R_SUCCESS, 922 FW_VI_MAC_R_F_NONEXISTENT_NOMEM, 923 FW_VI_MAC_R_SMAC_FAIL, 924 FW_VI_MAC_R_F_ACL_CHECK 925 }; 926 927 struct fw_vi_mac_cmd { 928 __be32 op_to_viid; 929 __be32 freemacs_to_len16; 930 union fw_vi_mac { 931 struct fw_vi_mac_exact { 932 __be16 valid_to_idx; 933 u8 macaddr[6]; 934 } exact[7]; 935 struct fw_vi_mac_hash { 936 __be64 hashvec; 937 } hash; 938 } u; 939 }; 940 941 #define FW_VI_MAC_CMD_VIID(x) ((x) << 0) 942 #define FW_VI_MAC_CMD_FREEMACS(x) ((x) << 31) 943 #define FW_VI_MAC_CMD_HASHVECEN (1U << 23) 944 #define FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << 22) 945 #define FW_VI_MAC_CMD_VALID (1U << 15) 946 #define FW_VI_MAC_CMD_PRIO(x) ((x) << 12) 947 #define FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << 10) 948 #define FW_VI_MAC_CMD_SMAC_RESULT_GET(x) (((x) >> 10) & 0x3) 949 #define FW_VI_MAC_CMD_IDX(x) ((x) << 0) 950 #define FW_VI_MAC_CMD_IDX_GET(x) (((x) >> 0) & 0x3ff) 951 952 #define FW_RXMODE_MTU_NO_CHG 65535 953 954 struct fw_vi_rxmode_cmd { 955 __be32 op_to_viid; 956 __be32 retval_len16; 957 __be32 mtu_to_vlanexen; 958 __be32 r4_lo; 959 }; 960 961 #define FW_VI_RXMODE_CMD_VIID(x) ((x) << 0) 962 #define FW_VI_RXMODE_CMD_MTU_MASK 0xffff 963 #define FW_VI_RXMODE_CMD_MTU(x) ((x) << 16) 964 #define FW_VI_RXMODE_CMD_PROMISCEN_MASK 0x3 965 #define FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << 14) 966 #define FW_VI_RXMODE_CMD_ALLMULTIEN_MASK 0x3 967 #define FW_VI_RXMODE_CMD_ALLMULTIEN(x) ((x) << 12) 968 #define FW_VI_RXMODE_CMD_BROADCASTEN_MASK 0x3 969 #define FW_VI_RXMODE_CMD_BROADCASTEN(x) ((x) << 10) 970 #define FW_VI_RXMODE_CMD_VLANEXEN_MASK 0x3 971 #define FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << 8) 972 973 struct fw_vi_enable_cmd { 974 __be32 op_to_viid; 975 __be32 ien_to_len16; 976 __be16 blinkdur; 977 __be16 r3; 978 __be32 r4; 979 }; 980 981 #define FW_VI_ENABLE_CMD_VIID(x) ((x) << 0) 982 #define FW_VI_ENABLE_CMD_IEN(x) ((x) << 31) 983 #define FW_VI_ENABLE_CMD_EEN(x) ((x) << 30) 984 #define FW_VI_ENABLE_CMD_LED (1U << 29) 985 986 /* VI VF stats offset definitions */ 987 #define VI_VF_NUM_STATS 16 988 enum fw_vi_stats_vf_index { 989 FW_VI_VF_STAT_TX_BCAST_BYTES_IX, 990 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, 991 FW_VI_VF_STAT_TX_MCAST_BYTES_IX, 992 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, 993 FW_VI_VF_STAT_TX_UCAST_BYTES_IX, 994 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, 995 FW_VI_VF_STAT_TX_DROP_FRAMES_IX, 996 FW_VI_VF_STAT_TX_OFLD_BYTES_IX, 997 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, 998 FW_VI_VF_STAT_RX_BCAST_BYTES_IX, 999 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, 1000 FW_VI_VF_STAT_RX_MCAST_BYTES_IX, 1001 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, 1002 FW_VI_VF_STAT_RX_UCAST_BYTES_IX, 1003 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, 1004 FW_VI_VF_STAT_RX_ERR_FRAMES_IX 1005 }; 1006 1007 /* VI PF stats offset definitions */ 1008 #define VI_PF_NUM_STATS 17 1009 enum fw_vi_stats_pf_index { 1010 FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 1011 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 1012 FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 1013 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 1014 FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 1015 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 1016 FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 1017 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 1018 FW_VI_PF_STAT_RX_BYTES_IX, 1019 FW_VI_PF_STAT_RX_FRAMES_IX, 1020 FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 1021 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 1022 FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 1023 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 1024 FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 1025 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 1026 FW_VI_PF_STAT_RX_ERR_FRAMES_IX 1027 }; 1028 1029 struct fw_vi_stats_cmd { 1030 __be32 op_to_viid; 1031 __be32 retval_len16; 1032 union fw_vi_stats { 1033 struct fw_vi_stats_ctl { 1034 __be16 nstats_ix; 1035 __be16 r6; 1036 __be32 r7; 1037 __be64 stat0; 1038 __be64 stat1; 1039 __be64 stat2; 1040 __be64 stat3; 1041 __be64 stat4; 1042 __be64 stat5; 1043 } ctl; 1044 struct fw_vi_stats_pf { 1045 __be64 tx_bcast_bytes; 1046 __be64 tx_bcast_frames; 1047 __be64 tx_mcast_bytes; 1048 __be64 tx_mcast_frames; 1049 __be64 tx_ucast_bytes; 1050 __be64 tx_ucast_frames; 1051 __be64 tx_offload_bytes; 1052 __be64 tx_offload_frames; 1053 __be64 rx_pf_bytes; 1054 __be64 rx_pf_frames; 1055 __be64 rx_bcast_bytes; 1056 __be64 rx_bcast_frames; 1057 __be64 rx_mcast_bytes; 1058 __be64 rx_mcast_frames; 1059 __be64 rx_ucast_bytes; 1060 __be64 rx_ucast_frames; 1061 __be64 rx_err_frames; 1062 } pf; 1063 struct fw_vi_stats_vf { 1064 __be64 tx_bcast_bytes; 1065 __be64 tx_bcast_frames; 1066 __be64 tx_mcast_bytes; 1067 __be64 tx_mcast_frames; 1068 __be64 tx_ucast_bytes; 1069 __be64 tx_ucast_frames; 1070 __be64 tx_drop_frames; 1071 __be64 tx_offload_bytes; 1072 __be64 tx_offload_frames; 1073 __be64 rx_bcast_bytes; 1074 __be64 rx_bcast_frames; 1075 __be64 rx_mcast_bytes; 1076 __be64 rx_mcast_frames; 1077 __be64 rx_ucast_bytes; 1078 __be64 rx_ucast_frames; 1079 __be64 rx_err_frames; 1080 } vf; 1081 } u; 1082 }; 1083 1084 #define FW_VI_STATS_CMD_VIID(x) ((x) << 0) 1085 #define FW_VI_STATS_CMD_NSTATS(x) ((x) << 12) 1086 #define FW_VI_STATS_CMD_IX(x) ((x) << 0) 1087 1088 struct fw_acl_mac_cmd { 1089 __be32 op_to_vfn; 1090 __be32 en_to_len16; 1091 u8 nmac; 1092 u8 r3[7]; 1093 __be16 r4; 1094 u8 macaddr0[6]; 1095 __be16 r5; 1096 u8 macaddr1[6]; 1097 __be16 r6; 1098 u8 macaddr2[6]; 1099 __be16 r7; 1100 u8 macaddr3[6]; 1101 }; 1102 1103 #define FW_ACL_MAC_CMD_PFN(x) ((x) << 8) 1104 #define FW_ACL_MAC_CMD_VFN(x) ((x) << 0) 1105 #define FW_ACL_MAC_CMD_EN(x) ((x) << 31) 1106 1107 struct fw_acl_vlan_cmd { 1108 __be32 op_to_vfn; 1109 __be32 en_to_len16; 1110 u8 nvlan; 1111 u8 dropnovlan_fm; 1112 u8 r3_lo[6]; 1113 __be16 vlanid[16]; 1114 }; 1115 1116 #define FW_ACL_VLAN_CMD_PFN(x) ((x) << 8) 1117 #define FW_ACL_VLAN_CMD_VFN(x) ((x) << 0) 1118 #define FW_ACL_VLAN_CMD_EN(x) ((x) << 31) 1119 #define FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << 7) 1120 #define FW_ACL_VLAN_CMD_FM(x) ((x) << 6) 1121 1122 enum fw_port_cap { 1123 FW_PORT_CAP_SPEED_100M = 0x0001, 1124 FW_PORT_CAP_SPEED_1G = 0x0002, 1125 FW_PORT_CAP_SPEED_2_5G = 0x0004, 1126 FW_PORT_CAP_SPEED_10G = 0x0008, 1127 FW_PORT_CAP_SPEED_40G = 0x0010, 1128 FW_PORT_CAP_SPEED_100G = 0x0020, 1129 FW_PORT_CAP_FC_RX = 0x0040, 1130 FW_PORT_CAP_FC_TX = 0x0080, 1131 FW_PORT_CAP_ANEG = 0x0100, 1132 FW_PORT_CAP_MDI_0 = 0x0200, 1133 FW_PORT_CAP_MDI_1 = 0x0400, 1134 FW_PORT_CAP_BEAN = 0x0800, 1135 FW_PORT_CAP_PMA_LPBK = 0x1000, 1136 FW_PORT_CAP_PCS_LPBK = 0x2000, 1137 FW_PORT_CAP_PHYXS_LPBK = 0x4000, 1138 FW_PORT_CAP_FAR_END_LPBK = 0x8000, 1139 }; 1140 1141 enum fw_port_mdi { 1142 FW_PORT_MDI_UNCHANGED, 1143 FW_PORT_MDI_AUTO, 1144 FW_PORT_MDI_F_STRAIGHT, 1145 FW_PORT_MDI_F_CROSSOVER 1146 }; 1147 1148 #define FW_PORT_MDI(x) ((x) << 9) 1149 1150 enum fw_port_action { 1151 FW_PORT_ACTION_L1_CFG = 0x0001, 1152 FW_PORT_ACTION_L2_CFG = 0x0002, 1153 FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 1154 FW_PORT_ACTION_L2_PPP_CFG = 0x0004, 1155 FW_PORT_ACTION_L2_DCB_CFG = 0x0005, 1156 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, 1157 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, 1158 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, 1159 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, 1160 FW_PORT_ACTION_L1_LPBK = 0x0021, 1161 FW_PORT_ACTION_L1_PMA_LPBK = 0x0022, 1162 FW_PORT_ACTION_L1_PCS_LPBK = 0x0023, 1163 FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024, 1164 FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025, 1165 FW_PORT_ACTION_PHY_RESET = 0x0040, 1166 FW_PORT_ACTION_PMA_RESET = 0x0041, 1167 FW_PORT_ACTION_PCS_RESET = 0x0042, 1168 FW_PORT_ACTION_PHYXS_RESET = 0x0043, 1169 FW_PORT_ACTION_DTEXS_REEST = 0x0044, 1170 FW_PORT_ACTION_AN_RESET = 0x0045 1171 }; 1172 1173 enum fw_port_l2cfg_ctlbf { 1174 FW_PORT_L2_CTLBF_OVLAN0 = 0x01, 1175 FW_PORT_L2_CTLBF_OVLAN1 = 0x02, 1176 FW_PORT_L2_CTLBF_OVLAN2 = 0x04, 1177 FW_PORT_L2_CTLBF_OVLAN3 = 0x08, 1178 FW_PORT_L2_CTLBF_IVLAN = 0x10, 1179 FW_PORT_L2_CTLBF_TXIPG = 0x20 1180 }; 1181 1182 enum fw_port_dcb_cfg { 1183 FW_PORT_DCB_CFG_PG = 0x01, 1184 FW_PORT_DCB_CFG_PFC = 0x02, 1185 FW_PORT_DCB_CFG_APPL = 0x04 1186 }; 1187 1188 enum fw_port_dcb_cfg_rc { 1189 FW_PORT_DCB_CFG_SUCCESS = 0x0, 1190 FW_PORT_DCB_CFG_ERROR = 0x1 1191 }; 1192 1193 struct fw_port_cmd { 1194 __be32 op_to_portid; 1195 __be32 action_to_len16; 1196 union fw_port { 1197 struct fw_port_l1cfg { 1198 __be32 rcap; 1199 __be32 r; 1200 } l1cfg; 1201 struct fw_port_l2cfg { 1202 __be16 ctlbf_to_ivlan0; 1203 __be16 ivlantype; 1204 __be32 txipg_pkd; 1205 __be16 ovlan0mask; 1206 __be16 ovlan0type; 1207 __be16 ovlan1mask; 1208 __be16 ovlan1type; 1209 __be16 ovlan2mask; 1210 __be16 ovlan2type; 1211 __be16 ovlan3mask; 1212 __be16 ovlan3type; 1213 } l2cfg; 1214 struct fw_port_info { 1215 __be32 lstatus_to_modtype; 1216 __be16 pcap; 1217 __be16 acap; 1218 __be16 mtu; 1219 __u8 cbllen; 1220 __u8 r9; 1221 __be32 r10; 1222 __be64 r11; 1223 } info; 1224 struct fw_port_ppp { 1225 __be32 pppen_to_ncsich; 1226 __be32 r11; 1227 } ppp; 1228 struct fw_port_dcb { 1229 __be16 cfg; 1230 u8 up_map; 1231 u8 sf_cfgrc; 1232 __be16 prot_ix; 1233 u8 pe7_to_pe0; 1234 u8 numTCPFCs; 1235 __be32 pgid0_to_pgid7; 1236 __be32 numTCs_oui; 1237 u8 pgpc[8]; 1238 } dcb; 1239 } u; 1240 }; 1241 1242 #define FW_PORT_CMD_READ (1U << 22) 1243 1244 #define FW_PORT_CMD_PORTID(x) ((x) << 0) 1245 #define FW_PORT_CMD_PORTID_GET(x) (((x) >> 0) & 0xf) 1246 1247 #define FW_PORT_CMD_ACTION(x) ((x) << 16) 1248 #define FW_PORT_CMD_ACTION_GET(x) (((x) >> 16) & 0xffff) 1249 1250 #define FW_PORT_CMD_CTLBF(x) ((x) << 10) 1251 #define FW_PORT_CMD_OVLAN3(x) ((x) << 7) 1252 #define FW_PORT_CMD_OVLAN2(x) ((x) << 6) 1253 #define FW_PORT_CMD_OVLAN1(x) ((x) << 5) 1254 #define FW_PORT_CMD_OVLAN0(x) ((x) << 4) 1255 #define FW_PORT_CMD_IVLAN0(x) ((x) << 3) 1256 1257 #define FW_PORT_CMD_TXIPG(x) ((x) << 19) 1258 1259 #define FW_PORT_CMD_LSTATUS (1U << 31) 1260 #define FW_PORT_CMD_LSPEED(x) ((x) << 24) 1261 #define FW_PORT_CMD_LSPEED_GET(x) (((x) >> 24) & 0x3f) 1262 #define FW_PORT_CMD_TXPAUSE (1U << 23) 1263 #define FW_PORT_CMD_RXPAUSE (1U << 22) 1264 #define FW_PORT_CMD_MDIOCAP (1U << 21) 1265 #define FW_PORT_CMD_MDIOADDR_GET(x) (((x) >> 16) & 0x1f) 1266 #define FW_PORT_CMD_LPTXPAUSE (1U << 15) 1267 #define FW_PORT_CMD_LPRXPAUSE (1U << 14) 1268 #define FW_PORT_CMD_PTYPE_MASK 0x1f 1269 #define FW_PORT_CMD_PTYPE_GET(x) (((x) >> 8) & FW_PORT_CMD_PTYPE_MASK) 1270 #define FW_PORT_CMD_MODTYPE_MASK 0x1f 1271 #define FW_PORT_CMD_MODTYPE_GET(x) (((x) >> 0) & FW_PORT_CMD_MODTYPE_MASK) 1272 1273 #define FW_PORT_CMD_PPPEN(x) ((x) << 31) 1274 #define FW_PORT_CMD_TPSRC(x) ((x) << 28) 1275 #define FW_PORT_CMD_NCSISRC(x) ((x) << 24) 1276 1277 #define FW_PORT_CMD_CH0(x) ((x) << 20) 1278 #define FW_PORT_CMD_CH1(x) ((x) << 16) 1279 #define FW_PORT_CMD_CH2(x) ((x) << 12) 1280 #define FW_PORT_CMD_CH3(x) ((x) << 8) 1281 #define FW_PORT_CMD_NCSICH(x) ((x) << 4) 1282 1283 enum fw_port_type { 1284 FW_PORT_TYPE_FIBER_XFI, 1285 FW_PORT_TYPE_FIBER_XAUI, 1286 FW_PORT_TYPE_BT_SGMII, 1287 FW_PORT_TYPE_BT_XFI, 1288 FW_PORT_TYPE_BT_XAUI, 1289 FW_PORT_TYPE_KX4, 1290 FW_PORT_TYPE_CX4, 1291 FW_PORT_TYPE_KX, 1292 FW_PORT_TYPE_KR, 1293 FW_PORT_TYPE_SFP, 1294 FW_PORT_TYPE_BP_AP, 1295 FW_PORT_TYPE_BP4_AP, 1296 1297 FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_MASK 1298 }; 1299 1300 enum fw_port_module_type { 1301 FW_PORT_MOD_TYPE_NA, 1302 FW_PORT_MOD_TYPE_LR, 1303 FW_PORT_MOD_TYPE_SR, 1304 FW_PORT_MOD_TYPE_ER, 1305 FW_PORT_MOD_TYPE_TWINAX_PASSIVE, 1306 FW_PORT_MOD_TYPE_TWINAX_ACTIVE, 1307 FW_PORT_MOD_TYPE_LRM, 1308 1309 FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_MASK 1310 }; 1311 1312 /* port stats */ 1313 #define FW_NUM_PORT_STATS 50 1314 #define FW_NUM_PORT_TX_STATS 23 1315 #define FW_NUM_PORT_RX_STATS 27 1316 1317 enum fw_port_stats_tx_index { 1318 FW_STAT_TX_PORT_BYTES_IX, 1319 FW_STAT_TX_PORT_FRAMES_IX, 1320 FW_STAT_TX_PORT_BCAST_IX, 1321 FW_STAT_TX_PORT_MCAST_IX, 1322 FW_STAT_TX_PORT_UCAST_IX, 1323 FW_STAT_TX_PORT_ERROR_IX, 1324 FW_STAT_TX_PORT_64B_IX, 1325 FW_STAT_TX_PORT_65B_127B_IX, 1326 FW_STAT_TX_PORT_128B_255B_IX, 1327 FW_STAT_TX_PORT_256B_511B_IX, 1328 FW_STAT_TX_PORT_512B_1023B_IX, 1329 FW_STAT_TX_PORT_1024B_1518B_IX, 1330 FW_STAT_TX_PORT_1519B_MAX_IX, 1331 FW_STAT_TX_PORT_DROP_IX, 1332 FW_STAT_TX_PORT_PAUSE_IX, 1333 FW_STAT_TX_PORT_PPP0_IX, 1334 FW_STAT_TX_PORT_PPP1_IX, 1335 FW_STAT_TX_PORT_PPP2_IX, 1336 FW_STAT_TX_PORT_PPP3_IX, 1337 FW_STAT_TX_PORT_PPP4_IX, 1338 FW_STAT_TX_PORT_PPP5_IX, 1339 FW_STAT_TX_PORT_PPP6_IX, 1340 FW_STAT_TX_PORT_PPP7_IX 1341 }; 1342 1343 enum fw_port_stat_rx_index { 1344 FW_STAT_RX_PORT_BYTES_IX, 1345 FW_STAT_RX_PORT_FRAMES_IX, 1346 FW_STAT_RX_PORT_BCAST_IX, 1347 FW_STAT_RX_PORT_MCAST_IX, 1348 FW_STAT_RX_PORT_UCAST_IX, 1349 FW_STAT_RX_PORT_MTU_ERROR_IX, 1350 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 1351 FW_STAT_RX_PORT_CRC_ERROR_IX, 1352 FW_STAT_RX_PORT_LEN_ERROR_IX, 1353 FW_STAT_RX_PORT_SYM_ERROR_IX, 1354 FW_STAT_RX_PORT_64B_IX, 1355 FW_STAT_RX_PORT_65B_127B_IX, 1356 FW_STAT_RX_PORT_128B_255B_IX, 1357 FW_STAT_RX_PORT_256B_511B_IX, 1358 FW_STAT_RX_PORT_512B_1023B_IX, 1359 FW_STAT_RX_PORT_1024B_1518B_IX, 1360 FW_STAT_RX_PORT_1519B_MAX_IX, 1361 FW_STAT_RX_PORT_PAUSE_IX, 1362 FW_STAT_RX_PORT_PPP0_IX, 1363 FW_STAT_RX_PORT_PPP1_IX, 1364 FW_STAT_RX_PORT_PPP2_IX, 1365 FW_STAT_RX_PORT_PPP3_IX, 1366 FW_STAT_RX_PORT_PPP4_IX, 1367 FW_STAT_RX_PORT_PPP5_IX, 1368 FW_STAT_RX_PORT_PPP6_IX, 1369 FW_STAT_RX_PORT_PPP7_IX, 1370 FW_STAT_RX_PORT_LESS_64B_IX 1371 }; 1372 1373 struct fw_port_stats_cmd { 1374 __be32 op_to_portid; 1375 __be32 retval_len16; 1376 union fw_port_stats { 1377 struct fw_port_stats_ctl { 1378 u8 nstats_bg_bm; 1379 u8 tx_ix; 1380 __be16 r6; 1381 __be32 r7; 1382 __be64 stat0; 1383 __be64 stat1; 1384 __be64 stat2; 1385 __be64 stat3; 1386 __be64 stat4; 1387 __be64 stat5; 1388 } ctl; 1389 struct fw_port_stats_all { 1390 __be64 tx_bytes; 1391 __be64 tx_frames; 1392 __be64 tx_bcast; 1393 __be64 tx_mcast; 1394 __be64 tx_ucast; 1395 __be64 tx_error; 1396 __be64 tx_64b; 1397 __be64 tx_65b_127b; 1398 __be64 tx_128b_255b; 1399 __be64 tx_256b_511b; 1400 __be64 tx_512b_1023b; 1401 __be64 tx_1024b_1518b; 1402 __be64 tx_1519b_max; 1403 __be64 tx_drop; 1404 __be64 tx_pause; 1405 __be64 tx_ppp0; 1406 __be64 tx_ppp1; 1407 __be64 tx_ppp2; 1408 __be64 tx_ppp3; 1409 __be64 tx_ppp4; 1410 __be64 tx_ppp5; 1411 __be64 tx_ppp6; 1412 __be64 tx_ppp7; 1413 __be64 rx_bytes; 1414 __be64 rx_frames; 1415 __be64 rx_bcast; 1416 __be64 rx_mcast; 1417 __be64 rx_ucast; 1418 __be64 rx_mtu_error; 1419 __be64 rx_mtu_crc_error; 1420 __be64 rx_crc_error; 1421 __be64 rx_len_error; 1422 __be64 rx_sym_error; 1423 __be64 rx_64b; 1424 __be64 rx_65b_127b; 1425 __be64 rx_128b_255b; 1426 __be64 rx_256b_511b; 1427 __be64 rx_512b_1023b; 1428 __be64 rx_1024b_1518b; 1429 __be64 rx_1519b_max; 1430 __be64 rx_pause; 1431 __be64 rx_ppp0; 1432 __be64 rx_ppp1; 1433 __be64 rx_ppp2; 1434 __be64 rx_ppp3; 1435 __be64 rx_ppp4; 1436 __be64 rx_ppp5; 1437 __be64 rx_ppp6; 1438 __be64 rx_ppp7; 1439 __be64 rx_less_64b; 1440 __be64 rx_bg_drop; 1441 __be64 rx_bg_trunc; 1442 } all; 1443 } u; 1444 }; 1445 1446 #define FW_PORT_STATS_CMD_NSTATS(x) ((x) << 4) 1447 #define FW_PORT_STATS_CMD_BG_BM(x) ((x) << 0) 1448 #define FW_PORT_STATS_CMD_TX(x) ((x) << 7) 1449 #define FW_PORT_STATS_CMD_IX(x) ((x) << 0) 1450 1451 /* port loopback stats */ 1452 #define FW_NUM_LB_STATS 16 1453 enum fw_port_lb_stats_index { 1454 FW_STAT_LB_PORT_BYTES_IX, 1455 FW_STAT_LB_PORT_FRAMES_IX, 1456 FW_STAT_LB_PORT_BCAST_IX, 1457 FW_STAT_LB_PORT_MCAST_IX, 1458 FW_STAT_LB_PORT_UCAST_IX, 1459 FW_STAT_LB_PORT_ERROR_IX, 1460 FW_STAT_LB_PORT_64B_IX, 1461 FW_STAT_LB_PORT_65B_127B_IX, 1462 FW_STAT_LB_PORT_128B_255B_IX, 1463 FW_STAT_LB_PORT_256B_511B_IX, 1464 FW_STAT_LB_PORT_512B_1023B_IX, 1465 FW_STAT_LB_PORT_1024B_1518B_IX, 1466 FW_STAT_LB_PORT_1519B_MAX_IX, 1467 FW_STAT_LB_PORT_DROP_FRAMES_IX 1468 }; 1469 1470 struct fw_port_lb_stats_cmd { 1471 __be32 op_to_lbport; 1472 __be32 retval_len16; 1473 union fw_port_lb_stats { 1474 struct fw_port_lb_stats_ctl { 1475 u8 nstats_bg_bm; 1476 u8 ix_pkd; 1477 __be16 r6; 1478 __be32 r7; 1479 __be64 stat0; 1480 __be64 stat1; 1481 __be64 stat2; 1482 __be64 stat3; 1483 __be64 stat4; 1484 __be64 stat5; 1485 } ctl; 1486 struct fw_port_lb_stats_all { 1487 __be64 tx_bytes; 1488 __be64 tx_frames; 1489 __be64 tx_bcast; 1490 __be64 tx_mcast; 1491 __be64 tx_ucast; 1492 __be64 tx_error; 1493 __be64 tx_64b; 1494 __be64 tx_65b_127b; 1495 __be64 tx_128b_255b; 1496 __be64 tx_256b_511b; 1497 __be64 tx_512b_1023b; 1498 __be64 tx_1024b_1518b; 1499 __be64 tx_1519b_max; 1500 __be64 rx_lb_drop; 1501 __be64 rx_lb_trunc; 1502 } all; 1503 } u; 1504 }; 1505 1506 #define FW_PORT_LB_STATS_CMD_LBPORT(x) ((x) << 0) 1507 #define FW_PORT_LB_STATS_CMD_NSTATS(x) ((x) << 4) 1508 #define FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << 0) 1509 #define FW_PORT_LB_STATS_CMD_IX(x) ((x) << 0) 1510 1511 struct fw_rss_ind_tbl_cmd { 1512 __be32 op_to_viid; 1513 #define FW_RSS_IND_TBL_CMD_VIID(x) ((x) << 0) 1514 __be32 retval_len16; 1515 __be16 niqid; 1516 __be16 startidx; 1517 __be32 r3; 1518 __be32 iq0_to_iq2; 1519 #define FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << 20) 1520 #define FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << 10) 1521 #define FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << 0) 1522 __be32 iq3_to_iq5; 1523 __be32 iq6_to_iq8; 1524 __be32 iq9_to_iq11; 1525 __be32 iq12_to_iq14; 1526 __be32 iq15_to_iq17; 1527 __be32 iq18_to_iq20; 1528 __be32 iq21_to_iq23; 1529 __be32 iq24_to_iq26; 1530 __be32 iq27_to_iq29; 1531 __be32 iq30_iq31; 1532 __be32 r15_lo; 1533 }; 1534 1535 struct fw_rss_glb_config_cmd { 1536 __be32 op_to_write; 1537 __be32 retval_len16; 1538 union fw_rss_glb_config { 1539 struct fw_rss_glb_config_manual { 1540 __be32 mode_pkd; 1541 __be32 r3; 1542 __be64 r4; 1543 __be64 r5; 1544 } manual; 1545 struct fw_rss_glb_config_basicvirtual { 1546 __be32 mode_pkd; 1547 __be32 synmapen_to_hashtoeplitz; 1548 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN (1U << 8) 1549 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 (1U << 7) 1550 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 (1U << 6) 1551 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 (1U << 5) 1552 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 (1U << 4) 1553 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN (1U << 3) 1554 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN (1U << 2) 1555 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP (1U << 1) 1556 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ (1U << 0) 1557 __be64 r8; 1558 __be64 r9; 1559 } basicvirtual; 1560 } u; 1561 }; 1562 1563 #define FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << 28) 1564 #define FW_RSS_GLB_CONFIG_CMD_MODE_GET(x) (((x) >> 28) & 0xf) 1565 1566 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 1567 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 1568 1569 struct fw_rss_vi_config_cmd { 1570 __be32 op_to_viid; 1571 #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0) 1572 __be32 retval_len16; 1573 union fw_rss_vi_config { 1574 struct fw_rss_vi_config_manual { 1575 __be64 r3; 1576 __be64 r4; 1577 __be64 r5; 1578 } manual; 1579 struct fw_rss_vi_config_basicvirtual { 1580 __be32 r6; 1581 __be32 defaultq_to_udpen; 1582 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) ((x) << 16) 1583 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_GET(x) (((x) >> 16) & 0x3ff) 1584 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN (1U << 4) 1585 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN (1U << 3) 1586 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN (1U << 2) 1587 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN (1U << 1) 1588 #define FW_RSS_VI_CONFIG_CMD_UDPEN (1U << 0) 1589 __be64 r9; 1590 __be64 r10; 1591 } basicvirtual; 1592 } u; 1593 }; 1594 1595 enum fw_error_type { 1596 FW_ERROR_TYPE_EXCEPTION = 0x0, 1597 FW_ERROR_TYPE_HWMODULE = 0x1, 1598 FW_ERROR_TYPE_WR = 0x2, 1599 FW_ERROR_TYPE_ACL = 0x3, 1600 }; 1601 1602 struct fw_error_cmd { 1603 __be32 op_to_type; 1604 __be32 len16_pkd; 1605 union fw_error { 1606 struct fw_error_exception { 1607 __be32 info[6]; 1608 } exception; 1609 struct fw_error_hwmodule { 1610 __be32 regaddr; 1611 __be32 regval; 1612 } hwmodule; 1613 struct fw_error_wr { 1614 __be16 cidx; 1615 __be16 pfn_vfn; 1616 __be32 eqid; 1617 u8 wrhdr[16]; 1618 } wr; 1619 struct fw_error_acl { 1620 __be16 cidx; 1621 __be16 pfn_vfn; 1622 __be32 eqid; 1623 __be16 mv_pkd; 1624 u8 val[6]; 1625 __be64 r4; 1626 } acl; 1627 } u; 1628 }; 1629 1630 struct fw_debug_cmd { 1631 __be32 op_type; 1632 #define FW_DEBUG_CMD_TYPE_GET(x) ((x) & 0xff) 1633 __be32 len16_pkd; 1634 union fw_debug { 1635 struct fw_debug_assert { 1636 __be32 fcid; 1637 __be32 line; 1638 __be32 x; 1639 __be32 y; 1640 u8 filename_0_7[8]; 1641 u8 filename_8_15[8]; 1642 __be64 r3; 1643 } assert; 1644 struct fw_debug_prt { 1645 __be16 dprtstridx; 1646 __be16 r3[3]; 1647 __be32 dprtstrparam0; 1648 __be32 dprtstrparam1; 1649 __be32 dprtstrparam2; 1650 __be32 dprtstrparam3; 1651 } prt; 1652 } u; 1653 }; 1654 1655 #define FW_PCIE_FW_ERR (1U << 31) 1656 #define FW_PCIE_FW_INIT (1U << 30) 1657 #define FW_PCIE_FW_HALT (1U << 29) 1658 #define FW_PCIE_FW_MASTER_VLD (1U << 15) 1659 #define FW_PCIE_FW_MASTER_MASK 0x7 1660 #define FW_PCIE_FW_MASTER_SHIFT 12 1661 #define FW_PCIE_FW_MASTER(x) ((x) << FW_PCIE_FW_MASTER_SHIFT) 1662 #define FW_PCIE_FW_MASTER_GET(x) (((x) >> FW_PCIE_FW_MASTER_SHIFT) & \ 1663 FW_PCIE_FW_MASTER_MASK) 1664 1665 struct fw_hdr { 1666 u8 ver; 1667 u8 reserved1; 1668 __be16 len512; /* bin length in units of 512-bytes */ 1669 __be32 fw_ver; /* firmware version */ 1670 __be32 tp_microcode_ver; 1671 u8 intfver_nic; 1672 u8 intfver_vnic; 1673 u8 intfver_ofld; 1674 u8 intfver_ri; 1675 u8 intfver_iscsipdu; 1676 u8 intfver_iscsi; 1677 u8 intfver_fcoe; 1678 u8 reserved2; 1679 __u32 reserved3; 1680 __u32 reserved4; 1681 __u32 reserved5; 1682 __be32 flags; 1683 __be32 reserved6[23]; 1684 }; 1685 1686 #define FW_HDR_FW_VER_MAJOR_GET(x) (((x) >> 24) & 0xff) 1687 #define FW_HDR_FW_VER_MINOR_GET(x) (((x) >> 16) & 0xff) 1688 #define FW_HDR_FW_VER_MICRO_GET(x) (((x) >> 8) & 0xff) 1689 #define FW_HDR_FW_VER_BUILD_GET(x) (((x) >> 0) & 0xff) 1690 1691 enum fw_hdr_flags { 1692 FW_HDR_FLAGS_RESET_HALT = 0x00000001, 1693 }; 1694 1695 #endif /* _T4FW_INTERFACE_H_ */ 1696