1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2010 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __T4_REGS_H 36 #define __T4_REGS_H 37 38 #define MYPF_BASE 0x1b000 39 #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr)) 40 41 #define PF0_BASE 0x1e000 42 #define PF0_REG(reg_addr) (PF0_BASE + (reg_addr)) 43 44 #define PF_STRIDE 0x400 45 #define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE) 46 #define PF_REG(idx, reg) (PF_BASE(idx) + (reg)) 47 48 #define MYPORT_BASE 0x1c000 49 #define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr)) 50 51 #define PORT0_BASE 0x20000 52 #define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr)) 53 54 #define PORT_STRIDE 0x2000 55 #define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE) 56 #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg)) 57 58 #define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR) 59 #define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx) 60 61 #define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) 62 #define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) 63 #define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) 64 #define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) 65 66 #define SGE_PF_KDOORBELL 0x0 67 #define QID_MASK 0xffff8000U 68 #define QID_SHIFT 15 69 #define QID(x) ((x) << QID_SHIFT) 70 #define DBPRIO(x) ((x) << 14) 71 #define PIDX_MASK 0x00003fffU 72 #define PIDX_SHIFT 0 73 #define PIDX(x) ((x) << PIDX_SHIFT) 74 75 #define SGE_PF_GTS 0x4 76 #define INGRESSQID_MASK 0xffff0000U 77 #define INGRESSQID_SHIFT 16 78 #define INGRESSQID(x) ((x) << INGRESSQID_SHIFT) 79 #define TIMERREG_MASK 0x0000e000U 80 #define TIMERREG_SHIFT 13 81 #define TIMERREG(x) ((x) << TIMERREG_SHIFT) 82 #define SEINTARM_MASK 0x00001000U 83 #define SEINTARM_SHIFT 12 84 #define SEINTARM(x) ((x) << SEINTARM_SHIFT) 85 #define CIDXINC_MASK 0x00000fffU 86 #define CIDXINC_SHIFT 0 87 #define CIDXINC(x) ((x) << CIDXINC_SHIFT) 88 89 #define X_RXPKTCPLMODE_SPLIT 1 90 #define X_INGPADBOUNDARY_SHIFT 5 91 92 #define SGE_CONTROL 0x1008 93 #define DCASYSTYPE 0x00080000U 94 #define RXPKTCPLMODE_MASK 0x00040000U 95 #define RXPKTCPLMODE_SHIFT 18 96 #define RXPKTCPLMODE(x) ((x) << RXPKTCPLMODE_SHIFT) 97 #define EGRSTATUSPAGESIZE_MASK 0x00020000U 98 #define EGRSTATUSPAGESIZE_SHIFT 17 99 #define EGRSTATUSPAGESIZE(x) ((x) << EGRSTATUSPAGESIZE_SHIFT) 100 #define PKTSHIFT_MASK 0x00001c00U 101 #define PKTSHIFT_SHIFT 10 102 #define PKTSHIFT(x) ((x) << PKTSHIFT_SHIFT) 103 #define PKTSHIFT_GET(x) (((x) & PKTSHIFT_MASK) >> PKTSHIFT_SHIFT) 104 #define INGPCIEBOUNDARY_MASK 0x00000380U 105 #define INGPCIEBOUNDARY_SHIFT 7 106 #define INGPCIEBOUNDARY(x) ((x) << INGPCIEBOUNDARY_SHIFT) 107 #define INGPADBOUNDARY_MASK 0x00000070U 108 #define INGPADBOUNDARY_SHIFT 4 109 #define INGPADBOUNDARY(x) ((x) << INGPADBOUNDARY_SHIFT) 110 #define INGPADBOUNDARY_GET(x) (((x) & INGPADBOUNDARY_MASK) \ 111 >> INGPADBOUNDARY_SHIFT) 112 #define EGRPCIEBOUNDARY_MASK 0x0000000eU 113 #define EGRPCIEBOUNDARY_SHIFT 1 114 #define EGRPCIEBOUNDARY(x) ((x) << EGRPCIEBOUNDARY_SHIFT) 115 #define GLOBALENABLE 0x00000001U 116 117 #define SGE_HOST_PAGE_SIZE 0x100c 118 119 #define HOSTPAGESIZEPF7_MASK 0x0000000fU 120 #define HOSTPAGESIZEPF7_SHIFT 28 121 #define HOSTPAGESIZEPF7(x) ((x) << HOSTPAGESIZEPF7_SHIFT) 122 123 #define HOSTPAGESIZEPF6_MASK 0x0000000fU 124 #define HOSTPAGESIZEPF6_SHIFT 24 125 #define HOSTPAGESIZEPF6(x) ((x) << HOSTPAGESIZEPF6_SHIFT) 126 127 #define HOSTPAGESIZEPF5_MASK 0x0000000fU 128 #define HOSTPAGESIZEPF5_SHIFT 20 129 #define HOSTPAGESIZEPF5(x) ((x) << HOSTPAGESIZEPF5_SHIFT) 130 131 #define HOSTPAGESIZEPF4_MASK 0x0000000fU 132 #define HOSTPAGESIZEPF4_SHIFT 16 133 #define HOSTPAGESIZEPF4(x) ((x) << HOSTPAGESIZEPF4_SHIFT) 134 135 #define HOSTPAGESIZEPF3_MASK 0x0000000fU 136 #define HOSTPAGESIZEPF3_SHIFT 12 137 #define HOSTPAGESIZEPF3(x) ((x) << HOSTPAGESIZEPF3_SHIFT) 138 139 #define HOSTPAGESIZEPF2_MASK 0x0000000fU 140 #define HOSTPAGESIZEPF2_SHIFT 8 141 #define HOSTPAGESIZEPF2(x) ((x) << HOSTPAGESIZEPF2_SHIFT) 142 143 #define HOSTPAGESIZEPF1_MASK 0x0000000fU 144 #define HOSTPAGESIZEPF1_SHIFT 4 145 #define HOSTPAGESIZEPF1(x) ((x) << HOSTPAGESIZEPF1_SHIFT) 146 147 #define HOSTPAGESIZEPF0_MASK 0x0000000fU 148 #define HOSTPAGESIZEPF0_SHIFT 0 149 #define HOSTPAGESIZEPF0(x) ((x) << HOSTPAGESIZEPF0_SHIFT) 150 151 #define SGE_EGRESS_QUEUES_PER_PAGE_PF 0x1010 152 #define QUEUESPERPAGEPF0_MASK 0x0000000fU 153 #define QUEUESPERPAGEPF0_GET(x) ((x) & QUEUESPERPAGEPF0_MASK) 154 155 #define SGE_INT_CAUSE1 0x1024 156 #define SGE_INT_CAUSE2 0x1030 157 #define SGE_INT_CAUSE3 0x103c 158 #define ERR_FLM_DBP 0x80000000U 159 #define ERR_FLM_IDMA1 0x40000000U 160 #define ERR_FLM_IDMA0 0x20000000U 161 #define ERR_FLM_HINT 0x10000000U 162 #define ERR_PCIE_ERROR3 0x08000000U 163 #define ERR_PCIE_ERROR2 0x04000000U 164 #define ERR_PCIE_ERROR1 0x02000000U 165 #define ERR_PCIE_ERROR0 0x01000000U 166 #define ERR_TIMER_ABOVE_MAX_QID 0x00800000U 167 #define ERR_CPL_EXCEED_IQE_SIZE 0x00400000U 168 #define ERR_INVALID_CIDX_INC 0x00200000U 169 #define ERR_ITP_TIME_PAUSED 0x00100000U 170 #define ERR_CPL_OPCODE_0 0x00080000U 171 #define ERR_DROPPED_DB 0x00040000U 172 #define ERR_DATA_CPL_ON_HIGH_QID1 0x00020000U 173 #define ERR_DATA_CPL_ON_HIGH_QID0 0x00010000U 174 #define ERR_BAD_DB_PIDX3 0x00008000U 175 #define ERR_BAD_DB_PIDX2 0x00004000U 176 #define ERR_BAD_DB_PIDX1 0x00002000U 177 #define ERR_BAD_DB_PIDX0 0x00001000U 178 #define ERR_ING_PCIE_CHAN 0x00000800U 179 #define ERR_ING_CTXT_PRIO 0x00000400U 180 #define ERR_EGR_CTXT_PRIO 0x00000200U 181 #define DBFIFO_HP_INT 0x00000100U 182 #define DBFIFO_LP_INT 0x00000080U 183 #define REG_ADDRESS_ERR 0x00000040U 184 #define INGRESS_SIZE_ERR 0x00000020U 185 #define EGRESS_SIZE_ERR 0x00000010U 186 #define ERR_INV_CTXT3 0x00000008U 187 #define ERR_INV_CTXT2 0x00000004U 188 #define ERR_INV_CTXT1 0x00000002U 189 #define ERR_INV_CTXT0 0x00000001U 190 191 #define SGE_INT_ENABLE3 0x1040 192 #define SGE_FL_BUFFER_SIZE0 0x1044 193 #define SGE_FL_BUFFER_SIZE1 0x1048 194 #define SGE_FL_BUFFER_SIZE2 0x104c 195 #define SGE_FL_BUFFER_SIZE3 0x1050 196 #define SGE_FL_BUFFER_SIZE4 0x1054 197 #define SGE_FL_BUFFER_SIZE5 0x1058 198 #define SGE_FL_BUFFER_SIZE6 0x105c 199 #define SGE_FL_BUFFER_SIZE7 0x1060 200 #define SGE_FL_BUFFER_SIZE8 0x1064 201 202 #define SGE_INGRESS_RX_THRESHOLD 0x10a0 203 #define THRESHOLD_0_MASK 0x3f000000U 204 #define THRESHOLD_0_SHIFT 24 205 #define THRESHOLD_0(x) ((x) << THRESHOLD_0_SHIFT) 206 #define THRESHOLD_0_GET(x) (((x) & THRESHOLD_0_MASK) >> THRESHOLD_0_SHIFT) 207 #define THRESHOLD_1_MASK 0x003f0000U 208 #define THRESHOLD_1_SHIFT 16 209 #define THRESHOLD_1(x) ((x) << THRESHOLD_1_SHIFT) 210 #define THRESHOLD_1_GET(x) (((x) & THRESHOLD_1_MASK) >> THRESHOLD_1_SHIFT) 211 #define THRESHOLD_2_MASK 0x00003f00U 212 #define THRESHOLD_2_SHIFT 8 213 #define THRESHOLD_2(x) ((x) << THRESHOLD_2_SHIFT) 214 #define THRESHOLD_2_GET(x) (((x) & THRESHOLD_2_MASK) >> THRESHOLD_2_SHIFT) 215 #define THRESHOLD_3_MASK 0x0000003fU 216 #define THRESHOLD_3_SHIFT 0 217 #define THRESHOLD_3(x) ((x) << THRESHOLD_3_SHIFT) 218 #define THRESHOLD_3_GET(x) (((x) & THRESHOLD_3_MASK) >> THRESHOLD_3_SHIFT) 219 220 #define SGE_CONM_CTRL 0x1094 221 #define EGRTHRESHOLD_MASK 0x00003f00U 222 #define EGRTHRESHOLDshift 8 223 #define EGRTHRESHOLD(x) ((x) << EGRTHRESHOLDshift) 224 #define EGRTHRESHOLD_GET(x) (((x) & EGRTHRESHOLD_MASK) >> EGRTHRESHOLDshift) 225 226 #define SGE_DBFIFO_STATUS 0x10a4 227 #define HP_INT_THRESH_SHIFT 28 228 #define HP_INT_THRESH_MASK 0xfU 229 #define HP_INT_THRESH(x) ((x) << HP_INT_THRESH_SHIFT) 230 #define LP_INT_THRESH_SHIFT 12 231 #define LP_INT_THRESH_MASK 0xfU 232 #define LP_INT_THRESH(x) ((x) << LP_INT_THRESH_SHIFT) 233 234 #define SGE_DOORBELL_CONTROL 0x10a8 235 #define ENABLE_DROP (1 << 13) 236 237 #define SGE_TIMER_VALUE_0_AND_1 0x10b8 238 #define TIMERVALUE0_MASK 0xffff0000U 239 #define TIMERVALUE0_SHIFT 16 240 #define TIMERVALUE0(x) ((x) << TIMERVALUE0_SHIFT) 241 #define TIMERVALUE0_GET(x) (((x) & TIMERVALUE0_MASK) >> TIMERVALUE0_SHIFT) 242 #define TIMERVALUE1_MASK 0x0000ffffU 243 #define TIMERVALUE1_SHIFT 0 244 #define TIMERVALUE1(x) ((x) << TIMERVALUE1_SHIFT) 245 #define TIMERVALUE1_GET(x) (((x) & TIMERVALUE1_MASK) >> TIMERVALUE1_SHIFT) 246 247 #define SGE_TIMER_VALUE_2_AND_3 0x10bc 248 #define TIMERVALUE2_MASK 0xffff0000U 249 #define TIMERVALUE2_SHIFT 16 250 #define TIMERVALUE2(x) ((x) << TIMERVALUE2_SHIFT) 251 #define TIMERVALUE2_GET(x) (((x) & TIMERVALUE2_MASK) >> TIMERVALUE2_SHIFT) 252 #define TIMERVALUE3_MASK 0x0000ffffU 253 #define TIMERVALUE3_SHIFT 0 254 #define TIMERVALUE3(x) ((x) << TIMERVALUE3_SHIFT) 255 #define TIMERVALUE3_GET(x) (((x) & TIMERVALUE3_MASK) >> TIMERVALUE3_SHIFT) 256 257 #define SGE_TIMER_VALUE_4_AND_5 0x10c0 258 #define TIMERVALUE4_MASK 0xffff0000U 259 #define TIMERVALUE4_SHIFT 16 260 #define TIMERVALUE4(x) ((x) << TIMERVALUE4_SHIFT) 261 #define TIMERVALUE4_GET(x) (((x) & TIMERVALUE4_MASK) >> TIMERVALUE4_SHIFT) 262 #define TIMERVALUE5_MASK 0x0000ffffU 263 #define TIMERVALUE5_SHIFT 0 264 #define TIMERVALUE5(x) ((x) << TIMERVALUE5_SHIFT) 265 #define TIMERVALUE5_GET(x) (((x) & TIMERVALUE5_MASK) >> TIMERVALUE5_SHIFT) 266 267 #define SGE_DEBUG_INDEX 0x10cc 268 #define SGE_DEBUG_DATA_HIGH 0x10d0 269 #define SGE_DEBUG_DATA_LOW 0x10d4 270 #define SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4 271 272 #define S_HP_INT_THRESH 28 273 #define M_HP_INT_THRESH 0xfU 274 #define V_HP_INT_THRESH(x) ((x) << S_HP_INT_THRESH) 275 #define M_HP_COUNT 0x7ffU 276 #define S_HP_COUNT 16 277 #define G_HP_COUNT(x) (((x) >> S_HP_COUNT) & M_HP_COUNT) 278 #define S_LP_INT_THRESH 12 279 #define M_LP_INT_THRESH 0xfU 280 #define V_LP_INT_THRESH(x) ((x) << S_LP_INT_THRESH) 281 #define M_LP_COUNT 0x7ffU 282 #define S_LP_COUNT 0 283 #define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT) 284 #define A_SGE_DBFIFO_STATUS 0x10a4 285 286 #define S_ENABLE_DROP 13 287 #define V_ENABLE_DROP(x) ((x) << S_ENABLE_DROP) 288 #define F_ENABLE_DROP V_ENABLE_DROP(1U) 289 #define S_DROPPED_DB 0 290 #define V_DROPPED_DB(x) ((x) << S_DROPPED_DB) 291 #define F_DROPPED_DB V_DROPPED_DB(1U) 292 #define A_SGE_DOORBELL_CONTROL 0x10a8 293 294 #define A_SGE_CTXT_CMD 0x11fc 295 #define A_SGE_DBQ_CTXT_BADDR 0x1084 296 297 #define PCIE_PF_CFG 0x40 298 #define AIVEC(x) ((x) << 4) 299 #define AIVEC_MASK 0x3ffU 300 301 #define PCIE_PF_CLI 0x44 302 #define PCIE_INT_CAUSE 0x3004 303 #define UNXSPLCPLERR 0x20000000U 304 #define PCIEPINT 0x10000000U 305 #define PCIESINT 0x08000000U 306 #define RPLPERR 0x04000000U 307 #define RXWRPERR 0x02000000U 308 #define RXCPLPERR 0x01000000U 309 #define PIOTAGPERR 0x00800000U 310 #define MATAGPERR 0x00400000U 311 #define INTXCLRPERR 0x00200000U 312 #define FIDPERR 0x00100000U 313 #define CFGSNPPERR 0x00080000U 314 #define HRSPPERR 0x00040000U 315 #define HREQPERR 0x00020000U 316 #define HCNTPERR 0x00010000U 317 #define DRSPPERR 0x00008000U 318 #define DREQPERR 0x00004000U 319 #define DCNTPERR 0x00002000U 320 #define CRSPPERR 0x00001000U 321 #define CREQPERR 0x00000800U 322 #define CCNTPERR 0x00000400U 323 #define TARTAGPERR 0x00000200U 324 #define PIOREQPERR 0x00000100U 325 #define PIOCPLPERR 0x00000080U 326 #define MSIXDIPERR 0x00000040U 327 #define MSIXDATAPERR 0x00000020U 328 #define MSIXADDRHPERR 0x00000010U 329 #define MSIXADDRLPERR 0x00000008U 330 #define MSIDATAPERR 0x00000004U 331 #define MSIADDRHPERR 0x00000002U 332 #define MSIADDRLPERR 0x00000001U 333 334 #define PCIE_NONFAT_ERR 0x3010 335 #define PCIE_MEM_ACCESS_BASE_WIN 0x3068 336 #define PCIEOFST_MASK 0xfffffc00U 337 #define BIR_MASK 0x00000300U 338 #define BIR_SHIFT 8 339 #define BIR(x) ((x) << BIR_SHIFT) 340 #define WINDOW_MASK 0x000000ffU 341 #define WINDOW_SHIFT 0 342 #define WINDOW(x) ((x) << WINDOW_SHIFT) 343 #define PCIE_MEM_ACCESS_OFFSET 0x306c 344 345 #define PCIE_FW 0x30b8 346 #define PCIE_FW_ERR 0x80000000U 347 #define PCIE_FW_INIT 0x40000000U 348 #define PCIE_FW_HALT 0x20000000U 349 #define PCIE_FW_MASTER_VLD 0x00008000U 350 #define PCIE_FW_MASTER(x) ((x) << 12) 351 #define PCIE_FW_MASTER_MASK 0x7 352 #define PCIE_FW_MASTER_GET(x) (((x) >> 12) & PCIE_FW_MASTER_MASK) 353 354 #define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS 0x5908 355 #define RNPP 0x80000000U 356 #define RPCP 0x20000000U 357 #define RCIP 0x08000000U 358 #define RCCP 0x04000000U 359 #define RFTP 0x00800000U 360 #define PTRP 0x00100000U 361 362 #define PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS 0x59a4 363 #define TPCP 0x40000000U 364 #define TNPP 0x20000000U 365 #define TFTP 0x10000000U 366 #define TCAP 0x08000000U 367 #define TCIP 0x04000000U 368 #define RCAP 0x02000000U 369 #define PLUP 0x00800000U 370 #define PLDN 0x00400000U 371 #define OTDD 0x00200000U 372 #define GTRP 0x00100000U 373 #define RDPE 0x00040000U 374 #define TDCE 0x00020000U 375 #define TDUE 0x00010000U 376 377 #define MC_INT_CAUSE 0x7518 378 #define ECC_UE_INT_CAUSE 0x00000004U 379 #define ECC_CE_INT_CAUSE 0x00000002U 380 #define PERR_INT_CAUSE 0x00000001U 381 382 #define MC_ECC_STATUS 0x751c 383 #define ECC_CECNT_MASK 0xffff0000U 384 #define ECC_CECNT_SHIFT 16 385 #define ECC_CECNT(x) ((x) << ECC_CECNT_SHIFT) 386 #define ECC_CECNT_GET(x) (((x) & ECC_CECNT_MASK) >> ECC_CECNT_SHIFT) 387 #define ECC_UECNT_MASK 0x0000ffffU 388 #define ECC_UECNT_SHIFT 0 389 #define ECC_UECNT(x) ((x) << ECC_UECNT_SHIFT) 390 #define ECC_UECNT_GET(x) (((x) & ECC_UECNT_MASK) >> ECC_UECNT_SHIFT) 391 392 #define MC_BIST_CMD 0x7600 393 #define START_BIST 0x80000000U 394 #define BIST_CMD_GAP_MASK 0x0000ff00U 395 #define BIST_CMD_GAP_SHIFT 8 396 #define BIST_CMD_GAP(x) ((x) << BIST_CMD_GAP_SHIFT) 397 #define BIST_OPCODE_MASK 0x00000003U 398 #define BIST_OPCODE_SHIFT 0 399 #define BIST_OPCODE(x) ((x) << BIST_OPCODE_SHIFT) 400 401 #define MC_BIST_CMD_ADDR 0x7604 402 #define MC_BIST_CMD_LEN 0x7608 403 #define MC_BIST_DATA_PATTERN 0x760c 404 #define BIST_DATA_TYPE_MASK 0x0000000fU 405 #define BIST_DATA_TYPE_SHIFT 0 406 #define BIST_DATA_TYPE(x) ((x) << BIST_DATA_TYPE_SHIFT) 407 408 #define MC_BIST_STATUS_RDATA 0x7688 409 410 #define MA_EXT_MEMORY_BAR 0x77c8 411 #define EXT_MEM_SIZE_MASK 0x00000fffU 412 #define EXT_MEM_SIZE_SHIFT 0 413 #define EXT_MEM_SIZE_GET(x) (((x) & EXT_MEM_SIZE_MASK) >> EXT_MEM_SIZE_SHIFT) 414 415 #define MA_TARGET_MEM_ENABLE 0x77d8 416 #define EXT_MEM_ENABLE 0x00000004U 417 #define EDRAM1_ENABLE 0x00000002U 418 #define EDRAM0_ENABLE 0x00000001U 419 420 #define MA_INT_CAUSE 0x77e0 421 #define MEM_PERR_INT_CAUSE 0x00000002U 422 #define MEM_WRAP_INT_CAUSE 0x00000001U 423 424 #define MA_INT_WRAP_STATUS 0x77e4 425 #define MEM_WRAP_ADDRESS_MASK 0xfffffff0U 426 #define MEM_WRAP_ADDRESS_SHIFT 4 427 #define MEM_WRAP_ADDRESS_GET(x) (((x) & MEM_WRAP_ADDRESS_MASK) >> MEM_WRAP_ADDRESS_SHIFT) 428 #define MEM_WRAP_CLIENT_NUM_MASK 0x0000000fU 429 #define MEM_WRAP_CLIENT_NUM_SHIFT 0 430 #define MEM_WRAP_CLIENT_NUM_GET(x) (((x) & MEM_WRAP_CLIENT_NUM_MASK) >> MEM_WRAP_CLIENT_NUM_SHIFT) 431 #define MA_PCIE_FW 0x30b8 432 #define MA_PARITY_ERROR_STATUS 0x77f4 433 434 #define EDC_0_BASE_ADDR 0x7900 435 436 #define EDC_BIST_CMD 0x7904 437 #define EDC_BIST_CMD_ADDR 0x7908 438 #define EDC_BIST_CMD_LEN 0x790c 439 #define EDC_BIST_DATA_PATTERN 0x7910 440 #define EDC_BIST_STATUS_RDATA 0x7928 441 #define EDC_INT_CAUSE 0x7978 442 #define ECC_UE_PAR 0x00000020U 443 #define ECC_CE_PAR 0x00000010U 444 #define PERR_PAR_CAUSE 0x00000008U 445 446 #define EDC_ECC_STATUS 0x797c 447 448 #define EDC_1_BASE_ADDR 0x7980 449 450 #define CIM_BOOT_CFG 0x7b00 451 #define BOOTADDR_MASK 0xffffff00U 452 #define UPCRST 0x1U 453 454 #define CIM_PF_MAILBOX_DATA 0x240 455 #define CIM_PF_MAILBOX_CTRL 0x280 456 #define MBMSGVALID 0x00000008U 457 #define MBINTREQ 0x00000004U 458 #define MBOWNER_MASK 0x00000003U 459 #define MBOWNER_SHIFT 0 460 #define MBOWNER(x) ((x) << MBOWNER_SHIFT) 461 #define MBOWNER_GET(x) (((x) & MBOWNER_MASK) >> MBOWNER_SHIFT) 462 463 #define CIM_PF_HOST_INT_ENABLE 0x288 464 #define MBMSGRDYINTEN(x) ((x) << 19) 465 466 #define CIM_PF_HOST_INT_CAUSE 0x28c 467 #define MBMSGRDYINT 0x00080000U 468 469 #define CIM_HOST_INT_CAUSE 0x7b2c 470 #define TIEQOUTPARERRINT 0x00100000U 471 #define TIEQINPARERRINT 0x00080000U 472 #define MBHOSTPARERR 0x00040000U 473 #define MBUPPARERR 0x00020000U 474 #define IBQPARERR 0x0001f800U 475 #define IBQTP0PARERR 0x00010000U 476 #define IBQTP1PARERR 0x00008000U 477 #define IBQULPPARERR 0x00004000U 478 #define IBQSGELOPARERR 0x00002000U 479 #define IBQSGEHIPARERR 0x00001000U 480 #define IBQNCSIPARERR 0x00000800U 481 #define OBQPARERR 0x000007e0U 482 #define OBQULP0PARERR 0x00000400U 483 #define OBQULP1PARERR 0x00000200U 484 #define OBQULP2PARERR 0x00000100U 485 #define OBQULP3PARERR 0x00000080U 486 #define OBQSGEPARERR 0x00000040U 487 #define OBQNCSIPARERR 0x00000020U 488 #define PREFDROPINT 0x00000002U 489 #define UPACCNONZERO 0x00000001U 490 491 #define CIM_HOST_UPACC_INT_CAUSE 0x7b34 492 #define EEPROMWRINT 0x40000000U 493 #define TIMEOUTMAINT 0x20000000U 494 #define TIMEOUTINT 0x10000000U 495 #define RSPOVRLOOKUPINT 0x08000000U 496 #define REQOVRLOOKUPINT 0x04000000U 497 #define BLKWRPLINT 0x02000000U 498 #define BLKRDPLINT 0x01000000U 499 #define SGLWRPLINT 0x00800000U 500 #define SGLRDPLINT 0x00400000U 501 #define BLKWRCTLINT 0x00200000U 502 #define BLKRDCTLINT 0x00100000U 503 #define SGLWRCTLINT 0x00080000U 504 #define SGLRDCTLINT 0x00040000U 505 #define BLKWREEPROMINT 0x00020000U 506 #define BLKRDEEPROMINT 0x00010000U 507 #define SGLWREEPROMINT 0x00008000U 508 #define SGLRDEEPROMINT 0x00004000U 509 #define BLKWRFLASHINT 0x00002000U 510 #define BLKRDFLASHINT 0x00001000U 511 #define SGLWRFLASHINT 0x00000800U 512 #define SGLRDFLASHINT 0x00000400U 513 #define BLKWRBOOTINT 0x00000200U 514 #define BLKRDBOOTINT 0x00000100U 515 #define SGLWRBOOTINT 0x00000080U 516 #define SGLRDBOOTINT 0x00000040U 517 #define ILLWRBEINT 0x00000020U 518 #define ILLRDBEINT 0x00000010U 519 #define ILLRDINT 0x00000008U 520 #define ILLWRINT 0x00000004U 521 #define ILLTRANSINT 0x00000002U 522 #define RSVDSPACEINT 0x00000001U 523 524 #define TP_OUT_CONFIG 0x7d04 525 #define VLANEXTENABLE_MASK 0x0000f000U 526 #define VLANEXTENABLE_SHIFT 12 527 528 #define TP_GLOBAL_CONFIG 0x7d08 529 #define FIVETUPLELOOKUP_SHIFT 17 530 #define FIVETUPLELOOKUP_MASK 0x00060000U 531 #define FIVETUPLELOOKUP(x) ((x) << FIVETUPLELOOKUP_SHIFT) 532 #define FIVETUPLELOOKUP_GET(x) (((x) & FIVETUPLELOOKUP_MASK) >> \ 533 FIVETUPLELOOKUP_SHIFT) 534 535 #define TP_PARA_REG2 0x7d68 536 #define MAXRXDATA_MASK 0xffff0000U 537 #define MAXRXDATA_SHIFT 16 538 #define MAXRXDATA_GET(x) (((x) & MAXRXDATA_MASK) >> MAXRXDATA_SHIFT) 539 540 #define TP_TIMER_RESOLUTION 0x7d90 541 #define TIMERRESOLUTION_MASK 0x00ff0000U 542 #define TIMERRESOLUTION_SHIFT 16 543 #define TIMERRESOLUTION_GET(x) (((x) & TIMERRESOLUTION_MASK) >> TIMERRESOLUTION_SHIFT) 544 #define DELAYEDACKRESOLUTION_MASK 0x000000ffU 545 #define DELAYEDACKRESOLUTION_SHIFT 0 546 #define DELAYEDACKRESOLUTION_GET(x) \ 547 (((x) & DELAYEDACKRESOLUTION_MASK) >> DELAYEDACKRESOLUTION_SHIFT) 548 549 #define TP_SHIFT_CNT 0x7dc0 550 #define SYNSHIFTMAX_SHIFT 24 551 #define SYNSHIFTMAX_MASK 0xff000000U 552 #define SYNSHIFTMAX(x) ((x) << SYNSHIFTMAX_SHIFT) 553 #define SYNSHIFTMAX_GET(x) (((x) & SYNSHIFTMAX_MASK) >> \ 554 SYNSHIFTMAX_SHIFT) 555 #define RXTSHIFTMAXR1_SHIFT 20 556 #define RXTSHIFTMAXR1_MASK 0x00f00000U 557 #define RXTSHIFTMAXR1(x) ((x) << RXTSHIFTMAXR1_SHIFT) 558 #define RXTSHIFTMAXR1_GET(x) (((x) & RXTSHIFTMAXR1_MASK) >> \ 559 RXTSHIFTMAXR1_SHIFT) 560 #define RXTSHIFTMAXR2_SHIFT 16 561 #define RXTSHIFTMAXR2_MASK 0x000f0000U 562 #define RXTSHIFTMAXR2(x) ((x) << RXTSHIFTMAXR2_SHIFT) 563 #define RXTSHIFTMAXR2_GET(x) (((x) & RXTSHIFTMAXR2_MASK) >> \ 564 RXTSHIFTMAXR2_SHIFT) 565 #define PERSHIFTBACKOFFMAX_SHIFT 12 566 #define PERSHIFTBACKOFFMAX_MASK 0x0000f000U 567 #define PERSHIFTBACKOFFMAX(x) ((x) << PERSHIFTBACKOFFMAX_SHIFT) 568 #define PERSHIFTBACKOFFMAX_GET(x) (((x) & PERSHIFTBACKOFFMAX_MASK) >> \ 569 PERSHIFTBACKOFFMAX_SHIFT) 570 #define PERSHIFTMAX_SHIFT 8 571 #define PERSHIFTMAX_MASK 0x00000f00U 572 #define PERSHIFTMAX(x) ((x) << PERSHIFTMAX_SHIFT) 573 #define PERSHIFTMAX_GET(x) (((x) & PERSHIFTMAX_MASK) >> \ 574 PERSHIFTMAX_SHIFT) 575 #define KEEPALIVEMAXR1_SHIFT 4 576 #define KEEPALIVEMAXR1_MASK 0x000000f0U 577 #define KEEPALIVEMAXR1(x) ((x) << KEEPALIVEMAXR1_SHIFT) 578 #define KEEPALIVEMAXR1_GET(x) (((x) & KEEPALIVEMAXR1_MASK) >> \ 579 KEEPALIVEMAXR1_SHIFT) 580 #define KEEPALIVEMAXR2_SHIFT 0 581 #define KEEPALIVEMAXR2_MASK 0x0000000fU 582 #define KEEPALIVEMAXR2(x) ((x) << KEEPALIVEMAXR2_SHIFT) 583 #define KEEPALIVEMAXR2_GET(x) (((x) & KEEPALIVEMAXR2_MASK) >> \ 584 KEEPALIVEMAXR2_SHIFT) 585 586 #define TP_CCTRL_TABLE 0x7ddc 587 #define TP_MTU_TABLE 0x7de4 588 #define MTUINDEX_MASK 0xff000000U 589 #define MTUINDEX_SHIFT 24 590 #define MTUINDEX(x) ((x) << MTUINDEX_SHIFT) 591 #define MTUWIDTH_MASK 0x000f0000U 592 #define MTUWIDTH_SHIFT 16 593 #define MTUWIDTH(x) ((x) << MTUWIDTH_SHIFT) 594 #define MTUWIDTH_GET(x) (((x) & MTUWIDTH_MASK) >> MTUWIDTH_SHIFT) 595 #define MTUVALUE_MASK 0x00003fffU 596 #define MTUVALUE_SHIFT 0 597 #define MTUVALUE(x) ((x) << MTUVALUE_SHIFT) 598 #define MTUVALUE_GET(x) (((x) & MTUVALUE_MASK) >> MTUVALUE_SHIFT) 599 600 #define TP_RSS_LKP_TABLE 0x7dec 601 #define LKPTBLROWVLD 0x80000000U 602 #define LKPTBLQUEUE1_MASK 0x000ffc00U 603 #define LKPTBLQUEUE1_SHIFT 10 604 #define LKPTBLQUEUE1(x) ((x) << LKPTBLQUEUE1_SHIFT) 605 #define LKPTBLQUEUE1_GET(x) (((x) & LKPTBLQUEUE1_MASK) >> LKPTBLQUEUE1_SHIFT) 606 #define LKPTBLQUEUE0_MASK 0x000003ffU 607 #define LKPTBLQUEUE0_SHIFT 0 608 #define LKPTBLQUEUE0(x) ((x) << LKPTBLQUEUE0_SHIFT) 609 #define LKPTBLQUEUE0_GET(x) (((x) & LKPTBLQUEUE0_MASK) >> LKPTBLQUEUE0_SHIFT) 610 611 #define TP_PIO_ADDR 0x7e40 612 #define TP_PIO_DATA 0x7e44 613 #define TP_MIB_INDEX 0x7e50 614 #define TP_MIB_DATA 0x7e54 615 #define TP_INT_CAUSE 0x7e74 616 #define FLMTXFLSTEMPTY 0x40000000U 617 618 #define TP_VLAN_PRI_MAP 0x140 619 #define FRAGMENTATION_SHIFT 9 620 #define FRAGMENTATION_MASK 0x00000200U 621 #define MPSHITTYPE_MASK 0x00000100U 622 #define MACMATCH_MASK 0x00000080U 623 #define ETHERTYPE_MASK 0x00000040U 624 #define PROTOCOL_MASK 0x00000020U 625 #define TOS_MASK 0x00000010U 626 #define VLAN_MASK 0x00000008U 627 #define VNIC_ID_MASK 0x00000004U 628 #define PORT_MASK 0x00000002U 629 #define FCOE_SHIFT 0 630 #define FCOE_MASK 0x00000001U 631 632 #define TP_INGRESS_CONFIG 0x141 633 #define VNIC 0x00000800U 634 #define CSUM_HAS_PSEUDO_HDR 0x00000400U 635 #define RM_OVLAN 0x00000200U 636 #define LOOKUPEVERYPKT 0x00000100U 637 638 #define TP_MIB_MAC_IN_ERR_0 0x0 639 #define TP_MIB_TCP_OUT_RST 0xc 640 #define TP_MIB_TCP_IN_SEG_HI 0x10 641 #define TP_MIB_TCP_IN_SEG_LO 0x11 642 #define TP_MIB_TCP_OUT_SEG_HI 0x12 643 #define TP_MIB_TCP_OUT_SEG_LO 0x13 644 #define TP_MIB_TCP_RXT_SEG_HI 0x14 645 #define TP_MIB_TCP_RXT_SEG_LO 0x15 646 #define TP_MIB_TNL_CNG_DROP_0 0x18 647 #define TP_MIB_TCP_V6IN_ERR_0 0x28 648 #define TP_MIB_TCP_V6OUT_RST 0x2c 649 #define TP_MIB_OFD_ARP_DROP 0x36 650 #define TP_MIB_TNL_DROP_0 0x44 651 #define TP_MIB_OFD_VLN_DROP_0 0x58 652 653 #define ULP_TX_INT_CAUSE 0x8dcc 654 #define PBL_BOUND_ERR_CH3 0x80000000U 655 #define PBL_BOUND_ERR_CH2 0x40000000U 656 #define PBL_BOUND_ERR_CH1 0x20000000U 657 #define PBL_BOUND_ERR_CH0 0x10000000U 658 659 #define PM_RX_INT_CAUSE 0x8fdc 660 #define ZERO_E_CMD_ERROR 0x00400000U 661 #define PMRX_FRAMING_ERROR 0x003ffff0U 662 #define OCSPI_PAR_ERROR 0x00000008U 663 #define DB_OPTIONS_PAR_ERROR 0x00000004U 664 #define IESPI_PAR_ERROR 0x00000002U 665 #define E_PCMD_PAR_ERROR 0x00000001U 666 667 #define PM_TX_INT_CAUSE 0x8ffc 668 #define PCMD_LEN_OVFL0 0x80000000U 669 #define PCMD_LEN_OVFL1 0x40000000U 670 #define PCMD_LEN_OVFL2 0x20000000U 671 #define ZERO_C_CMD_ERROR 0x10000000U 672 #define PMTX_FRAMING_ERROR 0x0ffffff0U 673 #define OESPI_PAR_ERROR 0x00000008U 674 #define ICSPI_PAR_ERROR 0x00000002U 675 #define C_PCMD_PAR_ERROR 0x00000001U 676 677 #define MPS_PORT_STAT_TX_PORT_BYTES_L 0x400 678 #define MPS_PORT_STAT_TX_PORT_BYTES_H 0x404 679 #define MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408 680 #define MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c 681 #define MPS_PORT_STAT_TX_PORT_BCAST_L 0x410 682 #define MPS_PORT_STAT_TX_PORT_BCAST_H 0x414 683 #define MPS_PORT_STAT_TX_PORT_MCAST_L 0x418 684 #define MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c 685 #define MPS_PORT_STAT_TX_PORT_UCAST_L 0x420 686 #define MPS_PORT_STAT_TX_PORT_UCAST_H 0x424 687 #define MPS_PORT_STAT_TX_PORT_ERROR_L 0x428 688 #define MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c 689 #define MPS_PORT_STAT_TX_PORT_64B_L 0x430 690 #define MPS_PORT_STAT_TX_PORT_64B_H 0x434 691 #define MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438 692 #define MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c 693 #define MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440 694 #define MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444 695 #define MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448 696 #define MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c 697 #define MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450 698 #define MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454 699 #define MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458 700 #define MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c 701 #define MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460 702 #define MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464 703 #define MPS_PORT_STAT_TX_PORT_DROP_L 0x468 704 #define MPS_PORT_STAT_TX_PORT_DROP_H 0x46c 705 #define MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470 706 #define MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474 707 #define MPS_PORT_STAT_TX_PORT_PPP0_L 0x478 708 #define MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c 709 #define MPS_PORT_STAT_TX_PORT_PPP1_L 0x480 710 #define MPS_PORT_STAT_TX_PORT_PPP1_H 0x484 711 #define MPS_PORT_STAT_TX_PORT_PPP2_L 0x488 712 #define MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c 713 #define MPS_PORT_STAT_TX_PORT_PPP3_L 0x490 714 #define MPS_PORT_STAT_TX_PORT_PPP3_H 0x494 715 #define MPS_PORT_STAT_TX_PORT_PPP4_L 0x498 716 #define MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c 717 #define MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0 718 #define MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4 719 #define MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8 720 #define MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac 721 #define MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0 722 #define MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4 723 #define MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0 724 #define MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4 725 #define MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8 726 #define MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc 727 #define MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0 728 #define MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4 729 #define MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8 730 #define MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc 731 #define MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0 732 #define MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4 733 #define MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8 734 #define MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec 735 #define MPS_PORT_STAT_LB_PORT_64B_L 0x4f0 736 #define MPS_PORT_STAT_LB_PORT_64B_H 0x4f4 737 #define MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8 738 #define MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc 739 #define MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500 740 #define MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504 741 #define MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508 742 #define MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c 743 #define MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510 744 #define MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514 745 #define MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518 746 #define MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c 747 #define MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520 748 #define MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524 749 #define MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528 750 #define MPS_PORT_STAT_RX_PORT_BYTES_L 0x540 751 #define MPS_PORT_STAT_RX_PORT_BYTES_H 0x544 752 #define MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548 753 #define MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c 754 #define MPS_PORT_STAT_RX_PORT_BCAST_L 0x550 755 #define MPS_PORT_STAT_RX_PORT_BCAST_H 0x554 756 #define MPS_PORT_STAT_RX_PORT_MCAST_L 0x558 757 #define MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c 758 #define MPS_PORT_STAT_RX_PORT_UCAST_L 0x560 759 #define MPS_PORT_STAT_RX_PORT_UCAST_H 0x564 760 #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568 761 #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c 762 #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570 763 #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574 764 #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578 765 #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c 766 #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580 767 #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584 768 #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588 769 #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c 770 #define MPS_PORT_STAT_RX_PORT_64B_L 0x590 771 #define MPS_PORT_STAT_RX_PORT_64B_H 0x594 772 #define MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598 773 #define MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c 774 #define MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0 775 #define MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4 776 #define MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8 777 #define MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac 778 #define MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0 779 #define MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4 780 #define MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8 781 #define MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc 782 #define MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0 783 #define MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4 784 #define MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8 785 #define MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc 786 #define MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0 787 #define MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4 788 #define MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8 789 #define MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc 790 #define MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0 791 #define MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4 792 #define MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8 793 #define MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec 794 #define MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0 795 #define MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4 796 #define MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8 797 #define MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc 798 #define MPS_PORT_STAT_RX_PORT_PPP6_L 0x600 799 #define MPS_PORT_STAT_RX_PORT_PPP6_H 0x604 800 #define MPS_PORT_STAT_RX_PORT_PPP7_L 0x608 801 #define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c 802 #define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610 803 #define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614 804 #define MPS_CMN_CTL 0x9000 805 #define NUMPORTS_MASK 0x00000003U 806 #define NUMPORTS_SHIFT 0 807 #define NUMPORTS_GET(x) (((x) & NUMPORTS_MASK) >> NUMPORTS_SHIFT) 808 809 #define MPS_INT_CAUSE 0x9008 810 #define STATINT 0x00000020U 811 #define TXINT 0x00000010U 812 #define RXINT 0x00000008U 813 #define TRCINT 0x00000004U 814 #define CLSINT 0x00000002U 815 #define PLINT 0x00000001U 816 817 #define MPS_TX_INT_CAUSE 0x9408 818 #define PORTERR 0x00010000U 819 #define FRMERR 0x00008000U 820 #define SECNTERR 0x00004000U 821 #define BUBBLE 0x00002000U 822 #define TXDESCFIFO 0x00001e00U 823 #define TXDATAFIFO 0x000001e0U 824 #define NCSIFIFO 0x00000010U 825 #define TPFIFO 0x0000000fU 826 827 #define MPS_STAT_PERR_INT_CAUSE_SRAM 0x9614 828 #define MPS_STAT_PERR_INT_CAUSE_TX_FIFO 0x9620 829 #define MPS_STAT_PERR_INT_CAUSE_RX_FIFO 0x962c 830 831 #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640 832 #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644 833 #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648 834 #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c 835 #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650 836 #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654 837 #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658 838 #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c 839 #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660 840 #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664 841 #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668 842 #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c 843 #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670 844 #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674 845 #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678 846 #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c 847 #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680 848 #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684 849 #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688 850 #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c 851 #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690 852 #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694 853 #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698 854 #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c 855 #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0 856 #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4 857 #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8 858 #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac 859 #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0 860 #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4 861 #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8 862 #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc 863 #define MPS_TRC_CFG 0x9800 864 #define TRCFIFOEMPTY 0x00000010U 865 #define TRCIGNOREDROPINPUT 0x00000008U 866 #define TRCKEEPDUPLICATES 0x00000004U 867 #define TRCEN 0x00000002U 868 #define TRCMULTIFILTER 0x00000001U 869 870 #define MPS_TRC_RSS_CONTROL 0x9808 871 #define RSSCONTROL_MASK 0x00ff0000U 872 #define RSSCONTROL_SHIFT 16 873 #define RSSCONTROL(x) ((x) << RSSCONTROL_SHIFT) 874 #define QUEUENUMBER_MASK 0x0000ffffU 875 #define QUEUENUMBER_SHIFT 0 876 #define QUEUENUMBER(x) ((x) << QUEUENUMBER_SHIFT) 877 878 #define MPS_TRC_FILTER_MATCH_CTL_A 0x9810 879 #define TFINVERTMATCH 0x01000000U 880 #define TFPKTTOOLARGE 0x00800000U 881 #define TFEN 0x00400000U 882 #define TFPORT_MASK 0x003c0000U 883 #define TFPORT_SHIFT 18 884 #define TFPORT(x) ((x) << TFPORT_SHIFT) 885 #define TFPORT_GET(x) (((x) & TFPORT_MASK) >> TFPORT_SHIFT) 886 #define TFDROP 0x00020000U 887 #define TFSOPEOPERR 0x00010000U 888 #define TFLENGTH_MASK 0x00001f00U 889 #define TFLENGTH_SHIFT 8 890 #define TFLENGTH(x) ((x) << TFLENGTH_SHIFT) 891 #define TFLENGTH_GET(x) (((x) & TFLENGTH_MASK) >> TFLENGTH_SHIFT) 892 #define TFOFFSET_MASK 0x0000001fU 893 #define TFOFFSET_SHIFT 0 894 #define TFOFFSET(x) ((x) << TFOFFSET_SHIFT) 895 #define TFOFFSET_GET(x) (((x) & TFOFFSET_MASK) >> TFOFFSET_SHIFT) 896 897 #define MPS_TRC_FILTER_MATCH_CTL_B 0x9820 898 #define TFMINPKTSIZE_MASK 0x01ff0000U 899 #define TFMINPKTSIZE_SHIFT 16 900 #define TFMINPKTSIZE(x) ((x) << TFMINPKTSIZE_SHIFT) 901 #define TFMINPKTSIZE_GET(x) (((x) & TFMINPKTSIZE_MASK) >> TFMINPKTSIZE_SHIFT) 902 #define TFCAPTUREMAX_MASK 0x00003fffU 903 #define TFCAPTUREMAX_SHIFT 0 904 #define TFCAPTUREMAX(x) ((x) << TFCAPTUREMAX_SHIFT) 905 #define TFCAPTUREMAX_GET(x) (((x) & TFCAPTUREMAX_MASK) >> TFCAPTUREMAX_SHIFT) 906 907 #define MPS_TRC_INT_CAUSE 0x985c 908 #define MISCPERR 0x00000100U 909 #define PKTFIFO 0x000000f0U 910 #define FILTMEM 0x0000000fU 911 912 #define MPS_TRC_FILTER0_MATCH 0x9c00 913 #define MPS_TRC_FILTER0_DONT_CARE 0x9c80 914 #define MPS_TRC_FILTER1_MATCH 0x9d00 915 #define MPS_CLS_INT_CAUSE 0xd028 916 #define PLERRENB 0x00000008U 917 #define HASHSRAM 0x00000004U 918 #define MATCHTCAM 0x00000002U 919 #define MATCHSRAM 0x00000001U 920 921 #define MPS_RX_PERR_INT_CAUSE 0x11074 922 923 #define CPL_INTR_CAUSE 0x19054 924 #define CIM_OP_MAP_PERR 0x00000020U 925 #define CIM_OVFL_ERROR 0x00000010U 926 #define TP_FRAMING_ERROR 0x00000008U 927 #define SGE_FRAMING_ERROR 0x00000004U 928 #define CIM_FRAMING_ERROR 0x00000002U 929 #define ZERO_SWITCH_ERROR 0x00000001U 930 931 #define SMB_INT_CAUSE 0x19090 932 #define MSTTXFIFOPARINT 0x00200000U 933 #define MSTRXFIFOPARINT 0x00100000U 934 #define SLVFIFOPARINT 0x00080000U 935 936 #define ULP_RX_INT_CAUSE 0x19158 937 #define ULP_RX_ISCSI_TAGMASK 0x19164 938 #define ULP_RX_ISCSI_PSZ 0x19168 939 #define HPZ3_MASK 0x0f000000U 940 #define HPZ3_SHIFT 24 941 #define HPZ3(x) ((x) << HPZ3_SHIFT) 942 #define HPZ2_MASK 0x000f0000U 943 #define HPZ2_SHIFT 16 944 #define HPZ2(x) ((x) << HPZ2_SHIFT) 945 #define HPZ1_MASK 0x00000f00U 946 #define HPZ1_SHIFT 8 947 #define HPZ1(x) ((x) << HPZ1_SHIFT) 948 #define HPZ0_MASK 0x0000000fU 949 #define HPZ0_SHIFT 0 950 #define HPZ0(x) ((x) << HPZ0_SHIFT) 951 952 #define ULP_RX_TDDP_PSZ 0x19178 953 954 #define SF_DATA 0x193f8 955 #define SF_OP 0x193fc 956 #define SF_BUSY 0x80000000U 957 #define SF_LOCK 0x00000010U 958 #define SF_CONT 0x00000008U 959 #define BYTECNT_MASK 0x00000006U 960 #define BYTECNT_SHIFT 1 961 #define BYTECNT(x) ((x) << BYTECNT_SHIFT) 962 #define OP_WR 0x00000001U 963 964 #define PL_PF_INT_CAUSE 0x3c0 965 #define PFSW 0x00000008U 966 #define PFSGE 0x00000004U 967 #define PFCIM 0x00000002U 968 #define PFMPS 0x00000001U 969 970 #define PL_PF_INT_ENABLE 0x3c4 971 #define PL_PF_CTL 0x3c8 972 #define SWINT 0x00000001U 973 974 #define PL_WHOAMI 0x19400 975 #define SOURCEPF_MASK 0x00000700U 976 #define SOURCEPF_SHIFT 8 977 #define SOURCEPF(x) ((x) << SOURCEPF_SHIFT) 978 #define SOURCEPF_GET(x) (((x) & SOURCEPF_MASK) >> SOURCEPF_SHIFT) 979 #define ISVF 0x00000080U 980 #define VFID_MASK 0x0000007fU 981 #define VFID_SHIFT 0 982 #define VFID(x) ((x) << VFID_SHIFT) 983 #define VFID_GET(x) (((x) & VFID_MASK) >> VFID_SHIFT) 984 985 #define PL_INT_CAUSE 0x1940c 986 #define ULP_TX 0x08000000U 987 #define SGE 0x04000000U 988 #define HMA 0x02000000U 989 #define CPL_SWITCH 0x01000000U 990 #define ULP_RX 0x00800000U 991 #define PM_RX 0x00400000U 992 #define PM_TX 0x00200000U 993 #define MA 0x00100000U 994 #define TP 0x00080000U 995 #define LE 0x00040000U 996 #define EDC1 0x00020000U 997 #define EDC0 0x00010000U 998 #define MC 0x00008000U 999 #define PCIE 0x00004000U 1000 #define PMU 0x00002000U 1001 #define XGMAC_KR1 0x00001000U 1002 #define XGMAC_KR0 0x00000800U 1003 #define XGMAC1 0x00000400U 1004 #define XGMAC0 0x00000200U 1005 #define SMB 0x00000100U 1006 #define SF 0x00000080U 1007 #define PL 0x00000040U 1008 #define NCSI 0x00000020U 1009 #define MPS 0x00000010U 1010 #define MI 0x00000008U 1011 #define DBG 0x00000004U 1012 #define I2CM 0x00000002U 1013 #define CIM 0x00000001U 1014 1015 #define PL_INT_ENABLE 0x19410 1016 #define PL_INT_MAP0 0x19414 1017 #define PL_RST 0x19428 1018 #define PIORST 0x00000002U 1019 #define PIORSTMODE 0x00000001U 1020 1021 #define PL_PL_INT_CAUSE 0x19430 1022 #define FATALPERR 0x00000010U 1023 #define PERRVFID 0x00000001U 1024 1025 #define PL_REV 0x1943c 1026 1027 #define LE_DB_CONFIG 0x19c04 1028 #define HASHEN 0x00100000U 1029 1030 #define LE_DB_SERVER_INDEX 0x19c18 1031 #define LE_DB_ACT_CNT_IPV4 0x19c20 1032 #define LE_DB_ACT_CNT_IPV6 0x19c24 1033 1034 #define LE_DB_INT_CAUSE 0x19c3c 1035 #define REQQPARERR 0x00010000U 1036 #define UNKNOWNCMD 0x00008000U 1037 #define PARITYERR 0x00000040U 1038 #define LIPMISS 0x00000020U 1039 #define LIP0 0x00000010U 1040 1041 #define LE_DB_TID_HASHBASE 0x19df8 1042 1043 #define NCSI_INT_CAUSE 0x1a0d8 1044 #define CIM_DM_PRTY_ERR 0x00000100U 1045 #define MPS_DM_PRTY_ERR 0x00000080U 1046 #define TXFIFO_PRTY_ERR 0x00000002U 1047 #define RXFIFO_PRTY_ERR 0x00000001U 1048 1049 #define XGMAC_PORT_CFG2 0x1018 1050 #define PATEN 0x00040000U 1051 #define MAGICEN 0x00020000U 1052 1053 #define XGMAC_PORT_MAGIC_MACID_LO 0x1024 1054 #define XGMAC_PORT_MAGIC_MACID_HI 0x1028 1055 1056 #define XGMAC_PORT_EPIO_DATA0 0x10c0 1057 #define XGMAC_PORT_EPIO_DATA1 0x10c4 1058 #define XGMAC_PORT_EPIO_DATA2 0x10c8 1059 #define XGMAC_PORT_EPIO_DATA3 0x10cc 1060 #define XGMAC_PORT_EPIO_OP 0x10d0 1061 #define EPIOWR 0x00000100U 1062 #define ADDRESS_MASK 0x000000ffU 1063 #define ADDRESS_SHIFT 0 1064 #define ADDRESS(x) ((x) << ADDRESS_SHIFT) 1065 1066 #define XGMAC_PORT_INT_CAUSE 0x10dc 1067 1068 #define A_TP_TX_MOD_QUEUE_REQ_MAP 0x7e28 1069 1070 #define A_TP_TX_MOD_CHANNEL_WEIGHT 0x7e34 1071 1072 #define S_TX_MOD_QUEUE_REQ_MAP 0 1073 #define M_TX_MOD_QUEUE_REQ_MAP 0xffffU 1074 #define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP) 1075 1076 #define A_TP_TX_MOD_QUEUE_WEIGHT0 0x7e30 1077 1078 #define S_TX_MODQ_WEIGHT3 24 1079 #define M_TX_MODQ_WEIGHT3 0xffU 1080 #define V_TX_MODQ_WEIGHT3(x) ((x) << S_TX_MODQ_WEIGHT3) 1081 1082 #define S_TX_MODQ_WEIGHT2 16 1083 #define M_TX_MODQ_WEIGHT2 0xffU 1084 #define V_TX_MODQ_WEIGHT2(x) ((x) << S_TX_MODQ_WEIGHT2) 1085 1086 #define S_TX_MODQ_WEIGHT1 8 1087 #define M_TX_MODQ_WEIGHT1 0xffU 1088 #define V_TX_MODQ_WEIGHT1(x) ((x) << S_TX_MODQ_WEIGHT1) 1089 1090 #define S_TX_MODQ_WEIGHT0 0 1091 #define M_TX_MODQ_WEIGHT0 0xffU 1092 #define V_TX_MODQ_WEIGHT0(x) ((x) << S_TX_MODQ_WEIGHT0) 1093 1094 #define A_TP_TX_SCHED_HDR 0x23 1095 1096 #define A_TP_TX_SCHED_FIFO 0x24 1097 1098 #define A_TP_TX_SCHED_PCMD 0x25 1099 1100 #define S_PORT 1 1101 #define V_PORT(x) ((x) << S_PORT) 1102 #define F_PORT V_PORT(1U) 1103 1104 #endif /* __T4_REGS_H */ 1105