1 /*
2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
3  *
4  * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
5  *
6  * This software is available to you under a choice of one of two
7  * licenses.  You may choose to be licensed under the terms of the GNU
8  * General Public License (GPL) Version 2, available from the file
9  * COPYING in the main directory of this source tree, or the
10  * OpenIB.org BSD license below:
11  *
12  *     Redistribution and use in source and binary forms, with or
13  *     without modification, are permitted provided that the following
14  *     conditions are met:
15  *
16  *      - Redistributions of source code must retain the above
17  *        copyright notice, this list of conditions and the following
18  *        disclaimer.
19  *
20  *      - Redistributions in binary form must reproduce the above
21  *        copyright notice, this list of conditions and the following
22  *        disclaimer in the documentation and/or other materials
23  *        provided with the distribution.
24  *
25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32  * SOFTWARE.
33  */
34 
35 #ifndef __T4_REGS_H
36 #define __T4_REGS_H
37 
38 #define MYPF_BASE 0x1b000
39 #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))
40 
41 #define PF0_BASE 0x1e000
42 #define PF0_REG(reg_addr) (PF0_BASE + (reg_addr))
43 
44 #define PF_STRIDE 0x400
45 #define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE)
46 #define PF_REG(idx, reg) (PF_BASE(idx) + (reg))
47 
48 #define MYPORT_BASE 0x1c000
49 #define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr))
50 
51 #define PORT0_BASE 0x20000
52 #define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr))
53 
54 #define PORT_STRIDE 0x2000
55 #define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE)
56 #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))
57 
58 #define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR)
59 #define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx)
60 
61 #define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
62 #define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
63 #define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
64 #define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
65 
66 #define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
67 
68 #define SGE_PF_KDOORBELL_A 0x0
69 
70 #define QID_S    15
71 #define QID_V(x) ((x) << QID_S)
72 
73 #define DBPRIO_S    14
74 #define DBPRIO_V(x) ((x) << DBPRIO_S)
75 #define DBPRIO_F    DBPRIO_V(1U)
76 
77 #define PIDX_S    0
78 #define PIDX_V(x) ((x) << PIDX_S)
79 
80 #define SGE_VF_KDOORBELL_A 0x0
81 
82 #define DBTYPE_S    13
83 #define DBTYPE_V(x) ((x) << DBTYPE_S)
84 #define DBTYPE_F    DBTYPE_V(1U)
85 
86 #define PIDX_T5_S    0
87 #define PIDX_T5_M    0x1fffU
88 #define PIDX_T5_V(x) ((x) << PIDX_T5_S)
89 #define PIDX_T5_G(x) (((x) >> PIDX_T5_S) & PIDX_T5_M)
90 
91 #define SGE_PF_GTS_A 0x4
92 
93 #define INGRESSQID_S    16
94 #define INGRESSQID_V(x) ((x) << INGRESSQID_S)
95 
96 #define TIMERREG_S    13
97 #define TIMERREG_V(x) ((x) << TIMERREG_S)
98 
99 #define SEINTARM_S    12
100 #define SEINTARM_V(x) ((x) << SEINTARM_S)
101 
102 #define CIDXINC_S    0
103 #define CIDXINC_M    0xfffU
104 #define CIDXINC_V(x) ((x) << CIDXINC_S)
105 
106 #define SGE_CONTROL_A	0x1008
107 #define SGE_CONTROL2_A	0x1124
108 
109 #define RXPKTCPLMODE_S    18
110 #define RXPKTCPLMODE_V(x) ((x) << RXPKTCPLMODE_S)
111 #define RXPKTCPLMODE_F    RXPKTCPLMODE_V(1U)
112 
113 #define EGRSTATUSPAGESIZE_S    17
114 #define EGRSTATUSPAGESIZE_V(x) ((x) << EGRSTATUSPAGESIZE_S)
115 #define EGRSTATUSPAGESIZE_F    EGRSTATUSPAGESIZE_V(1U)
116 
117 #define PKTSHIFT_S    10
118 #define PKTSHIFT_M    0x7U
119 #define PKTSHIFT_V(x) ((x) << PKTSHIFT_S)
120 #define PKTSHIFT_G(x) (((x) >> PKTSHIFT_S) & PKTSHIFT_M)
121 
122 #define INGPCIEBOUNDARY_S    7
123 #define INGPCIEBOUNDARY_V(x) ((x) << INGPCIEBOUNDARY_S)
124 
125 #define INGPADBOUNDARY_S    4
126 #define INGPADBOUNDARY_M    0x7U
127 #define INGPADBOUNDARY_V(x) ((x) << INGPADBOUNDARY_S)
128 #define INGPADBOUNDARY_G(x) (((x) >> INGPADBOUNDARY_S) & INGPADBOUNDARY_M)
129 
130 #define EGRPCIEBOUNDARY_S    1
131 #define EGRPCIEBOUNDARY_V(x) ((x) << EGRPCIEBOUNDARY_S)
132 
133 #define  INGPACKBOUNDARY_S	16
134 #define  INGPACKBOUNDARY_M	0x7U
135 #define  INGPACKBOUNDARY_V(x)	((x) << INGPACKBOUNDARY_S)
136 #define  INGPACKBOUNDARY_G(x)	(((x) >> INGPACKBOUNDARY_S) \
137 				 & INGPACKBOUNDARY_M)
138 
139 #define VFIFO_ENABLE_S    10
140 #define VFIFO_ENABLE_V(x) ((x) << VFIFO_ENABLE_S)
141 #define VFIFO_ENABLE_F    VFIFO_ENABLE_V(1U)
142 
143 #define SGE_DBVFIFO_BADDR_A 0x1138
144 
145 #define DBVFIFO_SIZE_S    6
146 #define DBVFIFO_SIZE_M    0xfffU
147 #define DBVFIFO_SIZE_G(x) (((x) >> DBVFIFO_SIZE_S) & DBVFIFO_SIZE_M)
148 
149 #define T6_DBVFIFO_SIZE_S    0
150 #define T6_DBVFIFO_SIZE_M    0x1fffU
151 #define T6_DBVFIFO_SIZE_G(x) (((x) >> T6_DBVFIFO_SIZE_S) & T6_DBVFIFO_SIZE_M)
152 
153 #define GLOBALENABLE_S    0
154 #define GLOBALENABLE_V(x) ((x) << GLOBALENABLE_S)
155 #define GLOBALENABLE_F    GLOBALENABLE_V(1U)
156 
157 #define SGE_HOST_PAGE_SIZE_A 0x100c
158 
159 #define HOSTPAGESIZEPF7_S    28
160 #define HOSTPAGESIZEPF7_M    0xfU
161 #define HOSTPAGESIZEPF7_V(x) ((x) << HOSTPAGESIZEPF7_S)
162 #define HOSTPAGESIZEPF7_G(x) (((x) >> HOSTPAGESIZEPF7_S) & HOSTPAGESIZEPF7_M)
163 
164 #define HOSTPAGESIZEPF6_S    24
165 #define HOSTPAGESIZEPF6_M    0xfU
166 #define HOSTPAGESIZEPF6_V(x) ((x) << HOSTPAGESIZEPF6_S)
167 #define HOSTPAGESIZEPF6_G(x) (((x) >> HOSTPAGESIZEPF6_S) & HOSTPAGESIZEPF6_M)
168 
169 #define HOSTPAGESIZEPF5_S    20
170 #define HOSTPAGESIZEPF5_M    0xfU
171 #define HOSTPAGESIZEPF5_V(x) ((x) << HOSTPAGESIZEPF5_S)
172 #define HOSTPAGESIZEPF5_G(x) (((x) >> HOSTPAGESIZEPF5_S) & HOSTPAGESIZEPF5_M)
173 
174 #define HOSTPAGESIZEPF4_S    16
175 #define HOSTPAGESIZEPF4_M    0xfU
176 #define HOSTPAGESIZEPF4_V(x) ((x) << HOSTPAGESIZEPF4_S)
177 #define HOSTPAGESIZEPF4_G(x) (((x) >> HOSTPAGESIZEPF4_S) & HOSTPAGESIZEPF4_M)
178 
179 #define HOSTPAGESIZEPF3_S    12
180 #define HOSTPAGESIZEPF3_M    0xfU
181 #define HOSTPAGESIZEPF3_V(x) ((x) << HOSTPAGESIZEPF3_S)
182 #define HOSTPAGESIZEPF3_G(x) (((x) >> HOSTPAGESIZEPF3_S) & HOSTPAGESIZEPF3_M)
183 
184 #define HOSTPAGESIZEPF2_S    8
185 #define HOSTPAGESIZEPF2_M    0xfU
186 #define HOSTPAGESIZEPF2_V(x) ((x) << HOSTPAGESIZEPF2_S)
187 #define HOSTPAGESIZEPF2_G(x) (((x) >> HOSTPAGESIZEPF2_S) & HOSTPAGESIZEPF2_M)
188 
189 #define HOSTPAGESIZEPF1_S    4
190 #define HOSTPAGESIZEPF1_M    0xfU
191 #define HOSTPAGESIZEPF1_V(x) ((x) << HOSTPAGESIZEPF1_S)
192 #define HOSTPAGESIZEPF1_G(x) (((x) >> HOSTPAGESIZEPF1_S) & HOSTPAGESIZEPF1_M)
193 
194 #define HOSTPAGESIZEPF0_S    0
195 #define HOSTPAGESIZEPF0_M    0xfU
196 #define HOSTPAGESIZEPF0_V(x) ((x) << HOSTPAGESIZEPF0_S)
197 #define HOSTPAGESIZEPF0_G(x) (((x) >> HOSTPAGESIZEPF0_S) & HOSTPAGESIZEPF0_M)
198 
199 #define SGE_EGRESS_QUEUES_PER_PAGE_PF_A 0x1010
200 #define SGE_EGRESS_QUEUES_PER_PAGE_VF_A 0x1014
201 
202 #define QUEUESPERPAGEPF1_S    4
203 
204 #define QUEUESPERPAGEPF0_S    0
205 #define QUEUESPERPAGEPF0_M    0xfU
206 #define QUEUESPERPAGEPF0_V(x) ((x) << QUEUESPERPAGEPF0_S)
207 #define QUEUESPERPAGEPF0_G(x) (((x) >> QUEUESPERPAGEPF0_S) & QUEUESPERPAGEPF0_M)
208 
209 #define SGE_INT_CAUSE1_A	0x1024
210 #define SGE_INT_CAUSE2_A	0x1030
211 #define SGE_INT_CAUSE3_A	0x103c
212 
213 #define ERR_FLM_DBP_S    31
214 #define ERR_FLM_DBP_V(x) ((x) << ERR_FLM_DBP_S)
215 #define ERR_FLM_DBP_F    ERR_FLM_DBP_V(1U)
216 
217 #define ERR_FLM_IDMA1_S    30
218 #define ERR_FLM_IDMA1_V(x) ((x) << ERR_FLM_IDMA1_S)
219 #define ERR_FLM_IDMA1_F    ERR_FLM_IDMA1_V(1U)
220 
221 #define ERR_FLM_IDMA0_S    29
222 #define ERR_FLM_IDMA0_V(x) ((x) << ERR_FLM_IDMA0_S)
223 #define ERR_FLM_IDMA0_F    ERR_FLM_IDMA0_V(1U)
224 
225 #define ERR_FLM_HINT_S    28
226 #define ERR_FLM_HINT_V(x) ((x) << ERR_FLM_HINT_S)
227 #define ERR_FLM_HINT_F    ERR_FLM_HINT_V(1U)
228 
229 #define ERR_PCIE_ERROR3_S    27
230 #define ERR_PCIE_ERROR3_V(x) ((x) << ERR_PCIE_ERROR3_S)
231 #define ERR_PCIE_ERROR3_F    ERR_PCIE_ERROR3_V(1U)
232 
233 #define ERR_PCIE_ERROR2_S    26
234 #define ERR_PCIE_ERROR2_V(x) ((x) << ERR_PCIE_ERROR2_S)
235 #define ERR_PCIE_ERROR2_F    ERR_PCIE_ERROR2_V(1U)
236 
237 #define ERR_PCIE_ERROR1_S    25
238 #define ERR_PCIE_ERROR1_V(x) ((x) << ERR_PCIE_ERROR1_S)
239 #define ERR_PCIE_ERROR1_F    ERR_PCIE_ERROR1_V(1U)
240 
241 #define ERR_PCIE_ERROR0_S    24
242 #define ERR_PCIE_ERROR0_V(x) ((x) << ERR_PCIE_ERROR0_S)
243 #define ERR_PCIE_ERROR0_F    ERR_PCIE_ERROR0_V(1U)
244 
245 #define ERR_CPL_EXCEED_IQE_SIZE_S    22
246 #define ERR_CPL_EXCEED_IQE_SIZE_V(x) ((x) << ERR_CPL_EXCEED_IQE_SIZE_S)
247 #define ERR_CPL_EXCEED_IQE_SIZE_F    ERR_CPL_EXCEED_IQE_SIZE_V(1U)
248 
249 #define ERR_INVALID_CIDX_INC_S    21
250 #define ERR_INVALID_CIDX_INC_V(x) ((x) << ERR_INVALID_CIDX_INC_S)
251 #define ERR_INVALID_CIDX_INC_F    ERR_INVALID_CIDX_INC_V(1U)
252 
253 #define ERR_CPL_OPCODE_0_S    19
254 #define ERR_CPL_OPCODE_0_V(x) ((x) << ERR_CPL_OPCODE_0_S)
255 #define ERR_CPL_OPCODE_0_F    ERR_CPL_OPCODE_0_V(1U)
256 
257 #define ERR_DROPPED_DB_S    18
258 #define ERR_DROPPED_DB_V(x) ((x) << ERR_DROPPED_DB_S)
259 #define ERR_DROPPED_DB_F    ERR_DROPPED_DB_V(1U)
260 
261 #define ERR_DATA_CPL_ON_HIGH_QID1_S    17
262 #define ERR_DATA_CPL_ON_HIGH_QID1_V(x) ((x) << ERR_DATA_CPL_ON_HIGH_QID1_S)
263 #define ERR_DATA_CPL_ON_HIGH_QID1_F    ERR_DATA_CPL_ON_HIGH_QID1_V(1U)
264 
265 #define ERR_DATA_CPL_ON_HIGH_QID0_S    16
266 #define ERR_DATA_CPL_ON_HIGH_QID0_V(x) ((x) << ERR_DATA_CPL_ON_HIGH_QID0_S)
267 #define ERR_DATA_CPL_ON_HIGH_QID0_F    ERR_DATA_CPL_ON_HIGH_QID0_V(1U)
268 
269 #define ERR_BAD_DB_PIDX3_S    15
270 #define ERR_BAD_DB_PIDX3_V(x) ((x) << ERR_BAD_DB_PIDX3_S)
271 #define ERR_BAD_DB_PIDX3_F    ERR_BAD_DB_PIDX3_V(1U)
272 
273 #define ERR_BAD_DB_PIDX2_S    14
274 #define ERR_BAD_DB_PIDX2_V(x) ((x) << ERR_BAD_DB_PIDX2_S)
275 #define ERR_BAD_DB_PIDX2_F    ERR_BAD_DB_PIDX2_V(1U)
276 
277 #define ERR_BAD_DB_PIDX1_S    13
278 #define ERR_BAD_DB_PIDX1_V(x) ((x) << ERR_BAD_DB_PIDX1_S)
279 #define ERR_BAD_DB_PIDX1_F    ERR_BAD_DB_PIDX1_V(1U)
280 
281 #define ERR_BAD_DB_PIDX0_S    12
282 #define ERR_BAD_DB_PIDX0_V(x) ((x) << ERR_BAD_DB_PIDX0_S)
283 #define ERR_BAD_DB_PIDX0_F    ERR_BAD_DB_PIDX0_V(1U)
284 
285 #define ERR_ING_CTXT_PRIO_S    10
286 #define ERR_ING_CTXT_PRIO_V(x) ((x) << ERR_ING_CTXT_PRIO_S)
287 #define ERR_ING_CTXT_PRIO_F    ERR_ING_CTXT_PRIO_V(1U)
288 
289 #define ERR_EGR_CTXT_PRIO_S    9
290 #define ERR_EGR_CTXT_PRIO_V(x) ((x) << ERR_EGR_CTXT_PRIO_S)
291 #define ERR_EGR_CTXT_PRIO_F    ERR_EGR_CTXT_PRIO_V(1U)
292 
293 #define DBFIFO_HP_INT_S    8
294 #define DBFIFO_HP_INT_V(x) ((x) << DBFIFO_HP_INT_S)
295 #define DBFIFO_HP_INT_F    DBFIFO_HP_INT_V(1U)
296 
297 #define DBFIFO_LP_INT_S    7
298 #define DBFIFO_LP_INT_V(x) ((x) << DBFIFO_LP_INT_S)
299 #define DBFIFO_LP_INT_F    DBFIFO_LP_INT_V(1U)
300 
301 #define INGRESS_SIZE_ERR_S    5
302 #define INGRESS_SIZE_ERR_V(x) ((x) << INGRESS_SIZE_ERR_S)
303 #define INGRESS_SIZE_ERR_F    INGRESS_SIZE_ERR_V(1U)
304 
305 #define EGRESS_SIZE_ERR_S    4
306 #define EGRESS_SIZE_ERR_V(x) ((x) << EGRESS_SIZE_ERR_S)
307 #define EGRESS_SIZE_ERR_F    EGRESS_SIZE_ERR_V(1U)
308 
309 #define SGE_INT_ENABLE3_A 0x1040
310 #define SGE_FL_BUFFER_SIZE0_A 0x1044
311 #define SGE_FL_BUFFER_SIZE1_A 0x1048
312 #define SGE_FL_BUFFER_SIZE2_A 0x104c
313 #define SGE_FL_BUFFER_SIZE3_A 0x1050
314 #define SGE_FL_BUFFER_SIZE4_A 0x1054
315 #define SGE_FL_BUFFER_SIZE5_A 0x1058
316 #define SGE_FL_BUFFER_SIZE6_A 0x105c
317 #define SGE_FL_BUFFER_SIZE7_A 0x1060
318 #define SGE_FL_BUFFER_SIZE8_A 0x1064
319 
320 #define SGE_IMSG_CTXT_BADDR_A 0x1088
321 #define SGE_FLM_CACHE_BADDR_A 0x108c
322 #define SGE_INGRESS_RX_THRESHOLD_A 0x10a0
323 
324 #define THRESHOLD_0_S    24
325 #define THRESHOLD_0_M    0x3fU
326 #define THRESHOLD_0_V(x) ((x) << THRESHOLD_0_S)
327 #define THRESHOLD_0_G(x) (((x) >> THRESHOLD_0_S) & THRESHOLD_0_M)
328 
329 #define THRESHOLD_1_S    16
330 #define THRESHOLD_1_M    0x3fU
331 #define THRESHOLD_1_V(x) ((x) << THRESHOLD_1_S)
332 #define THRESHOLD_1_G(x) (((x) >> THRESHOLD_1_S) & THRESHOLD_1_M)
333 
334 #define THRESHOLD_2_S    8
335 #define THRESHOLD_2_M    0x3fU
336 #define THRESHOLD_2_V(x) ((x) << THRESHOLD_2_S)
337 #define THRESHOLD_2_G(x) (((x) >> THRESHOLD_2_S) & THRESHOLD_2_M)
338 
339 #define THRESHOLD_3_S    0
340 #define THRESHOLD_3_M    0x3fU
341 #define THRESHOLD_3_V(x) ((x) << THRESHOLD_3_S)
342 #define THRESHOLD_3_G(x) (((x) >> THRESHOLD_3_S) & THRESHOLD_3_M)
343 
344 #define SGE_CONM_CTRL_A 0x1094
345 
346 #define EGRTHRESHOLD_S    8
347 #define EGRTHRESHOLD_M    0x3fU
348 #define EGRTHRESHOLD_V(x) ((x) << EGRTHRESHOLD_S)
349 #define EGRTHRESHOLD_G(x) (((x) >> EGRTHRESHOLD_S) & EGRTHRESHOLD_M)
350 
351 #define EGRTHRESHOLDPACKING_S    14
352 #define EGRTHRESHOLDPACKING_M    0x3fU
353 #define EGRTHRESHOLDPACKING_V(x) ((x) << EGRTHRESHOLDPACKING_S)
354 #define EGRTHRESHOLDPACKING_G(x) \
355 	(((x) >> EGRTHRESHOLDPACKING_S) & EGRTHRESHOLDPACKING_M)
356 
357 #define T6_EGRTHRESHOLDPACKING_S    16
358 #define T6_EGRTHRESHOLDPACKING_M    0xffU
359 #define T6_EGRTHRESHOLDPACKING_G(x) \
360 	(((x) >> T6_EGRTHRESHOLDPACKING_S) & T6_EGRTHRESHOLDPACKING_M)
361 
362 #define SGE_TIMESTAMP_LO_A 0x1098
363 #define SGE_TIMESTAMP_HI_A 0x109c
364 
365 #define TSOP_S    28
366 #define TSOP_M    0x3U
367 #define TSOP_V(x) ((x) << TSOP_S)
368 #define TSOP_G(x) (((x) >> TSOP_S) & TSOP_M)
369 
370 #define TSVAL_S    0
371 #define TSVAL_M    0xfffffffU
372 #define TSVAL_V(x) ((x) << TSVAL_S)
373 #define TSVAL_G(x) (((x) >> TSVAL_S) & TSVAL_M)
374 
375 #define SGE_DBFIFO_STATUS_A 0x10a4
376 #define SGE_DBVFIFO_SIZE_A 0x113c
377 
378 #define HP_INT_THRESH_S    28
379 #define HP_INT_THRESH_M    0xfU
380 #define HP_INT_THRESH_V(x) ((x) << HP_INT_THRESH_S)
381 
382 #define LP_INT_THRESH_S    12
383 #define LP_INT_THRESH_M    0xfU
384 #define LP_INT_THRESH_V(x) ((x) << LP_INT_THRESH_S)
385 
386 #define SGE_DOORBELL_CONTROL_A 0x10a8
387 
388 #define NOCOALESCE_S    26
389 #define NOCOALESCE_V(x) ((x) << NOCOALESCE_S)
390 #define NOCOALESCE_F    NOCOALESCE_V(1U)
391 
392 #define ENABLE_DROP_S    13
393 #define ENABLE_DROP_V(x) ((x) << ENABLE_DROP_S)
394 #define ENABLE_DROP_F    ENABLE_DROP_V(1U)
395 
396 #define SGE_TIMER_VALUE_0_AND_1_A 0x10b8
397 
398 #define TIMERVALUE0_S    16
399 #define TIMERVALUE0_M    0xffffU
400 #define TIMERVALUE0_V(x) ((x) << TIMERVALUE0_S)
401 #define TIMERVALUE0_G(x) (((x) >> TIMERVALUE0_S) & TIMERVALUE0_M)
402 
403 #define TIMERVALUE1_S    0
404 #define TIMERVALUE1_M    0xffffU
405 #define TIMERVALUE1_V(x) ((x) << TIMERVALUE1_S)
406 #define TIMERVALUE1_G(x) (((x) >> TIMERVALUE1_S) & TIMERVALUE1_M)
407 
408 #define SGE_TIMER_VALUE_2_AND_3_A 0x10bc
409 
410 #define TIMERVALUE2_S    16
411 #define TIMERVALUE2_M    0xffffU
412 #define TIMERVALUE2_V(x) ((x) << TIMERVALUE2_S)
413 #define TIMERVALUE2_G(x) (((x) >> TIMERVALUE2_S) & TIMERVALUE2_M)
414 
415 #define TIMERVALUE3_S    0
416 #define TIMERVALUE3_M    0xffffU
417 #define TIMERVALUE3_V(x) ((x) << TIMERVALUE3_S)
418 #define TIMERVALUE3_G(x) (((x) >> TIMERVALUE3_S) & TIMERVALUE3_M)
419 
420 #define SGE_TIMER_VALUE_4_AND_5_A 0x10c0
421 
422 #define TIMERVALUE4_S    16
423 #define TIMERVALUE4_M    0xffffU
424 #define TIMERVALUE4_V(x) ((x) << TIMERVALUE4_S)
425 #define TIMERVALUE4_G(x) (((x) >> TIMERVALUE4_S) & TIMERVALUE4_M)
426 
427 #define TIMERVALUE5_S    0
428 #define TIMERVALUE5_M    0xffffU
429 #define TIMERVALUE5_V(x) ((x) << TIMERVALUE5_S)
430 #define TIMERVALUE5_G(x) (((x) >> TIMERVALUE5_S) & TIMERVALUE5_M)
431 
432 #define SGE_DEBUG_INDEX_A 0x10cc
433 #define SGE_DEBUG_DATA_HIGH_A 0x10d0
434 #define SGE_DEBUG_DATA_LOW_A 0x10d4
435 
436 #define SGE_DEBUG_DATA_LOW_INDEX_2_A	0x12c8
437 #define SGE_DEBUG_DATA_LOW_INDEX_3_A	0x12cc
438 #define SGE_DEBUG_DATA_HIGH_INDEX_10_A	0x12a8
439 
440 #define SGE_INGRESS_QUEUES_PER_PAGE_PF_A 0x10f4
441 #define SGE_INGRESS_QUEUES_PER_PAGE_VF_A 0x10f8
442 
443 #define SGE_ERROR_STATS_A 0x1100
444 
445 #define UNCAPTURED_ERROR_S    18
446 #define UNCAPTURED_ERROR_V(x) ((x) << UNCAPTURED_ERROR_S)
447 #define UNCAPTURED_ERROR_F    UNCAPTURED_ERROR_V(1U)
448 
449 #define ERROR_QID_VALID_S    17
450 #define ERROR_QID_VALID_V(x) ((x) << ERROR_QID_VALID_S)
451 #define ERROR_QID_VALID_F    ERROR_QID_VALID_V(1U)
452 
453 #define ERROR_QID_S    0
454 #define ERROR_QID_M    0x1ffffU
455 #define ERROR_QID_G(x) (((x) >> ERROR_QID_S) & ERROR_QID_M)
456 
457 #define HP_INT_THRESH_S    28
458 #define HP_INT_THRESH_M    0xfU
459 #define HP_INT_THRESH_V(x) ((x) << HP_INT_THRESH_S)
460 
461 #define HP_COUNT_S    16
462 #define HP_COUNT_M    0x7ffU
463 #define HP_COUNT_G(x) (((x) >> HP_COUNT_S) & HP_COUNT_M)
464 
465 #define LP_INT_THRESH_S    12
466 #define LP_INT_THRESH_M    0xfU
467 #define LP_INT_THRESH_V(x) ((x) << LP_INT_THRESH_S)
468 
469 #define LP_COUNT_S    0
470 #define LP_COUNT_M    0x7ffU
471 #define LP_COUNT_G(x) (((x) >> LP_COUNT_S) & LP_COUNT_M)
472 
473 #define LP_INT_THRESH_T5_S    18
474 #define LP_INT_THRESH_T5_M    0xfffU
475 #define LP_INT_THRESH_T5_V(x) ((x) << LP_INT_THRESH_T5_S)
476 
477 #define LP_COUNT_T5_S    0
478 #define LP_COUNT_T5_M    0x3ffffU
479 #define LP_COUNT_T5_G(x) (((x) >> LP_COUNT_T5_S) & LP_COUNT_T5_M)
480 
481 #define SGE_DOORBELL_CONTROL_A 0x10a8
482 
483 #define SGE_STAT_TOTAL_A	0x10e4
484 #define SGE_STAT_MATCH_A	0x10e8
485 #define SGE_STAT_CFG_A		0x10ec
486 
487 #define STATMODE_S    2
488 #define STATMODE_V(x) ((x) << STATMODE_S)
489 
490 #define STATSOURCE_T5_S    9
491 #define STATSOURCE_T5_M    0xfU
492 #define STATSOURCE_T5_V(x) ((x) << STATSOURCE_T5_S)
493 #define STATSOURCE_T5_G(x) (((x) >> STATSOURCE_T5_S) & STATSOURCE_T5_M)
494 
495 #define T6_STATMODE_S    0
496 #define T6_STATMODE_V(x) ((x) << T6_STATMODE_S)
497 
498 #define SGE_DBFIFO_STATUS2_A 0x1118
499 
500 #define HP_INT_THRESH_T5_S    10
501 #define HP_INT_THRESH_T5_M    0xfU
502 #define HP_INT_THRESH_T5_V(x) ((x) << HP_INT_THRESH_T5_S)
503 
504 #define HP_COUNT_T5_S    0
505 #define HP_COUNT_T5_M    0x3ffU
506 #define HP_COUNT_T5_G(x) (((x) >> HP_COUNT_T5_S) & HP_COUNT_T5_M)
507 
508 #define ENABLE_DROP_S    13
509 #define ENABLE_DROP_V(x) ((x) << ENABLE_DROP_S)
510 #define ENABLE_DROP_F    ENABLE_DROP_V(1U)
511 
512 #define DROPPED_DB_S    0
513 #define DROPPED_DB_V(x) ((x) << DROPPED_DB_S)
514 #define DROPPED_DB_F    DROPPED_DB_V(1U)
515 
516 #define SGE_CTXT_CMD_A 0x11fc
517 #define SGE_DBQ_CTXT_BADDR_A 0x1084
518 
519 /* registers for module PCIE */
520 #define PCIE_PF_CFG_A	0x40
521 
522 #define AIVEC_S    4
523 #define AIVEC_M    0x3ffU
524 #define AIVEC_V(x) ((x) << AIVEC_S)
525 
526 #define PCIE_PF_CLI_A	0x44
527 #define PCIE_INT_CAUSE_A	0x3004
528 
529 #define UNXSPLCPLERR_S    29
530 #define UNXSPLCPLERR_V(x) ((x) << UNXSPLCPLERR_S)
531 #define UNXSPLCPLERR_F    UNXSPLCPLERR_V(1U)
532 
533 #define PCIEPINT_S    28
534 #define PCIEPINT_V(x) ((x) << PCIEPINT_S)
535 #define PCIEPINT_F    PCIEPINT_V(1U)
536 
537 #define PCIESINT_S    27
538 #define PCIESINT_V(x) ((x) << PCIESINT_S)
539 #define PCIESINT_F    PCIESINT_V(1U)
540 
541 #define RPLPERR_S    26
542 #define RPLPERR_V(x) ((x) << RPLPERR_S)
543 #define RPLPERR_F    RPLPERR_V(1U)
544 
545 #define RXWRPERR_S    25
546 #define RXWRPERR_V(x) ((x) << RXWRPERR_S)
547 #define RXWRPERR_F    RXWRPERR_V(1U)
548 
549 #define RXCPLPERR_S    24
550 #define RXCPLPERR_V(x) ((x) << RXCPLPERR_S)
551 #define RXCPLPERR_F    RXCPLPERR_V(1U)
552 
553 #define PIOTAGPERR_S    23
554 #define PIOTAGPERR_V(x) ((x) << PIOTAGPERR_S)
555 #define PIOTAGPERR_F    PIOTAGPERR_V(1U)
556 
557 #define MATAGPERR_S    22
558 #define MATAGPERR_V(x) ((x) << MATAGPERR_S)
559 #define MATAGPERR_F    MATAGPERR_V(1U)
560 
561 #define INTXCLRPERR_S    21
562 #define INTXCLRPERR_V(x) ((x) << INTXCLRPERR_S)
563 #define INTXCLRPERR_F    INTXCLRPERR_V(1U)
564 
565 #define FIDPERR_S    20
566 #define FIDPERR_V(x) ((x) << FIDPERR_S)
567 #define FIDPERR_F    FIDPERR_V(1U)
568 
569 #define CFGSNPPERR_S    19
570 #define CFGSNPPERR_V(x) ((x) << CFGSNPPERR_S)
571 #define CFGSNPPERR_F    CFGSNPPERR_V(1U)
572 
573 #define HRSPPERR_S    18
574 #define HRSPPERR_V(x) ((x) << HRSPPERR_S)
575 #define HRSPPERR_F    HRSPPERR_V(1U)
576 
577 #define HREQPERR_S    17
578 #define HREQPERR_V(x) ((x) << HREQPERR_S)
579 #define HREQPERR_F    HREQPERR_V(1U)
580 
581 #define HCNTPERR_S    16
582 #define HCNTPERR_V(x) ((x) << HCNTPERR_S)
583 #define HCNTPERR_F    HCNTPERR_V(1U)
584 
585 #define DRSPPERR_S    15
586 #define DRSPPERR_V(x) ((x) << DRSPPERR_S)
587 #define DRSPPERR_F    DRSPPERR_V(1U)
588 
589 #define DREQPERR_S    14
590 #define DREQPERR_V(x) ((x) << DREQPERR_S)
591 #define DREQPERR_F    DREQPERR_V(1U)
592 
593 #define DCNTPERR_S    13
594 #define DCNTPERR_V(x) ((x) << DCNTPERR_S)
595 #define DCNTPERR_F    DCNTPERR_V(1U)
596 
597 #define CRSPPERR_S    12
598 #define CRSPPERR_V(x) ((x) << CRSPPERR_S)
599 #define CRSPPERR_F    CRSPPERR_V(1U)
600 
601 #define CREQPERR_S    11
602 #define CREQPERR_V(x) ((x) << CREQPERR_S)
603 #define CREQPERR_F    CREQPERR_V(1U)
604 
605 #define CCNTPERR_S    10
606 #define CCNTPERR_V(x) ((x) << CCNTPERR_S)
607 #define CCNTPERR_F    CCNTPERR_V(1U)
608 
609 #define TARTAGPERR_S    9
610 #define TARTAGPERR_V(x) ((x) << TARTAGPERR_S)
611 #define TARTAGPERR_F    TARTAGPERR_V(1U)
612 
613 #define PIOREQPERR_S    8
614 #define PIOREQPERR_V(x) ((x) << PIOREQPERR_S)
615 #define PIOREQPERR_F    PIOREQPERR_V(1U)
616 
617 #define PIOCPLPERR_S    7
618 #define PIOCPLPERR_V(x) ((x) << PIOCPLPERR_S)
619 #define PIOCPLPERR_F    PIOCPLPERR_V(1U)
620 
621 #define MSIXDIPERR_S    6
622 #define MSIXDIPERR_V(x) ((x) << MSIXDIPERR_S)
623 #define MSIXDIPERR_F    MSIXDIPERR_V(1U)
624 
625 #define MSIXDATAPERR_S    5
626 #define MSIXDATAPERR_V(x) ((x) << MSIXDATAPERR_S)
627 #define MSIXDATAPERR_F    MSIXDATAPERR_V(1U)
628 
629 #define MSIXADDRHPERR_S    4
630 #define MSIXADDRHPERR_V(x) ((x) << MSIXADDRHPERR_S)
631 #define MSIXADDRHPERR_F    MSIXADDRHPERR_V(1U)
632 
633 #define MSIXADDRLPERR_S    3
634 #define MSIXADDRLPERR_V(x) ((x) << MSIXADDRLPERR_S)
635 #define MSIXADDRLPERR_F    MSIXADDRLPERR_V(1U)
636 
637 #define MSIDATAPERR_S    2
638 #define MSIDATAPERR_V(x) ((x) << MSIDATAPERR_S)
639 #define MSIDATAPERR_F    MSIDATAPERR_V(1U)
640 
641 #define MSIADDRHPERR_S    1
642 #define MSIADDRHPERR_V(x) ((x) << MSIADDRHPERR_S)
643 #define MSIADDRHPERR_F    MSIADDRHPERR_V(1U)
644 
645 #define MSIADDRLPERR_S    0
646 #define MSIADDRLPERR_V(x) ((x) << MSIADDRLPERR_S)
647 #define MSIADDRLPERR_F    MSIADDRLPERR_V(1U)
648 
649 #define READRSPERR_S    29
650 #define READRSPERR_V(x) ((x) << READRSPERR_S)
651 #define READRSPERR_F    READRSPERR_V(1U)
652 
653 #define TRGT1GRPPERR_S    28
654 #define TRGT1GRPPERR_V(x) ((x) << TRGT1GRPPERR_S)
655 #define TRGT1GRPPERR_F    TRGT1GRPPERR_V(1U)
656 
657 #define IPSOTPERR_S    27
658 #define IPSOTPERR_V(x) ((x) << IPSOTPERR_S)
659 #define IPSOTPERR_F    IPSOTPERR_V(1U)
660 
661 #define IPRETRYPERR_S    26
662 #define IPRETRYPERR_V(x) ((x) << IPRETRYPERR_S)
663 #define IPRETRYPERR_F    IPRETRYPERR_V(1U)
664 
665 #define IPRXDATAGRPPERR_S    25
666 #define IPRXDATAGRPPERR_V(x) ((x) << IPRXDATAGRPPERR_S)
667 #define IPRXDATAGRPPERR_F    IPRXDATAGRPPERR_V(1U)
668 
669 #define IPRXHDRGRPPERR_S    24
670 #define IPRXHDRGRPPERR_V(x) ((x) << IPRXHDRGRPPERR_S)
671 #define IPRXHDRGRPPERR_F    IPRXHDRGRPPERR_V(1U)
672 
673 #define MAGRPPERR_S    22
674 #define MAGRPPERR_V(x) ((x) << MAGRPPERR_S)
675 #define MAGRPPERR_F    MAGRPPERR_V(1U)
676 
677 #define VFIDPERR_S    21
678 #define VFIDPERR_V(x) ((x) << VFIDPERR_S)
679 #define VFIDPERR_F    VFIDPERR_V(1U)
680 
681 #define HREQWRPERR_S    16
682 #define HREQWRPERR_V(x) ((x) << HREQWRPERR_S)
683 #define HREQWRPERR_F    HREQWRPERR_V(1U)
684 
685 #define DREQWRPERR_S    13
686 #define DREQWRPERR_V(x) ((x) << DREQWRPERR_S)
687 #define DREQWRPERR_F    DREQWRPERR_V(1U)
688 
689 #define CREQRDPERR_S    11
690 #define CREQRDPERR_V(x) ((x) << CREQRDPERR_S)
691 #define CREQRDPERR_F    CREQRDPERR_V(1U)
692 
693 #define MSTTAGQPERR_S    10
694 #define MSTTAGQPERR_V(x) ((x) << MSTTAGQPERR_S)
695 #define MSTTAGQPERR_F    MSTTAGQPERR_V(1U)
696 
697 #define PIOREQGRPPERR_S    8
698 #define PIOREQGRPPERR_V(x) ((x) << PIOREQGRPPERR_S)
699 #define PIOREQGRPPERR_F    PIOREQGRPPERR_V(1U)
700 
701 #define PIOCPLGRPPERR_S    7
702 #define PIOCPLGRPPERR_V(x) ((x) << PIOCPLGRPPERR_S)
703 #define PIOCPLGRPPERR_F    PIOCPLGRPPERR_V(1U)
704 
705 #define MSIXSTIPERR_S    2
706 #define MSIXSTIPERR_V(x) ((x) << MSIXSTIPERR_S)
707 #define MSIXSTIPERR_F    MSIXSTIPERR_V(1U)
708 
709 #define MSTTIMEOUTPERR_S    1
710 #define MSTTIMEOUTPERR_V(x) ((x) << MSTTIMEOUTPERR_S)
711 #define MSTTIMEOUTPERR_F    MSTTIMEOUTPERR_V(1U)
712 
713 #define MSTGRPPERR_S    0
714 #define MSTGRPPERR_V(x) ((x) << MSTGRPPERR_S)
715 #define MSTGRPPERR_F    MSTGRPPERR_V(1U)
716 
717 #define PCIE_NONFAT_ERR_A	0x3010
718 #define PCIE_CFG_SPACE_REQ_A	0x3060
719 #define PCIE_CFG_SPACE_DATA_A	0x3064
720 #define PCIE_MEM_ACCESS_BASE_WIN_A 0x3068
721 
722 #define PCIEOFST_S    10
723 #define PCIEOFST_M    0x3fffffU
724 #define PCIEOFST_G(x) (((x) >> PCIEOFST_S) & PCIEOFST_M)
725 
726 #define BIR_S    8
727 #define BIR_M    0x3U
728 #define BIR_V(x) ((x) << BIR_S)
729 #define BIR_G(x) (((x) >> BIR_S) & BIR_M)
730 
731 #define WINDOW_S    0
732 #define WINDOW_M    0xffU
733 #define WINDOW_V(x) ((x) << WINDOW_S)
734 #define WINDOW_G(x) (((x) >> WINDOW_S) & WINDOW_M)
735 
736 #define PCIE_MEM_ACCESS_OFFSET_A 0x306c
737 
738 #define ENABLE_S    30
739 #define ENABLE_V(x) ((x) << ENABLE_S)
740 #define ENABLE_F    ENABLE_V(1U)
741 
742 #define LOCALCFG_S    28
743 #define LOCALCFG_V(x) ((x) << LOCALCFG_S)
744 #define LOCALCFG_F    LOCALCFG_V(1U)
745 
746 #define FUNCTION_S    12
747 #define FUNCTION_V(x) ((x) << FUNCTION_S)
748 
749 #define REGISTER_S    0
750 #define REGISTER_V(x) ((x) << REGISTER_S)
751 
752 #define T6_ENABLE_S    31
753 #define T6_ENABLE_V(x) ((x) << T6_ENABLE_S)
754 #define T6_ENABLE_F    T6_ENABLE_V(1U)
755 
756 #define PFNUM_S    0
757 #define PFNUM_V(x) ((x) << PFNUM_S)
758 
759 #define PCIE_FW_A 0x30b8
760 #define PCIE_FW_PF_A 0x30bc
761 
762 #define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A 0x5908
763 
764 #define RNPP_S    31
765 #define RNPP_V(x) ((x) << RNPP_S)
766 #define RNPP_F    RNPP_V(1U)
767 
768 #define RPCP_S    29
769 #define RPCP_V(x) ((x) << RPCP_S)
770 #define RPCP_F    RPCP_V(1U)
771 
772 #define RCIP_S    27
773 #define RCIP_V(x) ((x) << RCIP_S)
774 #define RCIP_F    RCIP_V(1U)
775 
776 #define RCCP_S    26
777 #define RCCP_V(x) ((x) << RCCP_S)
778 #define RCCP_F    RCCP_V(1U)
779 
780 #define RFTP_S    23
781 #define RFTP_V(x) ((x) << RFTP_S)
782 #define RFTP_F    RFTP_V(1U)
783 
784 #define PTRP_S    20
785 #define PTRP_V(x) ((x) << PTRP_S)
786 #define PTRP_F    PTRP_V(1U)
787 
788 #define PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A 0x59a4
789 
790 #define TPCP_S    30
791 #define TPCP_V(x) ((x) << TPCP_S)
792 #define TPCP_F    TPCP_V(1U)
793 
794 #define TNPP_S    29
795 #define TNPP_V(x) ((x) << TNPP_S)
796 #define TNPP_F    TNPP_V(1U)
797 
798 #define TFTP_S    28
799 #define TFTP_V(x) ((x) << TFTP_S)
800 #define TFTP_F    TFTP_V(1U)
801 
802 #define TCAP_S    27
803 #define TCAP_V(x) ((x) << TCAP_S)
804 #define TCAP_F    TCAP_V(1U)
805 
806 #define TCIP_S    26
807 #define TCIP_V(x) ((x) << TCIP_S)
808 #define TCIP_F    TCIP_V(1U)
809 
810 #define RCAP_S    25
811 #define RCAP_V(x) ((x) << RCAP_S)
812 #define RCAP_F    RCAP_V(1U)
813 
814 #define PLUP_S    23
815 #define PLUP_V(x) ((x) << PLUP_S)
816 #define PLUP_F    PLUP_V(1U)
817 
818 #define PLDN_S    22
819 #define PLDN_V(x) ((x) << PLDN_S)
820 #define PLDN_F    PLDN_V(1U)
821 
822 #define OTDD_S    21
823 #define OTDD_V(x) ((x) << OTDD_S)
824 #define OTDD_F    OTDD_V(1U)
825 
826 #define GTRP_S    20
827 #define GTRP_V(x) ((x) << GTRP_S)
828 #define GTRP_F    GTRP_V(1U)
829 
830 #define RDPE_S    18
831 #define RDPE_V(x) ((x) << RDPE_S)
832 #define RDPE_F    RDPE_V(1U)
833 
834 #define TDCE_S    17
835 #define TDCE_V(x) ((x) << TDCE_S)
836 #define TDCE_F    TDCE_V(1U)
837 
838 #define TDUE_S    16
839 #define TDUE_V(x) ((x) << TDUE_S)
840 #define TDUE_F    TDUE_V(1U)
841 
842 /* registers for module MC */
843 #define MC_INT_CAUSE_A		0x7518
844 #define MC_P_INT_CAUSE_A	0x41318
845 
846 #define ECC_UE_INT_CAUSE_S    2
847 #define ECC_UE_INT_CAUSE_V(x) ((x) << ECC_UE_INT_CAUSE_S)
848 #define ECC_UE_INT_CAUSE_F    ECC_UE_INT_CAUSE_V(1U)
849 
850 #define ECC_CE_INT_CAUSE_S    1
851 #define ECC_CE_INT_CAUSE_V(x) ((x) << ECC_CE_INT_CAUSE_S)
852 #define ECC_CE_INT_CAUSE_F    ECC_CE_INT_CAUSE_V(1U)
853 
854 #define PERR_INT_CAUSE_S    0
855 #define PERR_INT_CAUSE_V(x) ((x) << PERR_INT_CAUSE_S)
856 #define PERR_INT_CAUSE_F    PERR_INT_CAUSE_V(1U)
857 
858 #define MC_ECC_STATUS_A		0x751c
859 #define MC_P_ECC_STATUS_A	0x4131c
860 
861 #define ECC_CECNT_S    16
862 #define ECC_CECNT_M    0xffffU
863 #define ECC_CECNT_V(x) ((x) << ECC_CECNT_S)
864 #define ECC_CECNT_G(x) (((x) >> ECC_CECNT_S) & ECC_CECNT_M)
865 
866 #define ECC_UECNT_S    0
867 #define ECC_UECNT_M    0xffffU
868 #define ECC_UECNT_V(x) ((x) << ECC_UECNT_S)
869 #define ECC_UECNT_G(x) (((x) >> ECC_UECNT_S) & ECC_UECNT_M)
870 
871 #define MC_BIST_CMD_A 0x7600
872 
873 #define START_BIST_S    31
874 #define START_BIST_V(x) ((x) << START_BIST_S)
875 #define START_BIST_F    START_BIST_V(1U)
876 
877 #define BIST_CMD_GAP_S    8
878 #define BIST_CMD_GAP_V(x) ((x) << BIST_CMD_GAP_S)
879 
880 #define BIST_OPCODE_S    0
881 #define BIST_OPCODE_V(x) ((x) << BIST_OPCODE_S)
882 
883 #define MC_BIST_CMD_ADDR_A 0x7604
884 #define MC_BIST_CMD_LEN_A 0x7608
885 #define MC_BIST_DATA_PATTERN_A 0x760c
886 
887 #define MC_BIST_STATUS_RDATA_A 0x7688
888 
889 /* registers for module MA */
890 #define MA_EDRAM0_BAR_A 0x77c0
891 
892 #define EDRAM0_BASE_S    16
893 #define EDRAM0_BASE_M    0xfffU
894 #define EDRAM0_BASE_G(x) (((x) >> EDRAM0_BASE_S) & EDRAM0_BASE_M)
895 
896 #define EDRAM0_SIZE_S    0
897 #define EDRAM0_SIZE_M    0xfffU
898 #define EDRAM0_SIZE_V(x) ((x) << EDRAM0_SIZE_S)
899 #define EDRAM0_SIZE_G(x) (((x) >> EDRAM0_SIZE_S) & EDRAM0_SIZE_M)
900 
901 #define MA_EDRAM1_BAR_A 0x77c4
902 
903 #define EDRAM1_BASE_S    16
904 #define EDRAM1_BASE_M    0xfffU
905 #define EDRAM1_BASE_G(x) (((x) >> EDRAM1_BASE_S) & EDRAM1_BASE_M)
906 
907 #define EDRAM1_SIZE_S    0
908 #define EDRAM1_SIZE_M    0xfffU
909 #define EDRAM1_SIZE_V(x) ((x) << EDRAM1_SIZE_S)
910 #define EDRAM1_SIZE_G(x) (((x) >> EDRAM1_SIZE_S) & EDRAM1_SIZE_M)
911 
912 #define MA_EXT_MEMORY_BAR_A 0x77c8
913 
914 #define EXT_MEM_BASE_S    16
915 #define EXT_MEM_BASE_M    0xfffU
916 #define EXT_MEM_BASE_V(x) ((x) << EXT_MEM_BASE_S)
917 #define EXT_MEM_BASE_G(x) (((x) >> EXT_MEM_BASE_S) & EXT_MEM_BASE_M)
918 
919 #define EXT_MEM_SIZE_S    0
920 #define EXT_MEM_SIZE_M    0xfffU
921 #define EXT_MEM_SIZE_V(x) ((x) << EXT_MEM_SIZE_S)
922 #define EXT_MEM_SIZE_G(x) (((x) >> EXT_MEM_SIZE_S) & EXT_MEM_SIZE_M)
923 
924 #define MA_EXT_MEMORY1_BAR_A 0x7808
925 
926 #define EXT_MEM1_BASE_S    16
927 #define EXT_MEM1_BASE_M    0xfffU
928 #define EXT_MEM1_BASE_G(x) (((x) >> EXT_MEM1_BASE_S) & EXT_MEM1_BASE_M)
929 
930 #define EXT_MEM1_SIZE_S    0
931 #define EXT_MEM1_SIZE_M    0xfffU
932 #define EXT_MEM1_SIZE_V(x) ((x) << EXT_MEM1_SIZE_S)
933 #define EXT_MEM1_SIZE_G(x) (((x) >> EXT_MEM1_SIZE_S) & EXT_MEM1_SIZE_M)
934 
935 #define MA_EXT_MEMORY0_BAR_A 0x77c8
936 
937 #define EXT_MEM0_BASE_S    16
938 #define EXT_MEM0_BASE_M    0xfffU
939 #define EXT_MEM0_BASE_G(x) (((x) >> EXT_MEM0_BASE_S) & EXT_MEM0_BASE_M)
940 
941 #define EXT_MEM0_SIZE_S    0
942 #define EXT_MEM0_SIZE_M    0xfffU
943 #define EXT_MEM0_SIZE_V(x) ((x) << EXT_MEM0_SIZE_S)
944 #define EXT_MEM0_SIZE_G(x) (((x) >> EXT_MEM0_SIZE_S) & EXT_MEM0_SIZE_M)
945 
946 #define MA_TARGET_MEM_ENABLE_A 0x77d8
947 
948 #define EXT_MEM_ENABLE_S    2
949 #define EXT_MEM_ENABLE_V(x) ((x) << EXT_MEM_ENABLE_S)
950 #define EXT_MEM_ENABLE_F    EXT_MEM_ENABLE_V(1U)
951 
952 #define EDRAM1_ENABLE_S    1
953 #define EDRAM1_ENABLE_V(x) ((x) << EDRAM1_ENABLE_S)
954 #define EDRAM1_ENABLE_F    EDRAM1_ENABLE_V(1U)
955 
956 #define EDRAM0_ENABLE_S    0
957 #define EDRAM0_ENABLE_V(x) ((x) << EDRAM0_ENABLE_S)
958 #define EDRAM0_ENABLE_F    EDRAM0_ENABLE_V(1U)
959 
960 #define EXT_MEM1_ENABLE_S    4
961 #define EXT_MEM1_ENABLE_V(x) ((x) << EXT_MEM1_ENABLE_S)
962 #define EXT_MEM1_ENABLE_F    EXT_MEM1_ENABLE_V(1U)
963 
964 #define EXT_MEM0_ENABLE_S    2
965 #define EXT_MEM0_ENABLE_V(x) ((x) << EXT_MEM0_ENABLE_S)
966 #define EXT_MEM0_ENABLE_F    EXT_MEM0_ENABLE_V(1U)
967 
968 #define MA_INT_CAUSE_A	0x77e0
969 
970 #define MEM_PERR_INT_CAUSE_S    1
971 #define MEM_PERR_INT_CAUSE_V(x) ((x) << MEM_PERR_INT_CAUSE_S)
972 #define MEM_PERR_INT_CAUSE_F    MEM_PERR_INT_CAUSE_V(1U)
973 
974 #define MEM_WRAP_INT_CAUSE_S    0
975 #define MEM_WRAP_INT_CAUSE_V(x) ((x) << MEM_WRAP_INT_CAUSE_S)
976 #define MEM_WRAP_INT_CAUSE_F    MEM_WRAP_INT_CAUSE_V(1U)
977 
978 #define MA_INT_WRAP_STATUS_A	0x77e4
979 
980 #define MEM_WRAP_ADDRESS_S    4
981 #define MEM_WRAP_ADDRESS_M    0xfffffffU
982 #define MEM_WRAP_ADDRESS_G(x) (((x) >> MEM_WRAP_ADDRESS_S) & MEM_WRAP_ADDRESS_M)
983 
984 #define MEM_WRAP_CLIENT_NUM_S    0
985 #define MEM_WRAP_CLIENT_NUM_M    0xfU
986 #define MEM_WRAP_CLIENT_NUM_G(x) \
987 	(((x) >> MEM_WRAP_CLIENT_NUM_S) & MEM_WRAP_CLIENT_NUM_M)
988 
989 #define MA_PARITY_ERROR_STATUS_A	0x77f4
990 #define MA_PARITY_ERROR_STATUS1_A	0x77f4
991 #define MA_PARITY_ERROR_STATUS2_A	0x7804
992 
993 /* registers for module EDC_0 */
994 #define EDC_0_BASE_ADDR		0x7900
995 
996 #define EDC_BIST_CMD_A		0x7904
997 #define EDC_BIST_CMD_ADDR_A	0x7908
998 #define EDC_BIST_CMD_LEN_A	0x790c
999 #define EDC_BIST_DATA_PATTERN_A 0x7910
1000 #define EDC_BIST_STATUS_RDATA_A	0x7928
1001 #define EDC_INT_CAUSE_A		0x7978
1002 
1003 #define ECC_UE_PAR_S    5
1004 #define ECC_UE_PAR_V(x) ((x) << ECC_UE_PAR_S)
1005 #define ECC_UE_PAR_F    ECC_UE_PAR_V(1U)
1006 
1007 #define ECC_CE_PAR_S    4
1008 #define ECC_CE_PAR_V(x) ((x) << ECC_CE_PAR_S)
1009 #define ECC_CE_PAR_F    ECC_CE_PAR_V(1U)
1010 
1011 #define PERR_PAR_CAUSE_S    3
1012 #define PERR_PAR_CAUSE_V(x) ((x) << PERR_PAR_CAUSE_S)
1013 #define PERR_PAR_CAUSE_F    PERR_PAR_CAUSE_V(1U)
1014 
1015 #define EDC_ECC_STATUS_A	0x797c
1016 
1017 /* registers for module EDC_1 */
1018 #define EDC_1_BASE_ADDR	0x7980
1019 
1020 /* registers for module CIM */
1021 #define CIM_BOOT_CFG_A 0x7b00
1022 #define CIM_SDRAM_BASE_ADDR_A 0x7b14
1023 #define CIM_SDRAM_ADDR_SIZE_A 0x7b18
1024 #define CIM_EXTMEM2_BASE_ADDR_A 0x7b1c
1025 #define CIM_EXTMEM2_ADDR_SIZE_A 0x7b20
1026 #define CIM_PF_MAILBOX_CTRL_SHADOW_COPY_A 0x290
1027 
1028 #define  BOOTADDR_M	0xffffff00U
1029 
1030 #define UPCRST_S    0
1031 #define UPCRST_V(x) ((x) << UPCRST_S)
1032 #define UPCRST_F    UPCRST_V(1U)
1033 
1034 #define CIM_PF_MAILBOX_DATA_A 0x240
1035 #define CIM_PF_MAILBOX_CTRL_A 0x280
1036 
1037 #define MBMSGVALID_S    3
1038 #define MBMSGVALID_V(x) ((x) << MBMSGVALID_S)
1039 #define MBMSGVALID_F    MBMSGVALID_V(1U)
1040 
1041 #define MBINTREQ_S    2
1042 #define MBINTREQ_V(x) ((x) << MBINTREQ_S)
1043 #define MBINTREQ_F    MBINTREQ_V(1U)
1044 
1045 #define MBOWNER_S    0
1046 #define MBOWNER_M    0x3U
1047 #define MBOWNER_V(x) ((x) << MBOWNER_S)
1048 #define MBOWNER_G(x) (((x) >> MBOWNER_S) & MBOWNER_M)
1049 
1050 #define CIM_PF_HOST_INT_ENABLE_A 0x288
1051 
1052 #define MBMSGRDYINTEN_S    19
1053 #define MBMSGRDYINTEN_V(x) ((x) << MBMSGRDYINTEN_S)
1054 #define MBMSGRDYINTEN_F    MBMSGRDYINTEN_V(1U)
1055 
1056 #define CIM_PF_HOST_INT_CAUSE_A 0x28c
1057 
1058 #define MBMSGRDYINT_S    19
1059 #define MBMSGRDYINT_V(x) ((x) << MBMSGRDYINT_S)
1060 #define MBMSGRDYINT_F    MBMSGRDYINT_V(1U)
1061 
1062 #define CIM_HOST_INT_CAUSE_A 0x7b2c
1063 
1064 #define TIEQOUTPARERRINT_S    20
1065 #define TIEQOUTPARERRINT_V(x) ((x) << TIEQOUTPARERRINT_S)
1066 #define TIEQOUTPARERRINT_F    TIEQOUTPARERRINT_V(1U)
1067 
1068 #define TIEQINPARERRINT_S    19
1069 #define TIEQINPARERRINT_V(x) ((x) << TIEQINPARERRINT_S)
1070 #define TIEQINPARERRINT_F    TIEQINPARERRINT_V(1U)
1071 
1072 #define PREFDROPINT_S    1
1073 #define PREFDROPINT_V(x) ((x) << PREFDROPINT_S)
1074 #define PREFDROPINT_F    PREFDROPINT_V(1U)
1075 
1076 #define UPACCNONZERO_S    0
1077 #define UPACCNONZERO_V(x) ((x) << UPACCNONZERO_S)
1078 #define UPACCNONZERO_F    UPACCNONZERO_V(1U)
1079 
1080 #define MBHOSTPARERR_S    18
1081 #define MBHOSTPARERR_V(x) ((x) << MBHOSTPARERR_S)
1082 #define MBHOSTPARERR_F    MBHOSTPARERR_V(1U)
1083 
1084 #define MBUPPARERR_S    17
1085 #define MBUPPARERR_V(x) ((x) << MBUPPARERR_S)
1086 #define MBUPPARERR_F    MBUPPARERR_V(1U)
1087 
1088 #define IBQTP0PARERR_S    16
1089 #define IBQTP0PARERR_V(x) ((x) << IBQTP0PARERR_S)
1090 #define IBQTP0PARERR_F    IBQTP0PARERR_V(1U)
1091 
1092 #define IBQTP1PARERR_S    15
1093 #define IBQTP1PARERR_V(x) ((x) << IBQTP1PARERR_S)
1094 #define IBQTP1PARERR_F    IBQTP1PARERR_V(1U)
1095 
1096 #define IBQULPPARERR_S    14
1097 #define IBQULPPARERR_V(x) ((x) << IBQULPPARERR_S)
1098 #define IBQULPPARERR_F    IBQULPPARERR_V(1U)
1099 
1100 #define IBQSGELOPARERR_S    13
1101 #define IBQSGELOPARERR_V(x) ((x) << IBQSGELOPARERR_S)
1102 #define IBQSGELOPARERR_F    IBQSGELOPARERR_V(1U)
1103 
1104 #define IBQSGEHIPARERR_S    12
1105 #define IBQSGEHIPARERR_V(x) ((x) << IBQSGEHIPARERR_S)
1106 #define IBQSGEHIPARERR_F    IBQSGEHIPARERR_V(1U)
1107 
1108 #define IBQNCSIPARERR_S    11
1109 #define IBQNCSIPARERR_V(x) ((x) << IBQNCSIPARERR_S)
1110 #define IBQNCSIPARERR_F    IBQNCSIPARERR_V(1U)
1111 
1112 #define OBQULP0PARERR_S    10
1113 #define OBQULP0PARERR_V(x) ((x) << OBQULP0PARERR_S)
1114 #define OBQULP0PARERR_F    OBQULP0PARERR_V(1U)
1115 
1116 #define OBQULP1PARERR_S    9
1117 #define OBQULP1PARERR_V(x) ((x) << OBQULP1PARERR_S)
1118 #define OBQULP1PARERR_F    OBQULP1PARERR_V(1U)
1119 
1120 #define OBQULP2PARERR_S    8
1121 #define OBQULP2PARERR_V(x) ((x) << OBQULP2PARERR_S)
1122 #define OBQULP2PARERR_F    OBQULP2PARERR_V(1U)
1123 
1124 #define OBQULP3PARERR_S    7
1125 #define OBQULP3PARERR_V(x) ((x) << OBQULP3PARERR_S)
1126 #define OBQULP3PARERR_F    OBQULP3PARERR_V(1U)
1127 
1128 #define OBQSGEPARERR_S    6
1129 #define OBQSGEPARERR_V(x) ((x) << OBQSGEPARERR_S)
1130 #define OBQSGEPARERR_F    OBQSGEPARERR_V(1U)
1131 
1132 #define OBQNCSIPARERR_S    5
1133 #define OBQNCSIPARERR_V(x) ((x) << OBQNCSIPARERR_S)
1134 #define OBQNCSIPARERR_F    OBQNCSIPARERR_V(1U)
1135 
1136 #define CIM_HOST_UPACC_INT_CAUSE_A 0x7b34
1137 
1138 #define EEPROMWRINT_S    30
1139 #define EEPROMWRINT_V(x) ((x) << EEPROMWRINT_S)
1140 #define EEPROMWRINT_F    EEPROMWRINT_V(1U)
1141 
1142 #define TIMEOUTMAINT_S    29
1143 #define TIMEOUTMAINT_V(x) ((x) << TIMEOUTMAINT_S)
1144 #define TIMEOUTMAINT_F    TIMEOUTMAINT_V(1U)
1145 
1146 #define TIMEOUTINT_S    28
1147 #define TIMEOUTINT_V(x) ((x) << TIMEOUTINT_S)
1148 #define TIMEOUTINT_F    TIMEOUTINT_V(1U)
1149 
1150 #define RSPOVRLOOKUPINT_S    27
1151 #define RSPOVRLOOKUPINT_V(x) ((x) << RSPOVRLOOKUPINT_S)
1152 #define RSPOVRLOOKUPINT_F    RSPOVRLOOKUPINT_V(1U)
1153 
1154 #define REQOVRLOOKUPINT_S    26
1155 #define REQOVRLOOKUPINT_V(x) ((x) << REQOVRLOOKUPINT_S)
1156 #define REQOVRLOOKUPINT_F    REQOVRLOOKUPINT_V(1U)
1157 
1158 #define BLKWRPLINT_S    25
1159 #define BLKWRPLINT_V(x) ((x) << BLKWRPLINT_S)
1160 #define BLKWRPLINT_F    BLKWRPLINT_V(1U)
1161 
1162 #define BLKRDPLINT_S    24
1163 #define BLKRDPLINT_V(x) ((x) << BLKRDPLINT_S)
1164 #define BLKRDPLINT_F    BLKRDPLINT_V(1U)
1165 
1166 #define SGLWRPLINT_S    23
1167 #define SGLWRPLINT_V(x) ((x) << SGLWRPLINT_S)
1168 #define SGLWRPLINT_F    SGLWRPLINT_V(1U)
1169 
1170 #define SGLRDPLINT_S    22
1171 #define SGLRDPLINT_V(x) ((x) << SGLRDPLINT_S)
1172 #define SGLRDPLINT_F    SGLRDPLINT_V(1U)
1173 
1174 #define BLKWRCTLINT_S    21
1175 #define BLKWRCTLINT_V(x) ((x) << BLKWRCTLINT_S)
1176 #define BLKWRCTLINT_F    BLKWRCTLINT_V(1U)
1177 
1178 #define BLKRDCTLINT_S    20
1179 #define BLKRDCTLINT_V(x) ((x) << BLKRDCTLINT_S)
1180 #define BLKRDCTLINT_F    BLKRDCTLINT_V(1U)
1181 
1182 #define SGLWRCTLINT_S    19
1183 #define SGLWRCTLINT_V(x) ((x) << SGLWRCTLINT_S)
1184 #define SGLWRCTLINT_F    SGLWRCTLINT_V(1U)
1185 
1186 #define SGLRDCTLINT_S    18
1187 #define SGLRDCTLINT_V(x) ((x) << SGLRDCTLINT_S)
1188 #define SGLRDCTLINT_F    SGLRDCTLINT_V(1U)
1189 
1190 #define BLKWREEPROMINT_S    17
1191 #define BLKWREEPROMINT_V(x) ((x) << BLKWREEPROMINT_S)
1192 #define BLKWREEPROMINT_F    BLKWREEPROMINT_V(1U)
1193 
1194 #define BLKRDEEPROMINT_S    16
1195 #define BLKRDEEPROMINT_V(x) ((x) << BLKRDEEPROMINT_S)
1196 #define BLKRDEEPROMINT_F    BLKRDEEPROMINT_V(1U)
1197 
1198 #define SGLWREEPROMINT_S    15
1199 #define SGLWREEPROMINT_V(x) ((x) << SGLWREEPROMINT_S)
1200 #define SGLWREEPROMINT_F    SGLWREEPROMINT_V(1U)
1201 
1202 #define SGLRDEEPROMINT_S    14
1203 #define SGLRDEEPROMINT_V(x) ((x) << SGLRDEEPROMINT_S)
1204 #define SGLRDEEPROMINT_F    SGLRDEEPROMINT_V(1U)
1205 
1206 #define BLKWRFLASHINT_S    13
1207 #define BLKWRFLASHINT_V(x) ((x) << BLKWRFLASHINT_S)
1208 #define BLKWRFLASHINT_F    BLKWRFLASHINT_V(1U)
1209 
1210 #define BLKRDFLASHINT_S    12
1211 #define BLKRDFLASHINT_V(x) ((x) << BLKRDFLASHINT_S)
1212 #define BLKRDFLASHINT_F    BLKRDFLASHINT_V(1U)
1213 
1214 #define SGLWRFLASHINT_S    11
1215 #define SGLWRFLASHINT_V(x) ((x) << SGLWRFLASHINT_S)
1216 #define SGLWRFLASHINT_F    SGLWRFLASHINT_V(1U)
1217 
1218 #define SGLRDFLASHINT_S    10
1219 #define SGLRDFLASHINT_V(x) ((x) << SGLRDFLASHINT_S)
1220 #define SGLRDFLASHINT_F    SGLRDFLASHINT_V(1U)
1221 
1222 #define BLKWRBOOTINT_S    9
1223 #define BLKWRBOOTINT_V(x) ((x) << BLKWRBOOTINT_S)
1224 #define BLKWRBOOTINT_F    BLKWRBOOTINT_V(1U)
1225 
1226 #define BLKRDBOOTINT_S    8
1227 #define BLKRDBOOTINT_V(x) ((x) << BLKRDBOOTINT_S)
1228 #define BLKRDBOOTINT_F    BLKRDBOOTINT_V(1U)
1229 
1230 #define SGLWRBOOTINT_S    7
1231 #define SGLWRBOOTINT_V(x) ((x) << SGLWRBOOTINT_S)
1232 #define SGLWRBOOTINT_F    SGLWRBOOTINT_V(1U)
1233 
1234 #define SGLRDBOOTINT_S    6
1235 #define SGLRDBOOTINT_V(x) ((x) << SGLRDBOOTINT_S)
1236 #define SGLRDBOOTINT_F    SGLRDBOOTINT_V(1U)
1237 
1238 #define ILLWRBEINT_S    5
1239 #define ILLWRBEINT_V(x) ((x) << ILLWRBEINT_S)
1240 #define ILLWRBEINT_F    ILLWRBEINT_V(1U)
1241 
1242 #define ILLRDBEINT_S    4
1243 #define ILLRDBEINT_V(x) ((x) << ILLRDBEINT_S)
1244 #define ILLRDBEINT_F    ILLRDBEINT_V(1U)
1245 
1246 #define ILLRDINT_S    3
1247 #define ILLRDINT_V(x) ((x) << ILLRDINT_S)
1248 #define ILLRDINT_F    ILLRDINT_V(1U)
1249 
1250 #define ILLWRINT_S    2
1251 #define ILLWRINT_V(x) ((x) << ILLWRINT_S)
1252 #define ILLWRINT_F    ILLWRINT_V(1U)
1253 
1254 #define ILLTRANSINT_S    1
1255 #define ILLTRANSINT_V(x) ((x) << ILLTRANSINT_S)
1256 #define ILLTRANSINT_F    ILLTRANSINT_V(1U)
1257 
1258 #define RSVDSPACEINT_S    0
1259 #define RSVDSPACEINT_V(x) ((x) << RSVDSPACEINT_S)
1260 #define RSVDSPACEINT_F    RSVDSPACEINT_V(1U)
1261 
1262 /* registers for module TP */
1263 #define DBGLAWHLF_S    23
1264 #define DBGLAWHLF_V(x) ((x) << DBGLAWHLF_S)
1265 #define DBGLAWHLF_F    DBGLAWHLF_V(1U)
1266 
1267 #define DBGLAWPTR_S    16
1268 #define DBGLAWPTR_M    0x7fU
1269 #define DBGLAWPTR_G(x) (((x) >> DBGLAWPTR_S) & DBGLAWPTR_M)
1270 
1271 #define DBGLAENABLE_S    12
1272 #define DBGLAENABLE_V(x) ((x) << DBGLAENABLE_S)
1273 #define DBGLAENABLE_F    DBGLAENABLE_V(1U)
1274 
1275 #define DBGLARPTR_S    0
1276 #define DBGLARPTR_M    0x7fU
1277 #define DBGLARPTR_V(x) ((x) << DBGLARPTR_S)
1278 
1279 #define TP_DBG_LA_DATAL_A	0x7ed8
1280 #define TP_DBG_LA_CONFIG_A	0x7ed4
1281 #define TP_OUT_CONFIG_A		0x7d04
1282 #define TP_GLOBAL_CONFIG_A	0x7d08
1283 
1284 #define TP_CMM_TCB_BASE_A 0x7d10
1285 #define TP_CMM_MM_BASE_A 0x7d14
1286 #define TP_CMM_TIMER_BASE_A 0x7d18
1287 #define TP_PMM_TX_BASE_A 0x7d20
1288 #define TP_PMM_RX_BASE_A 0x7d28
1289 #define TP_PMM_RX_PAGE_SIZE_A 0x7d2c
1290 #define TP_PMM_RX_MAX_PAGE_A 0x7d30
1291 #define TP_PMM_TX_PAGE_SIZE_A 0x7d34
1292 #define TP_PMM_TX_MAX_PAGE_A 0x7d38
1293 #define TP_CMM_MM_MAX_PSTRUCT_A 0x7e6c
1294 
1295 #define PMRXNUMCHN_S    31
1296 #define PMRXNUMCHN_V(x) ((x) << PMRXNUMCHN_S)
1297 #define PMRXNUMCHN_F    PMRXNUMCHN_V(1U)
1298 
1299 #define PMTXNUMCHN_S    30
1300 #define PMTXNUMCHN_M    0x3U
1301 #define PMTXNUMCHN_G(x) (((x) >> PMTXNUMCHN_S) & PMTXNUMCHN_M)
1302 
1303 #define PMTXMAXPAGE_S    0
1304 #define PMTXMAXPAGE_M    0x1fffffU
1305 #define PMTXMAXPAGE_G(x) (((x) >> PMTXMAXPAGE_S) & PMTXMAXPAGE_M)
1306 
1307 #define PMRXMAXPAGE_S    0
1308 #define PMRXMAXPAGE_M    0x1fffffU
1309 #define PMRXMAXPAGE_G(x) (((x) >> PMRXMAXPAGE_S) & PMRXMAXPAGE_M)
1310 
1311 #define DBGLAMODE_S	14
1312 #define DBGLAMODE_M	0x3U
1313 #define DBGLAMODE_G(x)	(((x) >> DBGLAMODE_S) & DBGLAMODE_M)
1314 
1315 #define FIVETUPLELOOKUP_S    17
1316 #define FIVETUPLELOOKUP_M    0x3U
1317 #define FIVETUPLELOOKUP_V(x) ((x) << FIVETUPLELOOKUP_S)
1318 #define FIVETUPLELOOKUP_G(x) (((x) >> FIVETUPLELOOKUP_S) & FIVETUPLELOOKUP_M)
1319 
1320 #define TP_PARA_REG2_A 0x7d68
1321 
1322 #define MAXRXDATA_S    16
1323 #define MAXRXDATA_M    0xffffU
1324 #define MAXRXDATA_G(x) (((x) >> MAXRXDATA_S) & MAXRXDATA_M)
1325 
1326 #define TP_TIMER_RESOLUTION_A 0x7d90
1327 
1328 #define TIMERRESOLUTION_S    16
1329 #define TIMERRESOLUTION_M    0xffU
1330 #define TIMERRESOLUTION_G(x) (((x) >> TIMERRESOLUTION_S) & TIMERRESOLUTION_M)
1331 
1332 #define TIMESTAMPRESOLUTION_S    8
1333 #define TIMESTAMPRESOLUTION_M    0xffU
1334 #define TIMESTAMPRESOLUTION_G(x) \
1335 	(((x) >> TIMESTAMPRESOLUTION_S) & TIMESTAMPRESOLUTION_M)
1336 
1337 #define DELAYEDACKRESOLUTION_S    0
1338 #define DELAYEDACKRESOLUTION_M    0xffU
1339 #define DELAYEDACKRESOLUTION_G(x) \
1340 	(((x) >> DELAYEDACKRESOLUTION_S) & DELAYEDACKRESOLUTION_M)
1341 
1342 #define TP_SHIFT_CNT_A 0x7dc0
1343 #define TP_RXT_MIN_A 0x7d98
1344 #define TP_RXT_MAX_A 0x7d9c
1345 #define TP_PERS_MIN_A 0x7da0
1346 #define TP_PERS_MAX_A 0x7da4
1347 #define TP_KEEP_IDLE_A 0x7da8
1348 #define TP_KEEP_INTVL_A 0x7dac
1349 #define TP_INIT_SRTT_A 0x7db0
1350 #define TP_DACK_TIMER_A 0x7db4
1351 #define TP_FINWAIT2_TIMER_A 0x7db8
1352 
1353 #define INITSRTT_S    0
1354 #define INITSRTT_M    0xffffU
1355 #define INITSRTT_G(x) (((x) >> INITSRTT_S) & INITSRTT_M)
1356 
1357 #define PERSMAX_S    0
1358 #define PERSMAX_M    0x3fffffffU
1359 #define PERSMAX_V(x) ((x) << PERSMAX_S)
1360 #define PERSMAX_G(x) (((x) >> PERSMAX_S) & PERSMAX_M)
1361 
1362 #define SYNSHIFTMAX_S    24
1363 #define SYNSHIFTMAX_M    0xffU
1364 #define SYNSHIFTMAX_V(x) ((x) << SYNSHIFTMAX_S)
1365 #define SYNSHIFTMAX_G(x) (((x) >> SYNSHIFTMAX_S) & SYNSHIFTMAX_M)
1366 
1367 #define RXTSHIFTMAXR1_S    20
1368 #define RXTSHIFTMAXR1_M    0xfU
1369 #define RXTSHIFTMAXR1_V(x) ((x) << RXTSHIFTMAXR1_S)
1370 #define RXTSHIFTMAXR1_G(x) (((x) >> RXTSHIFTMAXR1_S) & RXTSHIFTMAXR1_M)
1371 
1372 #define RXTSHIFTMAXR2_S    16
1373 #define RXTSHIFTMAXR2_M    0xfU
1374 #define RXTSHIFTMAXR2_V(x) ((x) << RXTSHIFTMAXR2_S)
1375 #define RXTSHIFTMAXR2_G(x) (((x) >> RXTSHIFTMAXR2_S) & RXTSHIFTMAXR2_M)
1376 
1377 #define PERSHIFTBACKOFFMAX_S    12
1378 #define PERSHIFTBACKOFFMAX_M    0xfU
1379 #define PERSHIFTBACKOFFMAX_V(x) ((x) << PERSHIFTBACKOFFMAX_S)
1380 #define PERSHIFTBACKOFFMAX_G(x) \
1381 	(((x) >> PERSHIFTBACKOFFMAX_S) & PERSHIFTBACKOFFMAX_M)
1382 
1383 #define PERSHIFTMAX_S    8
1384 #define PERSHIFTMAX_M    0xfU
1385 #define PERSHIFTMAX_V(x) ((x) << PERSHIFTMAX_S)
1386 #define PERSHIFTMAX_G(x) (((x) >> PERSHIFTMAX_S) & PERSHIFTMAX_M)
1387 
1388 #define KEEPALIVEMAXR1_S    4
1389 #define KEEPALIVEMAXR1_M    0xfU
1390 #define KEEPALIVEMAXR1_V(x) ((x) << KEEPALIVEMAXR1_S)
1391 #define KEEPALIVEMAXR1_G(x) (((x) >> KEEPALIVEMAXR1_S) & KEEPALIVEMAXR1_M)
1392 
1393 #define KEEPALIVEMAXR2_S    0
1394 #define KEEPALIVEMAXR2_M    0xfU
1395 #define KEEPALIVEMAXR2_V(x) ((x) << KEEPALIVEMAXR2_S)
1396 #define KEEPALIVEMAXR2_G(x) (((x) >> KEEPALIVEMAXR2_S) & KEEPALIVEMAXR2_M)
1397 
1398 #define ROWINDEX_S    16
1399 #define ROWINDEX_V(x) ((x) << ROWINDEX_S)
1400 
1401 #define TP_CCTRL_TABLE_A	0x7ddc
1402 #define TP_MTU_TABLE_A		0x7de4
1403 
1404 #define MTUINDEX_S    24
1405 #define MTUINDEX_V(x) ((x) << MTUINDEX_S)
1406 
1407 #define MTUWIDTH_S    16
1408 #define MTUWIDTH_M    0xfU
1409 #define MTUWIDTH_V(x) ((x) << MTUWIDTH_S)
1410 #define MTUWIDTH_G(x) (((x) >> MTUWIDTH_S) & MTUWIDTH_M)
1411 
1412 #define MTUVALUE_S    0
1413 #define MTUVALUE_M    0x3fffU
1414 #define MTUVALUE_V(x) ((x) << MTUVALUE_S)
1415 #define MTUVALUE_G(x) (((x) >> MTUVALUE_S) & MTUVALUE_M)
1416 
1417 #define TP_RSS_LKP_TABLE_A	0x7dec
1418 #define TP_CMM_MM_RX_FLST_BASE_A 0x7e60
1419 #define TP_CMM_MM_TX_FLST_BASE_A 0x7e64
1420 #define TP_CMM_MM_PS_FLST_BASE_A 0x7e68
1421 
1422 #define LKPTBLROWVLD_S    31
1423 #define LKPTBLROWVLD_V(x) ((x) << LKPTBLROWVLD_S)
1424 #define LKPTBLROWVLD_F    LKPTBLROWVLD_V(1U)
1425 
1426 #define LKPTBLQUEUE1_S    10
1427 #define LKPTBLQUEUE1_M    0x3ffU
1428 #define LKPTBLQUEUE1_G(x) (((x) >> LKPTBLQUEUE1_S) & LKPTBLQUEUE1_M)
1429 
1430 #define LKPTBLQUEUE0_S    0
1431 #define LKPTBLQUEUE0_M    0x3ffU
1432 #define LKPTBLQUEUE0_G(x) (((x) >> LKPTBLQUEUE0_S) & LKPTBLQUEUE0_M)
1433 
1434 #define TP_PIO_ADDR_A	0x7e40
1435 #define TP_PIO_DATA_A	0x7e44
1436 #define TP_MIB_INDEX_A	0x7e50
1437 #define TP_MIB_DATA_A	0x7e54
1438 #define TP_INT_CAUSE_A	0x7e74
1439 
1440 #define FLMTXFLSTEMPTY_S    30
1441 #define FLMTXFLSTEMPTY_V(x) ((x) << FLMTXFLSTEMPTY_S)
1442 #define FLMTXFLSTEMPTY_F    FLMTXFLSTEMPTY_V(1U)
1443 
1444 #define TP_TX_ORATE_A 0x7ebc
1445 
1446 #define OFDRATE3_S    24
1447 #define OFDRATE3_M    0xffU
1448 #define OFDRATE3_G(x) (((x) >> OFDRATE3_S) & OFDRATE3_M)
1449 
1450 #define OFDRATE2_S    16
1451 #define OFDRATE2_M    0xffU
1452 #define OFDRATE2_G(x) (((x) >> OFDRATE2_S) & OFDRATE2_M)
1453 
1454 #define OFDRATE1_S    8
1455 #define OFDRATE1_M    0xffU
1456 #define OFDRATE1_G(x) (((x) >> OFDRATE1_S) & OFDRATE1_M)
1457 
1458 #define OFDRATE0_S    0
1459 #define OFDRATE0_M    0xffU
1460 #define OFDRATE0_G(x) (((x) >> OFDRATE0_S) & OFDRATE0_M)
1461 
1462 #define TP_TX_TRATE_A 0x7ed0
1463 
1464 #define TNLRATE3_S    24
1465 #define TNLRATE3_M    0xffU
1466 #define TNLRATE3_G(x) (((x) >> TNLRATE3_S) & TNLRATE3_M)
1467 
1468 #define TNLRATE2_S    16
1469 #define TNLRATE2_M    0xffU
1470 #define TNLRATE2_G(x) (((x) >> TNLRATE2_S) & TNLRATE2_M)
1471 
1472 #define TNLRATE1_S    8
1473 #define TNLRATE1_M    0xffU
1474 #define TNLRATE1_G(x) (((x) >> TNLRATE1_S) & TNLRATE1_M)
1475 
1476 #define TNLRATE0_S    0
1477 #define TNLRATE0_M    0xffU
1478 #define TNLRATE0_G(x) (((x) >> TNLRATE0_S) & TNLRATE0_M)
1479 
1480 #define TP_VLAN_PRI_MAP_A 0x140
1481 
1482 #define FRAGMENTATION_S    9
1483 #define FRAGMENTATION_V(x) ((x) << FRAGMENTATION_S)
1484 #define FRAGMENTATION_F    FRAGMENTATION_V(1U)
1485 
1486 #define MPSHITTYPE_S    8
1487 #define MPSHITTYPE_V(x) ((x) << MPSHITTYPE_S)
1488 #define MPSHITTYPE_F    MPSHITTYPE_V(1U)
1489 
1490 #define MACMATCH_S    7
1491 #define MACMATCH_V(x) ((x) << MACMATCH_S)
1492 #define MACMATCH_F    MACMATCH_V(1U)
1493 
1494 #define ETHERTYPE_S    6
1495 #define ETHERTYPE_V(x) ((x) << ETHERTYPE_S)
1496 #define ETHERTYPE_F    ETHERTYPE_V(1U)
1497 
1498 #define PROTOCOL_S    5
1499 #define PROTOCOL_V(x) ((x) << PROTOCOL_S)
1500 #define PROTOCOL_F    PROTOCOL_V(1U)
1501 
1502 #define TOS_S    4
1503 #define TOS_V(x) ((x) << TOS_S)
1504 #define TOS_F    TOS_V(1U)
1505 
1506 #define VLAN_S    3
1507 #define VLAN_V(x) ((x) << VLAN_S)
1508 #define VLAN_F    VLAN_V(1U)
1509 
1510 #define VNIC_ID_S    2
1511 #define VNIC_ID_V(x) ((x) << VNIC_ID_S)
1512 #define VNIC_ID_F    VNIC_ID_V(1U)
1513 
1514 #define PORT_S    1
1515 #define PORT_V(x) ((x) << PORT_S)
1516 #define PORT_F    PORT_V(1U)
1517 
1518 #define FCOE_S    0
1519 #define FCOE_V(x) ((x) << FCOE_S)
1520 #define FCOE_F    FCOE_V(1U)
1521 
1522 #define FILTERMODE_S    15
1523 #define FILTERMODE_V(x) ((x) << FILTERMODE_S)
1524 #define FILTERMODE_F    FILTERMODE_V(1U)
1525 
1526 #define FCOEMASK_S    14
1527 #define FCOEMASK_V(x) ((x) << FCOEMASK_S)
1528 #define FCOEMASK_F    FCOEMASK_V(1U)
1529 
1530 #define TP_INGRESS_CONFIG_A	0x141
1531 
1532 #define VNIC_S    11
1533 #define VNIC_V(x) ((x) << VNIC_S)
1534 #define VNIC_F    VNIC_V(1U)
1535 
1536 #define CSUM_HAS_PSEUDO_HDR_S    10
1537 #define CSUM_HAS_PSEUDO_HDR_V(x) ((x) << CSUM_HAS_PSEUDO_HDR_S)
1538 #define CSUM_HAS_PSEUDO_HDR_F    CSUM_HAS_PSEUDO_HDR_V(1U)
1539 
1540 #define TP_MIB_MAC_IN_ERR_0_A	0x0
1541 #define TP_MIB_HDR_IN_ERR_0_A	0x4
1542 #define TP_MIB_TCP_IN_ERR_0_A	0x8
1543 #define TP_MIB_TCP_OUT_RST_A	0xc
1544 #define TP_MIB_TCP_IN_SEG_HI_A	0x10
1545 #define TP_MIB_TCP_IN_SEG_LO_A	0x11
1546 #define TP_MIB_TCP_OUT_SEG_HI_A	0x12
1547 #define TP_MIB_TCP_OUT_SEG_LO_A 0x13
1548 #define TP_MIB_TCP_RXT_SEG_HI_A	0x14
1549 #define TP_MIB_TCP_RXT_SEG_LO_A	0x15
1550 #define TP_MIB_TNL_CNG_DROP_0_A 0x18
1551 #define TP_MIB_OFD_CHN_DROP_0_A 0x1c
1552 #define TP_MIB_TCP_V6IN_ERR_0_A 0x28
1553 #define TP_MIB_TCP_V6OUT_RST_A	0x2c
1554 #define TP_MIB_OFD_ARP_DROP_A	0x36
1555 #define TP_MIB_CPL_IN_REQ_0_A	0x38
1556 #define TP_MIB_CPL_OUT_RSP_0_A	0x3c
1557 #define TP_MIB_TNL_DROP_0_A	0x44
1558 #define TP_MIB_FCOE_DDP_0_A	0x48
1559 #define TP_MIB_FCOE_DROP_0_A	0x4c
1560 #define TP_MIB_FCOE_BYTE_0_HI_A	0x50
1561 #define TP_MIB_OFD_VLN_DROP_0_A	0x58
1562 #define TP_MIB_USM_PKTS_A	0x5c
1563 #define TP_MIB_RQE_DFR_PKT_A	0x64
1564 
1565 #define ULP_TX_INT_CAUSE_A	0x8dcc
1566 #define ULP_TX_TPT_LLIMIT_A	0x8dd4
1567 #define ULP_TX_TPT_ULIMIT_A	0x8dd8
1568 #define ULP_TX_PBL_LLIMIT_A	0x8ddc
1569 #define ULP_TX_PBL_ULIMIT_A	0x8de0
1570 #define ULP_TX_ERR_TABLE_BASE_A 0x8e04
1571 
1572 #define PBL_BOUND_ERR_CH3_S    31
1573 #define PBL_BOUND_ERR_CH3_V(x) ((x) << PBL_BOUND_ERR_CH3_S)
1574 #define PBL_BOUND_ERR_CH3_F    PBL_BOUND_ERR_CH3_V(1U)
1575 
1576 #define PBL_BOUND_ERR_CH2_S    30
1577 #define PBL_BOUND_ERR_CH2_V(x) ((x) << PBL_BOUND_ERR_CH2_S)
1578 #define PBL_BOUND_ERR_CH2_F    PBL_BOUND_ERR_CH2_V(1U)
1579 
1580 #define PBL_BOUND_ERR_CH1_S    29
1581 #define PBL_BOUND_ERR_CH1_V(x) ((x) << PBL_BOUND_ERR_CH1_S)
1582 #define PBL_BOUND_ERR_CH1_F    PBL_BOUND_ERR_CH1_V(1U)
1583 
1584 #define PBL_BOUND_ERR_CH0_S    28
1585 #define PBL_BOUND_ERR_CH0_V(x) ((x) << PBL_BOUND_ERR_CH0_S)
1586 #define PBL_BOUND_ERR_CH0_F    PBL_BOUND_ERR_CH0_V(1U)
1587 
1588 #define PM_RX_INT_CAUSE_A	0x8fdc
1589 #define PM_RX_STAT_CONFIG_A 0x8fc8
1590 #define PM_RX_STAT_COUNT_A 0x8fcc
1591 #define PM_RX_STAT_LSB_A 0x8fd0
1592 #define PM_RX_DBG_CTRL_A 0x8fd0
1593 #define PM_RX_DBG_DATA_A 0x8fd4
1594 #define PM_RX_DBG_STAT_MSB_A 0x10013
1595 
1596 #define PMRX_FRAMING_ERROR_F	0x003ffff0U
1597 
1598 #define ZERO_E_CMD_ERROR_S    22
1599 #define ZERO_E_CMD_ERROR_V(x) ((x) << ZERO_E_CMD_ERROR_S)
1600 #define ZERO_E_CMD_ERROR_F    ZERO_E_CMD_ERROR_V(1U)
1601 
1602 #define OCSPI_PAR_ERROR_S    3
1603 #define OCSPI_PAR_ERROR_V(x) ((x) << OCSPI_PAR_ERROR_S)
1604 #define OCSPI_PAR_ERROR_F    OCSPI_PAR_ERROR_V(1U)
1605 
1606 #define DB_OPTIONS_PAR_ERROR_S    2
1607 #define DB_OPTIONS_PAR_ERROR_V(x) ((x) << DB_OPTIONS_PAR_ERROR_S)
1608 #define DB_OPTIONS_PAR_ERROR_F    DB_OPTIONS_PAR_ERROR_V(1U)
1609 
1610 #define IESPI_PAR_ERROR_S    1
1611 #define IESPI_PAR_ERROR_V(x) ((x) << IESPI_PAR_ERROR_S)
1612 #define IESPI_PAR_ERROR_F    IESPI_PAR_ERROR_V(1U)
1613 
1614 #define PMRX_E_PCMD_PAR_ERROR_S    0
1615 #define PMRX_E_PCMD_PAR_ERROR_V(x) ((x) << PMRX_E_PCMD_PAR_ERROR_S)
1616 #define PMRX_E_PCMD_PAR_ERROR_F    PMRX_E_PCMD_PAR_ERROR_V(1U)
1617 
1618 #define PM_TX_INT_CAUSE_A	0x8ffc
1619 #define PM_TX_STAT_CONFIG_A 0x8fe8
1620 #define PM_TX_STAT_COUNT_A 0x8fec
1621 #define PM_TX_STAT_LSB_A 0x8ff0
1622 #define PM_TX_DBG_CTRL_A 0x8ff0
1623 #define PM_TX_DBG_DATA_A 0x8ff4
1624 #define PM_TX_DBG_STAT_MSB_A 0x1001a
1625 
1626 #define PCMD_LEN_OVFL0_S    31
1627 #define PCMD_LEN_OVFL0_V(x) ((x) << PCMD_LEN_OVFL0_S)
1628 #define PCMD_LEN_OVFL0_F    PCMD_LEN_OVFL0_V(1U)
1629 
1630 #define PCMD_LEN_OVFL1_S    30
1631 #define PCMD_LEN_OVFL1_V(x) ((x) << PCMD_LEN_OVFL1_S)
1632 #define PCMD_LEN_OVFL1_F    PCMD_LEN_OVFL1_V(1U)
1633 
1634 #define PCMD_LEN_OVFL2_S    29
1635 #define PCMD_LEN_OVFL2_V(x) ((x) << PCMD_LEN_OVFL2_S)
1636 #define PCMD_LEN_OVFL2_F    PCMD_LEN_OVFL2_V(1U)
1637 
1638 #define ZERO_C_CMD_ERROR_S    28
1639 #define ZERO_C_CMD_ERROR_V(x) ((x) << ZERO_C_CMD_ERROR_S)
1640 #define ZERO_C_CMD_ERROR_F    ZERO_C_CMD_ERROR_V(1U)
1641 
1642 #define  PMTX_FRAMING_ERROR_F 0x0ffffff0U
1643 
1644 #define OESPI_PAR_ERROR_S    3
1645 #define OESPI_PAR_ERROR_V(x) ((x) << OESPI_PAR_ERROR_S)
1646 #define OESPI_PAR_ERROR_F    OESPI_PAR_ERROR_V(1U)
1647 
1648 #define ICSPI_PAR_ERROR_S    1
1649 #define ICSPI_PAR_ERROR_V(x) ((x) << ICSPI_PAR_ERROR_S)
1650 #define ICSPI_PAR_ERROR_F    ICSPI_PAR_ERROR_V(1U)
1651 
1652 #define PMTX_C_PCMD_PAR_ERROR_S    0
1653 #define PMTX_C_PCMD_PAR_ERROR_V(x) ((x) << PMTX_C_PCMD_PAR_ERROR_S)
1654 #define PMTX_C_PCMD_PAR_ERROR_F    PMTX_C_PCMD_PAR_ERROR_V(1U)
1655 
1656 #define MPS_PORT_STAT_TX_PORT_BYTES_L 0x400
1657 #define MPS_PORT_STAT_TX_PORT_BYTES_H 0x404
1658 #define MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408
1659 #define MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c
1660 #define MPS_PORT_STAT_TX_PORT_BCAST_L 0x410
1661 #define MPS_PORT_STAT_TX_PORT_BCAST_H 0x414
1662 #define MPS_PORT_STAT_TX_PORT_MCAST_L 0x418
1663 #define MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c
1664 #define MPS_PORT_STAT_TX_PORT_UCAST_L 0x420
1665 #define MPS_PORT_STAT_TX_PORT_UCAST_H 0x424
1666 #define MPS_PORT_STAT_TX_PORT_ERROR_L 0x428
1667 #define MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c
1668 #define MPS_PORT_STAT_TX_PORT_64B_L 0x430
1669 #define MPS_PORT_STAT_TX_PORT_64B_H 0x434
1670 #define MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438
1671 #define MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c
1672 #define MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440
1673 #define MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444
1674 #define MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448
1675 #define MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c
1676 #define MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450
1677 #define MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454
1678 #define MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458
1679 #define MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c
1680 #define MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460
1681 #define MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464
1682 #define MPS_PORT_STAT_TX_PORT_DROP_L 0x468
1683 #define MPS_PORT_STAT_TX_PORT_DROP_H 0x46c
1684 #define MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470
1685 #define MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474
1686 #define MPS_PORT_STAT_TX_PORT_PPP0_L 0x478
1687 #define MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c
1688 #define MPS_PORT_STAT_TX_PORT_PPP1_L 0x480
1689 #define MPS_PORT_STAT_TX_PORT_PPP1_H 0x484
1690 #define MPS_PORT_STAT_TX_PORT_PPP2_L 0x488
1691 #define MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c
1692 #define MPS_PORT_STAT_TX_PORT_PPP3_L 0x490
1693 #define MPS_PORT_STAT_TX_PORT_PPP3_H 0x494
1694 #define MPS_PORT_STAT_TX_PORT_PPP4_L 0x498
1695 #define MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c
1696 #define MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0
1697 #define MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4
1698 #define MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8
1699 #define MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac
1700 #define MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0
1701 #define MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4
1702 #define MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0
1703 #define MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4
1704 #define MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8
1705 #define MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc
1706 #define MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0
1707 #define MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4
1708 #define MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8
1709 #define MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc
1710 #define MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0
1711 #define MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4
1712 #define MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8
1713 #define MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec
1714 #define MPS_PORT_STAT_LB_PORT_64B_L 0x4f0
1715 #define MPS_PORT_STAT_LB_PORT_64B_H 0x4f4
1716 #define MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8
1717 #define MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc
1718 #define MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500
1719 #define MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504
1720 #define MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508
1721 #define MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c
1722 #define MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510
1723 #define MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514
1724 #define MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518
1725 #define MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c
1726 #define MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520
1727 #define MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524
1728 #define MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528
1729 #define MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L 0x528
1730 #define MPS_PORT_STAT_RX_PORT_BYTES_L 0x540
1731 #define MPS_PORT_STAT_RX_PORT_BYTES_H 0x544
1732 #define MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548
1733 #define MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c
1734 #define MPS_PORT_STAT_RX_PORT_BCAST_L 0x550
1735 #define MPS_PORT_STAT_RX_PORT_BCAST_H 0x554
1736 #define MPS_PORT_STAT_RX_PORT_MCAST_L 0x558
1737 #define MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c
1738 #define MPS_PORT_STAT_RX_PORT_UCAST_L 0x560
1739 #define MPS_PORT_STAT_RX_PORT_UCAST_H 0x564
1740 #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568
1741 #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c
1742 #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570
1743 #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574
1744 #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578
1745 #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c
1746 #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580
1747 #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584
1748 #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588
1749 #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c
1750 #define MPS_PORT_STAT_RX_PORT_64B_L 0x590
1751 #define MPS_PORT_STAT_RX_PORT_64B_H 0x594
1752 #define MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598
1753 #define MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c
1754 #define MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0
1755 #define MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4
1756 #define MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8
1757 #define MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac
1758 #define MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0
1759 #define MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4
1760 #define MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8
1761 #define MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc
1762 #define MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0
1763 #define MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4
1764 #define MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8
1765 #define MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc
1766 #define MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0
1767 #define MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4
1768 #define MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8
1769 #define MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc
1770 #define MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0
1771 #define MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4
1772 #define MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8
1773 #define MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec
1774 #define MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0
1775 #define MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4
1776 #define MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8
1777 #define MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc
1778 #define MPS_PORT_STAT_RX_PORT_PPP6_L 0x600
1779 #define MPS_PORT_STAT_RX_PORT_PPP6_H 0x604
1780 #define MPS_PORT_STAT_RX_PORT_PPP7_L 0x608
1781 #define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c
1782 #define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610
1783 #define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
1784 #define MAC_PORT_MAGIC_MACID_LO 0x824
1785 #define MAC_PORT_MAGIC_MACID_HI 0x828
1786 
1787 #define MAC_PORT_EPIO_DATA0_A 0x8c0
1788 #define MAC_PORT_EPIO_DATA1_A 0x8c4
1789 #define MAC_PORT_EPIO_DATA2_A 0x8c8
1790 #define MAC_PORT_EPIO_DATA3_A 0x8cc
1791 #define MAC_PORT_EPIO_OP_A 0x8d0
1792 
1793 #define MAC_PORT_CFG2_A 0x818
1794 
1795 #define MPS_CMN_CTL_A	0x9000
1796 
1797 #define NUMPORTS_S    0
1798 #define NUMPORTS_M    0x3U
1799 #define NUMPORTS_G(x) (((x) >> NUMPORTS_S) & NUMPORTS_M)
1800 
1801 #define MPS_INT_CAUSE_A 0x9008
1802 #define MPS_TX_INT_CAUSE_A 0x9408
1803 
1804 #define FRMERR_S    15
1805 #define FRMERR_V(x) ((x) << FRMERR_S)
1806 #define FRMERR_F    FRMERR_V(1U)
1807 
1808 #define SECNTERR_S    14
1809 #define SECNTERR_V(x) ((x) << SECNTERR_S)
1810 #define SECNTERR_F    SECNTERR_V(1U)
1811 
1812 #define BUBBLE_S    13
1813 #define BUBBLE_V(x) ((x) << BUBBLE_S)
1814 #define BUBBLE_F    BUBBLE_V(1U)
1815 
1816 #define TXDESCFIFO_S    9
1817 #define TXDESCFIFO_M    0xfU
1818 #define TXDESCFIFO_V(x) ((x) << TXDESCFIFO_S)
1819 
1820 #define TXDATAFIFO_S    5
1821 #define TXDATAFIFO_M    0xfU
1822 #define TXDATAFIFO_V(x) ((x) << TXDATAFIFO_S)
1823 
1824 #define NCSIFIFO_S    4
1825 #define NCSIFIFO_V(x) ((x) << NCSIFIFO_S)
1826 #define NCSIFIFO_F    NCSIFIFO_V(1U)
1827 
1828 #define TPFIFO_S    0
1829 #define TPFIFO_M    0xfU
1830 #define TPFIFO_V(x) ((x) << TPFIFO_S)
1831 
1832 #define MPS_STAT_PERR_INT_CAUSE_SRAM_A		0x9614
1833 #define MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A	0x9620
1834 #define MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A	0x962c
1835 
1836 #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640
1837 #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644
1838 #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648
1839 #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c
1840 #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650
1841 #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654
1842 #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658
1843 #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c
1844 #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660
1845 #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664
1846 #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668
1847 #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c
1848 #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670
1849 #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674
1850 #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678
1851 #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c
1852 #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680
1853 #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684
1854 #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688
1855 #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c
1856 #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690
1857 #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694
1858 #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698
1859 #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c
1860 #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0
1861 #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4
1862 #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8
1863 #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac
1864 #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0
1865 #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4
1866 #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8
1867 #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc
1868 
1869 #define MPS_TRC_CFG_A 0x9800
1870 
1871 #define TRCFIFOEMPTY_S    4
1872 #define TRCFIFOEMPTY_V(x) ((x) << TRCFIFOEMPTY_S)
1873 #define TRCFIFOEMPTY_F    TRCFIFOEMPTY_V(1U)
1874 
1875 #define TRCIGNOREDROPINPUT_S    3
1876 #define TRCIGNOREDROPINPUT_V(x) ((x) << TRCIGNOREDROPINPUT_S)
1877 #define TRCIGNOREDROPINPUT_F    TRCIGNOREDROPINPUT_V(1U)
1878 
1879 #define TRCKEEPDUPLICATES_S    2
1880 #define TRCKEEPDUPLICATES_V(x) ((x) << TRCKEEPDUPLICATES_S)
1881 #define TRCKEEPDUPLICATES_F    TRCKEEPDUPLICATES_V(1U)
1882 
1883 #define TRCEN_S    1
1884 #define TRCEN_V(x) ((x) << TRCEN_S)
1885 #define TRCEN_F    TRCEN_V(1U)
1886 
1887 #define TRCMULTIFILTER_S    0
1888 #define TRCMULTIFILTER_V(x) ((x) << TRCMULTIFILTER_S)
1889 #define TRCMULTIFILTER_F    TRCMULTIFILTER_V(1U)
1890 
1891 #define MPS_TRC_RSS_CONTROL_A		0x9808
1892 #define MPS_TRC_FILTER1_RSS_CONTROL_A	0x9ff4
1893 #define MPS_TRC_FILTER2_RSS_CONTROL_A	0x9ffc
1894 #define MPS_TRC_FILTER3_RSS_CONTROL_A	0xa004
1895 #define MPS_T5_TRC_RSS_CONTROL_A	0xa00c
1896 
1897 #define RSSCONTROL_S    16
1898 #define RSSCONTROL_V(x) ((x) << RSSCONTROL_S)
1899 
1900 #define QUEUENUMBER_S    0
1901 #define QUEUENUMBER_V(x) ((x) << QUEUENUMBER_S)
1902 
1903 #define TFINVERTMATCH_S    24
1904 #define TFINVERTMATCH_V(x) ((x) << TFINVERTMATCH_S)
1905 #define TFINVERTMATCH_F    TFINVERTMATCH_V(1U)
1906 
1907 #define TFEN_S    22
1908 #define TFEN_V(x) ((x) << TFEN_S)
1909 #define TFEN_F    TFEN_V(1U)
1910 
1911 #define TFPORT_S    18
1912 #define TFPORT_M    0xfU
1913 #define TFPORT_V(x) ((x) << TFPORT_S)
1914 #define TFPORT_G(x) (((x) >> TFPORT_S) & TFPORT_M)
1915 
1916 #define TFLENGTH_S    8
1917 #define TFLENGTH_M    0x1fU
1918 #define TFLENGTH_V(x) ((x) << TFLENGTH_S)
1919 #define TFLENGTH_G(x) (((x) >> TFLENGTH_S) & TFLENGTH_M)
1920 
1921 #define TFOFFSET_S    0
1922 #define TFOFFSET_M    0x1fU
1923 #define TFOFFSET_V(x) ((x) << TFOFFSET_S)
1924 #define TFOFFSET_G(x) (((x) >> TFOFFSET_S) & TFOFFSET_M)
1925 
1926 #define T5_TFINVERTMATCH_S    25
1927 #define T5_TFINVERTMATCH_V(x) ((x) << T5_TFINVERTMATCH_S)
1928 #define T5_TFINVERTMATCH_F    T5_TFINVERTMATCH_V(1U)
1929 
1930 #define T5_TFEN_S    23
1931 #define T5_TFEN_V(x) ((x) << T5_TFEN_S)
1932 #define T5_TFEN_F    T5_TFEN_V(1U)
1933 
1934 #define T5_TFPORT_S    18
1935 #define T5_TFPORT_M    0x1fU
1936 #define T5_TFPORT_V(x) ((x) << T5_TFPORT_S)
1937 #define T5_TFPORT_G(x) (((x) >> T5_TFPORT_S) & T5_TFPORT_M)
1938 
1939 #define MPS_TRC_FILTER_MATCH_CTL_A_A 0x9810
1940 #define MPS_TRC_FILTER_MATCH_CTL_B_A 0x9820
1941 
1942 #define TFMINPKTSIZE_S    16
1943 #define TFMINPKTSIZE_M    0x1ffU
1944 #define TFMINPKTSIZE_V(x) ((x) << TFMINPKTSIZE_S)
1945 #define TFMINPKTSIZE_G(x) (((x) >> TFMINPKTSIZE_S) & TFMINPKTSIZE_M)
1946 
1947 #define TFCAPTUREMAX_S    0
1948 #define TFCAPTUREMAX_M    0x3fffU
1949 #define TFCAPTUREMAX_V(x) ((x) << TFCAPTUREMAX_S)
1950 #define TFCAPTUREMAX_G(x) (((x) >> TFCAPTUREMAX_S) & TFCAPTUREMAX_M)
1951 
1952 #define MPS_TRC_FILTER0_MATCH_A 0x9c00
1953 #define MPS_TRC_FILTER0_DONT_CARE_A 0x9c80
1954 #define MPS_TRC_FILTER1_MATCH_A 0x9d00
1955 
1956 #define TP_RSS_CONFIG_A 0x7df0
1957 
1958 #define TNL4TUPENIPV6_S    31
1959 #define TNL4TUPENIPV6_V(x) ((x) << TNL4TUPENIPV6_S)
1960 #define TNL4TUPENIPV6_F    TNL4TUPENIPV6_V(1U)
1961 
1962 #define TNL2TUPENIPV6_S    30
1963 #define TNL2TUPENIPV6_V(x) ((x) << TNL2TUPENIPV6_S)
1964 #define TNL2TUPENIPV6_F    TNL2TUPENIPV6_V(1U)
1965 
1966 #define TNL4TUPENIPV4_S    29
1967 #define TNL4TUPENIPV4_V(x) ((x) << TNL4TUPENIPV4_S)
1968 #define TNL4TUPENIPV4_F    TNL4TUPENIPV4_V(1U)
1969 
1970 #define TNL2TUPENIPV4_S    28
1971 #define TNL2TUPENIPV4_V(x) ((x) << TNL2TUPENIPV4_S)
1972 #define TNL2TUPENIPV4_F    TNL2TUPENIPV4_V(1U)
1973 
1974 #define TNLTCPSEL_S    27
1975 #define TNLTCPSEL_V(x) ((x) << TNLTCPSEL_S)
1976 #define TNLTCPSEL_F    TNLTCPSEL_V(1U)
1977 
1978 #define TNLIP6SEL_S    26
1979 #define TNLIP6SEL_V(x) ((x) << TNLIP6SEL_S)
1980 #define TNLIP6SEL_F    TNLIP6SEL_V(1U)
1981 
1982 #define TNLVRTSEL_S    25
1983 #define TNLVRTSEL_V(x) ((x) << TNLVRTSEL_S)
1984 #define TNLVRTSEL_F    TNLVRTSEL_V(1U)
1985 
1986 #define TNLMAPEN_S    24
1987 #define TNLMAPEN_V(x) ((x) << TNLMAPEN_S)
1988 #define TNLMAPEN_F    TNLMAPEN_V(1U)
1989 
1990 #define OFDHASHSAVE_S    19
1991 #define OFDHASHSAVE_V(x) ((x) << OFDHASHSAVE_S)
1992 #define OFDHASHSAVE_F    OFDHASHSAVE_V(1U)
1993 
1994 #define OFDVRTSEL_S    18
1995 #define OFDVRTSEL_V(x) ((x) << OFDVRTSEL_S)
1996 #define OFDVRTSEL_F    OFDVRTSEL_V(1U)
1997 
1998 #define OFDMAPEN_S    17
1999 #define OFDMAPEN_V(x) ((x) << OFDMAPEN_S)
2000 #define OFDMAPEN_F    OFDMAPEN_V(1U)
2001 
2002 #define OFDLKPEN_S    16
2003 #define OFDLKPEN_V(x) ((x) << OFDLKPEN_S)
2004 #define OFDLKPEN_F    OFDLKPEN_V(1U)
2005 
2006 #define SYN4TUPENIPV6_S    15
2007 #define SYN4TUPENIPV6_V(x) ((x) << SYN4TUPENIPV6_S)
2008 #define SYN4TUPENIPV6_F    SYN4TUPENIPV6_V(1U)
2009 
2010 #define SYN2TUPENIPV6_S    14
2011 #define SYN2TUPENIPV6_V(x) ((x) << SYN2TUPENIPV6_S)
2012 #define SYN2TUPENIPV6_F    SYN2TUPENIPV6_V(1U)
2013 
2014 #define SYN4TUPENIPV4_S    13
2015 #define SYN4TUPENIPV4_V(x) ((x) << SYN4TUPENIPV4_S)
2016 #define SYN4TUPENIPV4_F    SYN4TUPENIPV4_V(1U)
2017 
2018 #define SYN2TUPENIPV4_S    12
2019 #define SYN2TUPENIPV4_V(x) ((x) << SYN2TUPENIPV4_S)
2020 #define SYN2TUPENIPV4_F    SYN2TUPENIPV4_V(1U)
2021 
2022 #define SYNIP6SEL_S    11
2023 #define SYNIP6SEL_V(x) ((x) << SYNIP6SEL_S)
2024 #define SYNIP6SEL_F    SYNIP6SEL_V(1U)
2025 
2026 #define SYNVRTSEL_S    10
2027 #define SYNVRTSEL_V(x) ((x) << SYNVRTSEL_S)
2028 #define SYNVRTSEL_F    SYNVRTSEL_V(1U)
2029 
2030 #define SYNMAPEN_S    9
2031 #define SYNMAPEN_V(x) ((x) << SYNMAPEN_S)
2032 #define SYNMAPEN_F    SYNMAPEN_V(1U)
2033 
2034 #define SYNLKPEN_S    8
2035 #define SYNLKPEN_V(x) ((x) << SYNLKPEN_S)
2036 #define SYNLKPEN_F    SYNLKPEN_V(1U)
2037 
2038 #define CHANNELENABLE_S    7
2039 #define CHANNELENABLE_V(x) ((x) << CHANNELENABLE_S)
2040 #define CHANNELENABLE_F    CHANNELENABLE_V(1U)
2041 
2042 #define PORTENABLE_S    6
2043 #define PORTENABLE_V(x) ((x) << PORTENABLE_S)
2044 #define PORTENABLE_F    PORTENABLE_V(1U)
2045 
2046 #define TNLALLLOOKUP_S    5
2047 #define TNLALLLOOKUP_V(x) ((x) << TNLALLLOOKUP_S)
2048 #define TNLALLLOOKUP_F    TNLALLLOOKUP_V(1U)
2049 
2050 #define VIRTENABLE_S    4
2051 #define VIRTENABLE_V(x) ((x) << VIRTENABLE_S)
2052 #define VIRTENABLE_F    VIRTENABLE_V(1U)
2053 
2054 #define CONGESTIONENABLE_S    3
2055 #define CONGESTIONENABLE_V(x) ((x) << CONGESTIONENABLE_S)
2056 #define CONGESTIONENABLE_F    CONGESTIONENABLE_V(1U)
2057 
2058 #define HASHTOEPLITZ_S    2
2059 #define HASHTOEPLITZ_V(x) ((x) << HASHTOEPLITZ_S)
2060 #define HASHTOEPLITZ_F    HASHTOEPLITZ_V(1U)
2061 
2062 #define UDPENABLE_S    1
2063 #define UDPENABLE_V(x) ((x) << UDPENABLE_S)
2064 #define UDPENABLE_F    UDPENABLE_V(1U)
2065 
2066 #define DISABLE_S    0
2067 #define DISABLE_V(x) ((x) << DISABLE_S)
2068 #define DISABLE_F    DISABLE_V(1U)
2069 
2070 #define TP_RSS_CONFIG_TNL_A 0x7df4
2071 
2072 #define MASKSIZE_S    28
2073 #define MASKSIZE_M    0xfU
2074 #define MASKSIZE_V(x) ((x) << MASKSIZE_S)
2075 #define MASKSIZE_G(x) (((x) >> MASKSIZE_S) & MASKSIZE_M)
2076 
2077 #define MASKFILTER_S    16
2078 #define MASKFILTER_M    0x7ffU
2079 #define MASKFILTER_V(x) ((x) << MASKFILTER_S)
2080 #define MASKFILTER_G(x) (((x) >> MASKFILTER_S) & MASKFILTER_M)
2081 
2082 #define USEWIRECH_S    0
2083 #define USEWIRECH_V(x) ((x) << USEWIRECH_S)
2084 #define USEWIRECH_F    USEWIRECH_V(1U)
2085 
2086 #define HASHALL_S    2
2087 #define HASHALL_V(x) ((x) << HASHALL_S)
2088 #define HASHALL_F    HASHALL_V(1U)
2089 
2090 #define HASHETH_S    1
2091 #define HASHETH_V(x) ((x) << HASHETH_S)
2092 #define HASHETH_F    HASHETH_V(1U)
2093 
2094 #define TP_RSS_CONFIG_OFD_A 0x7df8
2095 
2096 #define RRCPLMAPEN_S    20
2097 #define RRCPLMAPEN_V(x) ((x) << RRCPLMAPEN_S)
2098 #define RRCPLMAPEN_F    RRCPLMAPEN_V(1U)
2099 
2100 #define RRCPLQUEWIDTH_S    16
2101 #define RRCPLQUEWIDTH_M    0xfU
2102 #define RRCPLQUEWIDTH_V(x) ((x) << RRCPLQUEWIDTH_S)
2103 #define RRCPLQUEWIDTH_G(x) (((x) >> RRCPLQUEWIDTH_S) & RRCPLQUEWIDTH_M)
2104 
2105 #define TP_RSS_CONFIG_SYN_A 0x7dfc
2106 #define TP_RSS_CONFIG_VRT_A 0x7e00
2107 
2108 #define VFRDRG_S    25
2109 #define VFRDRG_V(x) ((x) << VFRDRG_S)
2110 #define VFRDRG_F    VFRDRG_V(1U)
2111 
2112 #define VFRDEN_S    24
2113 #define VFRDEN_V(x) ((x) << VFRDEN_S)
2114 #define VFRDEN_F    VFRDEN_V(1U)
2115 
2116 #define VFPERREN_S    23
2117 #define VFPERREN_V(x) ((x) << VFPERREN_S)
2118 #define VFPERREN_F    VFPERREN_V(1U)
2119 
2120 #define KEYPERREN_S    22
2121 #define KEYPERREN_V(x) ((x) << KEYPERREN_S)
2122 #define KEYPERREN_F    KEYPERREN_V(1U)
2123 
2124 #define DISABLEVLAN_S    21
2125 #define DISABLEVLAN_V(x) ((x) << DISABLEVLAN_S)
2126 #define DISABLEVLAN_F    DISABLEVLAN_V(1U)
2127 
2128 #define ENABLEUP0_S    20
2129 #define ENABLEUP0_V(x) ((x) << ENABLEUP0_S)
2130 #define ENABLEUP0_F    ENABLEUP0_V(1U)
2131 
2132 #define HASHDELAY_S    16
2133 #define HASHDELAY_M    0xfU
2134 #define HASHDELAY_V(x) ((x) << HASHDELAY_S)
2135 #define HASHDELAY_G(x) (((x) >> HASHDELAY_S) & HASHDELAY_M)
2136 
2137 #define VFWRADDR_S    8
2138 #define VFWRADDR_M    0x7fU
2139 #define VFWRADDR_V(x) ((x) << VFWRADDR_S)
2140 #define VFWRADDR_G(x) (((x) >> VFWRADDR_S) & VFWRADDR_M)
2141 
2142 #define KEYMODE_S    6
2143 #define KEYMODE_M    0x3U
2144 #define KEYMODE_V(x) ((x) << KEYMODE_S)
2145 #define KEYMODE_G(x) (((x) >> KEYMODE_S) & KEYMODE_M)
2146 
2147 #define VFWREN_S    5
2148 #define VFWREN_V(x) ((x) << VFWREN_S)
2149 #define VFWREN_F    VFWREN_V(1U)
2150 
2151 #define KEYWREN_S    4
2152 #define KEYWREN_V(x) ((x) << KEYWREN_S)
2153 #define KEYWREN_F    KEYWREN_V(1U)
2154 
2155 #define KEYWRADDR_S    0
2156 #define KEYWRADDR_M    0xfU
2157 #define KEYWRADDR_V(x) ((x) << KEYWRADDR_S)
2158 #define KEYWRADDR_G(x) (((x) >> KEYWRADDR_S) & KEYWRADDR_M)
2159 
2160 #define KEYWRADDRX_S    30
2161 #define KEYWRADDRX_M    0x3U
2162 #define KEYWRADDRX_V(x) ((x) << KEYWRADDRX_S)
2163 #define KEYWRADDRX_G(x) (((x) >> KEYWRADDRX_S) & KEYWRADDRX_M)
2164 
2165 #define KEYEXTEND_S    26
2166 #define KEYEXTEND_V(x) ((x) << KEYEXTEND_S)
2167 #define KEYEXTEND_F    KEYEXTEND_V(1U)
2168 
2169 #define LKPIDXSIZE_S    24
2170 #define LKPIDXSIZE_M    0x3U
2171 #define LKPIDXSIZE_V(x) ((x) << LKPIDXSIZE_S)
2172 #define LKPIDXSIZE_G(x) (((x) >> LKPIDXSIZE_S) & LKPIDXSIZE_M)
2173 
2174 #define TP_RSS_VFL_CONFIG_A 0x3a
2175 #define TP_RSS_VFH_CONFIG_A 0x3b
2176 
2177 #define ENABLEUDPHASH_S    31
2178 #define ENABLEUDPHASH_V(x) ((x) << ENABLEUDPHASH_S)
2179 #define ENABLEUDPHASH_F    ENABLEUDPHASH_V(1U)
2180 
2181 #define VFUPEN_S    30
2182 #define VFUPEN_V(x) ((x) << VFUPEN_S)
2183 #define VFUPEN_F    VFUPEN_V(1U)
2184 
2185 #define VFVLNEX_S    28
2186 #define VFVLNEX_V(x) ((x) << VFVLNEX_S)
2187 #define VFVLNEX_F    VFVLNEX_V(1U)
2188 
2189 #define VFPRTEN_S    27
2190 #define VFPRTEN_V(x) ((x) << VFPRTEN_S)
2191 #define VFPRTEN_F    VFPRTEN_V(1U)
2192 
2193 #define VFCHNEN_S    26
2194 #define VFCHNEN_V(x) ((x) << VFCHNEN_S)
2195 #define VFCHNEN_F    VFCHNEN_V(1U)
2196 
2197 #define DEFAULTQUEUE_S    16
2198 #define DEFAULTQUEUE_M    0x3ffU
2199 #define DEFAULTQUEUE_G(x) (((x) >> DEFAULTQUEUE_S) & DEFAULTQUEUE_M)
2200 
2201 #define VFIP6TWOTUPEN_S    6
2202 #define VFIP6TWOTUPEN_V(x) ((x) << VFIP6TWOTUPEN_S)
2203 #define VFIP6TWOTUPEN_F    VFIP6TWOTUPEN_V(1U)
2204 
2205 #define VFIP4FOURTUPEN_S    5
2206 #define VFIP4FOURTUPEN_V(x) ((x) << VFIP4FOURTUPEN_S)
2207 #define VFIP4FOURTUPEN_F    VFIP4FOURTUPEN_V(1U)
2208 
2209 #define VFIP4TWOTUPEN_S    4
2210 #define VFIP4TWOTUPEN_V(x) ((x) << VFIP4TWOTUPEN_S)
2211 #define VFIP4TWOTUPEN_F    VFIP4TWOTUPEN_V(1U)
2212 
2213 #define KEYINDEX_S    0
2214 #define KEYINDEX_M    0xfU
2215 #define KEYINDEX_G(x) (((x) >> KEYINDEX_S) & KEYINDEX_M)
2216 
2217 #define MAPENABLE_S    31
2218 #define MAPENABLE_V(x) ((x) << MAPENABLE_S)
2219 #define MAPENABLE_F    MAPENABLE_V(1U)
2220 
2221 #define CHNENABLE_S    30
2222 #define CHNENABLE_V(x) ((x) << CHNENABLE_S)
2223 #define CHNENABLE_F    CHNENABLE_V(1U)
2224 
2225 #define PRTENABLE_S    29
2226 #define PRTENABLE_V(x) ((x) << PRTENABLE_S)
2227 #define PRTENABLE_F    PRTENABLE_V(1U)
2228 
2229 #define UDPFOURTUPEN_S    28
2230 #define UDPFOURTUPEN_V(x) ((x) << UDPFOURTUPEN_S)
2231 #define UDPFOURTUPEN_F    UDPFOURTUPEN_V(1U)
2232 
2233 #define IP6FOURTUPEN_S    27
2234 #define IP6FOURTUPEN_V(x) ((x) << IP6FOURTUPEN_S)
2235 #define IP6FOURTUPEN_F    IP6FOURTUPEN_V(1U)
2236 
2237 #define IP6TWOTUPEN_S    26
2238 #define IP6TWOTUPEN_V(x) ((x) << IP6TWOTUPEN_S)
2239 #define IP6TWOTUPEN_F    IP6TWOTUPEN_V(1U)
2240 
2241 #define IP4FOURTUPEN_S    25
2242 #define IP4FOURTUPEN_V(x) ((x) << IP4FOURTUPEN_S)
2243 #define IP4FOURTUPEN_F    IP4FOURTUPEN_V(1U)
2244 
2245 #define IP4TWOTUPEN_S    24
2246 #define IP4TWOTUPEN_V(x) ((x) << IP4TWOTUPEN_S)
2247 #define IP4TWOTUPEN_F    IP4TWOTUPEN_V(1U)
2248 
2249 #define IVFWIDTH_S    20
2250 #define IVFWIDTH_M    0xfU
2251 #define IVFWIDTH_V(x) ((x) << IVFWIDTH_S)
2252 #define IVFWIDTH_G(x) (((x) >> IVFWIDTH_S) & IVFWIDTH_M)
2253 
2254 #define CH1DEFAULTQUEUE_S    10
2255 #define CH1DEFAULTQUEUE_M    0x3ffU
2256 #define CH1DEFAULTQUEUE_V(x) ((x) << CH1DEFAULTQUEUE_S)
2257 #define CH1DEFAULTQUEUE_G(x) (((x) >> CH1DEFAULTQUEUE_S) & CH1DEFAULTQUEUE_M)
2258 
2259 #define CH0DEFAULTQUEUE_S    0
2260 #define CH0DEFAULTQUEUE_M    0x3ffU
2261 #define CH0DEFAULTQUEUE_V(x) ((x) << CH0DEFAULTQUEUE_S)
2262 #define CH0DEFAULTQUEUE_G(x) (((x) >> CH0DEFAULTQUEUE_S) & CH0DEFAULTQUEUE_M)
2263 
2264 #define VFLKPIDX_S    8
2265 #define VFLKPIDX_M    0xffU
2266 #define VFLKPIDX_G(x) (((x) >> VFLKPIDX_S) & VFLKPIDX_M)
2267 
2268 #define T6_VFWRADDR_S    8
2269 #define T6_VFWRADDR_M    0xffU
2270 #define T6_VFWRADDR_V(x) ((x) << T6_VFWRADDR_S)
2271 #define T6_VFWRADDR_G(x) (((x) >> T6_VFWRADDR_S) & T6_VFWRADDR_M)
2272 
2273 #define TP_RSS_CONFIG_CNG_A 0x7e04
2274 #define TP_RSS_SECRET_KEY0_A 0x40
2275 #define TP_RSS_PF0_CONFIG_A 0x30
2276 #define TP_RSS_PF_MAP_A 0x38
2277 #define TP_RSS_PF_MSK_A 0x39
2278 
2279 #define PF1LKPIDX_S    3
2280 
2281 #define PF0LKPIDX_M    0x7U
2282 
2283 #define PF1MSKSIZE_S    4
2284 #define PF1MSKSIZE_M    0xfU
2285 
2286 #define CHNCOUNT3_S    31
2287 #define CHNCOUNT3_V(x) ((x) << CHNCOUNT3_S)
2288 #define CHNCOUNT3_F    CHNCOUNT3_V(1U)
2289 
2290 #define CHNCOUNT2_S    30
2291 #define CHNCOUNT2_V(x) ((x) << CHNCOUNT2_S)
2292 #define CHNCOUNT2_F    CHNCOUNT2_V(1U)
2293 
2294 #define CHNCOUNT1_S    29
2295 #define CHNCOUNT1_V(x) ((x) << CHNCOUNT1_S)
2296 #define CHNCOUNT1_F    CHNCOUNT1_V(1U)
2297 
2298 #define CHNCOUNT0_S    28
2299 #define CHNCOUNT0_V(x) ((x) << CHNCOUNT0_S)
2300 #define CHNCOUNT0_F    CHNCOUNT0_V(1U)
2301 
2302 #define CHNUNDFLOW3_S    27
2303 #define CHNUNDFLOW3_V(x) ((x) << CHNUNDFLOW3_S)
2304 #define CHNUNDFLOW3_F    CHNUNDFLOW3_V(1U)
2305 
2306 #define CHNUNDFLOW2_S    26
2307 #define CHNUNDFLOW2_V(x) ((x) << CHNUNDFLOW2_S)
2308 #define CHNUNDFLOW2_F    CHNUNDFLOW2_V(1U)
2309 
2310 #define CHNUNDFLOW1_S    25
2311 #define CHNUNDFLOW1_V(x) ((x) << CHNUNDFLOW1_S)
2312 #define CHNUNDFLOW1_F    CHNUNDFLOW1_V(1U)
2313 
2314 #define CHNUNDFLOW0_S    24
2315 #define CHNUNDFLOW0_V(x) ((x) << CHNUNDFLOW0_S)
2316 #define CHNUNDFLOW0_F    CHNUNDFLOW0_V(1U)
2317 
2318 #define RSTCHN3_S    19
2319 #define RSTCHN3_V(x) ((x) << RSTCHN3_S)
2320 #define RSTCHN3_F    RSTCHN3_V(1U)
2321 
2322 #define RSTCHN2_S    18
2323 #define RSTCHN2_V(x) ((x) << RSTCHN2_S)
2324 #define RSTCHN2_F    RSTCHN2_V(1U)
2325 
2326 #define RSTCHN1_S    17
2327 #define RSTCHN1_V(x) ((x) << RSTCHN1_S)
2328 #define RSTCHN1_F    RSTCHN1_V(1U)
2329 
2330 #define RSTCHN0_S    16
2331 #define RSTCHN0_V(x) ((x) << RSTCHN0_S)
2332 #define RSTCHN0_F    RSTCHN0_V(1U)
2333 
2334 #define UPDVLD_S    15
2335 #define UPDVLD_V(x) ((x) << UPDVLD_S)
2336 #define UPDVLD_F    UPDVLD_V(1U)
2337 
2338 #define XOFF_S    14
2339 #define XOFF_V(x) ((x) << XOFF_S)
2340 #define XOFF_F    XOFF_V(1U)
2341 
2342 #define UPDCHN3_S    13
2343 #define UPDCHN3_V(x) ((x) << UPDCHN3_S)
2344 #define UPDCHN3_F    UPDCHN3_V(1U)
2345 
2346 #define UPDCHN2_S    12
2347 #define UPDCHN2_V(x) ((x) << UPDCHN2_S)
2348 #define UPDCHN2_F    UPDCHN2_V(1U)
2349 
2350 #define UPDCHN1_S    11
2351 #define UPDCHN1_V(x) ((x) << UPDCHN1_S)
2352 #define UPDCHN1_F    UPDCHN1_V(1U)
2353 
2354 #define UPDCHN0_S    10
2355 #define UPDCHN0_V(x) ((x) << UPDCHN0_S)
2356 #define UPDCHN0_F    UPDCHN0_V(1U)
2357 
2358 #define QUEUE_S    0
2359 #define QUEUE_M    0x3ffU
2360 #define QUEUE_V(x) ((x) << QUEUE_S)
2361 #define QUEUE_G(x) (((x) >> QUEUE_S) & QUEUE_M)
2362 
2363 #define MPS_TRC_INT_CAUSE_A	0x985c
2364 
2365 #define MISCPERR_S    8
2366 #define MISCPERR_V(x) ((x) << MISCPERR_S)
2367 #define MISCPERR_F    MISCPERR_V(1U)
2368 
2369 #define PKTFIFO_S    4
2370 #define PKTFIFO_M    0xfU
2371 #define PKTFIFO_V(x) ((x) << PKTFIFO_S)
2372 
2373 #define FILTMEM_S    0
2374 #define FILTMEM_M    0xfU
2375 #define FILTMEM_V(x) ((x) << FILTMEM_S)
2376 
2377 #define MPS_CLS_INT_CAUSE_A 0xd028
2378 
2379 #define HASHSRAM_S    2
2380 #define HASHSRAM_V(x) ((x) << HASHSRAM_S)
2381 #define HASHSRAM_F    HASHSRAM_V(1U)
2382 
2383 #define MATCHTCAM_S    1
2384 #define MATCHTCAM_V(x) ((x) << MATCHTCAM_S)
2385 #define MATCHTCAM_F    MATCHTCAM_V(1U)
2386 
2387 #define MATCHSRAM_S    0
2388 #define MATCHSRAM_V(x) ((x) << MATCHSRAM_S)
2389 #define MATCHSRAM_F    MATCHSRAM_V(1U)
2390 
2391 #define MPS_RX_PG_RSV0_A 0x11010
2392 #define MPS_RX_PG_RSV4_A 0x11020
2393 #define MPS_RX_PERR_INT_CAUSE_A 0x11074
2394 #define MPS_RX_MAC_BG_PG_CNT0_A 0x11208
2395 #define MPS_RX_LPBK_BG_PG_CNT0_A 0x11218
2396 
2397 #define MPS_CLS_TCAM_Y_L_A 0xf000
2398 #define MPS_CLS_TCAM_DATA0_A 0xf000
2399 #define MPS_CLS_TCAM_DATA1_A 0xf004
2400 
2401 #define VIDL_S    16
2402 #define VIDL_M    0xffffU
2403 #define VIDL_G(x) (((x) >> VIDL_S) & VIDL_M)
2404 
2405 #define DATALKPTYPE_S    10
2406 #define DATALKPTYPE_M    0x3U
2407 #define DATALKPTYPE_G(x) (((x) >> DATALKPTYPE_S) & DATALKPTYPE_M)
2408 
2409 #define DATAPORTNUM_S    12
2410 #define DATAPORTNUM_M    0xfU
2411 #define DATAPORTNUM_G(x) (((x) >> DATAPORTNUM_S) & DATAPORTNUM_M)
2412 
2413 #define DATADIPHIT_S    8
2414 #define DATADIPHIT_V(x) ((x) << DATADIPHIT_S)
2415 #define DATADIPHIT_F    DATADIPHIT_V(1U)
2416 
2417 #define DATAVIDH2_S    7
2418 #define DATAVIDH2_V(x) ((x) << DATAVIDH2_S)
2419 #define DATAVIDH2_F    DATAVIDH2_V(1U)
2420 
2421 #define DATAVIDH1_S    0
2422 #define DATAVIDH1_M    0x7fU
2423 #define DATAVIDH1_G(x) (((x) >> DATAVIDH1_S) & DATAVIDH1_M)
2424 
2425 #define USED_S    16
2426 #define USED_M    0x7ffU
2427 #define USED_G(x) (((x) >> USED_S) & USED_M)
2428 
2429 #define ALLOC_S    0
2430 #define ALLOC_M    0x7ffU
2431 #define ALLOC_G(x) (((x) >> ALLOC_S) & ALLOC_M)
2432 
2433 #define T5_USED_S    16
2434 #define T5_USED_M    0xfffU
2435 #define T5_USED_G(x) (((x) >> T5_USED_S) & T5_USED_M)
2436 
2437 #define T5_ALLOC_S    0
2438 #define T5_ALLOC_M    0xfffU
2439 #define T5_ALLOC_G(x) (((x) >> T5_ALLOC_S) & T5_ALLOC_M)
2440 
2441 #define DMACH_S    0
2442 #define DMACH_M    0xffffU
2443 #define DMACH_G(x) (((x) >> DMACH_S) & DMACH_M)
2444 
2445 #define MPS_CLS_TCAM_X_L_A 0xf008
2446 #define MPS_CLS_TCAM_DATA2_CTL_A 0xf008
2447 
2448 #define CTLCMDTYPE_S    31
2449 #define CTLCMDTYPE_V(x) ((x) << CTLCMDTYPE_S)
2450 #define CTLCMDTYPE_F    CTLCMDTYPE_V(1U)
2451 
2452 #define CTLTCAMSEL_S    25
2453 #define CTLTCAMSEL_V(x) ((x) << CTLTCAMSEL_S)
2454 
2455 #define CTLTCAMINDEX_S    17
2456 #define CTLTCAMINDEX_V(x) ((x) << CTLTCAMINDEX_S)
2457 
2458 #define CTLXYBITSEL_S    16
2459 #define CTLXYBITSEL_V(x) ((x) << CTLXYBITSEL_S)
2460 
2461 #define MPS_CLS_TCAM_Y_L(idx) (MPS_CLS_TCAM_Y_L_A + (idx) * 16)
2462 #define NUM_MPS_CLS_TCAM_Y_L_INSTANCES 512
2463 
2464 #define MPS_CLS_TCAM_X_L(idx) (MPS_CLS_TCAM_X_L_A + (idx) * 16)
2465 #define NUM_MPS_CLS_TCAM_X_L_INSTANCES 512
2466 
2467 #define MPS_CLS_SRAM_L_A 0xe000
2468 
2469 #define T6_MULTILISTEN0_S    26
2470 
2471 #define T6_SRAM_PRIO3_S    23
2472 #define T6_SRAM_PRIO3_M    0x7U
2473 #define T6_SRAM_PRIO3_G(x) (((x) >> T6_SRAM_PRIO3_S) & T6_SRAM_PRIO3_M)
2474 
2475 #define T6_SRAM_PRIO2_S    20
2476 #define T6_SRAM_PRIO2_M    0x7U
2477 #define T6_SRAM_PRIO2_G(x) (((x) >> T6_SRAM_PRIO2_S) & T6_SRAM_PRIO2_M)
2478 
2479 #define T6_SRAM_PRIO1_S    17
2480 #define T6_SRAM_PRIO1_M    0x7U
2481 #define T6_SRAM_PRIO1_G(x) (((x) >> T6_SRAM_PRIO1_S) & T6_SRAM_PRIO1_M)
2482 
2483 #define T6_SRAM_PRIO0_S    14
2484 #define T6_SRAM_PRIO0_M    0x7U
2485 #define T6_SRAM_PRIO0_G(x) (((x) >> T6_SRAM_PRIO0_S) & T6_SRAM_PRIO0_M)
2486 
2487 #define T6_SRAM_VLD_S    13
2488 #define T6_SRAM_VLD_V(x) ((x) << T6_SRAM_VLD_S)
2489 #define T6_SRAM_VLD_F    T6_SRAM_VLD_V(1U)
2490 
2491 #define T6_REPLICATE_S    12
2492 #define T6_REPLICATE_V(x) ((x) << T6_REPLICATE_S)
2493 #define T6_REPLICATE_F    T6_REPLICATE_V(1U)
2494 
2495 #define T6_PF_S    9
2496 #define T6_PF_M    0x7U
2497 #define T6_PF_G(x) (((x) >> T6_PF_S) & T6_PF_M)
2498 
2499 #define T6_VF_VALID_S    8
2500 #define T6_VF_VALID_V(x) ((x) << T6_VF_VALID_S)
2501 #define T6_VF_VALID_F    T6_VF_VALID_V(1U)
2502 
2503 #define T6_VF_S    0
2504 #define T6_VF_M    0xffU
2505 #define T6_VF_G(x) (((x) >> T6_VF_S) & T6_VF_M)
2506 
2507 #define MPS_CLS_SRAM_H_A 0xe004
2508 
2509 #define MPS_CLS_SRAM_L(idx) (MPS_CLS_SRAM_L_A + (idx) * 8)
2510 #define NUM_MPS_CLS_SRAM_L_INSTANCES 336
2511 
2512 #define MPS_CLS_SRAM_H(idx) (MPS_CLS_SRAM_H_A + (idx) * 8)
2513 #define NUM_MPS_CLS_SRAM_H_INSTANCES 336
2514 
2515 #define MULTILISTEN0_S    25
2516 
2517 #define REPLICATE_S    11
2518 #define REPLICATE_V(x) ((x) << REPLICATE_S)
2519 #define REPLICATE_F    REPLICATE_V(1U)
2520 
2521 #define PF_S    8
2522 #define PF_M    0x7U
2523 #define PF_G(x) (((x) >> PF_S) & PF_M)
2524 
2525 #define VF_VALID_S    7
2526 #define VF_VALID_V(x) ((x) << VF_VALID_S)
2527 #define VF_VALID_F    VF_VALID_V(1U)
2528 
2529 #define VF_S    0
2530 #define VF_M    0x7fU
2531 #define VF_G(x) (((x) >> VF_S) & VF_M)
2532 
2533 #define SRAM_PRIO3_S    22
2534 #define SRAM_PRIO3_M    0x7U
2535 #define SRAM_PRIO3_G(x) (((x) >> SRAM_PRIO3_S) & SRAM_PRIO3_M)
2536 
2537 #define SRAM_PRIO2_S    19
2538 #define SRAM_PRIO2_M    0x7U
2539 #define SRAM_PRIO2_G(x) (((x) >> SRAM_PRIO2_S) & SRAM_PRIO2_M)
2540 
2541 #define SRAM_PRIO1_S    16
2542 #define SRAM_PRIO1_M    0x7U
2543 #define SRAM_PRIO1_G(x) (((x) >> SRAM_PRIO1_S) & SRAM_PRIO1_M)
2544 
2545 #define SRAM_PRIO0_S    13
2546 #define SRAM_PRIO0_M    0x7U
2547 #define SRAM_PRIO0_G(x) (((x) >> SRAM_PRIO0_S) & SRAM_PRIO0_M)
2548 
2549 #define SRAM_VLD_S    12
2550 #define SRAM_VLD_V(x) ((x) << SRAM_VLD_S)
2551 #define SRAM_VLD_F    SRAM_VLD_V(1U)
2552 
2553 #define PORTMAP_S    0
2554 #define PORTMAP_M    0xfU
2555 #define PORTMAP_G(x) (((x) >> PORTMAP_S) & PORTMAP_M)
2556 
2557 #define CPL_INTR_CAUSE_A 0x19054
2558 
2559 #define CIM_OP_MAP_PERR_S    5
2560 #define CIM_OP_MAP_PERR_V(x) ((x) << CIM_OP_MAP_PERR_S)
2561 #define CIM_OP_MAP_PERR_F    CIM_OP_MAP_PERR_V(1U)
2562 
2563 #define CIM_OVFL_ERROR_S    4
2564 #define CIM_OVFL_ERROR_V(x) ((x) << CIM_OVFL_ERROR_S)
2565 #define CIM_OVFL_ERROR_F    CIM_OVFL_ERROR_V(1U)
2566 
2567 #define TP_FRAMING_ERROR_S    3
2568 #define TP_FRAMING_ERROR_V(x) ((x) << TP_FRAMING_ERROR_S)
2569 #define TP_FRAMING_ERROR_F    TP_FRAMING_ERROR_V(1U)
2570 
2571 #define SGE_FRAMING_ERROR_S    2
2572 #define SGE_FRAMING_ERROR_V(x) ((x) << SGE_FRAMING_ERROR_S)
2573 #define SGE_FRAMING_ERROR_F    SGE_FRAMING_ERROR_V(1U)
2574 
2575 #define CIM_FRAMING_ERROR_S    1
2576 #define CIM_FRAMING_ERROR_V(x) ((x) << CIM_FRAMING_ERROR_S)
2577 #define CIM_FRAMING_ERROR_F    CIM_FRAMING_ERROR_V(1U)
2578 
2579 #define ZERO_SWITCH_ERROR_S    0
2580 #define ZERO_SWITCH_ERROR_V(x) ((x) << ZERO_SWITCH_ERROR_S)
2581 #define ZERO_SWITCH_ERROR_F    ZERO_SWITCH_ERROR_V(1U)
2582 
2583 #define SMB_INT_CAUSE_A 0x19090
2584 
2585 #define MSTTXFIFOPARINT_S    21
2586 #define MSTTXFIFOPARINT_V(x) ((x) << MSTTXFIFOPARINT_S)
2587 #define MSTTXFIFOPARINT_F    MSTTXFIFOPARINT_V(1U)
2588 
2589 #define MSTRXFIFOPARINT_S    20
2590 #define MSTRXFIFOPARINT_V(x) ((x) << MSTRXFIFOPARINT_S)
2591 #define MSTRXFIFOPARINT_F    MSTRXFIFOPARINT_V(1U)
2592 
2593 #define SLVFIFOPARINT_S    19
2594 #define SLVFIFOPARINT_V(x) ((x) << SLVFIFOPARINT_S)
2595 #define SLVFIFOPARINT_F    SLVFIFOPARINT_V(1U)
2596 
2597 #define ULP_RX_INT_CAUSE_A 0x19158
2598 #define ULP_RX_ISCSI_LLIMIT_A 0x1915c
2599 #define ULP_RX_ISCSI_ULIMIT_A 0x19160
2600 #define ULP_RX_ISCSI_TAGMASK_A 0x19164
2601 #define ULP_RX_ISCSI_PSZ_A 0x19168
2602 #define ULP_RX_TDDP_LLIMIT_A 0x1916c
2603 #define ULP_RX_TDDP_ULIMIT_A 0x19170
2604 #define ULP_RX_STAG_LLIMIT_A 0x1917c
2605 #define ULP_RX_STAG_ULIMIT_A 0x19180
2606 #define ULP_RX_RQ_LLIMIT_A 0x19184
2607 #define ULP_RX_RQ_ULIMIT_A 0x19188
2608 #define ULP_RX_PBL_LLIMIT_A 0x1918c
2609 #define ULP_RX_PBL_ULIMIT_A 0x19190
2610 #define ULP_RX_CTX_BASE_A 0x19194
2611 #define ULP_RX_RQUDP_LLIMIT_A 0x191a4
2612 #define ULP_RX_RQUDP_ULIMIT_A 0x191a8
2613 #define ULP_RX_LA_CTL_A 0x1923c
2614 #define ULP_RX_LA_RDPTR_A 0x19240
2615 #define ULP_RX_LA_RDDATA_A 0x19244
2616 #define ULP_RX_LA_WRPTR_A 0x19248
2617 
2618 #define HPZ3_S    24
2619 #define HPZ3_V(x) ((x) << HPZ3_S)
2620 
2621 #define HPZ2_S    16
2622 #define HPZ2_V(x) ((x) << HPZ2_S)
2623 
2624 #define HPZ1_S    8
2625 #define HPZ1_V(x) ((x) << HPZ1_S)
2626 
2627 #define HPZ0_S    0
2628 #define HPZ0_V(x) ((x) << HPZ0_S)
2629 
2630 #define ULP_RX_TDDP_PSZ_A 0x19178
2631 
2632 /* registers for module SF */
2633 #define SF_DATA_A 0x193f8
2634 #define SF_OP_A 0x193fc
2635 
2636 #define SF_BUSY_S    31
2637 #define SF_BUSY_V(x) ((x) << SF_BUSY_S)
2638 #define SF_BUSY_F    SF_BUSY_V(1U)
2639 
2640 #define SF_LOCK_S    4
2641 #define SF_LOCK_V(x) ((x) << SF_LOCK_S)
2642 #define SF_LOCK_F    SF_LOCK_V(1U)
2643 
2644 #define SF_CONT_S    3
2645 #define SF_CONT_V(x) ((x) << SF_CONT_S)
2646 #define SF_CONT_F    SF_CONT_V(1U)
2647 
2648 #define BYTECNT_S    1
2649 #define BYTECNT_V(x) ((x) << BYTECNT_S)
2650 
2651 #define OP_S    0
2652 #define OP_V(x) ((x) << OP_S)
2653 #define OP_F    OP_V(1U)
2654 
2655 #define PL_PF_INT_CAUSE_A 0x3c0
2656 
2657 #define PFSW_S    3
2658 #define PFSW_V(x) ((x) << PFSW_S)
2659 #define PFSW_F    PFSW_V(1U)
2660 
2661 #define PFCIM_S    1
2662 #define PFCIM_V(x) ((x) << PFCIM_S)
2663 #define PFCIM_F    PFCIM_V(1U)
2664 
2665 #define PL_PF_INT_ENABLE_A 0x3c4
2666 #define PL_PF_CTL_A 0x3c8
2667 
2668 #define PL_WHOAMI_A 0x19400
2669 
2670 #define SOURCEPF_S    8
2671 #define SOURCEPF_M    0x7U
2672 #define SOURCEPF_G(x) (((x) >> SOURCEPF_S) & SOURCEPF_M)
2673 
2674 #define T6_SOURCEPF_S    9
2675 #define T6_SOURCEPF_M    0x7U
2676 #define T6_SOURCEPF_G(x) (((x) >> T6_SOURCEPF_S) & T6_SOURCEPF_M)
2677 
2678 #define PL_INT_CAUSE_A 0x1940c
2679 
2680 #define ULP_TX_S    27
2681 #define ULP_TX_V(x) ((x) << ULP_TX_S)
2682 #define ULP_TX_F    ULP_TX_V(1U)
2683 
2684 #define SGE_S    26
2685 #define SGE_V(x) ((x) << SGE_S)
2686 #define SGE_F    SGE_V(1U)
2687 
2688 #define CPL_SWITCH_S    24
2689 #define CPL_SWITCH_V(x) ((x) << CPL_SWITCH_S)
2690 #define CPL_SWITCH_F    CPL_SWITCH_V(1U)
2691 
2692 #define ULP_RX_S    23
2693 #define ULP_RX_V(x) ((x) << ULP_RX_S)
2694 #define ULP_RX_F    ULP_RX_V(1U)
2695 
2696 #define PM_RX_S    22
2697 #define PM_RX_V(x) ((x) << PM_RX_S)
2698 #define PM_RX_F    PM_RX_V(1U)
2699 
2700 #define PM_TX_S    21
2701 #define PM_TX_V(x) ((x) << PM_TX_S)
2702 #define PM_TX_F    PM_TX_V(1U)
2703 
2704 #define MA_S    20
2705 #define MA_V(x) ((x) << MA_S)
2706 #define MA_F    MA_V(1U)
2707 
2708 #define TP_S    19
2709 #define TP_V(x) ((x) << TP_S)
2710 #define TP_F    TP_V(1U)
2711 
2712 #define LE_S    18
2713 #define LE_V(x) ((x) << LE_S)
2714 #define LE_F    LE_V(1U)
2715 
2716 #define EDC1_S    17
2717 #define EDC1_V(x) ((x) << EDC1_S)
2718 #define EDC1_F    EDC1_V(1U)
2719 
2720 #define EDC0_S    16
2721 #define EDC0_V(x) ((x) << EDC0_S)
2722 #define EDC0_F    EDC0_V(1U)
2723 
2724 #define MC_S    15
2725 #define MC_V(x) ((x) << MC_S)
2726 #define MC_F    MC_V(1U)
2727 
2728 #define PCIE_S    14
2729 #define PCIE_V(x) ((x) << PCIE_S)
2730 #define PCIE_F    PCIE_V(1U)
2731 
2732 #define XGMAC_KR1_S    12
2733 #define XGMAC_KR1_V(x) ((x) << XGMAC_KR1_S)
2734 #define XGMAC_KR1_F    XGMAC_KR1_V(1U)
2735 
2736 #define XGMAC_KR0_S    11
2737 #define XGMAC_KR0_V(x) ((x) << XGMAC_KR0_S)
2738 #define XGMAC_KR0_F    XGMAC_KR0_V(1U)
2739 
2740 #define XGMAC1_S    10
2741 #define XGMAC1_V(x) ((x) << XGMAC1_S)
2742 #define XGMAC1_F    XGMAC1_V(1U)
2743 
2744 #define XGMAC0_S    9
2745 #define XGMAC0_V(x) ((x) << XGMAC0_S)
2746 #define XGMAC0_F    XGMAC0_V(1U)
2747 
2748 #define SMB_S    8
2749 #define SMB_V(x) ((x) << SMB_S)
2750 #define SMB_F    SMB_V(1U)
2751 
2752 #define SF_S    7
2753 #define SF_V(x) ((x) << SF_S)
2754 #define SF_F    SF_V(1U)
2755 
2756 #define PL_S    6
2757 #define PL_V(x) ((x) << PL_S)
2758 #define PL_F    PL_V(1U)
2759 
2760 #define NCSI_S    5
2761 #define NCSI_V(x) ((x) << NCSI_S)
2762 #define NCSI_F    NCSI_V(1U)
2763 
2764 #define MPS_S    4
2765 #define MPS_V(x) ((x) << MPS_S)
2766 #define MPS_F    MPS_V(1U)
2767 
2768 #define CIM_S    0
2769 #define CIM_V(x) ((x) << CIM_S)
2770 #define CIM_F    CIM_V(1U)
2771 
2772 #define MC1_S    31
2773 #define MC1_V(x) ((x) << MC1_S)
2774 #define MC1_F    MC1_V(1U)
2775 
2776 #define PL_INT_ENABLE_A 0x19410
2777 #define PL_INT_MAP0_A 0x19414
2778 #define PL_RST_A 0x19428
2779 
2780 #define PIORST_S    1
2781 #define PIORST_V(x) ((x) << PIORST_S)
2782 #define PIORST_F    PIORST_V(1U)
2783 
2784 #define PIORSTMODE_S    0
2785 #define PIORSTMODE_V(x) ((x) << PIORSTMODE_S)
2786 #define PIORSTMODE_F    PIORSTMODE_V(1U)
2787 
2788 #define PL_PL_INT_CAUSE_A 0x19430
2789 
2790 #define FATALPERR_S    4
2791 #define FATALPERR_V(x) ((x) << FATALPERR_S)
2792 #define FATALPERR_F    FATALPERR_V(1U)
2793 
2794 #define PERRVFID_S    0
2795 #define PERRVFID_V(x) ((x) << PERRVFID_S)
2796 #define PERRVFID_F    PERRVFID_V(1U)
2797 
2798 #define PL_REV_A 0x1943c
2799 
2800 #define REV_S    0
2801 #define REV_M    0xfU
2802 #define REV_V(x) ((x) << REV_S)
2803 #define REV_G(x) (((x) >> REV_S) & REV_M)
2804 
2805 #define T6_UNKNOWNCMD_S    3
2806 #define T6_UNKNOWNCMD_V(x) ((x) << T6_UNKNOWNCMD_S)
2807 #define T6_UNKNOWNCMD_F    T6_UNKNOWNCMD_V(1U)
2808 
2809 #define T6_LIP0_S    2
2810 #define T6_LIP0_V(x) ((x) << T6_LIP0_S)
2811 #define T6_LIP0_F    T6_LIP0_V(1U)
2812 
2813 #define T6_LIPMISS_S    1
2814 #define T6_LIPMISS_V(x) ((x) << T6_LIPMISS_S)
2815 #define T6_LIPMISS_F    T6_LIPMISS_V(1U)
2816 
2817 #define LE_DB_CONFIG_A 0x19c04
2818 #define LE_DB_SERVER_INDEX_A 0x19c18
2819 #define LE_DB_SRVR_START_INDEX_A 0x19c18
2820 #define LE_DB_ACT_CNT_IPV4_A 0x19c20
2821 #define LE_DB_ACT_CNT_IPV6_A 0x19c24
2822 #define LE_DB_HASH_TID_BASE_A 0x19c30
2823 #define LE_DB_HASH_TBL_BASE_ADDR_A 0x19c30
2824 #define LE_DB_INT_CAUSE_A 0x19c3c
2825 #define LE_DB_TID_HASHBASE_A 0x19df8
2826 #define T6_LE_DB_HASH_TID_BASE_A 0x19df8
2827 
2828 #define HASHEN_S    20
2829 #define HASHEN_V(x) ((x) << HASHEN_S)
2830 #define HASHEN_F    HASHEN_V(1U)
2831 
2832 #define ASLIPCOMPEN_S    17
2833 #define ASLIPCOMPEN_V(x) ((x) << ASLIPCOMPEN_S)
2834 #define ASLIPCOMPEN_F    ASLIPCOMPEN_V(1U)
2835 
2836 #define REQQPARERR_S    16
2837 #define REQQPARERR_V(x) ((x) << REQQPARERR_S)
2838 #define REQQPARERR_F    REQQPARERR_V(1U)
2839 
2840 #define UNKNOWNCMD_S    15
2841 #define UNKNOWNCMD_V(x) ((x) << UNKNOWNCMD_S)
2842 #define UNKNOWNCMD_F    UNKNOWNCMD_V(1U)
2843 
2844 #define PARITYERR_S    6
2845 #define PARITYERR_V(x) ((x) << PARITYERR_S)
2846 #define PARITYERR_F    PARITYERR_V(1U)
2847 
2848 #define LIPMISS_S    5
2849 #define LIPMISS_V(x) ((x) << LIPMISS_S)
2850 #define LIPMISS_F    LIPMISS_V(1U)
2851 
2852 #define LIP0_S    4
2853 #define LIP0_V(x) ((x) << LIP0_S)
2854 #define LIP0_F    LIP0_V(1U)
2855 
2856 #define BASEADDR_S    3
2857 #define BASEADDR_M    0x1fffffffU
2858 #define BASEADDR_G(x) (((x) >> BASEADDR_S) & BASEADDR_M)
2859 
2860 #define TCAMINTPERR_S    13
2861 #define TCAMINTPERR_V(x) ((x) << TCAMINTPERR_S)
2862 #define TCAMINTPERR_F    TCAMINTPERR_V(1U)
2863 
2864 #define SSRAMINTPERR_S    10
2865 #define SSRAMINTPERR_V(x) ((x) << SSRAMINTPERR_S)
2866 #define SSRAMINTPERR_F    SSRAMINTPERR_V(1U)
2867 
2868 #define NCSI_INT_CAUSE_A 0x1a0d8
2869 
2870 #define CIM_DM_PRTY_ERR_S    8
2871 #define CIM_DM_PRTY_ERR_V(x) ((x) << CIM_DM_PRTY_ERR_S)
2872 #define CIM_DM_PRTY_ERR_F    CIM_DM_PRTY_ERR_V(1U)
2873 
2874 #define MPS_DM_PRTY_ERR_S    7
2875 #define MPS_DM_PRTY_ERR_V(x) ((x) << MPS_DM_PRTY_ERR_S)
2876 #define MPS_DM_PRTY_ERR_F    MPS_DM_PRTY_ERR_V(1U)
2877 
2878 #define TXFIFO_PRTY_ERR_S    1
2879 #define TXFIFO_PRTY_ERR_V(x) ((x) << TXFIFO_PRTY_ERR_S)
2880 #define TXFIFO_PRTY_ERR_F    TXFIFO_PRTY_ERR_V(1U)
2881 
2882 #define RXFIFO_PRTY_ERR_S    0
2883 #define RXFIFO_PRTY_ERR_V(x) ((x) << RXFIFO_PRTY_ERR_S)
2884 #define RXFIFO_PRTY_ERR_F    RXFIFO_PRTY_ERR_V(1U)
2885 
2886 #define XGMAC_PORT_CFG2_A 0x1018
2887 
2888 #define PATEN_S    18
2889 #define PATEN_V(x) ((x) << PATEN_S)
2890 #define PATEN_F    PATEN_V(1U)
2891 
2892 #define MAGICEN_S    17
2893 #define MAGICEN_V(x) ((x) << MAGICEN_S)
2894 #define MAGICEN_F    MAGICEN_V(1U)
2895 
2896 #define XGMAC_PORT_MAGIC_MACID_LO 0x1024
2897 #define XGMAC_PORT_MAGIC_MACID_HI 0x1028
2898 
2899 #define XGMAC_PORT_EPIO_DATA0_A 0x10c0
2900 #define XGMAC_PORT_EPIO_DATA1_A 0x10c4
2901 #define XGMAC_PORT_EPIO_DATA2_A 0x10c8
2902 #define XGMAC_PORT_EPIO_DATA3_A 0x10cc
2903 #define XGMAC_PORT_EPIO_OP_A 0x10d0
2904 
2905 #define EPIOWR_S    8
2906 #define EPIOWR_V(x) ((x) << EPIOWR_S)
2907 #define EPIOWR_F    EPIOWR_V(1U)
2908 
2909 #define ADDRESS_S    0
2910 #define ADDRESS_V(x) ((x) << ADDRESS_S)
2911 
2912 #define MAC_PORT_INT_CAUSE_A 0x8dc
2913 #define XGMAC_PORT_INT_CAUSE_A 0x10dc
2914 
2915 #define TP_TX_MOD_QUEUE_REQ_MAP_A 0x7e28
2916 
2917 #define TP_TX_MOD_QUEUE_WEIGHT0_A 0x7e30
2918 #define TP_TX_MOD_CHANNEL_WEIGHT_A 0x7e34
2919 
2920 #define TX_MOD_QUEUE_REQ_MAP_S    0
2921 #define TX_MOD_QUEUE_REQ_MAP_V(x) ((x) << TX_MOD_QUEUE_REQ_MAP_S)
2922 
2923 #define TX_MODQ_WEIGHT3_S    24
2924 #define TX_MODQ_WEIGHT3_V(x) ((x) << TX_MODQ_WEIGHT3_S)
2925 
2926 #define TX_MODQ_WEIGHT2_S    16
2927 #define TX_MODQ_WEIGHT2_V(x) ((x) << TX_MODQ_WEIGHT2_S)
2928 
2929 #define TX_MODQ_WEIGHT1_S    8
2930 #define TX_MODQ_WEIGHT1_V(x) ((x) << TX_MODQ_WEIGHT1_S)
2931 
2932 #define TX_MODQ_WEIGHT0_S    0
2933 #define TX_MODQ_WEIGHT0_V(x) ((x) << TX_MODQ_WEIGHT0_S)
2934 
2935 #define TP_TX_SCHED_HDR_A 0x23
2936 #define TP_TX_SCHED_FIFO_A 0x24
2937 #define TP_TX_SCHED_PCMD_A 0x25
2938 
2939 #define NUM_MPS_CLS_SRAM_L_INSTANCES 336
2940 #define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512
2941 
2942 #define T5_PORT0_BASE 0x30000
2943 #define T5_PORT_STRIDE 0x4000
2944 #define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE)
2945 #define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg))
2946 
2947 #define MC_0_BASE_ADDR 0x40000
2948 #define MC_1_BASE_ADDR 0x48000
2949 #define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR)
2950 #define MC_REG(reg, idx) (reg + MC_STRIDE * idx)
2951 
2952 #define MC_P_BIST_CMD_A			0x41400
2953 #define MC_P_BIST_CMD_ADDR_A		0x41404
2954 #define MC_P_BIST_CMD_LEN_A		0x41408
2955 #define MC_P_BIST_DATA_PATTERN_A	0x4140c
2956 #define MC_P_BIST_STATUS_RDATA_A	0x41488
2957 
2958 #define EDC_T50_BASE_ADDR		0x50000
2959 
2960 #define EDC_H_BIST_CMD_A		0x50004
2961 #define EDC_H_BIST_CMD_ADDR_A		0x50008
2962 #define EDC_H_BIST_CMD_LEN_A		0x5000c
2963 #define EDC_H_BIST_DATA_PATTERN_A	0x50010
2964 #define EDC_H_BIST_STATUS_RDATA_A	0x50028
2965 
2966 #define EDC_H_ECC_ERR_ADDR_A		0x50084
2967 #define EDC_T51_BASE_ADDR		0x50800
2968 
2969 #define EDC_T5_STRIDE (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
2970 #define EDC_T5_REG(reg, idx) (reg + EDC_T5_STRIDE * idx)
2971 
2972 #define PL_VF_REV_A 0x4
2973 #define PL_VF_WHOAMI_A 0x0
2974 #define PL_VF_REVISION_A 0x8
2975 
2976 /* registers for module CIM */
2977 #define CIM_HOST_ACC_CTRL_A	0x7b50
2978 #define CIM_HOST_ACC_DATA_A	0x7b54
2979 #define UP_UP_DBG_LA_CFG_A	0x140
2980 #define UP_UP_DBG_LA_DATA_A	0x144
2981 
2982 #define HOSTBUSY_S	17
2983 #define HOSTBUSY_V(x)	((x) << HOSTBUSY_S)
2984 #define HOSTBUSY_F	HOSTBUSY_V(1U)
2985 
2986 #define HOSTWRITE_S	16
2987 #define HOSTWRITE_V(x)	((x) << HOSTWRITE_S)
2988 #define HOSTWRITE_F	HOSTWRITE_V(1U)
2989 
2990 #define CIM_IBQ_DBG_CFG_A 0x7b60
2991 
2992 #define IBQDBGADDR_S    16
2993 #define IBQDBGADDR_M    0xfffU
2994 #define IBQDBGADDR_V(x) ((x) << IBQDBGADDR_S)
2995 #define IBQDBGADDR_G(x) (((x) >> IBQDBGADDR_S) & IBQDBGADDR_M)
2996 
2997 #define IBQDBGBUSY_S    1
2998 #define IBQDBGBUSY_V(x) ((x) << IBQDBGBUSY_S)
2999 #define IBQDBGBUSY_F    IBQDBGBUSY_V(1U)
3000 
3001 #define IBQDBGEN_S    0
3002 #define IBQDBGEN_V(x) ((x) << IBQDBGEN_S)
3003 #define IBQDBGEN_F    IBQDBGEN_V(1U)
3004 
3005 #define CIM_OBQ_DBG_CFG_A 0x7b64
3006 
3007 #define OBQDBGADDR_S    16
3008 #define OBQDBGADDR_M    0xfffU
3009 #define OBQDBGADDR_V(x) ((x) << OBQDBGADDR_S)
3010 #define OBQDBGADDR_G(x) (((x) >> OBQDBGADDR_S) & OBQDBGADDR_M)
3011 
3012 #define OBQDBGBUSY_S    1
3013 #define OBQDBGBUSY_V(x) ((x) << OBQDBGBUSY_S)
3014 #define OBQDBGBUSY_F    OBQDBGBUSY_V(1U)
3015 
3016 #define OBQDBGEN_S    0
3017 #define OBQDBGEN_V(x) ((x) << OBQDBGEN_S)
3018 #define OBQDBGEN_F    OBQDBGEN_V(1U)
3019 
3020 #define CIM_IBQ_DBG_DATA_A 0x7b68
3021 #define CIM_OBQ_DBG_DATA_A 0x7b6c
3022 #define CIM_DEBUGCFG_A 0x7b70
3023 #define CIM_DEBUGSTS_A 0x7b74
3024 
3025 #define POLADBGRDPTR_S		23
3026 #define POLADBGRDPTR_M		0x1ffU
3027 #define POLADBGRDPTR_V(x)	((x) << POLADBGRDPTR_S)
3028 
3029 #define POLADBGWRPTR_S		16
3030 #define POLADBGWRPTR_M		0x1ffU
3031 #define POLADBGWRPTR_G(x)	(((x) >> POLADBGWRPTR_S) & POLADBGWRPTR_M)
3032 
3033 #define PILADBGRDPTR_S		14
3034 #define PILADBGRDPTR_M		0x1ffU
3035 #define PILADBGRDPTR_V(x)	((x) << PILADBGRDPTR_S)
3036 
3037 #define PILADBGWRPTR_S		0
3038 #define PILADBGWRPTR_M		0x1ffU
3039 #define PILADBGWRPTR_G(x)	(((x) >> PILADBGWRPTR_S) & PILADBGWRPTR_M)
3040 
3041 #define LADBGEN_S	12
3042 #define LADBGEN_V(x)	((x) << LADBGEN_S)
3043 #define LADBGEN_F	LADBGEN_V(1U)
3044 
3045 #define CIM_PO_LA_DEBUGDATA_A 0x7b78
3046 #define CIM_PI_LA_DEBUGDATA_A 0x7b7c
3047 #define CIM_PO_LA_MADEBUGDATA_A	0x7b80
3048 #define CIM_PI_LA_MADEBUGDATA_A	0x7b84
3049 
3050 #define UPDBGLARDEN_S		1
3051 #define UPDBGLARDEN_V(x)	((x) << UPDBGLARDEN_S)
3052 #define UPDBGLARDEN_F		UPDBGLARDEN_V(1U)
3053 
3054 #define UPDBGLAEN_S	0
3055 #define UPDBGLAEN_V(x)	((x) << UPDBGLAEN_S)
3056 #define UPDBGLAEN_F	UPDBGLAEN_V(1U)
3057 
3058 #define UPDBGLARDPTR_S		2
3059 #define UPDBGLARDPTR_M		0xfffU
3060 #define UPDBGLARDPTR_V(x)	((x) << UPDBGLARDPTR_S)
3061 
3062 #define UPDBGLAWRPTR_S    16
3063 #define UPDBGLAWRPTR_M    0xfffU
3064 #define UPDBGLAWRPTR_G(x) (((x) >> UPDBGLAWRPTR_S) & UPDBGLAWRPTR_M)
3065 
3066 #define UPDBGLACAPTPCONLY_S	30
3067 #define UPDBGLACAPTPCONLY_V(x)	((x) << UPDBGLACAPTPCONLY_S)
3068 #define UPDBGLACAPTPCONLY_F	UPDBGLACAPTPCONLY_V(1U)
3069 
3070 #define CIM_QUEUE_CONFIG_REF_A 0x7b48
3071 #define CIM_QUEUE_CONFIG_CTRL_A 0x7b4c
3072 
3073 #define CIMQSIZE_S    24
3074 #define CIMQSIZE_M    0x3fU
3075 #define CIMQSIZE_G(x) (((x) >> CIMQSIZE_S) & CIMQSIZE_M)
3076 
3077 #define CIMQBASE_S    16
3078 #define CIMQBASE_M    0x3fU
3079 #define CIMQBASE_G(x) (((x) >> CIMQBASE_S) & CIMQBASE_M)
3080 
3081 #define QUEFULLTHRSH_S    0
3082 #define QUEFULLTHRSH_M    0x1ffU
3083 #define QUEFULLTHRSH_G(x) (((x) >> QUEFULLTHRSH_S) & QUEFULLTHRSH_M)
3084 
3085 #define UP_IBQ_0_RDADDR_A 0x10
3086 #define UP_IBQ_0_SHADOW_RDADDR_A 0x280
3087 #define UP_OBQ_0_REALADDR_A 0x104
3088 #define UP_OBQ_0_SHADOW_REALADDR_A 0x394
3089 
3090 #define IBQRDADDR_S    0
3091 #define IBQRDADDR_M    0x1fffU
3092 #define IBQRDADDR_G(x) (((x) >> IBQRDADDR_S) & IBQRDADDR_M)
3093 
3094 #define IBQWRADDR_S    0
3095 #define IBQWRADDR_M    0x1fffU
3096 #define IBQWRADDR_G(x) (((x) >> IBQWRADDR_S) & IBQWRADDR_M)
3097 
3098 #define QUERDADDR_S    0
3099 #define QUERDADDR_M    0x7fffU
3100 #define QUERDADDR_G(x) (((x) >> QUERDADDR_S) & QUERDADDR_M)
3101 
3102 #define QUEREMFLITS_S    0
3103 #define QUEREMFLITS_M    0x7ffU
3104 #define QUEREMFLITS_G(x) (((x) >> QUEREMFLITS_S) & QUEREMFLITS_M)
3105 
3106 #define QUEEOPCNT_S    16
3107 #define QUEEOPCNT_M    0xfffU
3108 #define QUEEOPCNT_G(x) (((x) >> QUEEOPCNT_S) & QUEEOPCNT_M)
3109 
3110 #define QUESOPCNT_S    0
3111 #define QUESOPCNT_M    0xfffU
3112 #define QUESOPCNT_G(x) (((x) >> QUESOPCNT_S) & QUESOPCNT_M)
3113 
3114 #define OBQSELECT_S    4
3115 #define OBQSELECT_V(x) ((x) << OBQSELECT_S)
3116 #define OBQSELECT_F    OBQSELECT_V(1U)
3117 
3118 #define IBQSELECT_S    3
3119 #define IBQSELECT_V(x) ((x) << IBQSELECT_S)
3120 #define IBQSELECT_F    IBQSELECT_V(1U)
3121 
3122 #define QUENUMSELECT_S    0
3123 #define QUENUMSELECT_V(x) ((x) << QUENUMSELECT_S)
3124 
3125 #endif /* __T4_REGS_H */
3126