1 /*
2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
3  *
4  * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
5  *
6  * This software is available to you under a choice of one of two
7  * licenses.  You may choose to be licensed under the terms of the GNU
8  * General Public License (GPL) Version 2, available from the file
9  * COPYING in the main directory of this source tree, or the
10  * OpenIB.org BSD license below:
11  *
12  *     Redistribution and use in source and binary forms, with or
13  *     without modification, are permitted provided that the following
14  *     conditions are met:
15  *
16  *      - Redistributions of source code must retain the above
17  *        copyright notice, this list of conditions and the following
18  *        disclaimer.
19  *
20  *      - Redistributions in binary form must reproduce the above
21  *        copyright notice, this list of conditions and the following
22  *        disclaimer in the documentation and/or other materials
23  *        provided with the distribution.
24  *
25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32  * SOFTWARE.
33  */
34 
35 #ifndef __T4_REGS_H
36 #define __T4_REGS_H
37 
38 #define MYPF_BASE 0x1b000
39 #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))
40 
41 #define PF0_BASE 0x1e000
42 #define PF0_REG(reg_addr) (PF0_BASE + (reg_addr))
43 
44 #define PF_STRIDE 0x400
45 #define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE)
46 #define PF_REG(idx, reg) (PF_BASE(idx) + (reg))
47 
48 #define NUM_CIM_CTL_TSCH_CHANNEL_INSTANCES 4
49 #define NUM_CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_INSTANCES 16
50 
51 #define MYPORT_BASE 0x1c000
52 #define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr))
53 
54 #define PORT0_BASE 0x20000
55 #define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr))
56 
57 #define PORT_STRIDE 0x2000
58 #define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE)
59 #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))
60 
61 #define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR)
62 #define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx)
63 
64 #define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
65 #define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
66 #define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
67 #define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
68 
69 #define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
70 
71 #define NUM_LE_DB_DBGI_REQ_DATA_INSTANCES 17
72 #define NUM_LE_DB_DBGI_RSP_DATA_INSTANCES 17
73 
74 #define SGE_PF_KDOORBELL_A 0x0
75 
76 #define QID_S    15
77 #define QID_V(x) ((x) << QID_S)
78 
79 #define DBPRIO_S    14
80 #define DBPRIO_V(x) ((x) << DBPRIO_S)
81 #define DBPRIO_F    DBPRIO_V(1U)
82 
83 #define PIDX_S    0
84 #define PIDX_V(x) ((x) << PIDX_S)
85 
86 #define SGE_VF_KDOORBELL_A 0x0
87 
88 #define DBTYPE_S    13
89 #define DBTYPE_V(x) ((x) << DBTYPE_S)
90 #define DBTYPE_F    DBTYPE_V(1U)
91 
92 #define PIDX_T5_S    0
93 #define PIDX_T5_M    0x1fffU
94 #define PIDX_T5_V(x) ((x) << PIDX_T5_S)
95 #define PIDX_T5_G(x) (((x) >> PIDX_T5_S) & PIDX_T5_M)
96 
97 #define SGE_PF_GTS_A 0x4
98 
99 #define INGRESSQID_S    16
100 #define INGRESSQID_V(x) ((x) << INGRESSQID_S)
101 
102 #define TIMERREG_S    13
103 #define TIMERREG_V(x) ((x) << TIMERREG_S)
104 
105 #define SEINTARM_S    12
106 #define SEINTARM_V(x) ((x) << SEINTARM_S)
107 
108 #define CIDXINC_S    0
109 #define CIDXINC_M    0xfffU
110 #define CIDXINC_V(x) ((x) << CIDXINC_S)
111 
112 #define SGE_CONTROL_A	0x1008
113 #define SGE_CONTROL2_A	0x1124
114 
115 #define RXPKTCPLMODE_S    18
116 #define RXPKTCPLMODE_V(x) ((x) << RXPKTCPLMODE_S)
117 #define RXPKTCPLMODE_F    RXPKTCPLMODE_V(1U)
118 
119 #define EGRSTATUSPAGESIZE_S    17
120 #define EGRSTATUSPAGESIZE_V(x) ((x) << EGRSTATUSPAGESIZE_S)
121 #define EGRSTATUSPAGESIZE_F    EGRSTATUSPAGESIZE_V(1U)
122 
123 #define PKTSHIFT_S    10
124 #define PKTSHIFT_M    0x7U
125 #define PKTSHIFT_V(x) ((x) << PKTSHIFT_S)
126 #define PKTSHIFT_G(x) (((x) >> PKTSHIFT_S) & PKTSHIFT_M)
127 
128 #define INGPCIEBOUNDARY_S    7
129 #define INGPCIEBOUNDARY_V(x) ((x) << INGPCIEBOUNDARY_S)
130 
131 #define INGPADBOUNDARY_S    4
132 #define INGPADBOUNDARY_M    0x7U
133 #define INGPADBOUNDARY_V(x) ((x) << INGPADBOUNDARY_S)
134 #define INGPADBOUNDARY_G(x) (((x) >> INGPADBOUNDARY_S) & INGPADBOUNDARY_M)
135 
136 #define EGRPCIEBOUNDARY_S    1
137 #define EGRPCIEBOUNDARY_V(x) ((x) << EGRPCIEBOUNDARY_S)
138 
139 #define  INGPACKBOUNDARY_S	16
140 #define  INGPACKBOUNDARY_M	0x7U
141 #define  INGPACKBOUNDARY_V(x)	((x) << INGPACKBOUNDARY_S)
142 #define  INGPACKBOUNDARY_G(x)	(((x) >> INGPACKBOUNDARY_S) \
143 				 & INGPACKBOUNDARY_M)
144 
145 #define VFIFO_ENABLE_S    10
146 #define VFIFO_ENABLE_V(x) ((x) << VFIFO_ENABLE_S)
147 #define VFIFO_ENABLE_F    VFIFO_ENABLE_V(1U)
148 
149 #define SGE_DBVFIFO_BADDR_A 0x1138
150 
151 #define DBVFIFO_SIZE_S    6
152 #define DBVFIFO_SIZE_M    0xfffU
153 #define DBVFIFO_SIZE_G(x) (((x) >> DBVFIFO_SIZE_S) & DBVFIFO_SIZE_M)
154 
155 #define T6_DBVFIFO_SIZE_S    0
156 #define T6_DBVFIFO_SIZE_M    0x1fffU
157 #define T6_DBVFIFO_SIZE_G(x) (((x) >> T6_DBVFIFO_SIZE_S) & T6_DBVFIFO_SIZE_M)
158 
159 #define SGE_CTXT_CMD_A 0x11fc
160 
161 #define BUSY_S    31
162 #define BUSY_V(x) ((x) << BUSY_S)
163 #define BUSY_F    BUSY_V(1U)
164 
165 #define CTXTTYPE_S    24
166 #define CTXTTYPE_M    0x3U
167 #define CTXTTYPE_V(x) ((x) << CTXTTYPE_S)
168 
169 #define CTXTQID_S    0
170 #define CTXTQID_M    0x1ffffU
171 #define CTXTQID_V(x) ((x) << CTXTQID_S)
172 
173 #define SGE_CTXT_DATA0_A 0x1200
174 #define SGE_CTXT_DATA5_A 0x1214
175 
176 #define GLOBALENABLE_S    0
177 #define GLOBALENABLE_V(x) ((x) << GLOBALENABLE_S)
178 #define GLOBALENABLE_F    GLOBALENABLE_V(1U)
179 
180 #define SGE_HOST_PAGE_SIZE_A 0x100c
181 
182 #define HOSTPAGESIZEPF7_S    28
183 #define HOSTPAGESIZEPF7_M    0xfU
184 #define HOSTPAGESIZEPF7_V(x) ((x) << HOSTPAGESIZEPF7_S)
185 #define HOSTPAGESIZEPF7_G(x) (((x) >> HOSTPAGESIZEPF7_S) & HOSTPAGESIZEPF7_M)
186 
187 #define HOSTPAGESIZEPF6_S    24
188 #define HOSTPAGESIZEPF6_M    0xfU
189 #define HOSTPAGESIZEPF6_V(x) ((x) << HOSTPAGESIZEPF6_S)
190 #define HOSTPAGESIZEPF6_G(x) (((x) >> HOSTPAGESIZEPF6_S) & HOSTPAGESIZEPF6_M)
191 
192 #define HOSTPAGESIZEPF5_S    20
193 #define HOSTPAGESIZEPF5_M    0xfU
194 #define HOSTPAGESIZEPF5_V(x) ((x) << HOSTPAGESIZEPF5_S)
195 #define HOSTPAGESIZEPF5_G(x) (((x) >> HOSTPAGESIZEPF5_S) & HOSTPAGESIZEPF5_M)
196 
197 #define HOSTPAGESIZEPF4_S    16
198 #define HOSTPAGESIZEPF4_M    0xfU
199 #define HOSTPAGESIZEPF4_V(x) ((x) << HOSTPAGESIZEPF4_S)
200 #define HOSTPAGESIZEPF4_G(x) (((x) >> HOSTPAGESIZEPF4_S) & HOSTPAGESIZEPF4_M)
201 
202 #define HOSTPAGESIZEPF3_S    12
203 #define HOSTPAGESIZEPF3_M    0xfU
204 #define HOSTPAGESIZEPF3_V(x) ((x) << HOSTPAGESIZEPF3_S)
205 #define HOSTPAGESIZEPF3_G(x) (((x) >> HOSTPAGESIZEPF3_S) & HOSTPAGESIZEPF3_M)
206 
207 #define HOSTPAGESIZEPF2_S    8
208 #define HOSTPAGESIZEPF2_M    0xfU
209 #define HOSTPAGESIZEPF2_V(x) ((x) << HOSTPAGESIZEPF2_S)
210 #define HOSTPAGESIZEPF2_G(x) (((x) >> HOSTPAGESIZEPF2_S) & HOSTPAGESIZEPF2_M)
211 
212 #define HOSTPAGESIZEPF1_S    4
213 #define HOSTPAGESIZEPF1_M    0xfU
214 #define HOSTPAGESIZEPF1_V(x) ((x) << HOSTPAGESIZEPF1_S)
215 #define HOSTPAGESIZEPF1_G(x) (((x) >> HOSTPAGESIZEPF1_S) & HOSTPAGESIZEPF1_M)
216 
217 #define HOSTPAGESIZEPF0_S    0
218 #define HOSTPAGESIZEPF0_M    0xfU
219 #define HOSTPAGESIZEPF0_V(x) ((x) << HOSTPAGESIZEPF0_S)
220 #define HOSTPAGESIZEPF0_G(x) (((x) >> HOSTPAGESIZEPF0_S) & HOSTPAGESIZEPF0_M)
221 
222 #define SGE_EGRESS_QUEUES_PER_PAGE_PF_A 0x1010
223 #define SGE_EGRESS_QUEUES_PER_PAGE_VF_A 0x1014
224 
225 #define QUEUESPERPAGEPF1_S    4
226 
227 #define QUEUESPERPAGEPF0_S    0
228 #define QUEUESPERPAGEPF0_M    0xfU
229 #define QUEUESPERPAGEPF0_V(x) ((x) << QUEUESPERPAGEPF0_S)
230 #define QUEUESPERPAGEPF0_G(x) (((x) >> QUEUESPERPAGEPF0_S) & QUEUESPERPAGEPF0_M)
231 
232 #define SGE_INT_CAUSE1_A	0x1024
233 #define SGE_INT_CAUSE2_A	0x1030
234 #define SGE_INT_CAUSE3_A	0x103c
235 
236 #define ERR_FLM_DBP_S    31
237 #define ERR_FLM_DBP_V(x) ((x) << ERR_FLM_DBP_S)
238 #define ERR_FLM_DBP_F    ERR_FLM_DBP_V(1U)
239 
240 #define ERR_FLM_IDMA1_S    30
241 #define ERR_FLM_IDMA1_V(x) ((x) << ERR_FLM_IDMA1_S)
242 #define ERR_FLM_IDMA1_F    ERR_FLM_IDMA1_V(1U)
243 
244 #define ERR_FLM_IDMA0_S    29
245 #define ERR_FLM_IDMA0_V(x) ((x) << ERR_FLM_IDMA0_S)
246 #define ERR_FLM_IDMA0_F    ERR_FLM_IDMA0_V(1U)
247 
248 #define ERR_FLM_HINT_S    28
249 #define ERR_FLM_HINT_V(x) ((x) << ERR_FLM_HINT_S)
250 #define ERR_FLM_HINT_F    ERR_FLM_HINT_V(1U)
251 
252 #define ERR_PCIE_ERROR3_S    27
253 #define ERR_PCIE_ERROR3_V(x) ((x) << ERR_PCIE_ERROR3_S)
254 #define ERR_PCIE_ERROR3_F    ERR_PCIE_ERROR3_V(1U)
255 
256 #define ERR_PCIE_ERROR2_S    26
257 #define ERR_PCIE_ERROR2_V(x) ((x) << ERR_PCIE_ERROR2_S)
258 #define ERR_PCIE_ERROR2_F    ERR_PCIE_ERROR2_V(1U)
259 
260 #define ERR_PCIE_ERROR1_S    25
261 #define ERR_PCIE_ERROR1_V(x) ((x) << ERR_PCIE_ERROR1_S)
262 #define ERR_PCIE_ERROR1_F    ERR_PCIE_ERROR1_V(1U)
263 
264 #define ERR_PCIE_ERROR0_S    24
265 #define ERR_PCIE_ERROR0_V(x) ((x) << ERR_PCIE_ERROR0_S)
266 #define ERR_PCIE_ERROR0_F    ERR_PCIE_ERROR0_V(1U)
267 
268 #define ERR_CPL_EXCEED_IQE_SIZE_S    22
269 #define ERR_CPL_EXCEED_IQE_SIZE_V(x) ((x) << ERR_CPL_EXCEED_IQE_SIZE_S)
270 #define ERR_CPL_EXCEED_IQE_SIZE_F    ERR_CPL_EXCEED_IQE_SIZE_V(1U)
271 
272 #define ERR_INVALID_CIDX_INC_S    21
273 #define ERR_INVALID_CIDX_INC_V(x) ((x) << ERR_INVALID_CIDX_INC_S)
274 #define ERR_INVALID_CIDX_INC_F    ERR_INVALID_CIDX_INC_V(1U)
275 
276 #define ERR_CPL_OPCODE_0_S    19
277 #define ERR_CPL_OPCODE_0_V(x) ((x) << ERR_CPL_OPCODE_0_S)
278 #define ERR_CPL_OPCODE_0_F    ERR_CPL_OPCODE_0_V(1U)
279 
280 #define ERR_DROPPED_DB_S    18
281 #define ERR_DROPPED_DB_V(x) ((x) << ERR_DROPPED_DB_S)
282 #define ERR_DROPPED_DB_F    ERR_DROPPED_DB_V(1U)
283 
284 #define ERR_DATA_CPL_ON_HIGH_QID1_S    17
285 #define ERR_DATA_CPL_ON_HIGH_QID1_V(x) ((x) << ERR_DATA_CPL_ON_HIGH_QID1_S)
286 #define ERR_DATA_CPL_ON_HIGH_QID1_F    ERR_DATA_CPL_ON_HIGH_QID1_V(1U)
287 
288 #define ERR_DATA_CPL_ON_HIGH_QID0_S    16
289 #define ERR_DATA_CPL_ON_HIGH_QID0_V(x) ((x) << ERR_DATA_CPL_ON_HIGH_QID0_S)
290 #define ERR_DATA_CPL_ON_HIGH_QID0_F    ERR_DATA_CPL_ON_HIGH_QID0_V(1U)
291 
292 #define ERR_BAD_DB_PIDX3_S    15
293 #define ERR_BAD_DB_PIDX3_V(x) ((x) << ERR_BAD_DB_PIDX3_S)
294 #define ERR_BAD_DB_PIDX3_F    ERR_BAD_DB_PIDX3_V(1U)
295 
296 #define ERR_BAD_DB_PIDX2_S    14
297 #define ERR_BAD_DB_PIDX2_V(x) ((x) << ERR_BAD_DB_PIDX2_S)
298 #define ERR_BAD_DB_PIDX2_F    ERR_BAD_DB_PIDX2_V(1U)
299 
300 #define ERR_BAD_DB_PIDX1_S    13
301 #define ERR_BAD_DB_PIDX1_V(x) ((x) << ERR_BAD_DB_PIDX1_S)
302 #define ERR_BAD_DB_PIDX1_F    ERR_BAD_DB_PIDX1_V(1U)
303 
304 #define ERR_BAD_DB_PIDX0_S    12
305 #define ERR_BAD_DB_PIDX0_V(x) ((x) << ERR_BAD_DB_PIDX0_S)
306 #define ERR_BAD_DB_PIDX0_F    ERR_BAD_DB_PIDX0_V(1U)
307 
308 #define ERR_ING_CTXT_PRIO_S    10
309 #define ERR_ING_CTXT_PRIO_V(x) ((x) << ERR_ING_CTXT_PRIO_S)
310 #define ERR_ING_CTXT_PRIO_F    ERR_ING_CTXT_PRIO_V(1U)
311 
312 #define ERR_EGR_CTXT_PRIO_S    9
313 #define ERR_EGR_CTXT_PRIO_V(x) ((x) << ERR_EGR_CTXT_PRIO_S)
314 #define ERR_EGR_CTXT_PRIO_F    ERR_EGR_CTXT_PRIO_V(1U)
315 
316 #define DBFIFO_HP_INT_S    8
317 #define DBFIFO_HP_INT_V(x) ((x) << DBFIFO_HP_INT_S)
318 #define DBFIFO_HP_INT_F    DBFIFO_HP_INT_V(1U)
319 
320 #define DBFIFO_LP_INT_S    7
321 #define DBFIFO_LP_INT_V(x) ((x) << DBFIFO_LP_INT_S)
322 #define DBFIFO_LP_INT_F    DBFIFO_LP_INT_V(1U)
323 
324 #define INGRESS_SIZE_ERR_S    5
325 #define INGRESS_SIZE_ERR_V(x) ((x) << INGRESS_SIZE_ERR_S)
326 #define INGRESS_SIZE_ERR_F    INGRESS_SIZE_ERR_V(1U)
327 
328 #define EGRESS_SIZE_ERR_S    4
329 #define EGRESS_SIZE_ERR_V(x) ((x) << EGRESS_SIZE_ERR_S)
330 #define EGRESS_SIZE_ERR_F    EGRESS_SIZE_ERR_V(1U)
331 
332 #define SGE_INT_ENABLE3_A 0x1040
333 #define SGE_FL_BUFFER_SIZE0_A 0x1044
334 #define SGE_FL_BUFFER_SIZE1_A 0x1048
335 #define SGE_FL_BUFFER_SIZE2_A 0x104c
336 #define SGE_FL_BUFFER_SIZE3_A 0x1050
337 #define SGE_FL_BUFFER_SIZE4_A 0x1054
338 #define SGE_FL_BUFFER_SIZE5_A 0x1058
339 #define SGE_FL_BUFFER_SIZE6_A 0x105c
340 #define SGE_FL_BUFFER_SIZE7_A 0x1060
341 #define SGE_FL_BUFFER_SIZE8_A 0x1064
342 
343 #define SGE_IMSG_CTXT_BADDR_A 0x1088
344 #define SGE_FLM_CACHE_BADDR_A 0x108c
345 #define SGE_FLM_CFG_A 0x1090
346 
347 #define NOHDR_S    18
348 #define NOHDR_V(x) ((x) << NOHDR_S)
349 #define NOHDR_F    NOHDR_V(1U)
350 
351 #define HDRSTARTFLQ_S    11
352 #define HDRSTARTFLQ_M    0x7U
353 #define HDRSTARTFLQ_G(x) (((x) >> HDRSTARTFLQ_S) & HDRSTARTFLQ_M)
354 
355 #define SGE_INGRESS_RX_THRESHOLD_A 0x10a0
356 
357 #define THRESHOLD_0_S    24
358 #define THRESHOLD_0_M    0x3fU
359 #define THRESHOLD_0_V(x) ((x) << THRESHOLD_0_S)
360 #define THRESHOLD_0_G(x) (((x) >> THRESHOLD_0_S) & THRESHOLD_0_M)
361 
362 #define THRESHOLD_1_S    16
363 #define THRESHOLD_1_M    0x3fU
364 #define THRESHOLD_1_V(x) ((x) << THRESHOLD_1_S)
365 #define THRESHOLD_1_G(x) (((x) >> THRESHOLD_1_S) & THRESHOLD_1_M)
366 
367 #define THRESHOLD_2_S    8
368 #define THRESHOLD_2_M    0x3fU
369 #define THRESHOLD_2_V(x) ((x) << THRESHOLD_2_S)
370 #define THRESHOLD_2_G(x) (((x) >> THRESHOLD_2_S) & THRESHOLD_2_M)
371 
372 #define THRESHOLD_3_S    0
373 #define THRESHOLD_3_M    0x3fU
374 #define THRESHOLD_3_V(x) ((x) << THRESHOLD_3_S)
375 #define THRESHOLD_3_G(x) (((x) >> THRESHOLD_3_S) & THRESHOLD_3_M)
376 
377 #define SGE_CONM_CTRL_A 0x1094
378 
379 #define EGRTHRESHOLD_S    8
380 #define EGRTHRESHOLD_M    0x3fU
381 #define EGRTHRESHOLD_V(x) ((x) << EGRTHRESHOLD_S)
382 #define EGRTHRESHOLD_G(x) (((x) >> EGRTHRESHOLD_S) & EGRTHRESHOLD_M)
383 
384 #define EGRTHRESHOLDPACKING_S    14
385 #define EGRTHRESHOLDPACKING_M    0x3fU
386 #define EGRTHRESHOLDPACKING_V(x) ((x) << EGRTHRESHOLDPACKING_S)
387 #define EGRTHRESHOLDPACKING_G(x) \
388 	(((x) >> EGRTHRESHOLDPACKING_S) & EGRTHRESHOLDPACKING_M)
389 
390 #define T6_EGRTHRESHOLDPACKING_S    16
391 #define T6_EGRTHRESHOLDPACKING_M    0xffU
392 #define T6_EGRTHRESHOLDPACKING_G(x) \
393 	(((x) >> T6_EGRTHRESHOLDPACKING_S) & T6_EGRTHRESHOLDPACKING_M)
394 
395 #define SGE_TIMESTAMP_LO_A 0x1098
396 #define SGE_TIMESTAMP_HI_A 0x109c
397 
398 #define TSOP_S    28
399 #define TSOP_M    0x3U
400 #define TSOP_V(x) ((x) << TSOP_S)
401 #define TSOP_G(x) (((x) >> TSOP_S) & TSOP_M)
402 
403 #define TSVAL_S    0
404 #define TSVAL_M    0xfffffffU
405 #define TSVAL_V(x) ((x) << TSVAL_S)
406 #define TSVAL_G(x) (((x) >> TSVAL_S) & TSVAL_M)
407 
408 #define SGE_DBFIFO_STATUS_A 0x10a4
409 #define SGE_DBVFIFO_SIZE_A 0x113c
410 
411 #define HP_INT_THRESH_S    28
412 #define HP_INT_THRESH_M    0xfU
413 #define HP_INT_THRESH_V(x) ((x) << HP_INT_THRESH_S)
414 
415 #define LP_INT_THRESH_S    12
416 #define LP_INT_THRESH_M    0xfU
417 #define LP_INT_THRESH_V(x) ((x) << LP_INT_THRESH_S)
418 
419 #define SGE_DOORBELL_CONTROL_A 0x10a8
420 
421 #define NOCOALESCE_S    26
422 #define NOCOALESCE_V(x) ((x) << NOCOALESCE_S)
423 #define NOCOALESCE_F    NOCOALESCE_V(1U)
424 
425 #define ENABLE_DROP_S    13
426 #define ENABLE_DROP_V(x) ((x) << ENABLE_DROP_S)
427 #define ENABLE_DROP_F    ENABLE_DROP_V(1U)
428 
429 #define SGE_TIMER_VALUE_0_AND_1_A 0x10b8
430 
431 #define TIMERVALUE0_S    16
432 #define TIMERVALUE0_M    0xffffU
433 #define TIMERVALUE0_V(x) ((x) << TIMERVALUE0_S)
434 #define TIMERVALUE0_G(x) (((x) >> TIMERVALUE0_S) & TIMERVALUE0_M)
435 
436 #define TIMERVALUE1_S    0
437 #define TIMERVALUE1_M    0xffffU
438 #define TIMERVALUE1_V(x) ((x) << TIMERVALUE1_S)
439 #define TIMERVALUE1_G(x) (((x) >> TIMERVALUE1_S) & TIMERVALUE1_M)
440 
441 #define SGE_TIMER_VALUE_2_AND_3_A 0x10bc
442 
443 #define TIMERVALUE2_S    16
444 #define TIMERVALUE2_M    0xffffU
445 #define TIMERVALUE2_V(x) ((x) << TIMERVALUE2_S)
446 #define TIMERVALUE2_G(x) (((x) >> TIMERVALUE2_S) & TIMERVALUE2_M)
447 
448 #define TIMERVALUE3_S    0
449 #define TIMERVALUE3_M    0xffffU
450 #define TIMERVALUE3_V(x) ((x) << TIMERVALUE3_S)
451 #define TIMERVALUE3_G(x) (((x) >> TIMERVALUE3_S) & TIMERVALUE3_M)
452 
453 #define SGE_TIMER_VALUE_4_AND_5_A 0x10c0
454 
455 #define TIMERVALUE4_S    16
456 #define TIMERVALUE4_M    0xffffU
457 #define TIMERVALUE4_V(x) ((x) << TIMERVALUE4_S)
458 #define TIMERVALUE4_G(x) (((x) >> TIMERVALUE4_S) & TIMERVALUE4_M)
459 
460 #define TIMERVALUE5_S    0
461 #define TIMERVALUE5_M    0xffffU
462 #define TIMERVALUE5_V(x) ((x) << TIMERVALUE5_S)
463 #define TIMERVALUE5_G(x) (((x) >> TIMERVALUE5_S) & TIMERVALUE5_M)
464 
465 #define SGE_DEBUG_INDEX_A 0x10cc
466 #define SGE_DEBUG_DATA_HIGH_A 0x10d0
467 #define SGE_DEBUG_DATA_LOW_A 0x10d4
468 
469 #define SGE_DEBUG_DATA_LOW_INDEX_2_A	0x12c8
470 #define SGE_DEBUG_DATA_LOW_INDEX_3_A	0x12cc
471 #define SGE_DEBUG_DATA_HIGH_INDEX_10_A	0x12a8
472 
473 #define SGE_INGRESS_QUEUES_PER_PAGE_PF_A 0x10f4
474 #define SGE_INGRESS_QUEUES_PER_PAGE_VF_A 0x10f8
475 
476 #define SGE_ERROR_STATS_A 0x1100
477 
478 #define UNCAPTURED_ERROR_S    18
479 #define UNCAPTURED_ERROR_V(x) ((x) << UNCAPTURED_ERROR_S)
480 #define UNCAPTURED_ERROR_F    UNCAPTURED_ERROR_V(1U)
481 
482 #define ERROR_QID_VALID_S    17
483 #define ERROR_QID_VALID_V(x) ((x) << ERROR_QID_VALID_S)
484 #define ERROR_QID_VALID_F    ERROR_QID_VALID_V(1U)
485 
486 #define ERROR_QID_S    0
487 #define ERROR_QID_M    0x1ffffU
488 #define ERROR_QID_G(x) (((x) >> ERROR_QID_S) & ERROR_QID_M)
489 
490 #define HP_INT_THRESH_S    28
491 #define HP_INT_THRESH_M    0xfU
492 #define HP_INT_THRESH_V(x) ((x) << HP_INT_THRESH_S)
493 
494 #define HP_COUNT_S    16
495 #define HP_COUNT_M    0x7ffU
496 #define HP_COUNT_G(x) (((x) >> HP_COUNT_S) & HP_COUNT_M)
497 
498 #define LP_INT_THRESH_S    12
499 #define LP_INT_THRESH_M    0xfU
500 #define LP_INT_THRESH_V(x) ((x) << LP_INT_THRESH_S)
501 
502 #define LP_COUNT_S    0
503 #define LP_COUNT_M    0x7ffU
504 #define LP_COUNT_G(x) (((x) >> LP_COUNT_S) & LP_COUNT_M)
505 
506 #define LP_INT_THRESH_T5_S    18
507 #define LP_INT_THRESH_T5_M    0xfffU
508 #define LP_INT_THRESH_T5_V(x) ((x) << LP_INT_THRESH_T5_S)
509 
510 #define LP_COUNT_T5_S    0
511 #define LP_COUNT_T5_M    0x3ffffU
512 #define LP_COUNT_T5_G(x) (((x) >> LP_COUNT_T5_S) & LP_COUNT_T5_M)
513 
514 #define SGE_DOORBELL_CONTROL_A 0x10a8
515 
516 #define SGE_STAT_TOTAL_A	0x10e4
517 #define SGE_STAT_MATCH_A	0x10e8
518 #define SGE_STAT_CFG_A		0x10ec
519 
520 #define STATMODE_S    2
521 #define STATMODE_V(x) ((x) << STATMODE_S)
522 
523 #define STATSOURCE_T5_S    9
524 #define STATSOURCE_T5_M    0xfU
525 #define STATSOURCE_T5_V(x) ((x) << STATSOURCE_T5_S)
526 #define STATSOURCE_T5_G(x) (((x) >> STATSOURCE_T5_S) & STATSOURCE_T5_M)
527 
528 #define T6_STATMODE_S    0
529 #define T6_STATMODE_V(x) ((x) << T6_STATMODE_S)
530 
531 #define SGE_DBFIFO_STATUS2_A 0x1118
532 
533 #define HP_INT_THRESH_T5_S    10
534 #define HP_INT_THRESH_T5_M    0xfU
535 #define HP_INT_THRESH_T5_V(x) ((x) << HP_INT_THRESH_T5_S)
536 
537 #define HP_COUNT_T5_S    0
538 #define HP_COUNT_T5_M    0x3ffU
539 #define HP_COUNT_T5_G(x) (((x) >> HP_COUNT_T5_S) & HP_COUNT_T5_M)
540 
541 #define ENABLE_DROP_S    13
542 #define ENABLE_DROP_V(x) ((x) << ENABLE_DROP_S)
543 #define ENABLE_DROP_F    ENABLE_DROP_V(1U)
544 
545 #define DROPPED_DB_S    0
546 #define DROPPED_DB_V(x) ((x) << DROPPED_DB_S)
547 #define DROPPED_DB_F    DROPPED_DB_V(1U)
548 
549 #define SGE_CTXT_CMD_A 0x11fc
550 #define SGE_DBQ_CTXT_BADDR_A 0x1084
551 
552 /* registers for module PCIE */
553 #define PCIE_PF_CFG_A	0x40
554 
555 #define AIVEC_S    4
556 #define AIVEC_M    0x3ffU
557 #define AIVEC_V(x) ((x) << AIVEC_S)
558 
559 #define PCIE_PF_CLI_A	0x44
560 #define PCIE_INT_CAUSE_A	0x3004
561 
562 #define UNXSPLCPLERR_S    29
563 #define UNXSPLCPLERR_V(x) ((x) << UNXSPLCPLERR_S)
564 #define UNXSPLCPLERR_F    UNXSPLCPLERR_V(1U)
565 
566 #define PCIEPINT_S    28
567 #define PCIEPINT_V(x) ((x) << PCIEPINT_S)
568 #define PCIEPINT_F    PCIEPINT_V(1U)
569 
570 #define PCIESINT_S    27
571 #define PCIESINT_V(x) ((x) << PCIESINT_S)
572 #define PCIESINT_F    PCIESINT_V(1U)
573 
574 #define RPLPERR_S    26
575 #define RPLPERR_V(x) ((x) << RPLPERR_S)
576 #define RPLPERR_F    RPLPERR_V(1U)
577 
578 #define RXWRPERR_S    25
579 #define RXWRPERR_V(x) ((x) << RXWRPERR_S)
580 #define RXWRPERR_F    RXWRPERR_V(1U)
581 
582 #define RXCPLPERR_S    24
583 #define RXCPLPERR_V(x) ((x) << RXCPLPERR_S)
584 #define RXCPLPERR_F    RXCPLPERR_V(1U)
585 
586 #define PIOTAGPERR_S    23
587 #define PIOTAGPERR_V(x) ((x) << PIOTAGPERR_S)
588 #define PIOTAGPERR_F    PIOTAGPERR_V(1U)
589 
590 #define MATAGPERR_S    22
591 #define MATAGPERR_V(x) ((x) << MATAGPERR_S)
592 #define MATAGPERR_F    MATAGPERR_V(1U)
593 
594 #define INTXCLRPERR_S    21
595 #define INTXCLRPERR_V(x) ((x) << INTXCLRPERR_S)
596 #define INTXCLRPERR_F    INTXCLRPERR_V(1U)
597 
598 #define FIDPERR_S    20
599 #define FIDPERR_V(x) ((x) << FIDPERR_S)
600 #define FIDPERR_F    FIDPERR_V(1U)
601 
602 #define CFGSNPPERR_S    19
603 #define CFGSNPPERR_V(x) ((x) << CFGSNPPERR_S)
604 #define CFGSNPPERR_F    CFGSNPPERR_V(1U)
605 
606 #define HRSPPERR_S    18
607 #define HRSPPERR_V(x) ((x) << HRSPPERR_S)
608 #define HRSPPERR_F    HRSPPERR_V(1U)
609 
610 #define HREQPERR_S    17
611 #define HREQPERR_V(x) ((x) << HREQPERR_S)
612 #define HREQPERR_F    HREQPERR_V(1U)
613 
614 #define HCNTPERR_S    16
615 #define HCNTPERR_V(x) ((x) << HCNTPERR_S)
616 #define HCNTPERR_F    HCNTPERR_V(1U)
617 
618 #define DRSPPERR_S    15
619 #define DRSPPERR_V(x) ((x) << DRSPPERR_S)
620 #define DRSPPERR_F    DRSPPERR_V(1U)
621 
622 #define DREQPERR_S    14
623 #define DREQPERR_V(x) ((x) << DREQPERR_S)
624 #define DREQPERR_F    DREQPERR_V(1U)
625 
626 #define DCNTPERR_S    13
627 #define DCNTPERR_V(x) ((x) << DCNTPERR_S)
628 #define DCNTPERR_F    DCNTPERR_V(1U)
629 
630 #define CRSPPERR_S    12
631 #define CRSPPERR_V(x) ((x) << CRSPPERR_S)
632 #define CRSPPERR_F    CRSPPERR_V(1U)
633 
634 #define CREQPERR_S    11
635 #define CREQPERR_V(x) ((x) << CREQPERR_S)
636 #define CREQPERR_F    CREQPERR_V(1U)
637 
638 #define CCNTPERR_S    10
639 #define CCNTPERR_V(x) ((x) << CCNTPERR_S)
640 #define CCNTPERR_F    CCNTPERR_V(1U)
641 
642 #define TARTAGPERR_S    9
643 #define TARTAGPERR_V(x) ((x) << TARTAGPERR_S)
644 #define TARTAGPERR_F    TARTAGPERR_V(1U)
645 
646 #define PIOREQPERR_S    8
647 #define PIOREQPERR_V(x) ((x) << PIOREQPERR_S)
648 #define PIOREQPERR_F    PIOREQPERR_V(1U)
649 
650 #define PIOCPLPERR_S    7
651 #define PIOCPLPERR_V(x) ((x) << PIOCPLPERR_S)
652 #define PIOCPLPERR_F    PIOCPLPERR_V(1U)
653 
654 #define MSIXDIPERR_S    6
655 #define MSIXDIPERR_V(x) ((x) << MSIXDIPERR_S)
656 #define MSIXDIPERR_F    MSIXDIPERR_V(1U)
657 
658 #define MSIXDATAPERR_S    5
659 #define MSIXDATAPERR_V(x) ((x) << MSIXDATAPERR_S)
660 #define MSIXDATAPERR_F    MSIXDATAPERR_V(1U)
661 
662 #define MSIXADDRHPERR_S    4
663 #define MSIXADDRHPERR_V(x) ((x) << MSIXADDRHPERR_S)
664 #define MSIXADDRHPERR_F    MSIXADDRHPERR_V(1U)
665 
666 #define MSIXADDRLPERR_S    3
667 #define MSIXADDRLPERR_V(x) ((x) << MSIXADDRLPERR_S)
668 #define MSIXADDRLPERR_F    MSIXADDRLPERR_V(1U)
669 
670 #define MSIDATAPERR_S    2
671 #define MSIDATAPERR_V(x) ((x) << MSIDATAPERR_S)
672 #define MSIDATAPERR_F    MSIDATAPERR_V(1U)
673 
674 #define MSIADDRHPERR_S    1
675 #define MSIADDRHPERR_V(x) ((x) << MSIADDRHPERR_S)
676 #define MSIADDRHPERR_F    MSIADDRHPERR_V(1U)
677 
678 #define MSIADDRLPERR_S    0
679 #define MSIADDRLPERR_V(x) ((x) << MSIADDRLPERR_S)
680 #define MSIADDRLPERR_F    MSIADDRLPERR_V(1U)
681 
682 #define READRSPERR_S    29
683 #define READRSPERR_V(x) ((x) << READRSPERR_S)
684 #define READRSPERR_F    READRSPERR_V(1U)
685 
686 #define TRGT1GRPPERR_S    28
687 #define TRGT1GRPPERR_V(x) ((x) << TRGT1GRPPERR_S)
688 #define TRGT1GRPPERR_F    TRGT1GRPPERR_V(1U)
689 
690 #define IPSOTPERR_S    27
691 #define IPSOTPERR_V(x) ((x) << IPSOTPERR_S)
692 #define IPSOTPERR_F    IPSOTPERR_V(1U)
693 
694 #define IPRETRYPERR_S    26
695 #define IPRETRYPERR_V(x) ((x) << IPRETRYPERR_S)
696 #define IPRETRYPERR_F    IPRETRYPERR_V(1U)
697 
698 #define IPRXDATAGRPPERR_S    25
699 #define IPRXDATAGRPPERR_V(x) ((x) << IPRXDATAGRPPERR_S)
700 #define IPRXDATAGRPPERR_F    IPRXDATAGRPPERR_V(1U)
701 
702 #define IPRXHDRGRPPERR_S    24
703 #define IPRXHDRGRPPERR_V(x) ((x) << IPRXHDRGRPPERR_S)
704 #define IPRXHDRGRPPERR_F    IPRXHDRGRPPERR_V(1U)
705 
706 #define MAGRPPERR_S    22
707 #define MAGRPPERR_V(x) ((x) << MAGRPPERR_S)
708 #define MAGRPPERR_F    MAGRPPERR_V(1U)
709 
710 #define VFIDPERR_S    21
711 #define VFIDPERR_V(x) ((x) << VFIDPERR_S)
712 #define VFIDPERR_F    VFIDPERR_V(1U)
713 
714 #define HREQWRPERR_S    16
715 #define HREQWRPERR_V(x) ((x) << HREQWRPERR_S)
716 #define HREQWRPERR_F    HREQWRPERR_V(1U)
717 
718 #define DREQWRPERR_S    13
719 #define DREQWRPERR_V(x) ((x) << DREQWRPERR_S)
720 #define DREQWRPERR_F    DREQWRPERR_V(1U)
721 
722 #define CREQRDPERR_S    11
723 #define CREQRDPERR_V(x) ((x) << CREQRDPERR_S)
724 #define CREQRDPERR_F    CREQRDPERR_V(1U)
725 
726 #define MSTTAGQPERR_S    10
727 #define MSTTAGQPERR_V(x) ((x) << MSTTAGQPERR_S)
728 #define MSTTAGQPERR_F    MSTTAGQPERR_V(1U)
729 
730 #define PIOREQGRPPERR_S    8
731 #define PIOREQGRPPERR_V(x) ((x) << PIOREQGRPPERR_S)
732 #define PIOREQGRPPERR_F    PIOREQGRPPERR_V(1U)
733 
734 #define PIOCPLGRPPERR_S    7
735 #define PIOCPLGRPPERR_V(x) ((x) << PIOCPLGRPPERR_S)
736 #define PIOCPLGRPPERR_F    PIOCPLGRPPERR_V(1U)
737 
738 #define MSIXSTIPERR_S    2
739 #define MSIXSTIPERR_V(x) ((x) << MSIXSTIPERR_S)
740 #define MSIXSTIPERR_F    MSIXSTIPERR_V(1U)
741 
742 #define MSTTIMEOUTPERR_S    1
743 #define MSTTIMEOUTPERR_V(x) ((x) << MSTTIMEOUTPERR_S)
744 #define MSTTIMEOUTPERR_F    MSTTIMEOUTPERR_V(1U)
745 
746 #define MSTGRPPERR_S    0
747 #define MSTGRPPERR_V(x) ((x) << MSTGRPPERR_S)
748 #define MSTGRPPERR_F    MSTGRPPERR_V(1U)
749 
750 #define PCIE_NONFAT_ERR_A	0x3010
751 #define PCIE_CFG_SPACE_REQ_A	0x3060
752 #define PCIE_CFG_SPACE_DATA_A	0x3064
753 #define PCIE_MEM_ACCESS_BASE_WIN_A 0x3068
754 
755 #define PCIEOFST_S    10
756 #define PCIEOFST_M    0x3fffffU
757 #define PCIEOFST_G(x) (((x) >> PCIEOFST_S) & PCIEOFST_M)
758 
759 #define BIR_S    8
760 #define BIR_M    0x3U
761 #define BIR_V(x) ((x) << BIR_S)
762 #define BIR_G(x) (((x) >> BIR_S) & BIR_M)
763 
764 #define WINDOW_S    0
765 #define WINDOW_M    0xffU
766 #define WINDOW_V(x) ((x) << WINDOW_S)
767 #define WINDOW_G(x) (((x) >> WINDOW_S) & WINDOW_M)
768 
769 #define PCIE_MEM_ACCESS_OFFSET_A 0x306c
770 
771 #define ENABLE_S    30
772 #define ENABLE_V(x) ((x) << ENABLE_S)
773 #define ENABLE_F    ENABLE_V(1U)
774 
775 #define LOCALCFG_S    28
776 #define LOCALCFG_V(x) ((x) << LOCALCFG_S)
777 #define LOCALCFG_F    LOCALCFG_V(1U)
778 
779 #define FUNCTION_S    12
780 #define FUNCTION_V(x) ((x) << FUNCTION_S)
781 
782 #define REGISTER_S    0
783 #define REGISTER_V(x) ((x) << REGISTER_S)
784 
785 #define T6_ENABLE_S    31
786 #define T6_ENABLE_V(x) ((x) << T6_ENABLE_S)
787 #define T6_ENABLE_F    T6_ENABLE_V(1U)
788 
789 #define PFNUM_S    0
790 #define PFNUM_V(x) ((x) << PFNUM_S)
791 
792 #define PCIE_FW_A 0x30b8
793 #define PCIE_FW_PF_A 0x30bc
794 
795 #define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A 0x5908
796 
797 #define RNPP_S    31
798 #define RNPP_V(x) ((x) << RNPP_S)
799 #define RNPP_F    RNPP_V(1U)
800 
801 #define RPCP_S    29
802 #define RPCP_V(x) ((x) << RPCP_S)
803 #define RPCP_F    RPCP_V(1U)
804 
805 #define RCIP_S    27
806 #define RCIP_V(x) ((x) << RCIP_S)
807 #define RCIP_F    RCIP_V(1U)
808 
809 #define RCCP_S    26
810 #define RCCP_V(x) ((x) << RCCP_S)
811 #define RCCP_F    RCCP_V(1U)
812 
813 #define RFTP_S    23
814 #define RFTP_V(x) ((x) << RFTP_S)
815 #define RFTP_F    RFTP_V(1U)
816 
817 #define PTRP_S    20
818 #define PTRP_V(x) ((x) << PTRP_S)
819 #define PTRP_F    PTRP_V(1U)
820 
821 #define PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A 0x59a4
822 
823 #define TPCP_S    30
824 #define TPCP_V(x) ((x) << TPCP_S)
825 #define TPCP_F    TPCP_V(1U)
826 
827 #define TNPP_S    29
828 #define TNPP_V(x) ((x) << TNPP_S)
829 #define TNPP_F    TNPP_V(1U)
830 
831 #define TFTP_S    28
832 #define TFTP_V(x) ((x) << TFTP_S)
833 #define TFTP_F    TFTP_V(1U)
834 
835 #define TCAP_S    27
836 #define TCAP_V(x) ((x) << TCAP_S)
837 #define TCAP_F    TCAP_V(1U)
838 
839 #define TCIP_S    26
840 #define TCIP_V(x) ((x) << TCIP_S)
841 #define TCIP_F    TCIP_V(1U)
842 
843 #define RCAP_S    25
844 #define RCAP_V(x) ((x) << RCAP_S)
845 #define RCAP_F    RCAP_V(1U)
846 
847 #define PLUP_S    23
848 #define PLUP_V(x) ((x) << PLUP_S)
849 #define PLUP_F    PLUP_V(1U)
850 
851 #define PLDN_S    22
852 #define PLDN_V(x) ((x) << PLDN_S)
853 #define PLDN_F    PLDN_V(1U)
854 
855 #define OTDD_S    21
856 #define OTDD_V(x) ((x) << OTDD_S)
857 #define OTDD_F    OTDD_V(1U)
858 
859 #define GTRP_S    20
860 #define GTRP_V(x) ((x) << GTRP_S)
861 #define GTRP_F    GTRP_V(1U)
862 
863 #define RDPE_S    18
864 #define RDPE_V(x) ((x) << RDPE_S)
865 #define RDPE_F    RDPE_V(1U)
866 
867 #define TDCE_S    17
868 #define TDCE_V(x) ((x) << TDCE_S)
869 #define TDCE_F    TDCE_V(1U)
870 
871 #define TDUE_S    16
872 #define TDUE_V(x) ((x) << TDUE_S)
873 #define TDUE_F    TDUE_V(1U)
874 
875 /* registers for module MC */
876 #define MC_INT_CAUSE_A		0x7518
877 #define MC_P_INT_CAUSE_A	0x41318
878 
879 #define ECC_UE_INT_CAUSE_S    2
880 #define ECC_UE_INT_CAUSE_V(x) ((x) << ECC_UE_INT_CAUSE_S)
881 #define ECC_UE_INT_CAUSE_F    ECC_UE_INT_CAUSE_V(1U)
882 
883 #define ECC_CE_INT_CAUSE_S    1
884 #define ECC_CE_INT_CAUSE_V(x) ((x) << ECC_CE_INT_CAUSE_S)
885 #define ECC_CE_INT_CAUSE_F    ECC_CE_INT_CAUSE_V(1U)
886 
887 #define PERR_INT_CAUSE_S    0
888 #define PERR_INT_CAUSE_V(x) ((x) << PERR_INT_CAUSE_S)
889 #define PERR_INT_CAUSE_F    PERR_INT_CAUSE_V(1U)
890 
891 #define DBG_GPIO_EN_A		0x6010
892 #define XGMAC_PORT_CFG_A	0x1000
893 #define MAC_PORT_CFG_A		0x800
894 
895 #define SIGNAL_DET_S    14
896 #define SIGNAL_DET_V(x) ((x) << SIGNAL_DET_S)
897 #define SIGNAL_DET_F    SIGNAL_DET_V(1U)
898 
899 #define MC_ECC_STATUS_A		0x751c
900 #define MC_P_ECC_STATUS_A	0x4131c
901 
902 #define ECC_CECNT_S    16
903 #define ECC_CECNT_M    0xffffU
904 #define ECC_CECNT_V(x) ((x) << ECC_CECNT_S)
905 #define ECC_CECNT_G(x) (((x) >> ECC_CECNT_S) & ECC_CECNT_M)
906 
907 #define ECC_UECNT_S    0
908 #define ECC_UECNT_M    0xffffU
909 #define ECC_UECNT_V(x) ((x) << ECC_UECNT_S)
910 #define ECC_UECNT_G(x) (((x) >> ECC_UECNT_S) & ECC_UECNT_M)
911 
912 #define MC_BIST_CMD_A 0x7600
913 
914 #define START_BIST_S    31
915 #define START_BIST_V(x) ((x) << START_BIST_S)
916 #define START_BIST_F    START_BIST_V(1U)
917 
918 #define BIST_CMD_GAP_S    8
919 #define BIST_CMD_GAP_V(x) ((x) << BIST_CMD_GAP_S)
920 
921 #define BIST_OPCODE_S    0
922 #define BIST_OPCODE_V(x) ((x) << BIST_OPCODE_S)
923 
924 #define MC_BIST_CMD_ADDR_A 0x7604
925 #define MC_BIST_CMD_LEN_A 0x7608
926 #define MC_BIST_DATA_PATTERN_A 0x760c
927 
928 #define MC_BIST_STATUS_RDATA_A 0x7688
929 
930 /* registers for module MA */
931 #define MA_EDRAM0_BAR_A 0x77c0
932 
933 #define EDRAM0_BASE_S    16
934 #define EDRAM0_BASE_M    0xfffU
935 #define EDRAM0_BASE_G(x) (((x) >> EDRAM0_BASE_S) & EDRAM0_BASE_M)
936 
937 #define EDRAM0_SIZE_S    0
938 #define EDRAM0_SIZE_M    0xfffU
939 #define EDRAM0_SIZE_V(x) ((x) << EDRAM0_SIZE_S)
940 #define EDRAM0_SIZE_G(x) (((x) >> EDRAM0_SIZE_S) & EDRAM0_SIZE_M)
941 
942 #define MA_EDRAM1_BAR_A 0x77c4
943 
944 #define EDRAM1_BASE_S    16
945 #define EDRAM1_BASE_M    0xfffU
946 #define EDRAM1_BASE_G(x) (((x) >> EDRAM1_BASE_S) & EDRAM1_BASE_M)
947 
948 #define EDRAM1_SIZE_S    0
949 #define EDRAM1_SIZE_M    0xfffU
950 #define EDRAM1_SIZE_V(x) ((x) << EDRAM1_SIZE_S)
951 #define EDRAM1_SIZE_G(x) (((x) >> EDRAM1_SIZE_S) & EDRAM1_SIZE_M)
952 
953 #define MA_EXT_MEMORY_BAR_A 0x77c8
954 
955 #define EXT_MEM_BASE_S    16
956 #define EXT_MEM_BASE_M    0xfffU
957 #define EXT_MEM_BASE_V(x) ((x) << EXT_MEM_BASE_S)
958 #define EXT_MEM_BASE_G(x) (((x) >> EXT_MEM_BASE_S) & EXT_MEM_BASE_M)
959 
960 #define EXT_MEM_SIZE_S    0
961 #define EXT_MEM_SIZE_M    0xfffU
962 #define EXT_MEM_SIZE_V(x) ((x) << EXT_MEM_SIZE_S)
963 #define EXT_MEM_SIZE_G(x) (((x) >> EXT_MEM_SIZE_S) & EXT_MEM_SIZE_M)
964 
965 #define MA_EXT_MEMORY1_BAR_A 0x7808
966 
967 #define HMA_MUX_S    5
968 #define HMA_MUX_V(x) ((x) << HMA_MUX_S)
969 #define HMA_MUX_F    HMA_MUX_V(1U)
970 
971 #define EXT_MEM1_BASE_S    16
972 #define EXT_MEM1_BASE_M    0xfffU
973 #define EXT_MEM1_BASE_G(x) (((x) >> EXT_MEM1_BASE_S) & EXT_MEM1_BASE_M)
974 
975 #define EXT_MEM1_SIZE_S    0
976 #define EXT_MEM1_SIZE_M    0xfffU
977 #define EXT_MEM1_SIZE_V(x) ((x) << EXT_MEM1_SIZE_S)
978 #define EXT_MEM1_SIZE_G(x) (((x) >> EXT_MEM1_SIZE_S) & EXT_MEM1_SIZE_M)
979 
980 #define MA_EXT_MEMORY0_BAR_A 0x77c8
981 
982 #define EXT_MEM0_BASE_S    16
983 #define EXT_MEM0_BASE_M    0xfffU
984 #define EXT_MEM0_BASE_G(x) (((x) >> EXT_MEM0_BASE_S) & EXT_MEM0_BASE_M)
985 
986 #define EXT_MEM0_SIZE_S    0
987 #define EXT_MEM0_SIZE_M    0xfffU
988 #define EXT_MEM0_SIZE_V(x) ((x) << EXT_MEM0_SIZE_S)
989 #define EXT_MEM0_SIZE_G(x) (((x) >> EXT_MEM0_SIZE_S) & EXT_MEM0_SIZE_M)
990 
991 #define MA_TARGET_MEM_ENABLE_A 0x77d8
992 
993 #define EXT_MEM_ENABLE_S    2
994 #define EXT_MEM_ENABLE_V(x) ((x) << EXT_MEM_ENABLE_S)
995 #define EXT_MEM_ENABLE_F    EXT_MEM_ENABLE_V(1U)
996 
997 #define EDRAM1_ENABLE_S    1
998 #define EDRAM1_ENABLE_V(x) ((x) << EDRAM1_ENABLE_S)
999 #define EDRAM1_ENABLE_F    EDRAM1_ENABLE_V(1U)
1000 
1001 #define EDRAM0_ENABLE_S    0
1002 #define EDRAM0_ENABLE_V(x) ((x) << EDRAM0_ENABLE_S)
1003 #define EDRAM0_ENABLE_F    EDRAM0_ENABLE_V(1U)
1004 
1005 #define EXT_MEM1_ENABLE_S    4
1006 #define EXT_MEM1_ENABLE_V(x) ((x) << EXT_MEM1_ENABLE_S)
1007 #define EXT_MEM1_ENABLE_F    EXT_MEM1_ENABLE_V(1U)
1008 
1009 #define EXT_MEM0_ENABLE_S    2
1010 #define EXT_MEM0_ENABLE_V(x) ((x) << EXT_MEM0_ENABLE_S)
1011 #define EXT_MEM0_ENABLE_F    EXT_MEM0_ENABLE_V(1U)
1012 
1013 #define MA_INT_CAUSE_A	0x77e0
1014 
1015 #define MEM_PERR_INT_CAUSE_S    1
1016 #define MEM_PERR_INT_CAUSE_V(x) ((x) << MEM_PERR_INT_CAUSE_S)
1017 #define MEM_PERR_INT_CAUSE_F    MEM_PERR_INT_CAUSE_V(1U)
1018 
1019 #define MEM_WRAP_INT_CAUSE_S    0
1020 #define MEM_WRAP_INT_CAUSE_V(x) ((x) << MEM_WRAP_INT_CAUSE_S)
1021 #define MEM_WRAP_INT_CAUSE_F    MEM_WRAP_INT_CAUSE_V(1U)
1022 
1023 #define MA_INT_WRAP_STATUS_A	0x77e4
1024 
1025 #define MEM_WRAP_ADDRESS_S    4
1026 #define MEM_WRAP_ADDRESS_M    0xfffffffU
1027 #define MEM_WRAP_ADDRESS_G(x) (((x) >> MEM_WRAP_ADDRESS_S) & MEM_WRAP_ADDRESS_M)
1028 
1029 #define MEM_WRAP_CLIENT_NUM_S    0
1030 #define MEM_WRAP_CLIENT_NUM_M    0xfU
1031 #define MEM_WRAP_CLIENT_NUM_G(x) \
1032 	(((x) >> MEM_WRAP_CLIENT_NUM_S) & MEM_WRAP_CLIENT_NUM_M)
1033 
1034 #define MA_PARITY_ERROR_STATUS_A	0x77f4
1035 #define MA_PARITY_ERROR_STATUS1_A	0x77f4
1036 #define MA_PARITY_ERROR_STATUS2_A	0x7804
1037 
1038 /* registers for module EDC_0 */
1039 #define EDC_0_BASE_ADDR		0x7900
1040 
1041 #define EDC_BIST_CMD_A		0x7904
1042 #define EDC_BIST_CMD_ADDR_A	0x7908
1043 #define EDC_BIST_CMD_LEN_A	0x790c
1044 #define EDC_BIST_DATA_PATTERN_A 0x7910
1045 #define EDC_BIST_STATUS_RDATA_A	0x7928
1046 #define EDC_INT_CAUSE_A		0x7978
1047 
1048 #define ECC_UE_PAR_S    5
1049 #define ECC_UE_PAR_V(x) ((x) << ECC_UE_PAR_S)
1050 #define ECC_UE_PAR_F    ECC_UE_PAR_V(1U)
1051 
1052 #define ECC_CE_PAR_S    4
1053 #define ECC_CE_PAR_V(x) ((x) << ECC_CE_PAR_S)
1054 #define ECC_CE_PAR_F    ECC_CE_PAR_V(1U)
1055 
1056 #define PERR_PAR_CAUSE_S    3
1057 #define PERR_PAR_CAUSE_V(x) ((x) << PERR_PAR_CAUSE_S)
1058 #define PERR_PAR_CAUSE_F    PERR_PAR_CAUSE_V(1U)
1059 
1060 #define EDC_ECC_STATUS_A	0x797c
1061 
1062 /* registers for module EDC_1 */
1063 #define EDC_1_BASE_ADDR	0x7980
1064 
1065 /* registers for module CIM */
1066 #define CIM_BOOT_CFG_A 0x7b00
1067 #define CIM_SDRAM_BASE_ADDR_A 0x7b14
1068 #define CIM_SDRAM_ADDR_SIZE_A 0x7b18
1069 #define CIM_EXTMEM2_BASE_ADDR_A 0x7b1c
1070 #define CIM_EXTMEM2_ADDR_SIZE_A 0x7b20
1071 #define CIM_PF_MAILBOX_CTRL_SHADOW_COPY_A 0x290
1072 
1073 #define  BOOTADDR_M	0xffffff00U
1074 
1075 #define UPCRST_S    0
1076 #define UPCRST_V(x) ((x) << UPCRST_S)
1077 #define UPCRST_F    UPCRST_V(1U)
1078 
1079 #define CIM_PF_MAILBOX_DATA_A 0x240
1080 #define CIM_PF_MAILBOX_CTRL_A 0x280
1081 
1082 #define MBMSGVALID_S    3
1083 #define MBMSGVALID_V(x) ((x) << MBMSGVALID_S)
1084 #define MBMSGVALID_F    MBMSGVALID_V(1U)
1085 
1086 #define MBINTREQ_S    2
1087 #define MBINTREQ_V(x) ((x) << MBINTREQ_S)
1088 #define MBINTREQ_F    MBINTREQ_V(1U)
1089 
1090 #define MBOWNER_S    0
1091 #define MBOWNER_M    0x3U
1092 #define MBOWNER_V(x) ((x) << MBOWNER_S)
1093 #define MBOWNER_G(x) (((x) >> MBOWNER_S) & MBOWNER_M)
1094 
1095 #define CIM_PF_HOST_INT_ENABLE_A 0x288
1096 
1097 #define MBMSGRDYINTEN_S    19
1098 #define MBMSGRDYINTEN_V(x) ((x) << MBMSGRDYINTEN_S)
1099 #define MBMSGRDYINTEN_F    MBMSGRDYINTEN_V(1U)
1100 
1101 #define CIM_PF_HOST_INT_CAUSE_A 0x28c
1102 
1103 #define MBMSGRDYINT_S    19
1104 #define MBMSGRDYINT_V(x) ((x) << MBMSGRDYINT_S)
1105 #define MBMSGRDYINT_F    MBMSGRDYINT_V(1U)
1106 
1107 #define CIM_HOST_INT_CAUSE_A 0x7b2c
1108 
1109 #define TIEQOUTPARERRINT_S    20
1110 #define TIEQOUTPARERRINT_V(x) ((x) << TIEQOUTPARERRINT_S)
1111 #define TIEQOUTPARERRINT_F    TIEQOUTPARERRINT_V(1U)
1112 
1113 #define TIEQINPARERRINT_S    19
1114 #define TIEQINPARERRINT_V(x) ((x) << TIEQINPARERRINT_S)
1115 #define TIEQINPARERRINT_F    TIEQINPARERRINT_V(1U)
1116 
1117 #define TIMER0INT_S    2
1118 #define TIMER0INT_V(x) ((x) << TIMER0INT_S)
1119 #define TIMER0INT_F    TIMER0INT_V(1U)
1120 
1121 #define PREFDROPINT_S    1
1122 #define PREFDROPINT_V(x) ((x) << PREFDROPINT_S)
1123 #define PREFDROPINT_F    PREFDROPINT_V(1U)
1124 
1125 #define UPACCNONZERO_S    0
1126 #define UPACCNONZERO_V(x) ((x) << UPACCNONZERO_S)
1127 #define UPACCNONZERO_F    UPACCNONZERO_V(1U)
1128 
1129 #define MBHOSTPARERR_S    18
1130 #define MBHOSTPARERR_V(x) ((x) << MBHOSTPARERR_S)
1131 #define MBHOSTPARERR_F    MBHOSTPARERR_V(1U)
1132 
1133 #define MBUPPARERR_S    17
1134 #define MBUPPARERR_V(x) ((x) << MBUPPARERR_S)
1135 #define MBUPPARERR_F    MBUPPARERR_V(1U)
1136 
1137 #define IBQTP0PARERR_S    16
1138 #define IBQTP0PARERR_V(x) ((x) << IBQTP0PARERR_S)
1139 #define IBQTP0PARERR_F    IBQTP0PARERR_V(1U)
1140 
1141 #define IBQTP1PARERR_S    15
1142 #define IBQTP1PARERR_V(x) ((x) << IBQTP1PARERR_S)
1143 #define IBQTP1PARERR_F    IBQTP1PARERR_V(1U)
1144 
1145 #define IBQULPPARERR_S    14
1146 #define IBQULPPARERR_V(x) ((x) << IBQULPPARERR_S)
1147 #define IBQULPPARERR_F    IBQULPPARERR_V(1U)
1148 
1149 #define IBQSGELOPARERR_S    13
1150 #define IBQSGELOPARERR_V(x) ((x) << IBQSGELOPARERR_S)
1151 #define IBQSGELOPARERR_F    IBQSGELOPARERR_V(1U)
1152 
1153 #define IBQSGEHIPARERR_S    12
1154 #define IBQSGEHIPARERR_V(x) ((x) << IBQSGEHIPARERR_S)
1155 #define IBQSGEHIPARERR_F    IBQSGEHIPARERR_V(1U)
1156 
1157 #define IBQNCSIPARERR_S    11
1158 #define IBQNCSIPARERR_V(x) ((x) << IBQNCSIPARERR_S)
1159 #define IBQNCSIPARERR_F    IBQNCSIPARERR_V(1U)
1160 
1161 #define OBQULP0PARERR_S    10
1162 #define OBQULP0PARERR_V(x) ((x) << OBQULP0PARERR_S)
1163 #define OBQULP0PARERR_F    OBQULP0PARERR_V(1U)
1164 
1165 #define OBQULP1PARERR_S    9
1166 #define OBQULP1PARERR_V(x) ((x) << OBQULP1PARERR_S)
1167 #define OBQULP1PARERR_F    OBQULP1PARERR_V(1U)
1168 
1169 #define OBQULP2PARERR_S    8
1170 #define OBQULP2PARERR_V(x) ((x) << OBQULP2PARERR_S)
1171 #define OBQULP2PARERR_F    OBQULP2PARERR_V(1U)
1172 
1173 #define OBQULP3PARERR_S    7
1174 #define OBQULP3PARERR_V(x) ((x) << OBQULP3PARERR_S)
1175 #define OBQULP3PARERR_F    OBQULP3PARERR_V(1U)
1176 
1177 #define OBQSGEPARERR_S    6
1178 #define OBQSGEPARERR_V(x) ((x) << OBQSGEPARERR_S)
1179 #define OBQSGEPARERR_F    OBQSGEPARERR_V(1U)
1180 
1181 #define OBQNCSIPARERR_S    5
1182 #define OBQNCSIPARERR_V(x) ((x) << OBQNCSIPARERR_S)
1183 #define OBQNCSIPARERR_F    OBQNCSIPARERR_V(1U)
1184 
1185 #define CIM_HOST_UPACC_INT_CAUSE_A 0x7b34
1186 
1187 #define EEPROMWRINT_S    30
1188 #define EEPROMWRINT_V(x) ((x) << EEPROMWRINT_S)
1189 #define EEPROMWRINT_F    EEPROMWRINT_V(1U)
1190 
1191 #define TIMEOUTMAINT_S    29
1192 #define TIMEOUTMAINT_V(x) ((x) << TIMEOUTMAINT_S)
1193 #define TIMEOUTMAINT_F    TIMEOUTMAINT_V(1U)
1194 
1195 #define TIMEOUTINT_S    28
1196 #define TIMEOUTINT_V(x) ((x) << TIMEOUTINT_S)
1197 #define TIMEOUTINT_F    TIMEOUTINT_V(1U)
1198 
1199 #define RSPOVRLOOKUPINT_S    27
1200 #define RSPOVRLOOKUPINT_V(x) ((x) << RSPOVRLOOKUPINT_S)
1201 #define RSPOVRLOOKUPINT_F    RSPOVRLOOKUPINT_V(1U)
1202 
1203 #define REQOVRLOOKUPINT_S    26
1204 #define REQOVRLOOKUPINT_V(x) ((x) << REQOVRLOOKUPINT_S)
1205 #define REQOVRLOOKUPINT_F    REQOVRLOOKUPINT_V(1U)
1206 
1207 #define BLKWRPLINT_S    25
1208 #define BLKWRPLINT_V(x) ((x) << BLKWRPLINT_S)
1209 #define BLKWRPLINT_F    BLKWRPLINT_V(1U)
1210 
1211 #define BLKRDPLINT_S    24
1212 #define BLKRDPLINT_V(x) ((x) << BLKRDPLINT_S)
1213 #define BLKRDPLINT_F    BLKRDPLINT_V(1U)
1214 
1215 #define SGLWRPLINT_S    23
1216 #define SGLWRPLINT_V(x) ((x) << SGLWRPLINT_S)
1217 #define SGLWRPLINT_F    SGLWRPLINT_V(1U)
1218 
1219 #define SGLRDPLINT_S    22
1220 #define SGLRDPLINT_V(x) ((x) << SGLRDPLINT_S)
1221 #define SGLRDPLINT_F    SGLRDPLINT_V(1U)
1222 
1223 #define BLKWRCTLINT_S    21
1224 #define BLKWRCTLINT_V(x) ((x) << BLKWRCTLINT_S)
1225 #define BLKWRCTLINT_F    BLKWRCTLINT_V(1U)
1226 
1227 #define BLKRDCTLINT_S    20
1228 #define BLKRDCTLINT_V(x) ((x) << BLKRDCTLINT_S)
1229 #define BLKRDCTLINT_F    BLKRDCTLINT_V(1U)
1230 
1231 #define SGLWRCTLINT_S    19
1232 #define SGLWRCTLINT_V(x) ((x) << SGLWRCTLINT_S)
1233 #define SGLWRCTLINT_F    SGLWRCTLINT_V(1U)
1234 
1235 #define SGLRDCTLINT_S    18
1236 #define SGLRDCTLINT_V(x) ((x) << SGLRDCTLINT_S)
1237 #define SGLRDCTLINT_F    SGLRDCTLINT_V(1U)
1238 
1239 #define BLKWREEPROMINT_S    17
1240 #define BLKWREEPROMINT_V(x) ((x) << BLKWREEPROMINT_S)
1241 #define BLKWREEPROMINT_F    BLKWREEPROMINT_V(1U)
1242 
1243 #define BLKRDEEPROMINT_S    16
1244 #define BLKRDEEPROMINT_V(x) ((x) << BLKRDEEPROMINT_S)
1245 #define BLKRDEEPROMINT_F    BLKRDEEPROMINT_V(1U)
1246 
1247 #define SGLWREEPROMINT_S    15
1248 #define SGLWREEPROMINT_V(x) ((x) << SGLWREEPROMINT_S)
1249 #define SGLWREEPROMINT_F    SGLWREEPROMINT_V(1U)
1250 
1251 #define SGLRDEEPROMINT_S    14
1252 #define SGLRDEEPROMINT_V(x) ((x) << SGLRDEEPROMINT_S)
1253 #define SGLRDEEPROMINT_F    SGLRDEEPROMINT_V(1U)
1254 
1255 #define BLKWRFLASHINT_S    13
1256 #define BLKWRFLASHINT_V(x) ((x) << BLKWRFLASHINT_S)
1257 #define BLKWRFLASHINT_F    BLKWRFLASHINT_V(1U)
1258 
1259 #define BLKRDFLASHINT_S    12
1260 #define BLKRDFLASHINT_V(x) ((x) << BLKRDFLASHINT_S)
1261 #define BLKRDFLASHINT_F    BLKRDFLASHINT_V(1U)
1262 
1263 #define SGLWRFLASHINT_S    11
1264 #define SGLWRFLASHINT_V(x) ((x) << SGLWRFLASHINT_S)
1265 #define SGLWRFLASHINT_F    SGLWRFLASHINT_V(1U)
1266 
1267 #define SGLRDFLASHINT_S    10
1268 #define SGLRDFLASHINT_V(x) ((x) << SGLRDFLASHINT_S)
1269 #define SGLRDFLASHINT_F    SGLRDFLASHINT_V(1U)
1270 
1271 #define BLKWRBOOTINT_S    9
1272 #define BLKWRBOOTINT_V(x) ((x) << BLKWRBOOTINT_S)
1273 #define BLKWRBOOTINT_F    BLKWRBOOTINT_V(1U)
1274 
1275 #define BLKRDBOOTINT_S    8
1276 #define BLKRDBOOTINT_V(x) ((x) << BLKRDBOOTINT_S)
1277 #define BLKRDBOOTINT_F    BLKRDBOOTINT_V(1U)
1278 
1279 #define SGLWRBOOTINT_S    7
1280 #define SGLWRBOOTINT_V(x) ((x) << SGLWRBOOTINT_S)
1281 #define SGLWRBOOTINT_F    SGLWRBOOTINT_V(1U)
1282 
1283 #define SGLRDBOOTINT_S    6
1284 #define SGLRDBOOTINT_V(x) ((x) << SGLRDBOOTINT_S)
1285 #define SGLRDBOOTINT_F    SGLRDBOOTINT_V(1U)
1286 
1287 #define ILLWRBEINT_S    5
1288 #define ILLWRBEINT_V(x) ((x) << ILLWRBEINT_S)
1289 #define ILLWRBEINT_F    ILLWRBEINT_V(1U)
1290 
1291 #define ILLRDBEINT_S    4
1292 #define ILLRDBEINT_V(x) ((x) << ILLRDBEINT_S)
1293 #define ILLRDBEINT_F    ILLRDBEINT_V(1U)
1294 
1295 #define ILLRDINT_S    3
1296 #define ILLRDINT_V(x) ((x) << ILLRDINT_S)
1297 #define ILLRDINT_F    ILLRDINT_V(1U)
1298 
1299 #define ILLWRINT_S    2
1300 #define ILLWRINT_V(x) ((x) << ILLWRINT_S)
1301 #define ILLWRINT_F    ILLWRINT_V(1U)
1302 
1303 #define ILLTRANSINT_S    1
1304 #define ILLTRANSINT_V(x) ((x) << ILLTRANSINT_S)
1305 #define ILLTRANSINT_F    ILLTRANSINT_V(1U)
1306 
1307 #define RSVDSPACEINT_S    0
1308 #define RSVDSPACEINT_V(x) ((x) << RSVDSPACEINT_S)
1309 #define RSVDSPACEINT_F    RSVDSPACEINT_V(1U)
1310 
1311 /* registers for module TP */
1312 #define DBGLAWHLF_S    23
1313 #define DBGLAWHLF_V(x) ((x) << DBGLAWHLF_S)
1314 #define DBGLAWHLF_F    DBGLAWHLF_V(1U)
1315 
1316 #define DBGLAWPTR_S    16
1317 #define DBGLAWPTR_M    0x7fU
1318 #define DBGLAWPTR_G(x) (((x) >> DBGLAWPTR_S) & DBGLAWPTR_M)
1319 
1320 #define DBGLAENABLE_S    12
1321 #define DBGLAENABLE_V(x) ((x) << DBGLAENABLE_S)
1322 #define DBGLAENABLE_F    DBGLAENABLE_V(1U)
1323 
1324 #define DBGLARPTR_S    0
1325 #define DBGLARPTR_M    0x7fU
1326 #define DBGLARPTR_V(x) ((x) << DBGLARPTR_S)
1327 
1328 #define CRXPKTENC_S    3
1329 #define CRXPKTENC_V(x) ((x) << CRXPKTENC_S)
1330 #define CRXPKTENC_F    CRXPKTENC_V(1U)
1331 
1332 #define TP_DBG_LA_DATAL_A	0x7ed8
1333 #define TP_DBG_LA_CONFIG_A	0x7ed4
1334 #define TP_OUT_CONFIG_A		0x7d04
1335 #define TP_GLOBAL_CONFIG_A	0x7d08
1336 
1337 #define TP_CMM_TCB_BASE_A 0x7d10
1338 #define TP_CMM_MM_BASE_A 0x7d14
1339 #define TP_CMM_TIMER_BASE_A 0x7d18
1340 #define TP_PMM_TX_BASE_A 0x7d20
1341 #define TP_PMM_RX_BASE_A 0x7d28
1342 #define TP_PMM_RX_PAGE_SIZE_A 0x7d2c
1343 #define TP_PMM_RX_MAX_PAGE_A 0x7d30
1344 #define TP_PMM_TX_PAGE_SIZE_A 0x7d34
1345 #define TP_PMM_TX_MAX_PAGE_A 0x7d38
1346 #define TP_CMM_MM_MAX_PSTRUCT_A 0x7e6c
1347 
1348 #define PMRXNUMCHN_S    31
1349 #define PMRXNUMCHN_V(x) ((x) << PMRXNUMCHN_S)
1350 #define PMRXNUMCHN_F    PMRXNUMCHN_V(1U)
1351 
1352 #define PMTXNUMCHN_S    30
1353 #define PMTXNUMCHN_M    0x3U
1354 #define PMTXNUMCHN_G(x) (((x) >> PMTXNUMCHN_S) & PMTXNUMCHN_M)
1355 
1356 #define PMTXMAXPAGE_S    0
1357 #define PMTXMAXPAGE_M    0x1fffffU
1358 #define PMTXMAXPAGE_G(x) (((x) >> PMTXMAXPAGE_S) & PMTXMAXPAGE_M)
1359 
1360 #define PMRXMAXPAGE_S    0
1361 #define PMRXMAXPAGE_M    0x1fffffU
1362 #define PMRXMAXPAGE_G(x) (((x) >> PMRXMAXPAGE_S) & PMRXMAXPAGE_M)
1363 
1364 #define DBGLAMODE_S	14
1365 #define DBGLAMODE_M	0x3U
1366 #define DBGLAMODE_G(x)	(((x) >> DBGLAMODE_S) & DBGLAMODE_M)
1367 
1368 #define FIVETUPLELOOKUP_S    17
1369 #define FIVETUPLELOOKUP_M    0x3U
1370 #define FIVETUPLELOOKUP_V(x) ((x) << FIVETUPLELOOKUP_S)
1371 #define FIVETUPLELOOKUP_G(x) (((x) >> FIVETUPLELOOKUP_S) & FIVETUPLELOOKUP_M)
1372 
1373 #define TP_PARA_REG2_A 0x7d68
1374 
1375 #define MAXRXDATA_S    16
1376 #define MAXRXDATA_M    0xffffU
1377 #define MAXRXDATA_G(x) (((x) >> MAXRXDATA_S) & MAXRXDATA_M)
1378 
1379 #define TP_TIMER_RESOLUTION_A 0x7d90
1380 
1381 #define TIMERRESOLUTION_S    16
1382 #define TIMERRESOLUTION_M    0xffU
1383 #define TIMERRESOLUTION_G(x) (((x) >> TIMERRESOLUTION_S) & TIMERRESOLUTION_M)
1384 
1385 #define TIMESTAMPRESOLUTION_S    8
1386 #define TIMESTAMPRESOLUTION_M    0xffU
1387 #define TIMESTAMPRESOLUTION_G(x) \
1388 	(((x) >> TIMESTAMPRESOLUTION_S) & TIMESTAMPRESOLUTION_M)
1389 
1390 #define DELAYEDACKRESOLUTION_S    0
1391 #define DELAYEDACKRESOLUTION_M    0xffU
1392 #define DELAYEDACKRESOLUTION_G(x) \
1393 	(((x) >> DELAYEDACKRESOLUTION_S) & DELAYEDACKRESOLUTION_M)
1394 
1395 #define TP_SHIFT_CNT_A 0x7dc0
1396 #define TP_RXT_MIN_A 0x7d98
1397 #define TP_RXT_MAX_A 0x7d9c
1398 #define TP_PERS_MIN_A 0x7da0
1399 #define TP_PERS_MAX_A 0x7da4
1400 #define TP_KEEP_IDLE_A 0x7da8
1401 #define TP_KEEP_INTVL_A 0x7dac
1402 #define TP_INIT_SRTT_A 0x7db0
1403 #define TP_DACK_TIMER_A 0x7db4
1404 #define TP_FINWAIT2_TIMER_A 0x7db8
1405 
1406 #define INITSRTT_S    0
1407 #define INITSRTT_M    0xffffU
1408 #define INITSRTT_G(x) (((x) >> INITSRTT_S) & INITSRTT_M)
1409 
1410 #define PERSMAX_S    0
1411 #define PERSMAX_M    0x3fffffffU
1412 #define PERSMAX_V(x) ((x) << PERSMAX_S)
1413 #define PERSMAX_G(x) (((x) >> PERSMAX_S) & PERSMAX_M)
1414 
1415 #define SYNSHIFTMAX_S    24
1416 #define SYNSHIFTMAX_M    0xffU
1417 #define SYNSHIFTMAX_V(x) ((x) << SYNSHIFTMAX_S)
1418 #define SYNSHIFTMAX_G(x) (((x) >> SYNSHIFTMAX_S) & SYNSHIFTMAX_M)
1419 
1420 #define RXTSHIFTMAXR1_S    20
1421 #define RXTSHIFTMAXR1_M    0xfU
1422 #define RXTSHIFTMAXR1_V(x) ((x) << RXTSHIFTMAXR1_S)
1423 #define RXTSHIFTMAXR1_G(x) (((x) >> RXTSHIFTMAXR1_S) & RXTSHIFTMAXR1_M)
1424 
1425 #define RXTSHIFTMAXR2_S    16
1426 #define RXTSHIFTMAXR2_M    0xfU
1427 #define RXTSHIFTMAXR2_V(x) ((x) << RXTSHIFTMAXR2_S)
1428 #define RXTSHIFTMAXR2_G(x) (((x) >> RXTSHIFTMAXR2_S) & RXTSHIFTMAXR2_M)
1429 
1430 #define PERSHIFTBACKOFFMAX_S    12
1431 #define PERSHIFTBACKOFFMAX_M    0xfU
1432 #define PERSHIFTBACKOFFMAX_V(x) ((x) << PERSHIFTBACKOFFMAX_S)
1433 #define PERSHIFTBACKOFFMAX_G(x) \
1434 	(((x) >> PERSHIFTBACKOFFMAX_S) & PERSHIFTBACKOFFMAX_M)
1435 
1436 #define PERSHIFTMAX_S    8
1437 #define PERSHIFTMAX_M    0xfU
1438 #define PERSHIFTMAX_V(x) ((x) << PERSHIFTMAX_S)
1439 #define PERSHIFTMAX_G(x) (((x) >> PERSHIFTMAX_S) & PERSHIFTMAX_M)
1440 
1441 #define KEEPALIVEMAXR1_S    4
1442 #define KEEPALIVEMAXR1_M    0xfU
1443 #define KEEPALIVEMAXR1_V(x) ((x) << KEEPALIVEMAXR1_S)
1444 #define KEEPALIVEMAXR1_G(x) (((x) >> KEEPALIVEMAXR1_S) & KEEPALIVEMAXR1_M)
1445 
1446 #define KEEPALIVEMAXR2_S    0
1447 #define KEEPALIVEMAXR2_M    0xfU
1448 #define KEEPALIVEMAXR2_V(x) ((x) << KEEPALIVEMAXR2_S)
1449 #define KEEPALIVEMAXR2_G(x) (((x) >> KEEPALIVEMAXR2_S) & KEEPALIVEMAXR2_M)
1450 
1451 #define ROWINDEX_S    16
1452 #define ROWINDEX_V(x) ((x) << ROWINDEX_S)
1453 
1454 #define TP_CCTRL_TABLE_A	0x7ddc
1455 #define TP_PACE_TABLE_A 0x7dd8
1456 #define TP_MTU_TABLE_A		0x7de4
1457 
1458 #define MTUINDEX_S    24
1459 #define MTUINDEX_V(x) ((x) << MTUINDEX_S)
1460 
1461 #define MTUWIDTH_S    16
1462 #define MTUWIDTH_M    0xfU
1463 #define MTUWIDTH_V(x) ((x) << MTUWIDTH_S)
1464 #define MTUWIDTH_G(x) (((x) >> MTUWIDTH_S) & MTUWIDTH_M)
1465 
1466 #define MTUVALUE_S    0
1467 #define MTUVALUE_M    0x3fffU
1468 #define MTUVALUE_V(x) ((x) << MTUVALUE_S)
1469 #define MTUVALUE_G(x) (((x) >> MTUVALUE_S) & MTUVALUE_M)
1470 
1471 #define TP_RSS_LKP_TABLE_A	0x7dec
1472 #define TP_CMM_MM_RX_FLST_BASE_A 0x7e60
1473 #define TP_CMM_MM_TX_FLST_BASE_A 0x7e64
1474 #define TP_CMM_MM_PS_FLST_BASE_A 0x7e68
1475 
1476 #define LKPTBLROWVLD_S    31
1477 #define LKPTBLROWVLD_V(x) ((x) << LKPTBLROWVLD_S)
1478 #define LKPTBLROWVLD_F    LKPTBLROWVLD_V(1U)
1479 
1480 #define LKPTBLQUEUE1_S    10
1481 #define LKPTBLQUEUE1_M    0x3ffU
1482 #define LKPTBLQUEUE1_G(x) (((x) >> LKPTBLQUEUE1_S) & LKPTBLQUEUE1_M)
1483 
1484 #define LKPTBLQUEUE0_S    0
1485 #define LKPTBLQUEUE0_M    0x3ffU
1486 #define LKPTBLQUEUE0_G(x) (((x) >> LKPTBLQUEUE0_S) & LKPTBLQUEUE0_M)
1487 
1488 #define TP_TM_PIO_ADDR_A 0x7e18
1489 #define TP_TM_PIO_DATA_A 0x7e1c
1490 #define TP_MOD_CONFIG_A 0x7e24
1491 
1492 #define TIMERMODE_S    8
1493 #define TIMERMODE_M    0xffU
1494 #define TIMERMODE_G(x) (((x) >> TIMERMODE_S) & TIMERMODE_M)
1495 
1496 #define TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR_A 0x3
1497 #define TP_TX_MOD_Q1_Q0_RATE_LIMIT_A 0x8
1498 
1499 #define TP_PIO_ADDR_A	0x7e40
1500 #define TP_PIO_DATA_A	0x7e44
1501 #define TP_MIB_INDEX_A	0x7e50
1502 #define TP_MIB_DATA_A	0x7e54
1503 #define TP_INT_CAUSE_A	0x7e74
1504 
1505 #define TP_FLM_FREE_PS_CNT_A 0x7e80
1506 #define TP_FLM_FREE_RX_CNT_A 0x7e84
1507 
1508 #define FREEPSTRUCTCOUNT_S    0
1509 #define FREEPSTRUCTCOUNT_M    0x1fffffU
1510 #define FREEPSTRUCTCOUNT_G(x) (((x) >> FREEPSTRUCTCOUNT_S) & FREEPSTRUCTCOUNT_M)
1511 
1512 #define FREERXPAGECOUNT_S    0
1513 #define FREERXPAGECOUNT_M    0x1fffffU
1514 #define FREERXPAGECOUNT_V(x) ((x) << FREERXPAGECOUNT_S)
1515 #define FREERXPAGECOUNT_G(x) (((x) >> FREERXPAGECOUNT_S) & FREERXPAGECOUNT_M)
1516 
1517 #define TP_FLM_FREE_TX_CNT_A 0x7e88
1518 
1519 #define FREETXPAGECOUNT_S    0
1520 #define FREETXPAGECOUNT_M    0x1fffffU
1521 #define FREETXPAGECOUNT_V(x) ((x) << FREETXPAGECOUNT_S)
1522 #define FREETXPAGECOUNT_G(x) (((x) >> FREETXPAGECOUNT_S) & FREETXPAGECOUNT_M)
1523 
1524 #define FLMTXFLSTEMPTY_S    30
1525 #define FLMTXFLSTEMPTY_V(x) ((x) << FLMTXFLSTEMPTY_S)
1526 #define FLMTXFLSTEMPTY_F    FLMTXFLSTEMPTY_V(1U)
1527 
1528 #define TP_TX_ORATE_A 0x7ebc
1529 
1530 #define OFDRATE3_S    24
1531 #define OFDRATE3_M    0xffU
1532 #define OFDRATE3_G(x) (((x) >> OFDRATE3_S) & OFDRATE3_M)
1533 
1534 #define OFDRATE2_S    16
1535 #define OFDRATE2_M    0xffU
1536 #define OFDRATE2_G(x) (((x) >> OFDRATE2_S) & OFDRATE2_M)
1537 
1538 #define OFDRATE1_S    8
1539 #define OFDRATE1_M    0xffU
1540 #define OFDRATE1_G(x) (((x) >> OFDRATE1_S) & OFDRATE1_M)
1541 
1542 #define OFDRATE0_S    0
1543 #define OFDRATE0_M    0xffU
1544 #define OFDRATE0_G(x) (((x) >> OFDRATE0_S) & OFDRATE0_M)
1545 
1546 #define TP_TX_TRATE_A 0x7ed0
1547 
1548 #define TNLRATE3_S    24
1549 #define TNLRATE3_M    0xffU
1550 #define TNLRATE3_G(x) (((x) >> TNLRATE3_S) & TNLRATE3_M)
1551 
1552 #define TNLRATE2_S    16
1553 #define TNLRATE2_M    0xffU
1554 #define TNLRATE2_G(x) (((x) >> TNLRATE2_S) & TNLRATE2_M)
1555 
1556 #define TNLRATE1_S    8
1557 #define TNLRATE1_M    0xffU
1558 #define TNLRATE1_G(x) (((x) >> TNLRATE1_S) & TNLRATE1_M)
1559 
1560 #define TNLRATE0_S    0
1561 #define TNLRATE0_M    0xffU
1562 #define TNLRATE0_G(x) (((x) >> TNLRATE0_S) & TNLRATE0_M)
1563 
1564 #define TP_VLAN_PRI_MAP_A 0x140
1565 
1566 #define FRAGMENTATION_S    9
1567 #define FRAGMENTATION_V(x) ((x) << FRAGMENTATION_S)
1568 #define FRAGMENTATION_F    FRAGMENTATION_V(1U)
1569 
1570 #define MPSHITTYPE_S    8
1571 #define MPSHITTYPE_V(x) ((x) << MPSHITTYPE_S)
1572 #define MPSHITTYPE_F    MPSHITTYPE_V(1U)
1573 
1574 #define MACMATCH_S    7
1575 #define MACMATCH_V(x) ((x) << MACMATCH_S)
1576 #define MACMATCH_F    MACMATCH_V(1U)
1577 
1578 #define ETHERTYPE_S    6
1579 #define ETHERTYPE_V(x) ((x) << ETHERTYPE_S)
1580 #define ETHERTYPE_F    ETHERTYPE_V(1U)
1581 
1582 #define PROTOCOL_S    5
1583 #define PROTOCOL_V(x) ((x) << PROTOCOL_S)
1584 #define PROTOCOL_F    PROTOCOL_V(1U)
1585 
1586 #define TOS_S    4
1587 #define TOS_V(x) ((x) << TOS_S)
1588 #define TOS_F    TOS_V(1U)
1589 
1590 #define VLAN_S    3
1591 #define VLAN_V(x) ((x) << VLAN_S)
1592 #define VLAN_F    VLAN_V(1U)
1593 
1594 #define VNIC_ID_S    2
1595 #define VNIC_ID_V(x) ((x) << VNIC_ID_S)
1596 #define VNIC_ID_F    VNIC_ID_V(1U)
1597 
1598 #define PORT_S    1
1599 #define PORT_V(x) ((x) << PORT_S)
1600 #define PORT_F    PORT_V(1U)
1601 
1602 #define FCOE_S    0
1603 #define FCOE_V(x) ((x) << FCOE_S)
1604 #define FCOE_F    FCOE_V(1U)
1605 
1606 #define FILTERMODE_S    15
1607 #define FILTERMODE_V(x) ((x) << FILTERMODE_S)
1608 #define FILTERMODE_F    FILTERMODE_V(1U)
1609 
1610 #define FCOEMASK_S    14
1611 #define FCOEMASK_V(x) ((x) << FCOEMASK_S)
1612 #define FCOEMASK_F    FCOEMASK_V(1U)
1613 
1614 #define TP_INGRESS_CONFIG_A	0x141
1615 
1616 #define VNIC_S    11
1617 #define VNIC_V(x) ((x) << VNIC_S)
1618 #define VNIC_F    VNIC_V(1U)
1619 
1620 #define USE_ENC_IDX_S		13
1621 #define USE_ENC_IDX_V(x)	((x) << USE_ENC_IDX_S)
1622 #define USE_ENC_IDX_F		USE_ENC_IDX_V(1U)
1623 
1624 #define CSUM_HAS_PSEUDO_HDR_S    10
1625 #define CSUM_HAS_PSEUDO_HDR_V(x) ((x) << CSUM_HAS_PSEUDO_HDR_S)
1626 #define CSUM_HAS_PSEUDO_HDR_F    CSUM_HAS_PSEUDO_HDR_V(1U)
1627 
1628 #define TP_MIB_MAC_IN_ERR_0_A	0x0
1629 #define TP_MIB_HDR_IN_ERR_0_A	0x4
1630 #define TP_MIB_TCP_IN_ERR_0_A	0x8
1631 #define TP_MIB_TCP_OUT_RST_A	0xc
1632 #define TP_MIB_TCP_IN_SEG_HI_A	0x10
1633 #define TP_MIB_TCP_IN_SEG_LO_A	0x11
1634 #define TP_MIB_TCP_OUT_SEG_HI_A	0x12
1635 #define TP_MIB_TCP_OUT_SEG_LO_A 0x13
1636 #define TP_MIB_TCP_RXT_SEG_HI_A	0x14
1637 #define TP_MIB_TCP_RXT_SEG_LO_A	0x15
1638 #define TP_MIB_TNL_CNG_DROP_0_A 0x18
1639 #define TP_MIB_OFD_CHN_DROP_0_A 0x1c
1640 #define TP_MIB_TCP_V6IN_ERR_0_A 0x28
1641 #define TP_MIB_TCP_V6OUT_RST_A	0x2c
1642 #define TP_MIB_OFD_ARP_DROP_A	0x36
1643 #define TP_MIB_CPL_IN_REQ_0_A	0x38
1644 #define TP_MIB_CPL_OUT_RSP_0_A	0x3c
1645 #define TP_MIB_TNL_DROP_0_A	0x44
1646 #define TP_MIB_FCOE_DDP_0_A	0x48
1647 #define TP_MIB_FCOE_DROP_0_A	0x4c
1648 #define TP_MIB_FCOE_BYTE_0_HI_A	0x50
1649 #define TP_MIB_OFD_VLN_DROP_0_A	0x58
1650 #define TP_MIB_USM_PKTS_A	0x5c
1651 #define TP_MIB_RQE_DFR_PKT_A	0x64
1652 
1653 #define ULP_TX_INT_CAUSE_A	0x8dcc
1654 #define ULP_TX_TPT_LLIMIT_A	0x8dd4
1655 #define ULP_TX_TPT_ULIMIT_A	0x8dd8
1656 #define ULP_TX_PBL_LLIMIT_A	0x8ddc
1657 #define ULP_TX_PBL_ULIMIT_A	0x8de0
1658 #define ULP_TX_ERR_TABLE_BASE_A 0x8e04
1659 
1660 #define PBL_BOUND_ERR_CH3_S    31
1661 #define PBL_BOUND_ERR_CH3_V(x) ((x) << PBL_BOUND_ERR_CH3_S)
1662 #define PBL_BOUND_ERR_CH3_F    PBL_BOUND_ERR_CH3_V(1U)
1663 
1664 #define PBL_BOUND_ERR_CH2_S    30
1665 #define PBL_BOUND_ERR_CH2_V(x) ((x) << PBL_BOUND_ERR_CH2_S)
1666 #define PBL_BOUND_ERR_CH2_F    PBL_BOUND_ERR_CH2_V(1U)
1667 
1668 #define PBL_BOUND_ERR_CH1_S    29
1669 #define PBL_BOUND_ERR_CH1_V(x) ((x) << PBL_BOUND_ERR_CH1_S)
1670 #define PBL_BOUND_ERR_CH1_F    PBL_BOUND_ERR_CH1_V(1U)
1671 
1672 #define PBL_BOUND_ERR_CH0_S    28
1673 #define PBL_BOUND_ERR_CH0_V(x) ((x) << PBL_BOUND_ERR_CH0_S)
1674 #define PBL_BOUND_ERR_CH0_F    PBL_BOUND_ERR_CH0_V(1U)
1675 
1676 #define PM_RX_INT_CAUSE_A	0x8fdc
1677 #define PM_RX_STAT_CONFIG_A 0x8fc8
1678 #define PM_RX_STAT_COUNT_A 0x8fcc
1679 #define PM_RX_STAT_LSB_A 0x8fd0
1680 #define PM_RX_DBG_CTRL_A 0x8fd0
1681 #define PM_RX_DBG_DATA_A 0x8fd4
1682 #define PM_RX_DBG_STAT_MSB_A 0x10013
1683 
1684 #define PMRX_FRAMING_ERROR_F	0x003ffff0U
1685 
1686 #define ZERO_E_CMD_ERROR_S    22
1687 #define ZERO_E_CMD_ERROR_V(x) ((x) << ZERO_E_CMD_ERROR_S)
1688 #define ZERO_E_CMD_ERROR_F    ZERO_E_CMD_ERROR_V(1U)
1689 
1690 #define OCSPI_PAR_ERROR_S    3
1691 #define OCSPI_PAR_ERROR_V(x) ((x) << OCSPI_PAR_ERROR_S)
1692 #define OCSPI_PAR_ERROR_F    OCSPI_PAR_ERROR_V(1U)
1693 
1694 #define DB_OPTIONS_PAR_ERROR_S    2
1695 #define DB_OPTIONS_PAR_ERROR_V(x) ((x) << DB_OPTIONS_PAR_ERROR_S)
1696 #define DB_OPTIONS_PAR_ERROR_F    DB_OPTIONS_PAR_ERROR_V(1U)
1697 
1698 #define IESPI_PAR_ERROR_S    1
1699 #define IESPI_PAR_ERROR_V(x) ((x) << IESPI_PAR_ERROR_S)
1700 #define IESPI_PAR_ERROR_F    IESPI_PAR_ERROR_V(1U)
1701 
1702 #define ULP_TX_LA_RDPTR_0_A 0x8ec0
1703 #define ULP_TX_LA_RDDATA_0_A 0x8ec4
1704 #define ULP_TX_LA_WRPTR_0_A 0x8ec8
1705 #define ULP_TX_ASIC_DEBUG_CTRL_A 0x8f70
1706 
1707 #define ULP_TX_ASIC_DEBUG_0_A 0x8f74
1708 #define ULP_TX_ASIC_DEBUG_1_A 0x8f78
1709 #define ULP_TX_ASIC_DEBUG_2_A 0x8f7c
1710 #define ULP_TX_ASIC_DEBUG_3_A 0x8f80
1711 #define ULP_TX_ASIC_DEBUG_4_A 0x8f84
1712 
1713 /* registers for module PM_RX */
1714 #define PM_RX_BASE_ADDR 0x8fc0
1715 
1716 #define PMRX_E_PCMD_PAR_ERROR_S    0
1717 #define PMRX_E_PCMD_PAR_ERROR_V(x) ((x) << PMRX_E_PCMD_PAR_ERROR_S)
1718 #define PMRX_E_PCMD_PAR_ERROR_F    PMRX_E_PCMD_PAR_ERROR_V(1U)
1719 
1720 #define PM_TX_INT_CAUSE_A	0x8ffc
1721 #define PM_TX_STAT_CONFIG_A 0x8fe8
1722 #define PM_TX_STAT_COUNT_A 0x8fec
1723 #define PM_TX_STAT_LSB_A 0x8ff0
1724 #define PM_TX_DBG_CTRL_A 0x8ff0
1725 #define PM_TX_DBG_DATA_A 0x8ff4
1726 #define PM_TX_DBG_STAT_MSB_A 0x1001a
1727 
1728 #define PCMD_LEN_OVFL0_S    31
1729 #define PCMD_LEN_OVFL0_V(x) ((x) << PCMD_LEN_OVFL0_S)
1730 #define PCMD_LEN_OVFL0_F    PCMD_LEN_OVFL0_V(1U)
1731 
1732 #define PCMD_LEN_OVFL1_S    30
1733 #define PCMD_LEN_OVFL1_V(x) ((x) << PCMD_LEN_OVFL1_S)
1734 #define PCMD_LEN_OVFL1_F    PCMD_LEN_OVFL1_V(1U)
1735 
1736 #define PCMD_LEN_OVFL2_S    29
1737 #define PCMD_LEN_OVFL2_V(x) ((x) << PCMD_LEN_OVFL2_S)
1738 #define PCMD_LEN_OVFL2_F    PCMD_LEN_OVFL2_V(1U)
1739 
1740 #define ZERO_C_CMD_ERROR_S    28
1741 #define ZERO_C_CMD_ERROR_V(x) ((x) << ZERO_C_CMD_ERROR_S)
1742 #define ZERO_C_CMD_ERROR_F    ZERO_C_CMD_ERROR_V(1U)
1743 
1744 #define  PMTX_FRAMING_ERROR_F 0x0ffffff0U
1745 
1746 #define OESPI_PAR_ERROR_S    3
1747 #define OESPI_PAR_ERROR_V(x) ((x) << OESPI_PAR_ERROR_S)
1748 #define OESPI_PAR_ERROR_F    OESPI_PAR_ERROR_V(1U)
1749 
1750 #define ICSPI_PAR_ERROR_S    1
1751 #define ICSPI_PAR_ERROR_V(x) ((x) << ICSPI_PAR_ERROR_S)
1752 #define ICSPI_PAR_ERROR_F    ICSPI_PAR_ERROR_V(1U)
1753 
1754 #define PMTX_C_PCMD_PAR_ERROR_S    0
1755 #define PMTX_C_PCMD_PAR_ERROR_V(x) ((x) << PMTX_C_PCMD_PAR_ERROR_S)
1756 #define PMTX_C_PCMD_PAR_ERROR_F    PMTX_C_PCMD_PAR_ERROR_V(1U)
1757 
1758 #define MPS_PORT_STAT_TX_PORT_BYTES_L 0x400
1759 #define MPS_PORT_STAT_TX_PORT_BYTES_H 0x404
1760 #define MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408
1761 #define MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c
1762 #define MPS_PORT_STAT_TX_PORT_BCAST_L 0x410
1763 #define MPS_PORT_STAT_TX_PORT_BCAST_H 0x414
1764 #define MPS_PORT_STAT_TX_PORT_MCAST_L 0x418
1765 #define MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c
1766 #define MPS_PORT_STAT_TX_PORT_UCAST_L 0x420
1767 #define MPS_PORT_STAT_TX_PORT_UCAST_H 0x424
1768 #define MPS_PORT_STAT_TX_PORT_ERROR_L 0x428
1769 #define MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c
1770 #define MPS_PORT_STAT_TX_PORT_64B_L 0x430
1771 #define MPS_PORT_STAT_TX_PORT_64B_H 0x434
1772 #define MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438
1773 #define MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c
1774 #define MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440
1775 #define MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444
1776 #define MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448
1777 #define MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c
1778 #define MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450
1779 #define MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454
1780 #define MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458
1781 #define MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c
1782 #define MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460
1783 #define MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464
1784 #define MPS_PORT_STAT_TX_PORT_DROP_L 0x468
1785 #define MPS_PORT_STAT_TX_PORT_DROP_H 0x46c
1786 #define MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470
1787 #define MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474
1788 #define MPS_PORT_STAT_TX_PORT_PPP0_L 0x478
1789 #define MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c
1790 #define MPS_PORT_STAT_TX_PORT_PPP1_L 0x480
1791 #define MPS_PORT_STAT_TX_PORT_PPP1_H 0x484
1792 #define MPS_PORT_STAT_TX_PORT_PPP2_L 0x488
1793 #define MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c
1794 #define MPS_PORT_STAT_TX_PORT_PPP3_L 0x490
1795 #define MPS_PORT_STAT_TX_PORT_PPP3_H 0x494
1796 #define MPS_PORT_STAT_TX_PORT_PPP4_L 0x498
1797 #define MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c
1798 #define MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0
1799 #define MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4
1800 #define MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8
1801 #define MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac
1802 #define MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0
1803 #define MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4
1804 #define MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0
1805 #define MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4
1806 #define MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8
1807 #define MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc
1808 #define MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0
1809 #define MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4
1810 #define MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8
1811 #define MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc
1812 #define MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0
1813 #define MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4
1814 #define MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8
1815 #define MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec
1816 #define MPS_PORT_STAT_LB_PORT_64B_L 0x4f0
1817 #define MPS_PORT_STAT_LB_PORT_64B_H 0x4f4
1818 #define MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8
1819 #define MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc
1820 #define MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500
1821 #define MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504
1822 #define MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508
1823 #define MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c
1824 #define MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510
1825 #define MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514
1826 #define MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518
1827 #define MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c
1828 #define MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520
1829 #define MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524
1830 #define MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528
1831 #define MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L 0x528
1832 #define MPS_PORT_STAT_RX_PORT_BYTES_L 0x540
1833 #define MPS_PORT_STAT_RX_PORT_BYTES_H 0x544
1834 #define MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548
1835 #define MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c
1836 #define MPS_PORT_STAT_RX_PORT_BCAST_L 0x550
1837 #define MPS_PORT_STAT_RX_PORT_BCAST_H 0x554
1838 #define MPS_PORT_STAT_RX_PORT_MCAST_L 0x558
1839 #define MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c
1840 #define MPS_PORT_STAT_RX_PORT_UCAST_L 0x560
1841 #define MPS_PORT_STAT_RX_PORT_UCAST_H 0x564
1842 #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568
1843 #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c
1844 #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570
1845 #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574
1846 #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578
1847 #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c
1848 #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580
1849 #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584
1850 #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588
1851 #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c
1852 #define MPS_PORT_STAT_RX_PORT_64B_L 0x590
1853 #define MPS_PORT_STAT_RX_PORT_64B_H 0x594
1854 #define MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598
1855 #define MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c
1856 #define MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0
1857 #define MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4
1858 #define MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8
1859 #define MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac
1860 #define MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0
1861 #define MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4
1862 #define MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8
1863 #define MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc
1864 #define MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0
1865 #define MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4
1866 #define MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8
1867 #define MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc
1868 #define MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0
1869 #define MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4
1870 #define MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8
1871 #define MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc
1872 #define MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0
1873 #define MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4
1874 #define MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8
1875 #define MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec
1876 #define MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0
1877 #define MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4
1878 #define MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8
1879 #define MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc
1880 #define MPS_PORT_STAT_RX_PORT_PPP6_L 0x600
1881 #define MPS_PORT_STAT_RX_PORT_PPP6_H 0x604
1882 #define MPS_PORT_STAT_RX_PORT_PPP7_L 0x608
1883 #define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c
1884 #define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610
1885 #define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
1886 #define MAC_PORT_MAGIC_MACID_LO 0x824
1887 #define MAC_PORT_MAGIC_MACID_HI 0x828
1888 #define MAC_PORT_TX_TS_VAL_LO   0x928
1889 #define MAC_PORT_TX_TS_VAL_HI   0x92c
1890 
1891 #define MAC_PORT_EPIO_DATA0_A 0x8c0
1892 #define MAC_PORT_EPIO_DATA1_A 0x8c4
1893 #define MAC_PORT_EPIO_DATA2_A 0x8c8
1894 #define MAC_PORT_EPIO_DATA3_A 0x8cc
1895 #define MAC_PORT_EPIO_OP_A 0x8d0
1896 
1897 #define MAC_PORT_CFG2_A 0x818
1898 
1899 #define MPS_CMN_CTL_A	0x9000
1900 
1901 #define COUNTPAUSEMCRX_S    5
1902 #define COUNTPAUSEMCRX_V(x) ((x) << COUNTPAUSEMCRX_S)
1903 #define COUNTPAUSEMCRX_F    COUNTPAUSEMCRX_V(1U)
1904 
1905 #define COUNTPAUSESTATRX_S    4
1906 #define COUNTPAUSESTATRX_V(x) ((x) << COUNTPAUSESTATRX_S)
1907 #define COUNTPAUSESTATRX_F    COUNTPAUSESTATRX_V(1U)
1908 
1909 #define COUNTPAUSEMCTX_S    3
1910 #define COUNTPAUSEMCTX_V(x) ((x) << COUNTPAUSEMCTX_S)
1911 #define COUNTPAUSEMCTX_F    COUNTPAUSEMCTX_V(1U)
1912 
1913 #define COUNTPAUSESTATTX_S    2
1914 #define COUNTPAUSESTATTX_V(x) ((x) << COUNTPAUSESTATTX_S)
1915 #define COUNTPAUSESTATTX_F    COUNTPAUSESTATTX_V(1U)
1916 
1917 #define NUMPORTS_S    0
1918 #define NUMPORTS_M    0x3U
1919 #define NUMPORTS_G(x) (((x) >> NUMPORTS_S) & NUMPORTS_M)
1920 
1921 #define MPS_INT_CAUSE_A 0x9008
1922 #define MPS_TX_INT_CAUSE_A 0x9408
1923 #define MPS_STAT_CTL_A 0x9600
1924 
1925 #define FRMERR_S    15
1926 #define FRMERR_V(x) ((x) << FRMERR_S)
1927 #define FRMERR_F    FRMERR_V(1U)
1928 
1929 #define SECNTERR_S    14
1930 #define SECNTERR_V(x) ((x) << SECNTERR_S)
1931 #define SECNTERR_F    SECNTERR_V(1U)
1932 
1933 #define BUBBLE_S    13
1934 #define BUBBLE_V(x) ((x) << BUBBLE_S)
1935 #define BUBBLE_F    BUBBLE_V(1U)
1936 
1937 #define TXDESCFIFO_S    9
1938 #define TXDESCFIFO_M    0xfU
1939 #define TXDESCFIFO_V(x) ((x) << TXDESCFIFO_S)
1940 
1941 #define TXDATAFIFO_S    5
1942 #define TXDATAFIFO_M    0xfU
1943 #define TXDATAFIFO_V(x) ((x) << TXDATAFIFO_S)
1944 
1945 #define NCSIFIFO_S    4
1946 #define NCSIFIFO_V(x) ((x) << NCSIFIFO_S)
1947 #define NCSIFIFO_F    NCSIFIFO_V(1U)
1948 
1949 #define TPFIFO_S    0
1950 #define TPFIFO_M    0xfU
1951 #define TPFIFO_V(x) ((x) << TPFIFO_S)
1952 
1953 #define MPS_STAT_PERR_INT_CAUSE_SRAM_A		0x9614
1954 #define MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A	0x9620
1955 #define MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A	0x962c
1956 
1957 #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640
1958 #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644
1959 #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648
1960 #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c
1961 #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650
1962 #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654
1963 #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658
1964 #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c
1965 #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660
1966 #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664
1967 #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668
1968 #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c
1969 #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670
1970 #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674
1971 #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678
1972 #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c
1973 #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680
1974 #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684
1975 #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688
1976 #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c
1977 #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690
1978 #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694
1979 #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698
1980 #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c
1981 #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0
1982 #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4
1983 #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8
1984 #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac
1985 #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0
1986 #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4
1987 #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8
1988 #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc
1989 
1990 #define MPS_TRC_CFG_A 0x9800
1991 
1992 #define TRCFIFOEMPTY_S    4
1993 #define TRCFIFOEMPTY_V(x) ((x) << TRCFIFOEMPTY_S)
1994 #define TRCFIFOEMPTY_F    TRCFIFOEMPTY_V(1U)
1995 
1996 #define TRCIGNOREDROPINPUT_S    3
1997 #define TRCIGNOREDROPINPUT_V(x) ((x) << TRCIGNOREDROPINPUT_S)
1998 #define TRCIGNOREDROPINPUT_F    TRCIGNOREDROPINPUT_V(1U)
1999 
2000 #define TRCKEEPDUPLICATES_S    2
2001 #define TRCKEEPDUPLICATES_V(x) ((x) << TRCKEEPDUPLICATES_S)
2002 #define TRCKEEPDUPLICATES_F    TRCKEEPDUPLICATES_V(1U)
2003 
2004 #define TRCEN_S    1
2005 #define TRCEN_V(x) ((x) << TRCEN_S)
2006 #define TRCEN_F    TRCEN_V(1U)
2007 
2008 #define TRCMULTIFILTER_S    0
2009 #define TRCMULTIFILTER_V(x) ((x) << TRCMULTIFILTER_S)
2010 #define TRCMULTIFILTER_F    TRCMULTIFILTER_V(1U)
2011 
2012 #define MPS_TRC_RSS_CONTROL_A		0x9808
2013 #define MPS_TRC_FILTER1_RSS_CONTROL_A	0x9ff4
2014 #define MPS_TRC_FILTER2_RSS_CONTROL_A	0x9ffc
2015 #define MPS_TRC_FILTER3_RSS_CONTROL_A	0xa004
2016 #define MPS_T5_TRC_RSS_CONTROL_A	0xa00c
2017 
2018 #define RSSCONTROL_S    16
2019 #define RSSCONTROL_V(x) ((x) << RSSCONTROL_S)
2020 
2021 #define QUEUENUMBER_S    0
2022 #define QUEUENUMBER_V(x) ((x) << QUEUENUMBER_S)
2023 
2024 #define TFINVERTMATCH_S    24
2025 #define TFINVERTMATCH_V(x) ((x) << TFINVERTMATCH_S)
2026 #define TFINVERTMATCH_F    TFINVERTMATCH_V(1U)
2027 
2028 #define TFEN_S    22
2029 #define TFEN_V(x) ((x) << TFEN_S)
2030 #define TFEN_F    TFEN_V(1U)
2031 
2032 #define TFPORT_S    18
2033 #define TFPORT_M    0xfU
2034 #define TFPORT_V(x) ((x) << TFPORT_S)
2035 #define TFPORT_G(x) (((x) >> TFPORT_S) & TFPORT_M)
2036 
2037 #define TFLENGTH_S    8
2038 #define TFLENGTH_M    0x1fU
2039 #define TFLENGTH_V(x) ((x) << TFLENGTH_S)
2040 #define TFLENGTH_G(x) (((x) >> TFLENGTH_S) & TFLENGTH_M)
2041 
2042 #define TFOFFSET_S    0
2043 #define TFOFFSET_M    0x1fU
2044 #define TFOFFSET_V(x) ((x) << TFOFFSET_S)
2045 #define TFOFFSET_G(x) (((x) >> TFOFFSET_S) & TFOFFSET_M)
2046 
2047 #define T5_TFINVERTMATCH_S    25
2048 #define T5_TFINVERTMATCH_V(x) ((x) << T5_TFINVERTMATCH_S)
2049 #define T5_TFINVERTMATCH_F    T5_TFINVERTMATCH_V(1U)
2050 
2051 #define T5_TFEN_S    23
2052 #define T5_TFEN_V(x) ((x) << T5_TFEN_S)
2053 #define T5_TFEN_F    T5_TFEN_V(1U)
2054 
2055 #define T5_TFPORT_S    18
2056 #define T5_TFPORT_M    0x1fU
2057 #define T5_TFPORT_V(x) ((x) << T5_TFPORT_S)
2058 #define T5_TFPORT_G(x) (((x) >> T5_TFPORT_S) & T5_TFPORT_M)
2059 
2060 #define MPS_TRC_FILTER_MATCH_CTL_A_A 0x9810
2061 #define MPS_TRC_FILTER_MATCH_CTL_B_A 0x9820
2062 
2063 #define TFMINPKTSIZE_S    16
2064 #define TFMINPKTSIZE_M    0x1ffU
2065 #define TFMINPKTSIZE_V(x) ((x) << TFMINPKTSIZE_S)
2066 #define TFMINPKTSIZE_G(x) (((x) >> TFMINPKTSIZE_S) & TFMINPKTSIZE_M)
2067 
2068 #define TFCAPTUREMAX_S    0
2069 #define TFCAPTUREMAX_M    0x3fffU
2070 #define TFCAPTUREMAX_V(x) ((x) << TFCAPTUREMAX_S)
2071 #define TFCAPTUREMAX_G(x) (((x) >> TFCAPTUREMAX_S) & TFCAPTUREMAX_M)
2072 
2073 #define MPS_TRC_FILTER0_MATCH_A 0x9c00
2074 #define MPS_TRC_FILTER0_DONT_CARE_A 0x9c80
2075 #define MPS_TRC_FILTER1_MATCH_A 0x9d00
2076 
2077 #define TP_RSS_CONFIG_A 0x7df0
2078 
2079 #define TNL4TUPENIPV6_S    31
2080 #define TNL4TUPENIPV6_V(x) ((x) << TNL4TUPENIPV6_S)
2081 #define TNL4TUPENIPV6_F    TNL4TUPENIPV6_V(1U)
2082 
2083 #define TNL2TUPENIPV6_S    30
2084 #define TNL2TUPENIPV6_V(x) ((x) << TNL2TUPENIPV6_S)
2085 #define TNL2TUPENIPV6_F    TNL2TUPENIPV6_V(1U)
2086 
2087 #define TNL4TUPENIPV4_S    29
2088 #define TNL4TUPENIPV4_V(x) ((x) << TNL4TUPENIPV4_S)
2089 #define TNL4TUPENIPV4_F    TNL4TUPENIPV4_V(1U)
2090 
2091 #define TNL2TUPENIPV4_S    28
2092 #define TNL2TUPENIPV4_V(x) ((x) << TNL2TUPENIPV4_S)
2093 #define TNL2TUPENIPV4_F    TNL2TUPENIPV4_V(1U)
2094 
2095 #define TNLTCPSEL_S    27
2096 #define TNLTCPSEL_V(x) ((x) << TNLTCPSEL_S)
2097 #define TNLTCPSEL_F    TNLTCPSEL_V(1U)
2098 
2099 #define TNLIP6SEL_S    26
2100 #define TNLIP6SEL_V(x) ((x) << TNLIP6SEL_S)
2101 #define TNLIP6SEL_F    TNLIP6SEL_V(1U)
2102 
2103 #define TNLVRTSEL_S    25
2104 #define TNLVRTSEL_V(x) ((x) << TNLVRTSEL_S)
2105 #define TNLVRTSEL_F    TNLVRTSEL_V(1U)
2106 
2107 #define TNLMAPEN_S    24
2108 #define TNLMAPEN_V(x) ((x) << TNLMAPEN_S)
2109 #define TNLMAPEN_F    TNLMAPEN_V(1U)
2110 
2111 #define OFDHASHSAVE_S    19
2112 #define OFDHASHSAVE_V(x) ((x) << OFDHASHSAVE_S)
2113 #define OFDHASHSAVE_F    OFDHASHSAVE_V(1U)
2114 
2115 #define OFDVRTSEL_S    18
2116 #define OFDVRTSEL_V(x) ((x) << OFDVRTSEL_S)
2117 #define OFDVRTSEL_F    OFDVRTSEL_V(1U)
2118 
2119 #define OFDMAPEN_S    17
2120 #define OFDMAPEN_V(x) ((x) << OFDMAPEN_S)
2121 #define OFDMAPEN_F    OFDMAPEN_V(1U)
2122 
2123 #define OFDLKPEN_S    16
2124 #define OFDLKPEN_V(x) ((x) << OFDLKPEN_S)
2125 #define OFDLKPEN_F    OFDLKPEN_V(1U)
2126 
2127 #define SYN4TUPENIPV6_S    15
2128 #define SYN4TUPENIPV6_V(x) ((x) << SYN4TUPENIPV6_S)
2129 #define SYN4TUPENIPV6_F    SYN4TUPENIPV6_V(1U)
2130 
2131 #define SYN2TUPENIPV6_S    14
2132 #define SYN2TUPENIPV6_V(x) ((x) << SYN2TUPENIPV6_S)
2133 #define SYN2TUPENIPV6_F    SYN2TUPENIPV6_V(1U)
2134 
2135 #define SYN4TUPENIPV4_S    13
2136 #define SYN4TUPENIPV4_V(x) ((x) << SYN4TUPENIPV4_S)
2137 #define SYN4TUPENIPV4_F    SYN4TUPENIPV4_V(1U)
2138 
2139 #define SYN2TUPENIPV4_S    12
2140 #define SYN2TUPENIPV4_V(x) ((x) << SYN2TUPENIPV4_S)
2141 #define SYN2TUPENIPV4_F    SYN2TUPENIPV4_V(1U)
2142 
2143 #define SYNIP6SEL_S    11
2144 #define SYNIP6SEL_V(x) ((x) << SYNIP6SEL_S)
2145 #define SYNIP6SEL_F    SYNIP6SEL_V(1U)
2146 
2147 #define SYNVRTSEL_S    10
2148 #define SYNVRTSEL_V(x) ((x) << SYNVRTSEL_S)
2149 #define SYNVRTSEL_F    SYNVRTSEL_V(1U)
2150 
2151 #define SYNMAPEN_S    9
2152 #define SYNMAPEN_V(x) ((x) << SYNMAPEN_S)
2153 #define SYNMAPEN_F    SYNMAPEN_V(1U)
2154 
2155 #define SYNLKPEN_S    8
2156 #define SYNLKPEN_V(x) ((x) << SYNLKPEN_S)
2157 #define SYNLKPEN_F    SYNLKPEN_V(1U)
2158 
2159 #define CHANNELENABLE_S    7
2160 #define CHANNELENABLE_V(x) ((x) << CHANNELENABLE_S)
2161 #define CHANNELENABLE_F    CHANNELENABLE_V(1U)
2162 
2163 #define PORTENABLE_S    6
2164 #define PORTENABLE_V(x) ((x) << PORTENABLE_S)
2165 #define PORTENABLE_F    PORTENABLE_V(1U)
2166 
2167 #define TNLALLLOOKUP_S    5
2168 #define TNLALLLOOKUP_V(x) ((x) << TNLALLLOOKUP_S)
2169 #define TNLALLLOOKUP_F    TNLALLLOOKUP_V(1U)
2170 
2171 #define VIRTENABLE_S    4
2172 #define VIRTENABLE_V(x) ((x) << VIRTENABLE_S)
2173 #define VIRTENABLE_F    VIRTENABLE_V(1U)
2174 
2175 #define CONGESTIONENABLE_S    3
2176 #define CONGESTIONENABLE_V(x) ((x) << CONGESTIONENABLE_S)
2177 #define CONGESTIONENABLE_F    CONGESTIONENABLE_V(1U)
2178 
2179 #define HASHTOEPLITZ_S    2
2180 #define HASHTOEPLITZ_V(x) ((x) << HASHTOEPLITZ_S)
2181 #define HASHTOEPLITZ_F    HASHTOEPLITZ_V(1U)
2182 
2183 #define UDPENABLE_S    1
2184 #define UDPENABLE_V(x) ((x) << UDPENABLE_S)
2185 #define UDPENABLE_F    UDPENABLE_V(1U)
2186 
2187 #define DISABLE_S    0
2188 #define DISABLE_V(x) ((x) << DISABLE_S)
2189 #define DISABLE_F    DISABLE_V(1U)
2190 
2191 #define TP_RSS_CONFIG_TNL_A 0x7df4
2192 
2193 #define MASKSIZE_S    28
2194 #define MASKSIZE_M    0xfU
2195 #define MASKSIZE_V(x) ((x) << MASKSIZE_S)
2196 #define MASKSIZE_G(x) (((x) >> MASKSIZE_S) & MASKSIZE_M)
2197 
2198 #define MASKFILTER_S    16
2199 #define MASKFILTER_M    0x7ffU
2200 #define MASKFILTER_V(x) ((x) << MASKFILTER_S)
2201 #define MASKFILTER_G(x) (((x) >> MASKFILTER_S) & MASKFILTER_M)
2202 
2203 #define USEWIRECH_S    0
2204 #define USEWIRECH_V(x) ((x) << USEWIRECH_S)
2205 #define USEWIRECH_F    USEWIRECH_V(1U)
2206 
2207 #define HASHALL_S    2
2208 #define HASHALL_V(x) ((x) << HASHALL_S)
2209 #define HASHALL_F    HASHALL_V(1U)
2210 
2211 #define HASHETH_S    1
2212 #define HASHETH_V(x) ((x) << HASHETH_S)
2213 #define HASHETH_F    HASHETH_V(1U)
2214 
2215 #define TP_RSS_CONFIG_OFD_A 0x7df8
2216 
2217 #define RRCPLMAPEN_S    20
2218 #define RRCPLMAPEN_V(x) ((x) << RRCPLMAPEN_S)
2219 #define RRCPLMAPEN_F    RRCPLMAPEN_V(1U)
2220 
2221 #define RRCPLQUEWIDTH_S    16
2222 #define RRCPLQUEWIDTH_M    0xfU
2223 #define RRCPLQUEWIDTH_V(x) ((x) << RRCPLQUEWIDTH_S)
2224 #define RRCPLQUEWIDTH_G(x) (((x) >> RRCPLQUEWIDTH_S) & RRCPLQUEWIDTH_M)
2225 
2226 #define TP_RSS_CONFIG_SYN_A 0x7dfc
2227 #define TP_RSS_CONFIG_VRT_A 0x7e00
2228 
2229 #define VFRDRG_S    25
2230 #define VFRDRG_V(x) ((x) << VFRDRG_S)
2231 #define VFRDRG_F    VFRDRG_V(1U)
2232 
2233 #define VFRDEN_S    24
2234 #define VFRDEN_V(x) ((x) << VFRDEN_S)
2235 #define VFRDEN_F    VFRDEN_V(1U)
2236 
2237 #define VFPERREN_S    23
2238 #define VFPERREN_V(x) ((x) << VFPERREN_S)
2239 #define VFPERREN_F    VFPERREN_V(1U)
2240 
2241 #define KEYPERREN_S    22
2242 #define KEYPERREN_V(x) ((x) << KEYPERREN_S)
2243 #define KEYPERREN_F    KEYPERREN_V(1U)
2244 
2245 #define DISABLEVLAN_S    21
2246 #define DISABLEVLAN_V(x) ((x) << DISABLEVLAN_S)
2247 #define DISABLEVLAN_F    DISABLEVLAN_V(1U)
2248 
2249 #define ENABLEUP0_S    20
2250 #define ENABLEUP0_V(x) ((x) << ENABLEUP0_S)
2251 #define ENABLEUP0_F    ENABLEUP0_V(1U)
2252 
2253 #define HASHDELAY_S    16
2254 #define HASHDELAY_M    0xfU
2255 #define HASHDELAY_V(x) ((x) << HASHDELAY_S)
2256 #define HASHDELAY_G(x) (((x) >> HASHDELAY_S) & HASHDELAY_M)
2257 
2258 #define VFWRADDR_S    8
2259 #define VFWRADDR_M    0x7fU
2260 #define VFWRADDR_V(x) ((x) << VFWRADDR_S)
2261 #define VFWRADDR_G(x) (((x) >> VFWRADDR_S) & VFWRADDR_M)
2262 
2263 #define KEYMODE_S    6
2264 #define KEYMODE_M    0x3U
2265 #define KEYMODE_V(x) ((x) << KEYMODE_S)
2266 #define KEYMODE_G(x) (((x) >> KEYMODE_S) & KEYMODE_M)
2267 
2268 #define VFWREN_S    5
2269 #define VFWREN_V(x) ((x) << VFWREN_S)
2270 #define VFWREN_F    VFWREN_V(1U)
2271 
2272 #define KEYWREN_S    4
2273 #define KEYWREN_V(x) ((x) << KEYWREN_S)
2274 #define KEYWREN_F    KEYWREN_V(1U)
2275 
2276 #define KEYWRADDR_S    0
2277 #define KEYWRADDR_M    0xfU
2278 #define KEYWRADDR_V(x) ((x) << KEYWRADDR_S)
2279 #define KEYWRADDR_G(x) (((x) >> KEYWRADDR_S) & KEYWRADDR_M)
2280 
2281 #define KEYWRADDRX_S    30
2282 #define KEYWRADDRX_M    0x3U
2283 #define KEYWRADDRX_V(x) ((x) << KEYWRADDRX_S)
2284 #define KEYWRADDRX_G(x) (((x) >> KEYWRADDRX_S) & KEYWRADDRX_M)
2285 
2286 #define KEYEXTEND_S    26
2287 #define KEYEXTEND_V(x) ((x) << KEYEXTEND_S)
2288 #define KEYEXTEND_F    KEYEXTEND_V(1U)
2289 
2290 #define LKPIDXSIZE_S    24
2291 #define LKPIDXSIZE_M    0x3U
2292 #define LKPIDXSIZE_V(x) ((x) << LKPIDXSIZE_S)
2293 #define LKPIDXSIZE_G(x) (((x) >> LKPIDXSIZE_S) & LKPIDXSIZE_M)
2294 
2295 #define TP_RSS_VFL_CONFIG_A 0x3a
2296 #define TP_RSS_VFH_CONFIG_A 0x3b
2297 
2298 #define ENABLEUDPHASH_S    31
2299 #define ENABLEUDPHASH_V(x) ((x) << ENABLEUDPHASH_S)
2300 #define ENABLEUDPHASH_F    ENABLEUDPHASH_V(1U)
2301 
2302 #define VFUPEN_S    30
2303 #define VFUPEN_V(x) ((x) << VFUPEN_S)
2304 #define VFUPEN_F    VFUPEN_V(1U)
2305 
2306 #define VFVLNEX_S    28
2307 #define VFVLNEX_V(x) ((x) << VFVLNEX_S)
2308 #define VFVLNEX_F    VFVLNEX_V(1U)
2309 
2310 #define VFPRTEN_S    27
2311 #define VFPRTEN_V(x) ((x) << VFPRTEN_S)
2312 #define VFPRTEN_F    VFPRTEN_V(1U)
2313 
2314 #define VFCHNEN_S    26
2315 #define VFCHNEN_V(x) ((x) << VFCHNEN_S)
2316 #define VFCHNEN_F    VFCHNEN_V(1U)
2317 
2318 #define DEFAULTQUEUE_S    16
2319 #define DEFAULTQUEUE_M    0x3ffU
2320 #define DEFAULTQUEUE_G(x) (((x) >> DEFAULTQUEUE_S) & DEFAULTQUEUE_M)
2321 
2322 #define VFIP6TWOTUPEN_S    6
2323 #define VFIP6TWOTUPEN_V(x) ((x) << VFIP6TWOTUPEN_S)
2324 #define VFIP6TWOTUPEN_F    VFIP6TWOTUPEN_V(1U)
2325 
2326 #define VFIP4FOURTUPEN_S    5
2327 #define VFIP4FOURTUPEN_V(x) ((x) << VFIP4FOURTUPEN_S)
2328 #define VFIP4FOURTUPEN_F    VFIP4FOURTUPEN_V(1U)
2329 
2330 #define VFIP4TWOTUPEN_S    4
2331 #define VFIP4TWOTUPEN_V(x) ((x) << VFIP4TWOTUPEN_S)
2332 #define VFIP4TWOTUPEN_F    VFIP4TWOTUPEN_V(1U)
2333 
2334 #define KEYINDEX_S    0
2335 #define KEYINDEX_M    0xfU
2336 #define KEYINDEX_G(x) (((x) >> KEYINDEX_S) & KEYINDEX_M)
2337 
2338 #define MAPENABLE_S    31
2339 #define MAPENABLE_V(x) ((x) << MAPENABLE_S)
2340 #define MAPENABLE_F    MAPENABLE_V(1U)
2341 
2342 #define CHNENABLE_S    30
2343 #define CHNENABLE_V(x) ((x) << CHNENABLE_S)
2344 #define CHNENABLE_F    CHNENABLE_V(1U)
2345 
2346 #define LE_DB_DBGI_CONFIG_A 0x19cf0
2347 
2348 #define DBGICMDBUSY_S    3
2349 #define DBGICMDBUSY_V(x) ((x) << DBGICMDBUSY_S)
2350 #define DBGICMDBUSY_F    DBGICMDBUSY_V(1U)
2351 
2352 #define DBGICMDSTRT_S    2
2353 #define DBGICMDSTRT_V(x) ((x) << DBGICMDSTRT_S)
2354 #define DBGICMDSTRT_F    DBGICMDSTRT_V(1U)
2355 
2356 #define DBGICMDMODE_S    0
2357 #define DBGICMDMODE_M    0x3U
2358 #define DBGICMDMODE_V(x) ((x) << DBGICMDMODE_S)
2359 
2360 #define LE_DB_DBGI_REQ_TCAM_CMD_A 0x19cf4
2361 
2362 #define DBGICMD_S    20
2363 #define DBGICMD_M    0xfU
2364 #define DBGICMD_V(x) ((x) << DBGICMD_S)
2365 
2366 #define DBGITID_S    0
2367 #define DBGITID_M    0xfffffU
2368 #define DBGITID_V(x) ((x) << DBGITID_S)
2369 
2370 #define LE_DB_DBGI_REQ_DATA_A 0x19d00
2371 #define LE_DB_DBGI_RSP_STATUS_A 0x19d94
2372 
2373 #define LE_DB_DBGI_RSP_DATA_A 0x19da0
2374 
2375 #define PRTENABLE_S    29
2376 #define PRTENABLE_V(x) ((x) << PRTENABLE_S)
2377 #define PRTENABLE_F    PRTENABLE_V(1U)
2378 
2379 #define UDPFOURTUPEN_S    28
2380 #define UDPFOURTUPEN_V(x) ((x) << UDPFOURTUPEN_S)
2381 #define UDPFOURTUPEN_F    UDPFOURTUPEN_V(1U)
2382 
2383 #define IP6FOURTUPEN_S    27
2384 #define IP6FOURTUPEN_V(x) ((x) << IP6FOURTUPEN_S)
2385 #define IP6FOURTUPEN_F    IP6FOURTUPEN_V(1U)
2386 
2387 #define IP6TWOTUPEN_S    26
2388 #define IP6TWOTUPEN_V(x) ((x) << IP6TWOTUPEN_S)
2389 #define IP6TWOTUPEN_F    IP6TWOTUPEN_V(1U)
2390 
2391 #define IP4FOURTUPEN_S    25
2392 #define IP4FOURTUPEN_V(x) ((x) << IP4FOURTUPEN_S)
2393 #define IP4FOURTUPEN_F    IP4FOURTUPEN_V(1U)
2394 
2395 #define IP4TWOTUPEN_S    24
2396 #define IP4TWOTUPEN_V(x) ((x) << IP4TWOTUPEN_S)
2397 #define IP4TWOTUPEN_F    IP4TWOTUPEN_V(1U)
2398 
2399 #define IVFWIDTH_S    20
2400 #define IVFWIDTH_M    0xfU
2401 #define IVFWIDTH_V(x) ((x) << IVFWIDTH_S)
2402 #define IVFWIDTH_G(x) (((x) >> IVFWIDTH_S) & IVFWIDTH_M)
2403 
2404 #define CH1DEFAULTQUEUE_S    10
2405 #define CH1DEFAULTQUEUE_M    0x3ffU
2406 #define CH1DEFAULTQUEUE_V(x) ((x) << CH1DEFAULTQUEUE_S)
2407 #define CH1DEFAULTQUEUE_G(x) (((x) >> CH1DEFAULTQUEUE_S) & CH1DEFAULTQUEUE_M)
2408 
2409 #define CH0DEFAULTQUEUE_S    0
2410 #define CH0DEFAULTQUEUE_M    0x3ffU
2411 #define CH0DEFAULTQUEUE_V(x) ((x) << CH0DEFAULTQUEUE_S)
2412 #define CH0DEFAULTQUEUE_G(x) (((x) >> CH0DEFAULTQUEUE_S) & CH0DEFAULTQUEUE_M)
2413 
2414 #define VFLKPIDX_S    8
2415 #define VFLKPIDX_M    0xffU
2416 #define VFLKPIDX_G(x) (((x) >> VFLKPIDX_S) & VFLKPIDX_M)
2417 
2418 #define T6_VFWRADDR_S    8
2419 #define T6_VFWRADDR_M    0xffU
2420 #define T6_VFWRADDR_V(x) ((x) << T6_VFWRADDR_S)
2421 #define T6_VFWRADDR_G(x) (((x) >> T6_VFWRADDR_S) & T6_VFWRADDR_M)
2422 
2423 #define TP_RSS_CONFIG_CNG_A 0x7e04
2424 #define TP_RSS_SECRET_KEY0_A 0x40
2425 #define TP_RSS_PF0_CONFIG_A 0x30
2426 #define TP_RSS_PF_MAP_A 0x38
2427 #define TP_RSS_PF_MSK_A 0x39
2428 
2429 #define PF1LKPIDX_S    3
2430 
2431 #define PF0LKPIDX_M    0x7U
2432 
2433 #define PF1MSKSIZE_S    4
2434 #define PF1MSKSIZE_M    0xfU
2435 
2436 #define CHNCOUNT3_S    31
2437 #define CHNCOUNT3_V(x) ((x) << CHNCOUNT3_S)
2438 #define CHNCOUNT3_F    CHNCOUNT3_V(1U)
2439 
2440 #define CHNCOUNT2_S    30
2441 #define CHNCOUNT2_V(x) ((x) << CHNCOUNT2_S)
2442 #define CHNCOUNT2_F    CHNCOUNT2_V(1U)
2443 
2444 #define CHNCOUNT1_S    29
2445 #define CHNCOUNT1_V(x) ((x) << CHNCOUNT1_S)
2446 #define CHNCOUNT1_F    CHNCOUNT1_V(1U)
2447 
2448 #define CHNCOUNT0_S    28
2449 #define CHNCOUNT0_V(x) ((x) << CHNCOUNT0_S)
2450 #define CHNCOUNT0_F    CHNCOUNT0_V(1U)
2451 
2452 #define CHNUNDFLOW3_S    27
2453 #define CHNUNDFLOW3_V(x) ((x) << CHNUNDFLOW3_S)
2454 #define CHNUNDFLOW3_F    CHNUNDFLOW3_V(1U)
2455 
2456 #define CHNUNDFLOW2_S    26
2457 #define CHNUNDFLOW2_V(x) ((x) << CHNUNDFLOW2_S)
2458 #define CHNUNDFLOW2_F    CHNUNDFLOW2_V(1U)
2459 
2460 #define CHNUNDFLOW1_S    25
2461 #define CHNUNDFLOW1_V(x) ((x) << CHNUNDFLOW1_S)
2462 #define CHNUNDFLOW1_F    CHNUNDFLOW1_V(1U)
2463 
2464 #define CHNUNDFLOW0_S    24
2465 #define CHNUNDFLOW0_V(x) ((x) << CHNUNDFLOW0_S)
2466 #define CHNUNDFLOW0_F    CHNUNDFLOW0_V(1U)
2467 
2468 #define RSTCHN3_S    19
2469 #define RSTCHN3_V(x) ((x) << RSTCHN3_S)
2470 #define RSTCHN3_F    RSTCHN3_V(1U)
2471 
2472 #define RSTCHN2_S    18
2473 #define RSTCHN2_V(x) ((x) << RSTCHN2_S)
2474 #define RSTCHN2_F    RSTCHN2_V(1U)
2475 
2476 #define RSTCHN1_S    17
2477 #define RSTCHN1_V(x) ((x) << RSTCHN1_S)
2478 #define RSTCHN1_F    RSTCHN1_V(1U)
2479 
2480 #define RSTCHN0_S    16
2481 #define RSTCHN0_V(x) ((x) << RSTCHN0_S)
2482 #define RSTCHN0_F    RSTCHN0_V(1U)
2483 
2484 #define UPDVLD_S    15
2485 #define UPDVLD_V(x) ((x) << UPDVLD_S)
2486 #define UPDVLD_F    UPDVLD_V(1U)
2487 
2488 #define XOFF_S    14
2489 #define XOFF_V(x) ((x) << XOFF_S)
2490 #define XOFF_F    XOFF_V(1U)
2491 
2492 #define UPDCHN3_S    13
2493 #define UPDCHN3_V(x) ((x) << UPDCHN3_S)
2494 #define UPDCHN3_F    UPDCHN3_V(1U)
2495 
2496 #define UPDCHN2_S    12
2497 #define UPDCHN2_V(x) ((x) << UPDCHN2_S)
2498 #define UPDCHN2_F    UPDCHN2_V(1U)
2499 
2500 #define UPDCHN1_S    11
2501 #define UPDCHN1_V(x) ((x) << UPDCHN1_S)
2502 #define UPDCHN1_F    UPDCHN1_V(1U)
2503 
2504 #define UPDCHN0_S    10
2505 #define UPDCHN0_V(x) ((x) << UPDCHN0_S)
2506 #define UPDCHN0_F    UPDCHN0_V(1U)
2507 
2508 #define QUEUE_S    0
2509 #define QUEUE_M    0x3ffU
2510 #define QUEUE_V(x) ((x) << QUEUE_S)
2511 #define QUEUE_G(x) (((x) >> QUEUE_S) & QUEUE_M)
2512 
2513 #define MPS_TRC_INT_CAUSE_A	0x985c
2514 
2515 #define MISCPERR_S    8
2516 #define MISCPERR_V(x) ((x) << MISCPERR_S)
2517 #define MISCPERR_F    MISCPERR_V(1U)
2518 
2519 #define PKTFIFO_S    4
2520 #define PKTFIFO_M    0xfU
2521 #define PKTFIFO_V(x) ((x) << PKTFIFO_S)
2522 
2523 #define FILTMEM_S    0
2524 #define FILTMEM_M    0xfU
2525 #define FILTMEM_V(x) ((x) << FILTMEM_S)
2526 
2527 #define MPS_CLS_INT_CAUSE_A 0xd028
2528 
2529 #define HASHSRAM_S    2
2530 #define HASHSRAM_V(x) ((x) << HASHSRAM_S)
2531 #define HASHSRAM_F    HASHSRAM_V(1U)
2532 
2533 #define MATCHTCAM_S    1
2534 #define MATCHTCAM_V(x) ((x) << MATCHTCAM_S)
2535 #define MATCHTCAM_F    MATCHTCAM_V(1U)
2536 
2537 #define MATCHSRAM_S    0
2538 #define MATCHSRAM_V(x) ((x) << MATCHSRAM_S)
2539 #define MATCHSRAM_F    MATCHSRAM_V(1U)
2540 
2541 #define MPS_RX_PG_RSV0_A 0x11010
2542 #define MPS_RX_PG_RSV4_A 0x11020
2543 #define MPS_RX_PERR_INT_CAUSE_A 0x11074
2544 #define MPS_RX_MAC_BG_PG_CNT0_A 0x11208
2545 #define MPS_RX_LPBK_BG_PG_CNT0_A 0x11218
2546 
2547 #define MPS_RX_VXLAN_TYPE_A 0x11234
2548 
2549 #define VXLAN_EN_S    16
2550 #define VXLAN_EN_V(x) ((x) << VXLAN_EN_S)
2551 #define VXLAN_EN_F    VXLAN_EN_V(1U)
2552 
2553 #define VXLAN_S    0
2554 #define VXLAN_M    0xffffU
2555 #define VXLAN_V(x) ((x) << VXLAN_S)
2556 #define VXLAN_G(x) (((x) >> VXLAN_S) & VXLAN_M)
2557 
2558 #define MPS_RX_GENEVE_TYPE_A 0x11238
2559 
2560 #define GENEVE_EN_S    16
2561 #define GENEVE_EN_V(x) ((x) << GENEVE_EN_S)
2562 #define GENEVE_EN_F    GENEVE_EN_V(1U)
2563 
2564 #define GENEVE_S    0
2565 #define GENEVE_M    0xffffU
2566 #define GENEVE_V(x) ((x) << GENEVE_S)
2567 #define GENEVE_G(x) (((x) >> GENEVE_S) & GENEVE_M)
2568 
2569 #define MPS_CLS_TCAM_Y_L_A 0xf000
2570 #define MPS_CLS_TCAM_DATA0_A 0xf000
2571 #define MPS_CLS_TCAM_DATA1_A 0xf004
2572 
2573 #define CTLREQID_S    30
2574 #define CTLREQID_V(x) ((x) << CTLREQID_S)
2575 
2576 #define MPS_VF_RPLCT_MAP0_A 0x1111c
2577 #define MPS_VF_RPLCT_MAP1_A 0x11120
2578 #define MPS_VF_RPLCT_MAP2_A 0x11124
2579 #define MPS_VF_RPLCT_MAP3_A 0x11128
2580 #define MPS_VF_RPLCT_MAP4_A 0x11300
2581 #define MPS_VF_RPLCT_MAP5_A 0x11304
2582 #define MPS_VF_RPLCT_MAP6_A 0x11308
2583 #define MPS_VF_RPLCT_MAP7_A 0x1130c
2584 
2585 #define VIDL_S    16
2586 #define VIDL_M    0xffffU
2587 #define VIDL_G(x) (((x) >> VIDL_S) & VIDL_M)
2588 
2589 #define DATALKPTYPE_S    10
2590 #define DATALKPTYPE_M    0x3U
2591 #define DATALKPTYPE_G(x) (((x) >> DATALKPTYPE_S) & DATALKPTYPE_M)
2592 
2593 #define DATAPORTNUM_S    12
2594 #define DATAPORTNUM_M    0xfU
2595 #define DATAPORTNUM_V(x) ((x) << DATAPORTNUM_S)
2596 #define DATAPORTNUM_G(x) (((x) >> DATAPORTNUM_S) & DATAPORTNUM_M)
2597 
2598 #define DATALKPTYPE_S    10
2599 #define DATALKPTYPE_M    0x3U
2600 #define DATALKPTYPE_V(x) ((x) << DATALKPTYPE_S)
2601 #define DATALKPTYPE_G(x) (((x) >> DATALKPTYPE_S) & DATALKPTYPE_M)
2602 
2603 #define DATADIPHIT_S    8
2604 #define DATADIPHIT_V(x) ((x) << DATADIPHIT_S)
2605 #define DATADIPHIT_F    DATADIPHIT_V(1U)
2606 
2607 #define DATAVIDH2_S    7
2608 #define DATAVIDH2_V(x) ((x) << DATAVIDH2_S)
2609 #define DATAVIDH2_F    DATAVIDH2_V(1U)
2610 
2611 #define DATAVIDH1_S    0
2612 #define DATAVIDH1_M    0x7fU
2613 #define DATAVIDH1_G(x) (((x) >> DATAVIDH1_S) & DATAVIDH1_M)
2614 
2615 #define MPS_CLS_TCAM_RDATA0_REQ_ID1_A 0xf020
2616 #define MPS_CLS_TCAM_RDATA1_REQ_ID1_A 0xf024
2617 #define MPS_CLS_TCAM_RDATA2_REQ_ID1_A 0xf028
2618 
2619 #define USED_S    16
2620 #define USED_M    0x7ffU
2621 #define USED_G(x) (((x) >> USED_S) & USED_M)
2622 
2623 #define ALLOC_S    0
2624 #define ALLOC_M    0x7ffU
2625 #define ALLOC_G(x) (((x) >> ALLOC_S) & ALLOC_M)
2626 
2627 #define T5_USED_S    16
2628 #define T5_USED_M    0xfffU
2629 #define T5_USED_G(x) (((x) >> T5_USED_S) & T5_USED_M)
2630 
2631 #define T5_ALLOC_S    0
2632 #define T5_ALLOC_M    0xfffU
2633 #define T5_ALLOC_G(x) (((x) >> T5_ALLOC_S) & T5_ALLOC_M)
2634 
2635 #define DMACH_S    0
2636 #define DMACH_M    0xffffU
2637 #define DMACH_G(x) (((x) >> DMACH_S) & DMACH_M)
2638 
2639 #define MPS_CLS_TCAM_X_L_A 0xf008
2640 #define MPS_CLS_TCAM_DATA2_CTL_A 0xf008
2641 
2642 #define CTLCMDTYPE_S    31
2643 #define CTLCMDTYPE_V(x) ((x) << CTLCMDTYPE_S)
2644 #define CTLCMDTYPE_F    CTLCMDTYPE_V(1U)
2645 
2646 #define CTLTCAMSEL_S    25
2647 #define CTLTCAMSEL_V(x) ((x) << CTLTCAMSEL_S)
2648 
2649 #define CTLTCAMINDEX_S    17
2650 #define CTLTCAMINDEX_V(x) ((x) << CTLTCAMINDEX_S)
2651 
2652 #define CTLXYBITSEL_S    16
2653 #define CTLXYBITSEL_V(x) ((x) << CTLXYBITSEL_S)
2654 
2655 #define MPS_CLS_TCAM_Y_L(idx) (MPS_CLS_TCAM_Y_L_A + (idx) * 16)
2656 #define NUM_MPS_CLS_TCAM_Y_L_INSTANCES 512
2657 
2658 #define MPS_CLS_TCAM_X_L(idx) (MPS_CLS_TCAM_X_L_A + (idx) * 16)
2659 #define NUM_MPS_CLS_TCAM_X_L_INSTANCES 512
2660 
2661 #define MPS_CLS_SRAM_L_A 0xe000
2662 
2663 #define T6_MULTILISTEN0_S    26
2664 
2665 #define T6_SRAM_PRIO3_S    23
2666 #define T6_SRAM_PRIO3_M    0x7U
2667 #define T6_SRAM_PRIO3_G(x) (((x) >> T6_SRAM_PRIO3_S) & T6_SRAM_PRIO3_M)
2668 
2669 #define T6_SRAM_PRIO2_S    20
2670 #define T6_SRAM_PRIO2_M    0x7U
2671 #define T6_SRAM_PRIO2_G(x) (((x) >> T6_SRAM_PRIO2_S) & T6_SRAM_PRIO2_M)
2672 
2673 #define T6_SRAM_PRIO1_S    17
2674 #define T6_SRAM_PRIO1_M    0x7U
2675 #define T6_SRAM_PRIO1_G(x) (((x) >> T6_SRAM_PRIO1_S) & T6_SRAM_PRIO1_M)
2676 
2677 #define T6_SRAM_PRIO0_S    14
2678 #define T6_SRAM_PRIO0_M    0x7U
2679 #define T6_SRAM_PRIO0_G(x) (((x) >> T6_SRAM_PRIO0_S) & T6_SRAM_PRIO0_M)
2680 
2681 #define T6_SRAM_VLD_S    13
2682 #define T6_SRAM_VLD_V(x) ((x) << T6_SRAM_VLD_S)
2683 #define T6_SRAM_VLD_F    T6_SRAM_VLD_V(1U)
2684 
2685 #define T6_REPLICATE_S    12
2686 #define T6_REPLICATE_V(x) ((x) << T6_REPLICATE_S)
2687 #define T6_REPLICATE_F    T6_REPLICATE_V(1U)
2688 
2689 #define T6_PF_S    9
2690 #define T6_PF_M    0x7U
2691 #define T6_PF_G(x) (((x) >> T6_PF_S) & T6_PF_M)
2692 
2693 #define T6_VF_VALID_S    8
2694 #define T6_VF_VALID_V(x) ((x) << T6_VF_VALID_S)
2695 #define T6_VF_VALID_F    T6_VF_VALID_V(1U)
2696 
2697 #define T6_VF_S    0
2698 #define T6_VF_M    0xffU
2699 #define T6_VF_G(x) (((x) >> T6_VF_S) & T6_VF_M)
2700 
2701 #define MPS_CLS_SRAM_H_A 0xe004
2702 
2703 #define MPS_CLS_SRAM_L(idx) (MPS_CLS_SRAM_L_A + (idx) * 8)
2704 #define NUM_MPS_CLS_SRAM_L_INSTANCES 336
2705 
2706 #define MPS_CLS_SRAM_H(idx) (MPS_CLS_SRAM_H_A + (idx) * 8)
2707 #define NUM_MPS_CLS_SRAM_H_INSTANCES 336
2708 
2709 #define MULTILISTEN0_S    25
2710 
2711 #define REPLICATE_S    11
2712 #define REPLICATE_V(x) ((x) << REPLICATE_S)
2713 #define REPLICATE_F    REPLICATE_V(1U)
2714 
2715 #define PF_S    8
2716 #define PF_M    0x7U
2717 #define PF_G(x) (((x) >> PF_S) & PF_M)
2718 
2719 #define VF_VALID_S    7
2720 #define VF_VALID_V(x) ((x) << VF_VALID_S)
2721 #define VF_VALID_F    VF_VALID_V(1U)
2722 
2723 #define VF_S    0
2724 #define VF_M    0x7fU
2725 #define VF_G(x) (((x) >> VF_S) & VF_M)
2726 
2727 #define SRAM_PRIO3_S    22
2728 #define SRAM_PRIO3_M    0x7U
2729 #define SRAM_PRIO3_G(x) (((x) >> SRAM_PRIO3_S) & SRAM_PRIO3_M)
2730 
2731 #define SRAM_PRIO2_S    19
2732 #define SRAM_PRIO2_M    0x7U
2733 #define SRAM_PRIO2_G(x) (((x) >> SRAM_PRIO2_S) & SRAM_PRIO2_M)
2734 
2735 #define SRAM_PRIO1_S    16
2736 #define SRAM_PRIO1_M    0x7U
2737 #define SRAM_PRIO1_G(x) (((x) >> SRAM_PRIO1_S) & SRAM_PRIO1_M)
2738 
2739 #define SRAM_PRIO0_S    13
2740 #define SRAM_PRIO0_M    0x7U
2741 #define SRAM_PRIO0_G(x) (((x) >> SRAM_PRIO0_S) & SRAM_PRIO0_M)
2742 
2743 #define SRAM_VLD_S    12
2744 #define SRAM_VLD_V(x) ((x) << SRAM_VLD_S)
2745 #define SRAM_VLD_F    SRAM_VLD_V(1U)
2746 
2747 #define PORTMAP_S    0
2748 #define PORTMAP_M    0xfU
2749 #define PORTMAP_G(x) (((x) >> PORTMAP_S) & PORTMAP_M)
2750 
2751 #define CPL_INTR_CAUSE_A 0x19054
2752 
2753 #define CIM_OP_MAP_PERR_S    5
2754 #define CIM_OP_MAP_PERR_V(x) ((x) << CIM_OP_MAP_PERR_S)
2755 #define CIM_OP_MAP_PERR_F    CIM_OP_MAP_PERR_V(1U)
2756 
2757 #define CIM_OVFL_ERROR_S    4
2758 #define CIM_OVFL_ERROR_V(x) ((x) << CIM_OVFL_ERROR_S)
2759 #define CIM_OVFL_ERROR_F    CIM_OVFL_ERROR_V(1U)
2760 
2761 #define TP_FRAMING_ERROR_S    3
2762 #define TP_FRAMING_ERROR_V(x) ((x) << TP_FRAMING_ERROR_S)
2763 #define TP_FRAMING_ERROR_F    TP_FRAMING_ERROR_V(1U)
2764 
2765 #define SGE_FRAMING_ERROR_S    2
2766 #define SGE_FRAMING_ERROR_V(x) ((x) << SGE_FRAMING_ERROR_S)
2767 #define SGE_FRAMING_ERROR_F    SGE_FRAMING_ERROR_V(1U)
2768 
2769 #define CIM_FRAMING_ERROR_S    1
2770 #define CIM_FRAMING_ERROR_V(x) ((x) << CIM_FRAMING_ERROR_S)
2771 #define CIM_FRAMING_ERROR_F    CIM_FRAMING_ERROR_V(1U)
2772 
2773 #define ZERO_SWITCH_ERROR_S    0
2774 #define ZERO_SWITCH_ERROR_V(x) ((x) << ZERO_SWITCH_ERROR_S)
2775 #define ZERO_SWITCH_ERROR_F    ZERO_SWITCH_ERROR_V(1U)
2776 
2777 #define SMB_INT_CAUSE_A 0x19090
2778 
2779 #define MSTTXFIFOPARINT_S    21
2780 #define MSTTXFIFOPARINT_V(x) ((x) << MSTTXFIFOPARINT_S)
2781 #define MSTTXFIFOPARINT_F    MSTTXFIFOPARINT_V(1U)
2782 
2783 #define MSTRXFIFOPARINT_S    20
2784 #define MSTRXFIFOPARINT_V(x) ((x) << MSTRXFIFOPARINT_S)
2785 #define MSTRXFIFOPARINT_F    MSTRXFIFOPARINT_V(1U)
2786 
2787 #define SLVFIFOPARINT_S    19
2788 #define SLVFIFOPARINT_V(x) ((x) << SLVFIFOPARINT_S)
2789 #define SLVFIFOPARINT_F    SLVFIFOPARINT_V(1U)
2790 
2791 #define ULP_RX_INT_CAUSE_A 0x19158
2792 #define ULP_RX_ISCSI_LLIMIT_A 0x1915c
2793 #define ULP_RX_ISCSI_ULIMIT_A 0x19160
2794 #define ULP_RX_ISCSI_TAGMASK_A 0x19164
2795 #define ULP_RX_ISCSI_PSZ_A 0x19168
2796 #define ULP_RX_TDDP_LLIMIT_A 0x1916c
2797 #define ULP_RX_TDDP_ULIMIT_A 0x19170
2798 #define ULP_RX_STAG_LLIMIT_A 0x1917c
2799 #define ULP_RX_STAG_ULIMIT_A 0x19180
2800 #define ULP_RX_RQ_LLIMIT_A 0x19184
2801 #define ULP_RX_RQ_ULIMIT_A 0x19188
2802 #define ULP_RX_PBL_LLIMIT_A 0x1918c
2803 #define ULP_RX_PBL_ULIMIT_A 0x19190
2804 #define ULP_RX_CTX_BASE_A 0x19194
2805 #define ULP_RX_RQUDP_LLIMIT_A 0x191a4
2806 #define ULP_RX_RQUDP_ULIMIT_A 0x191a8
2807 #define ULP_RX_LA_CTL_A 0x1923c
2808 #define ULP_RX_LA_RDPTR_A 0x19240
2809 #define ULP_RX_LA_RDDATA_A 0x19244
2810 #define ULP_RX_LA_WRPTR_A 0x19248
2811 #define ULP_RX_TLS_KEY_LLIMIT_A 0x192ac
2812 #define ULP_RX_TLS_KEY_ULIMIT_A 0x192b0
2813 
2814 #define HPZ3_S    24
2815 #define HPZ3_V(x) ((x) << HPZ3_S)
2816 
2817 #define HPZ2_S    16
2818 #define HPZ2_V(x) ((x) << HPZ2_S)
2819 
2820 #define HPZ1_S    8
2821 #define HPZ1_V(x) ((x) << HPZ1_S)
2822 
2823 #define HPZ0_S    0
2824 #define HPZ0_V(x) ((x) << HPZ0_S)
2825 
2826 #define ULP_RX_TDDP_PSZ_A 0x19178
2827 
2828 /* registers for module SF */
2829 #define SF_DATA_A 0x193f8
2830 #define SF_OP_A 0x193fc
2831 
2832 #define SF_BUSY_S    31
2833 #define SF_BUSY_V(x) ((x) << SF_BUSY_S)
2834 #define SF_BUSY_F    SF_BUSY_V(1U)
2835 
2836 #define SF_LOCK_S    4
2837 #define SF_LOCK_V(x) ((x) << SF_LOCK_S)
2838 #define SF_LOCK_F    SF_LOCK_V(1U)
2839 
2840 #define SF_CONT_S    3
2841 #define SF_CONT_V(x) ((x) << SF_CONT_S)
2842 #define SF_CONT_F    SF_CONT_V(1U)
2843 
2844 #define BYTECNT_S    1
2845 #define BYTECNT_V(x) ((x) << BYTECNT_S)
2846 
2847 #define OP_S    0
2848 #define OP_V(x) ((x) << OP_S)
2849 #define OP_F    OP_V(1U)
2850 
2851 #define PL_PF_INT_CAUSE_A 0x3c0
2852 
2853 #define PFSW_S    3
2854 #define PFSW_V(x) ((x) << PFSW_S)
2855 #define PFSW_F    PFSW_V(1U)
2856 
2857 #define PFCIM_S    1
2858 #define PFCIM_V(x) ((x) << PFCIM_S)
2859 #define PFCIM_F    PFCIM_V(1U)
2860 
2861 #define PL_PF_INT_ENABLE_A 0x3c4
2862 #define PL_PF_CTL_A 0x3c8
2863 
2864 #define PL_WHOAMI_A 0x19400
2865 
2866 #define SOURCEPF_S    8
2867 #define SOURCEPF_M    0x7U
2868 #define SOURCEPF_G(x) (((x) >> SOURCEPF_S) & SOURCEPF_M)
2869 
2870 #define T6_SOURCEPF_S    9
2871 #define T6_SOURCEPF_M    0x7U
2872 #define T6_SOURCEPF_G(x) (((x) >> T6_SOURCEPF_S) & T6_SOURCEPF_M)
2873 
2874 #define PL_INT_CAUSE_A 0x1940c
2875 
2876 #define ULP_TX_S    27
2877 #define ULP_TX_V(x) ((x) << ULP_TX_S)
2878 #define ULP_TX_F    ULP_TX_V(1U)
2879 
2880 #define SGE_S    26
2881 #define SGE_V(x) ((x) << SGE_S)
2882 #define SGE_F    SGE_V(1U)
2883 
2884 #define CPL_SWITCH_S    24
2885 #define CPL_SWITCH_V(x) ((x) << CPL_SWITCH_S)
2886 #define CPL_SWITCH_F    CPL_SWITCH_V(1U)
2887 
2888 #define ULP_RX_S    23
2889 #define ULP_RX_V(x) ((x) << ULP_RX_S)
2890 #define ULP_RX_F    ULP_RX_V(1U)
2891 
2892 #define PM_RX_S    22
2893 #define PM_RX_V(x) ((x) << PM_RX_S)
2894 #define PM_RX_F    PM_RX_V(1U)
2895 
2896 #define PM_TX_S    21
2897 #define PM_TX_V(x) ((x) << PM_TX_S)
2898 #define PM_TX_F    PM_TX_V(1U)
2899 
2900 #define MA_S    20
2901 #define MA_V(x) ((x) << MA_S)
2902 #define MA_F    MA_V(1U)
2903 
2904 #define TP_S    19
2905 #define TP_V(x) ((x) << TP_S)
2906 #define TP_F    TP_V(1U)
2907 
2908 #define LE_S    18
2909 #define LE_V(x) ((x) << LE_S)
2910 #define LE_F    LE_V(1U)
2911 
2912 #define EDC1_S    17
2913 #define EDC1_V(x) ((x) << EDC1_S)
2914 #define EDC1_F    EDC1_V(1U)
2915 
2916 #define EDC0_S    16
2917 #define EDC0_V(x) ((x) << EDC0_S)
2918 #define EDC0_F    EDC0_V(1U)
2919 
2920 #define MC_S    15
2921 #define MC_V(x) ((x) << MC_S)
2922 #define MC_F    MC_V(1U)
2923 
2924 #define PCIE_S    14
2925 #define PCIE_V(x) ((x) << PCIE_S)
2926 #define PCIE_F    PCIE_V(1U)
2927 
2928 #define XGMAC_KR1_S    12
2929 #define XGMAC_KR1_V(x) ((x) << XGMAC_KR1_S)
2930 #define XGMAC_KR1_F    XGMAC_KR1_V(1U)
2931 
2932 #define XGMAC_KR0_S    11
2933 #define XGMAC_KR0_V(x) ((x) << XGMAC_KR0_S)
2934 #define XGMAC_KR0_F    XGMAC_KR0_V(1U)
2935 
2936 #define XGMAC1_S    10
2937 #define XGMAC1_V(x) ((x) << XGMAC1_S)
2938 #define XGMAC1_F    XGMAC1_V(1U)
2939 
2940 #define XGMAC0_S    9
2941 #define XGMAC0_V(x) ((x) << XGMAC0_S)
2942 #define XGMAC0_F    XGMAC0_V(1U)
2943 
2944 #define SMB_S    8
2945 #define SMB_V(x) ((x) << SMB_S)
2946 #define SMB_F    SMB_V(1U)
2947 
2948 #define SF_S    7
2949 #define SF_V(x) ((x) << SF_S)
2950 #define SF_F    SF_V(1U)
2951 
2952 #define PL_S    6
2953 #define PL_V(x) ((x) << PL_S)
2954 #define PL_F    PL_V(1U)
2955 
2956 #define NCSI_S    5
2957 #define NCSI_V(x) ((x) << NCSI_S)
2958 #define NCSI_F    NCSI_V(1U)
2959 
2960 #define MPS_S    4
2961 #define MPS_V(x) ((x) << MPS_S)
2962 #define MPS_F    MPS_V(1U)
2963 
2964 #define CIM_S    0
2965 #define CIM_V(x) ((x) << CIM_S)
2966 #define CIM_F    CIM_V(1U)
2967 
2968 #define MC1_S    31
2969 #define MC1_V(x) ((x) << MC1_S)
2970 #define MC1_F    MC1_V(1U)
2971 
2972 #define PL_INT_ENABLE_A 0x19410
2973 #define PL_INT_MAP0_A 0x19414
2974 #define PL_RST_A 0x19428
2975 
2976 #define PIORST_S    1
2977 #define PIORST_V(x) ((x) << PIORST_S)
2978 #define PIORST_F    PIORST_V(1U)
2979 
2980 #define PIORSTMODE_S    0
2981 #define PIORSTMODE_V(x) ((x) << PIORSTMODE_S)
2982 #define PIORSTMODE_F    PIORSTMODE_V(1U)
2983 
2984 #define PL_PL_INT_CAUSE_A 0x19430
2985 
2986 #define FATALPERR_S    4
2987 #define FATALPERR_V(x) ((x) << FATALPERR_S)
2988 #define FATALPERR_F    FATALPERR_V(1U)
2989 
2990 #define PERRVFID_S    0
2991 #define PERRVFID_V(x) ((x) << PERRVFID_S)
2992 #define PERRVFID_F    PERRVFID_V(1U)
2993 
2994 #define PL_REV_A 0x1943c
2995 
2996 #define REV_S    0
2997 #define REV_M    0xfU
2998 #define REV_V(x) ((x) << REV_S)
2999 #define REV_G(x) (((x) >> REV_S) & REV_M)
3000 
3001 #define T6_UNKNOWNCMD_S    3
3002 #define T6_UNKNOWNCMD_V(x) ((x) << T6_UNKNOWNCMD_S)
3003 #define T6_UNKNOWNCMD_F    T6_UNKNOWNCMD_V(1U)
3004 
3005 #define T6_LIP0_S    2
3006 #define T6_LIP0_V(x) ((x) << T6_LIP0_S)
3007 #define T6_LIP0_F    T6_LIP0_V(1U)
3008 
3009 #define T6_LIPMISS_S    1
3010 #define T6_LIPMISS_V(x) ((x) << T6_LIPMISS_S)
3011 #define T6_LIPMISS_F    T6_LIPMISS_V(1U)
3012 
3013 #define LE_DB_CONFIG_A 0x19c04
3014 #define LE_DB_ROUTING_TABLE_INDEX_A 0x19c10
3015 #define LE_DB_ACTIVE_TABLE_START_INDEX_A 0x19c10
3016 #define LE_DB_FILTER_TABLE_INDEX_A 0x19c14
3017 #define LE_DB_SERVER_INDEX_A 0x19c18
3018 #define LE_DB_SRVR_START_INDEX_A 0x19c18
3019 #define LE_DB_CLIP_TABLE_INDEX_A 0x19c1c
3020 #define LE_DB_ACT_CNT_IPV4_A 0x19c20
3021 #define LE_DB_ACT_CNT_IPV6_A 0x19c24
3022 #define LE_DB_HASH_CONFIG_A 0x19c28
3023 
3024 #define HASHTIDSIZE_S    16
3025 #define HASHTIDSIZE_M    0x3fU
3026 #define HASHTIDSIZE_G(x) (((x) >> HASHTIDSIZE_S) & HASHTIDSIZE_M)
3027 
3028 #define LE_DB_HASH_TID_BASE_A 0x19c30
3029 #define LE_DB_HASH_TBL_BASE_ADDR_A 0x19c30
3030 #define LE_DB_INT_CAUSE_A 0x19c3c
3031 #define LE_DB_CLCAM_TID_BASE_A 0x19df4
3032 #define LE_DB_TID_HASHBASE_A 0x19df8
3033 #define T6_LE_DB_HASH_TID_BASE_A 0x19df8
3034 
3035 #define HASHEN_S    20
3036 #define HASHEN_V(x) ((x) << HASHEN_S)
3037 #define HASHEN_F    HASHEN_V(1U)
3038 
3039 #define ASLIPCOMPEN_S    17
3040 #define ASLIPCOMPEN_V(x) ((x) << ASLIPCOMPEN_S)
3041 #define ASLIPCOMPEN_F    ASLIPCOMPEN_V(1U)
3042 
3043 #define REQQPARERR_S    16
3044 #define REQQPARERR_V(x) ((x) << REQQPARERR_S)
3045 #define REQQPARERR_F    REQQPARERR_V(1U)
3046 
3047 #define UNKNOWNCMD_S    15
3048 #define UNKNOWNCMD_V(x) ((x) << UNKNOWNCMD_S)
3049 #define UNKNOWNCMD_F    UNKNOWNCMD_V(1U)
3050 
3051 #define PARITYERR_S    6
3052 #define PARITYERR_V(x) ((x) << PARITYERR_S)
3053 #define PARITYERR_F    PARITYERR_V(1U)
3054 
3055 #define LIPMISS_S    5
3056 #define LIPMISS_V(x) ((x) << LIPMISS_S)
3057 #define LIPMISS_F    LIPMISS_V(1U)
3058 
3059 #define LIP0_S    4
3060 #define LIP0_V(x) ((x) << LIP0_S)
3061 #define LIP0_F    LIP0_V(1U)
3062 
3063 #define BASEADDR_S    3
3064 #define BASEADDR_M    0x1fffffffU
3065 #define BASEADDR_G(x) (((x) >> BASEADDR_S) & BASEADDR_M)
3066 
3067 #define TCAMINTPERR_S    13
3068 #define TCAMINTPERR_V(x) ((x) << TCAMINTPERR_S)
3069 #define TCAMINTPERR_F    TCAMINTPERR_V(1U)
3070 
3071 #define SSRAMINTPERR_S    10
3072 #define SSRAMINTPERR_V(x) ((x) << SSRAMINTPERR_S)
3073 #define SSRAMINTPERR_F    SSRAMINTPERR_V(1U)
3074 
3075 #define LE_DB_RSP_CODE_0_A	0x19c74
3076 
3077 #define TCAM_ACTV_HIT_S		0
3078 #define TCAM_ACTV_HIT_M		0x1fU
3079 #define TCAM_ACTV_HIT_V(x)	((x) << TCAM_ACTV_HIT_S)
3080 #define TCAM_ACTV_HIT_G(x)	(((x) >> TCAM_ACTV_HIT_S) & TCAM_ACTV_HIT_M)
3081 
3082 #define LE_DB_RSP_CODE_1_A     0x19c78
3083 
3084 #define HASH_ACTV_HIT_S		25
3085 #define HASH_ACTV_HIT_M		0x1fU
3086 #define HASH_ACTV_HIT_V(x)	((x) << HASH_ACTV_HIT_S)
3087 #define HASH_ACTV_HIT_G(x)	(((x) >> HASH_ACTV_HIT_S) & HASH_ACTV_HIT_M)
3088 
3089 #define LE_3_DB_HASH_MASK_GEN_IPV4_T6_A	0x19eac
3090 #define LE_4_DB_HASH_MASK_GEN_IPV4_T6_A	0x19eb0
3091 
3092 #define NCSI_INT_CAUSE_A 0x1a0d8
3093 
3094 #define CIM_DM_PRTY_ERR_S    8
3095 #define CIM_DM_PRTY_ERR_V(x) ((x) << CIM_DM_PRTY_ERR_S)
3096 #define CIM_DM_PRTY_ERR_F    CIM_DM_PRTY_ERR_V(1U)
3097 
3098 #define MPS_DM_PRTY_ERR_S    7
3099 #define MPS_DM_PRTY_ERR_V(x) ((x) << MPS_DM_PRTY_ERR_S)
3100 #define MPS_DM_PRTY_ERR_F    MPS_DM_PRTY_ERR_V(1U)
3101 
3102 #define TXFIFO_PRTY_ERR_S    1
3103 #define TXFIFO_PRTY_ERR_V(x) ((x) << TXFIFO_PRTY_ERR_S)
3104 #define TXFIFO_PRTY_ERR_F    TXFIFO_PRTY_ERR_V(1U)
3105 
3106 #define RXFIFO_PRTY_ERR_S    0
3107 #define RXFIFO_PRTY_ERR_V(x) ((x) << RXFIFO_PRTY_ERR_S)
3108 #define RXFIFO_PRTY_ERR_F    RXFIFO_PRTY_ERR_V(1U)
3109 
3110 #define XGMAC_PORT_CFG2_A 0x1018
3111 
3112 #define PATEN_S    18
3113 #define PATEN_V(x) ((x) << PATEN_S)
3114 #define PATEN_F    PATEN_V(1U)
3115 
3116 #define MAGICEN_S    17
3117 #define MAGICEN_V(x) ((x) << MAGICEN_S)
3118 #define MAGICEN_F    MAGICEN_V(1U)
3119 
3120 #define XGMAC_PORT_MAGIC_MACID_LO 0x1024
3121 #define XGMAC_PORT_MAGIC_MACID_HI 0x1028
3122 
3123 #define XGMAC_PORT_EPIO_DATA0_A 0x10c0
3124 #define XGMAC_PORT_EPIO_DATA1_A 0x10c4
3125 #define XGMAC_PORT_EPIO_DATA2_A 0x10c8
3126 #define XGMAC_PORT_EPIO_DATA3_A 0x10cc
3127 #define XGMAC_PORT_EPIO_OP_A 0x10d0
3128 
3129 #define EPIOWR_S    8
3130 #define EPIOWR_V(x) ((x) << EPIOWR_S)
3131 #define EPIOWR_F    EPIOWR_V(1U)
3132 
3133 #define ADDRESS_S    0
3134 #define ADDRESS_V(x) ((x) << ADDRESS_S)
3135 
3136 #define MAC_PORT_INT_CAUSE_A 0x8dc
3137 #define XGMAC_PORT_INT_CAUSE_A 0x10dc
3138 
3139 #define TP_TX_MOD_QUEUE_REQ_MAP_A 0x7e28
3140 
3141 #define TP_TX_MOD_QUEUE_WEIGHT0_A 0x7e30
3142 #define TP_TX_MOD_CHANNEL_WEIGHT_A 0x7e34
3143 
3144 #define TX_MOD_QUEUE_REQ_MAP_S    0
3145 #define TX_MOD_QUEUE_REQ_MAP_V(x) ((x) << TX_MOD_QUEUE_REQ_MAP_S)
3146 
3147 #define TX_MODQ_WEIGHT3_S    24
3148 #define TX_MODQ_WEIGHT3_V(x) ((x) << TX_MODQ_WEIGHT3_S)
3149 
3150 #define TX_MODQ_WEIGHT2_S    16
3151 #define TX_MODQ_WEIGHT2_V(x) ((x) << TX_MODQ_WEIGHT2_S)
3152 
3153 #define TX_MODQ_WEIGHT1_S    8
3154 #define TX_MODQ_WEIGHT1_V(x) ((x) << TX_MODQ_WEIGHT1_S)
3155 
3156 #define TX_MODQ_WEIGHT0_S    0
3157 #define TX_MODQ_WEIGHT0_V(x) ((x) << TX_MODQ_WEIGHT0_S)
3158 
3159 #define TP_TX_SCHED_HDR_A 0x23
3160 #define TP_TX_SCHED_FIFO_A 0x24
3161 #define TP_TX_SCHED_PCMD_A 0x25
3162 
3163 #define NUM_MPS_CLS_SRAM_L_INSTANCES 336
3164 #define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512
3165 
3166 #define T5_PORT0_BASE 0x30000
3167 #define T5_PORT_STRIDE 0x4000
3168 #define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE)
3169 #define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg))
3170 
3171 #define MC_0_BASE_ADDR 0x40000
3172 #define MC_1_BASE_ADDR 0x48000
3173 #define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR)
3174 #define MC_REG(reg, idx) (reg + MC_STRIDE * idx)
3175 
3176 #define MC_P_BIST_CMD_A			0x41400
3177 #define MC_P_BIST_CMD_ADDR_A		0x41404
3178 #define MC_P_BIST_CMD_LEN_A		0x41408
3179 #define MC_P_BIST_DATA_PATTERN_A	0x4140c
3180 #define MC_P_BIST_STATUS_RDATA_A	0x41488
3181 
3182 #define EDC_T50_BASE_ADDR		0x50000
3183 
3184 #define EDC_H_BIST_CMD_A		0x50004
3185 #define EDC_H_BIST_CMD_ADDR_A		0x50008
3186 #define EDC_H_BIST_CMD_LEN_A		0x5000c
3187 #define EDC_H_BIST_DATA_PATTERN_A	0x50010
3188 #define EDC_H_BIST_STATUS_RDATA_A	0x50028
3189 
3190 #define EDC_H_ECC_ERR_ADDR_A		0x50084
3191 #define EDC_T51_BASE_ADDR		0x50800
3192 
3193 #define EDC_T5_STRIDE (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
3194 #define EDC_T5_REG(reg, idx) (reg + EDC_T5_STRIDE * idx)
3195 
3196 #define PL_VF_REV_A 0x4
3197 #define PL_VF_WHOAMI_A 0x0
3198 #define PL_VF_REVISION_A 0x8
3199 
3200 /* registers for module CIM */
3201 #define CIM_HOST_ACC_CTRL_A	0x7b50
3202 #define CIM_HOST_ACC_DATA_A	0x7b54
3203 #define UP_UP_DBG_LA_CFG_A	0x140
3204 #define UP_UP_DBG_LA_DATA_A	0x144
3205 
3206 #define HOSTBUSY_S	17
3207 #define HOSTBUSY_V(x)	((x) << HOSTBUSY_S)
3208 #define HOSTBUSY_F	HOSTBUSY_V(1U)
3209 
3210 #define HOSTWRITE_S	16
3211 #define HOSTWRITE_V(x)	((x) << HOSTWRITE_S)
3212 #define HOSTWRITE_F	HOSTWRITE_V(1U)
3213 
3214 #define CIM_IBQ_DBG_CFG_A 0x7b60
3215 
3216 #define IBQDBGADDR_S    16
3217 #define IBQDBGADDR_M    0xfffU
3218 #define IBQDBGADDR_V(x) ((x) << IBQDBGADDR_S)
3219 #define IBQDBGADDR_G(x) (((x) >> IBQDBGADDR_S) & IBQDBGADDR_M)
3220 
3221 #define IBQDBGBUSY_S    1
3222 #define IBQDBGBUSY_V(x) ((x) << IBQDBGBUSY_S)
3223 #define IBQDBGBUSY_F    IBQDBGBUSY_V(1U)
3224 
3225 #define IBQDBGEN_S    0
3226 #define IBQDBGEN_V(x) ((x) << IBQDBGEN_S)
3227 #define IBQDBGEN_F    IBQDBGEN_V(1U)
3228 
3229 #define CIM_OBQ_DBG_CFG_A 0x7b64
3230 
3231 #define OBQDBGADDR_S    16
3232 #define OBQDBGADDR_M    0xfffU
3233 #define OBQDBGADDR_V(x) ((x) << OBQDBGADDR_S)
3234 #define OBQDBGADDR_G(x) (((x) >> OBQDBGADDR_S) & OBQDBGADDR_M)
3235 
3236 #define OBQDBGBUSY_S    1
3237 #define OBQDBGBUSY_V(x) ((x) << OBQDBGBUSY_S)
3238 #define OBQDBGBUSY_F    OBQDBGBUSY_V(1U)
3239 
3240 #define OBQDBGEN_S    0
3241 #define OBQDBGEN_V(x) ((x) << OBQDBGEN_S)
3242 #define OBQDBGEN_F    OBQDBGEN_V(1U)
3243 
3244 #define CIM_IBQ_DBG_DATA_A 0x7b68
3245 #define CIM_OBQ_DBG_DATA_A 0x7b6c
3246 #define CIM_DEBUGCFG_A 0x7b70
3247 #define CIM_DEBUGSTS_A 0x7b74
3248 
3249 #define POLADBGRDPTR_S		23
3250 #define POLADBGRDPTR_M		0x1ffU
3251 #define POLADBGRDPTR_V(x)	((x) << POLADBGRDPTR_S)
3252 
3253 #define POLADBGWRPTR_S		16
3254 #define POLADBGWRPTR_M		0x1ffU
3255 #define POLADBGWRPTR_G(x)	(((x) >> POLADBGWRPTR_S) & POLADBGWRPTR_M)
3256 
3257 #define PILADBGRDPTR_S		14
3258 #define PILADBGRDPTR_M		0x1ffU
3259 #define PILADBGRDPTR_V(x)	((x) << PILADBGRDPTR_S)
3260 
3261 #define PILADBGWRPTR_S		0
3262 #define PILADBGWRPTR_M		0x1ffU
3263 #define PILADBGWRPTR_G(x)	(((x) >> PILADBGWRPTR_S) & PILADBGWRPTR_M)
3264 
3265 #define LADBGEN_S	12
3266 #define LADBGEN_V(x)	((x) << LADBGEN_S)
3267 #define LADBGEN_F	LADBGEN_V(1U)
3268 
3269 #define CIM_PO_LA_DEBUGDATA_A 0x7b78
3270 #define CIM_PI_LA_DEBUGDATA_A 0x7b7c
3271 #define CIM_PO_LA_MADEBUGDATA_A	0x7b80
3272 #define CIM_PI_LA_MADEBUGDATA_A	0x7b84
3273 
3274 #define UPDBGLARDEN_S		1
3275 #define UPDBGLARDEN_V(x)	((x) << UPDBGLARDEN_S)
3276 #define UPDBGLARDEN_F		UPDBGLARDEN_V(1U)
3277 
3278 #define UPDBGLAEN_S	0
3279 #define UPDBGLAEN_V(x)	((x) << UPDBGLAEN_S)
3280 #define UPDBGLAEN_F	UPDBGLAEN_V(1U)
3281 
3282 #define UPDBGLARDPTR_S		2
3283 #define UPDBGLARDPTR_M		0xfffU
3284 #define UPDBGLARDPTR_V(x)	((x) << UPDBGLARDPTR_S)
3285 
3286 #define UPDBGLAWRPTR_S    16
3287 #define UPDBGLAWRPTR_M    0xfffU
3288 #define UPDBGLAWRPTR_G(x) (((x) >> UPDBGLAWRPTR_S) & UPDBGLAWRPTR_M)
3289 
3290 #define UPDBGLACAPTPCONLY_S	30
3291 #define UPDBGLACAPTPCONLY_V(x)	((x) << UPDBGLACAPTPCONLY_S)
3292 #define UPDBGLACAPTPCONLY_F	UPDBGLACAPTPCONLY_V(1U)
3293 
3294 #define CIM_QUEUE_CONFIG_REF_A 0x7b48
3295 #define CIM_QUEUE_CONFIG_CTRL_A 0x7b4c
3296 
3297 #define CIMQSIZE_S    24
3298 #define CIMQSIZE_M    0x3fU
3299 #define CIMQSIZE_G(x) (((x) >> CIMQSIZE_S) & CIMQSIZE_M)
3300 
3301 #define CIMQBASE_S    16
3302 #define CIMQBASE_M    0x3fU
3303 #define CIMQBASE_G(x) (((x) >> CIMQBASE_S) & CIMQBASE_M)
3304 
3305 #define QUEFULLTHRSH_S    0
3306 #define QUEFULLTHRSH_M    0x1ffU
3307 #define QUEFULLTHRSH_G(x) (((x) >> QUEFULLTHRSH_S) & QUEFULLTHRSH_M)
3308 
3309 #define UP_IBQ_0_RDADDR_A 0x10
3310 #define UP_IBQ_0_SHADOW_RDADDR_A 0x280
3311 #define UP_OBQ_0_REALADDR_A 0x104
3312 #define UP_OBQ_0_SHADOW_REALADDR_A 0x394
3313 
3314 #define IBQRDADDR_S    0
3315 #define IBQRDADDR_M    0x1fffU
3316 #define IBQRDADDR_G(x) (((x) >> IBQRDADDR_S) & IBQRDADDR_M)
3317 
3318 #define IBQWRADDR_S    0
3319 #define IBQWRADDR_M    0x1fffU
3320 #define IBQWRADDR_G(x) (((x) >> IBQWRADDR_S) & IBQWRADDR_M)
3321 
3322 #define QUERDADDR_S    0
3323 #define QUERDADDR_M    0x7fffU
3324 #define QUERDADDR_G(x) (((x) >> QUERDADDR_S) & QUERDADDR_M)
3325 
3326 #define QUEREMFLITS_S    0
3327 #define QUEREMFLITS_M    0x7ffU
3328 #define QUEREMFLITS_G(x) (((x) >> QUEREMFLITS_S) & QUEREMFLITS_M)
3329 
3330 #define QUEEOPCNT_S    16
3331 #define QUEEOPCNT_M    0xfffU
3332 #define QUEEOPCNT_G(x) (((x) >> QUEEOPCNT_S) & QUEEOPCNT_M)
3333 
3334 #define QUESOPCNT_S    0
3335 #define QUESOPCNT_M    0xfffU
3336 #define QUESOPCNT_G(x) (((x) >> QUESOPCNT_S) & QUESOPCNT_M)
3337 
3338 #define OBQSELECT_S    4
3339 #define OBQSELECT_V(x) ((x) << OBQSELECT_S)
3340 #define OBQSELECT_F    OBQSELECT_V(1U)
3341 
3342 #define IBQSELECT_S    3
3343 #define IBQSELECT_V(x) ((x) << IBQSELECT_S)
3344 #define IBQSELECT_F    IBQSELECT_V(1U)
3345 
3346 #define QUENUMSELECT_S    0
3347 #define QUENUMSELECT_V(x) ((x) << QUENUMSELECT_S)
3348 
3349 #endif /* __T4_REGS_H */
3350