1f7917c00SJeff Kirsher /* 2f7917c00SJeff Kirsher * This file is part of the Chelsio T4 Ethernet driver for Linux. 3f7917c00SJeff Kirsher * 4ce100b8bSAnish Bhatt * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5f7917c00SJeff Kirsher * 6f7917c00SJeff Kirsher * This software is available to you under a choice of one of two 7f7917c00SJeff Kirsher * licenses. You may choose to be licensed under the terms of the GNU 8f7917c00SJeff Kirsher * General Public License (GPL) Version 2, available from the file 9f7917c00SJeff Kirsher * COPYING in the main directory of this source tree, or the 10f7917c00SJeff Kirsher * OpenIB.org BSD license below: 11f7917c00SJeff Kirsher * 12f7917c00SJeff Kirsher * Redistribution and use in source and binary forms, with or 13f7917c00SJeff Kirsher * without modification, are permitted provided that the following 14f7917c00SJeff Kirsher * conditions are met: 15f7917c00SJeff Kirsher * 16f7917c00SJeff Kirsher * - Redistributions of source code must retain the above 17f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 18f7917c00SJeff Kirsher * disclaimer. 19f7917c00SJeff Kirsher * 20f7917c00SJeff Kirsher * - Redistributions in binary form must reproduce the above 21f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 22f7917c00SJeff Kirsher * disclaimer in the documentation and/or other materials 23f7917c00SJeff Kirsher * provided with the distribution. 24f7917c00SJeff Kirsher * 25f7917c00SJeff Kirsher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26f7917c00SJeff Kirsher * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27f7917c00SJeff Kirsher * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28f7917c00SJeff Kirsher * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29f7917c00SJeff Kirsher * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30f7917c00SJeff Kirsher * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31f7917c00SJeff Kirsher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32f7917c00SJeff Kirsher * SOFTWARE. 33f7917c00SJeff Kirsher */ 34f7917c00SJeff Kirsher 35f7917c00SJeff Kirsher #ifndef __T4_REGS_H 36f7917c00SJeff Kirsher #define __T4_REGS_H 37f7917c00SJeff Kirsher 38f7917c00SJeff Kirsher #define MYPF_BASE 0x1b000 39f7917c00SJeff Kirsher #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr)) 40f7917c00SJeff Kirsher 41f7917c00SJeff Kirsher #define PF0_BASE 0x1e000 42f7917c00SJeff Kirsher #define PF0_REG(reg_addr) (PF0_BASE + (reg_addr)) 43f7917c00SJeff Kirsher 44f7917c00SJeff Kirsher #define PF_STRIDE 0x400 45f7917c00SJeff Kirsher #define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE) 46f7917c00SJeff Kirsher #define PF_REG(idx, reg) (PF_BASE(idx) + (reg)) 47f7917c00SJeff Kirsher 48f7917c00SJeff Kirsher #define MYPORT_BASE 0x1c000 49f7917c00SJeff Kirsher #define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr)) 50f7917c00SJeff Kirsher 51f7917c00SJeff Kirsher #define PORT0_BASE 0x20000 52f7917c00SJeff Kirsher #define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr)) 53f7917c00SJeff Kirsher 54f7917c00SJeff Kirsher #define PORT_STRIDE 0x2000 55f7917c00SJeff Kirsher #define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE) 56f7917c00SJeff Kirsher #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg)) 57f7917c00SJeff Kirsher 58f7917c00SJeff Kirsher #define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR) 59f7917c00SJeff Kirsher #define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx) 60f7917c00SJeff Kirsher 61f7917c00SJeff Kirsher #define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) 62f7917c00SJeff Kirsher #define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) 63f7917c00SJeff Kirsher #define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) 64f7917c00SJeff Kirsher #define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) 65f7917c00SJeff Kirsher 66f7917c00SJeff Kirsher #define SGE_PF_KDOORBELL 0x0 67f7917c00SJeff Kirsher #define QID_MASK 0xffff8000U 68f7917c00SJeff Kirsher #define QID_SHIFT 15 69f7917c00SJeff Kirsher #define QID(x) ((x) << QID_SHIFT) 70ce91a923SNaresh Kumar Inna #define DBPRIO(x) ((x) << 14) 71b2decaddSSantosh Rastapur #define DBTYPE(x) ((x) << 13) 72f7917c00SJeff Kirsher #define PIDX_MASK 0x00003fffU 73f7917c00SJeff Kirsher #define PIDX_SHIFT 0 74f7917c00SJeff Kirsher #define PIDX(x) ((x) << PIDX_SHIFT) 75b2decaddSSantosh Rastapur #define S_PIDX_T5 0 76b2decaddSSantosh Rastapur #define M_PIDX_T5 0x1fffU 77b2decaddSSantosh Rastapur #define PIDX_T5(x) (((x) >> S_PIDX_T5) & M_PIDX_T5) 78b2decaddSSantosh Rastapur 79f7917c00SJeff Kirsher 80f7917c00SJeff Kirsher #define SGE_PF_GTS 0x4 81f7917c00SJeff Kirsher #define INGRESSQID_MASK 0xffff0000U 82f7917c00SJeff Kirsher #define INGRESSQID_SHIFT 16 83f7917c00SJeff Kirsher #define INGRESSQID(x) ((x) << INGRESSQID_SHIFT) 84f7917c00SJeff Kirsher #define TIMERREG_MASK 0x0000e000U 85f7917c00SJeff Kirsher #define TIMERREG_SHIFT 13 86f7917c00SJeff Kirsher #define TIMERREG(x) ((x) << TIMERREG_SHIFT) 87f7917c00SJeff Kirsher #define SEINTARM_MASK 0x00001000U 88f7917c00SJeff Kirsher #define SEINTARM_SHIFT 12 89f7917c00SJeff Kirsher #define SEINTARM(x) ((x) << SEINTARM_SHIFT) 90f7917c00SJeff Kirsher #define CIDXINC_MASK 0x00000fffU 91f7917c00SJeff Kirsher #define CIDXINC_SHIFT 0 92f7917c00SJeff Kirsher #define CIDXINC(x) ((x) << CIDXINC_SHIFT) 93f7917c00SJeff Kirsher 9452367a76SVipul Pandya #define X_RXPKTCPLMODE_SPLIT 1 9552367a76SVipul Pandya #define X_INGPADBOUNDARY_SHIFT 5 9652367a76SVipul Pandya 97f7917c00SJeff Kirsher #define SGE_CONTROL 0x1008 98f7917c00SJeff Kirsher #define DCASYSTYPE 0x00080000U 9952367a76SVipul Pandya #define RXPKTCPLMODE_MASK 0x00040000U 10052367a76SVipul Pandya #define RXPKTCPLMODE_SHIFT 18 10152367a76SVipul Pandya #define RXPKTCPLMODE(x) ((x) << RXPKTCPLMODE_SHIFT) 10252367a76SVipul Pandya #define EGRSTATUSPAGESIZE_MASK 0x00020000U 10352367a76SVipul Pandya #define EGRSTATUSPAGESIZE_SHIFT 17 10452367a76SVipul Pandya #define EGRSTATUSPAGESIZE(x) ((x) << EGRSTATUSPAGESIZE_SHIFT) 105f7917c00SJeff Kirsher #define PKTSHIFT_MASK 0x00001c00U 106f7917c00SJeff Kirsher #define PKTSHIFT_SHIFT 10 107f7917c00SJeff Kirsher #define PKTSHIFT(x) ((x) << PKTSHIFT_SHIFT) 108f7917c00SJeff Kirsher #define PKTSHIFT_GET(x) (((x) & PKTSHIFT_MASK) >> PKTSHIFT_SHIFT) 109f7917c00SJeff Kirsher #define INGPCIEBOUNDARY_MASK 0x00000380U 110f7917c00SJeff Kirsher #define INGPCIEBOUNDARY_SHIFT 7 111f7917c00SJeff Kirsher #define INGPCIEBOUNDARY(x) ((x) << INGPCIEBOUNDARY_SHIFT) 112f7917c00SJeff Kirsher #define INGPADBOUNDARY_MASK 0x00000070U 113f7917c00SJeff Kirsher #define INGPADBOUNDARY_SHIFT 4 114f7917c00SJeff Kirsher #define INGPADBOUNDARY(x) ((x) << INGPADBOUNDARY_SHIFT) 115f7917c00SJeff Kirsher #define INGPADBOUNDARY_GET(x) (((x) & INGPADBOUNDARY_MASK) \ 116f7917c00SJeff Kirsher >> INGPADBOUNDARY_SHIFT) 117f7917c00SJeff Kirsher #define EGRPCIEBOUNDARY_MASK 0x0000000eU 118f7917c00SJeff Kirsher #define EGRPCIEBOUNDARY_SHIFT 1 119f7917c00SJeff Kirsher #define EGRPCIEBOUNDARY(x) ((x) << EGRPCIEBOUNDARY_SHIFT) 120f7917c00SJeff Kirsher #define GLOBALENABLE 0x00000001U 121f7917c00SJeff Kirsher 122f7917c00SJeff Kirsher #define SGE_HOST_PAGE_SIZE 0x100c 123636f9d37SVipul Pandya 124636f9d37SVipul Pandya #define HOSTPAGESIZEPF7_MASK 0x0000000fU 125636f9d37SVipul Pandya #define HOSTPAGESIZEPF7_SHIFT 28 126636f9d37SVipul Pandya #define HOSTPAGESIZEPF7(x) ((x) << HOSTPAGESIZEPF7_SHIFT) 127636f9d37SVipul Pandya 128636f9d37SVipul Pandya #define HOSTPAGESIZEPF6_MASK 0x0000000fU 129636f9d37SVipul Pandya #define HOSTPAGESIZEPF6_SHIFT 24 130636f9d37SVipul Pandya #define HOSTPAGESIZEPF6(x) ((x) << HOSTPAGESIZEPF6_SHIFT) 131636f9d37SVipul Pandya 132636f9d37SVipul Pandya #define HOSTPAGESIZEPF5_MASK 0x0000000fU 133636f9d37SVipul Pandya #define HOSTPAGESIZEPF5_SHIFT 20 134636f9d37SVipul Pandya #define HOSTPAGESIZEPF5(x) ((x) << HOSTPAGESIZEPF5_SHIFT) 135636f9d37SVipul Pandya 136636f9d37SVipul Pandya #define HOSTPAGESIZEPF4_MASK 0x0000000fU 137636f9d37SVipul Pandya #define HOSTPAGESIZEPF4_SHIFT 16 138636f9d37SVipul Pandya #define HOSTPAGESIZEPF4(x) ((x) << HOSTPAGESIZEPF4_SHIFT) 139636f9d37SVipul Pandya 140636f9d37SVipul Pandya #define HOSTPAGESIZEPF3_MASK 0x0000000fU 141636f9d37SVipul Pandya #define HOSTPAGESIZEPF3_SHIFT 12 142636f9d37SVipul Pandya #define HOSTPAGESIZEPF3(x) ((x) << HOSTPAGESIZEPF3_SHIFT) 143636f9d37SVipul Pandya 144636f9d37SVipul Pandya #define HOSTPAGESIZEPF2_MASK 0x0000000fU 145636f9d37SVipul Pandya #define HOSTPAGESIZEPF2_SHIFT 8 146636f9d37SVipul Pandya #define HOSTPAGESIZEPF2(x) ((x) << HOSTPAGESIZEPF2_SHIFT) 147636f9d37SVipul Pandya 148636f9d37SVipul Pandya #define HOSTPAGESIZEPF1_MASK 0x0000000fU 149636f9d37SVipul Pandya #define HOSTPAGESIZEPF1_SHIFT 4 150636f9d37SVipul Pandya #define HOSTPAGESIZEPF1(x) ((x) << HOSTPAGESIZEPF1_SHIFT) 151636f9d37SVipul Pandya 152f7917c00SJeff Kirsher #define HOSTPAGESIZEPF0_MASK 0x0000000fU 153f7917c00SJeff Kirsher #define HOSTPAGESIZEPF0_SHIFT 0 154f7917c00SJeff Kirsher #define HOSTPAGESIZEPF0(x) ((x) << HOSTPAGESIZEPF0_SHIFT) 155f7917c00SJeff Kirsher 156f7917c00SJeff Kirsher #define SGE_EGRESS_QUEUES_PER_PAGE_PF 0x1010 157f7917c00SJeff Kirsher #define QUEUESPERPAGEPF0_MASK 0x0000000fU 158f7917c00SJeff Kirsher #define QUEUESPERPAGEPF0_GET(x) ((x) & QUEUESPERPAGEPF0_MASK) 159f7917c00SJeff Kirsher 160b2decaddSSantosh Rastapur #define QUEUESPERPAGEPF1 4 161b2decaddSSantosh Rastapur 162f7917c00SJeff Kirsher #define SGE_INT_CAUSE1 0x1024 163f7917c00SJeff Kirsher #define SGE_INT_CAUSE2 0x1030 164f7917c00SJeff Kirsher #define SGE_INT_CAUSE3 0x103c 165f7917c00SJeff Kirsher #define ERR_FLM_DBP 0x80000000U 166f7917c00SJeff Kirsher #define ERR_FLM_IDMA1 0x40000000U 167f7917c00SJeff Kirsher #define ERR_FLM_IDMA0 0x20000000U 168f7917c00SJeff Kirsher #define ERR_FLM_HINT 0x10000000U 169f7917c00SJeff Kirsher #define ERR_PCIE_ERROR3 0x08000000U 170f7917c00SJeff Kirsher #define ERR_PCIE_ERROR2 0x04000000U 171f7917c00SJeff Kirsher #define ERR_PCIE_ERROR1 0x02000000U 172f7917c00SJeff Kirsher #define ERR_PCIE_ERROR0 0x01000000U 173f7917c00SJeff Kirsher #define ERR_TIMER_ABOVE_MAX_QID 0x00800000U 174f7917c00SJeff Kirsher #define ERR_CPL_EXCEED_IQE_SIZE 0x00400000U 175f7917c00SJeff Kirsher #define ERR_INVALID_CIDX_INC 0x00200000U 176f7917c00SJeff Kirsher #define ERR_ITP_TIME_PAUSED 0x00100000U 177f7917c00SJeff Kirsher #define ERR_CPL_OPCODE_0 0x00080000U 178f7917c00SJeff Kirsher #define ERR_DROPPED_DB 0x00040000U 179f7917c00SJeff Kirsher #define ERR_DATA_CPL_ON_HIGH_QID1 0x00020000U 180f7917c00SJeff Kirsher #define ERR_DATA_CPL_ON_HIGH_QID0 0x00010000U 181f7917c00SJeff Kirsher #define ERR_BAD_DB_PIDX3 0x00008000U 182f7917c00SJeff Kirsher #define ERR_BAD_DB_PIDX2 0x00004000U 183f7917c00SJeff Kirsher #define ERR_BAD_DB_PIDX1 0x00002000U 184f7917c00SJeff Kirsher #define ERR_BAD_DB_PIDX0 0x00001000U 185f7917c00SJeff Kirsher #define ERR_ING_PCIE_CHAN 0x00000800U 186f7917c00SJeff Kirsher #define ERR_ING_CTXT_PRIO 0x00000400U 187f7917c00SJeff Kirsher #define ERR_EGR_CTXT_PRIO 0x00000200U 188f7917c00SJeff Kirsher #define DBFIFO_HP_INT 0x00000100U 189f7917c00SJeff Kirsher #define DBFIFO_LP_INT 0x00000080U 190f7917c00SJeff Kirsher #define REG_ADDRESS_ERR 0x00000040U 191f7917c00SJeff Kirsher #define INGRESS_SIZE_ERR 0x00000020U 192f7917c00SJeff Kirsher #define EGRESS_SIZE_ERR 0x00000010U 193f7917c00SJeff Kirsher #define ERR_INV_CTXT3 0x00000008U 194f7917c00SJeff Kirsher #define ERR_INV_CTXT2 0x00000004U 195f7917c00SJeff Kirsher #define ERR_INV_CTXT1 0x00000002U 196f7917c00SJeff Kirsher #define ERR_INV_CTXT0 0x00000001U 197f7917c00SJeff Kirsher 198f7917c00SJeff Kirsher #define SGE_INT_ENABLE3 0x1040 199f7917c00SJeff Kirsher #define SGE_FL_BUFFER_SIZE0 0x1044 200f7917c00SJeff Kirsher #define SGE_FL_BUFFER_SIZE1 0x1048 201636f9d37SVipul Pandya #define SGE_FL_BUFFER_SIZE2 0x104c 202636f9d37SVipul Pandya #define SGE_FL_BUFFER_SIZE3 0x1050 203ce91a923SNaresh Kumar Inna #define SGE_FL_BUFFER_SIZE4 0x1054 204ce91a923SNaresh Kumar Inna #define SGE_FL_BUFFER_SIZE5 0x1058 205ce91a923SNaresh Kumar Inna #define SGE_FL_BUFFER_SIZE6 0x105c 206ce91a923SNaresh Kumar Inna #define SGE_FL_BUFFER_SIZE7 0x1060 207ce91a923SNaresh Kumar Inna #define SGE_FL_BUFFER_SIZE8 0x1064 208ce91a923SNaresh Kumar Inna 209f7917c00SJeff Kirsher #define SGE_INGRESS_RX_THRESHOLD 0x10a0 210f7917c00SJeff Kirsher #define THRESHOLD_0_MASK 0x3f000000U 211f7917c00SJeff Kirsher #define THRESHOLD_0_SHIFT 24 212f7917c00SJeff Kirsher #define THRESHOLD_0(x) ((x) << THRESHOLD_0_SHIFT) 213f7917c00SJeff Kirsher #define THRESHOLD_0_GET(x) (((x) & THRESHOLD_0_MASK) >> THRESHOLD_0_SHIFT) 214f7917c00SJeff Kirsher #define THRESHOLD_1_MASK 0x003f0000U 215f7917c00SJeff Kirsher #define THRESHOLD_1_SHIFT 16 216f7917c00SJeff Kirsher #define THRESHOLD_1(x) ((x) << THRESHOLD_1_SHIFT) 217f7917c00SJeff Kirsher #define THRESHOLD_1_GET(x) (((x) & THRESHOLD_1_MASK) >> THRESHOLD_1_SHIFT) 218f7917c00SJeff Kirsher #define THRESHOLD_2_MASK 0x00003f00U 219f7917c00SJeff Kirsher #define THRESHOLD_2_SHIFT 8 220f7917c00SJeff Kirsher #define THRESHOLD_2(x) ((x) << THRESHOLD_2_SHIFT) 221f7917c00SJeff Kirsher #define THRESHOLD_2_GET(x) (((x) & THRESHOLD_2_MASK) >> THRESHOLD_2_SHIFT) 222f7917c00SJeff Kirsher #define THRESHOLD_3_MASK 0x0000003fU 223f7917c00SJeff Kirsher #define THRESHOLD_3_SHIFT 0 224f7917c00SJeff Kirsher #define THRESHOLD_3(x) ((x) << THRESHOLD_3_SHIFT) 225f7917c00SJeff Kirsher #define THRESHOLD_3_GET(x) (((x) & THRESHOLD_3_MASK) >> THRESHOLD_3_SHIFT) 226f7917c00SJeff Kirsher 22752367a76SVipul Pandya #define SGE_CONM_CTRL 0x1094 22852367a76SVipul Pandya #define EGRTHRESHOLD_MASK 0x00003f00U 22952367a76SVipul Pandya #define EGRTHRESHOLDshift 8 23052367a76SVipul Pandya #define EGRTHRESHOLD(x) ((x) << EGRTHRESHOLDshift) 23152367a76SVipul Pandya #define EGRTHRESHOLD_GET(x) (((x) & EGRTHRESHOLD_MASK) >> EGRTHRESHOLDshift) 23252367a76SVipul Pandya 233c2b955e0SKumar Sanghvi #define EGRTHRESHOLDPACKING_MASK 0x3fU 234c2b955e0SKumar Sanghvi #define EGRTHRESHOLDPACKING_SHIFT 14 235c2b955e0SKumar Sanghvi #define EGRTHRESHOLDPACKING(x) ((x) << EGRTHRESHOLDPACKING_SHIFT) 236c2b955e0SKumar Sanghvi #define EGRTHRESHOLDPACKING_GET(x) (((x) >> EGRTHRESHOLDPACKING_SHIFT) & \ 237c2b955e0SKumar Sanghvi EGRTHRESHOLDPACKING_MASK) 238c2b955e0SKumar Sanghvi 239ce91a923SNaresh Kumar Inna #define SGE_DBFIFO_STATUS 0x10a4 240ce91a923SNaresh Kumar Inna #define HP_INT_THRESH_SHIFT 28 241ce91a923SNaresh Kumar Inna #define HP_INT_THRESH_MASK 0xfU 242ce91a923SNaresh Kumar Inna #define HP_INT_THRESH(x) ((x) << HP_INT_THRESH_SHIFT) 243ce91a923SNaresh Kumar Inna #define LP_INT_THRESH_SHIFT 12 244ce91a923SNaresh Kumar Inna #define LP_INT_THRESH_MASK 0xfU 245ce91a923SNaresh Kumar Inna #define LP_INT_THRESH(x) ((x) << LP_INT_THRESH_SHIFT) 246ce91a923SNaresh Kumar Inna 247ce91a923SNaresh Kumar Inna #define SGE_DOORBELL_CONTROL 0x10a8 248ce91a923SNaresh Kumar Inna #define ENABLE_DROP (1 << 13) 249ce91a923SNaresh Kumar Inna 2503cbdb928SVipul Pandya #define S_NOCOALESCE 26 2513cbdb928SVipul Pandya #define V_NOCOALESCE(x) ((x) << S_NOCOALESCE) 2523cbdb928SVipul Pandya #define F_NOCOALESCE V_NOCOALESCE(1U) 2533cbdb928SVipul Pandya 254f7917c00SJeff Kirsher #define SGE_TIMER_VALUE_0_AND_1 0x10b8 255f7917c00SJeff Kirsher #define TIMERVALUE0_MASK 0xffff0000U 256f7917c00SJeff Kirsher #define TIMERVALUE0_SHIFT 16 257f7917c00SJeff Kirsher #define TIMERVALUE0(x) ((x) << TIMERVALUE0_SHIFT) 258f7917c00SJeff Kirsher #define TIMERVALUE0_GET(x) (((x) & TIMERVALUE0_MASK) >> TIMERVALUE0_SHIFT) 259f7917c00SJeff Kirsher #define TIMERVALUE1_MASK 0x0000ffffU 260f7917c00SJeff Kirsher #define TIMERVALUE1_SHIFT 0 261f7917c00SJeff Kirsher #define TIMERVALUE1(x) ((x) << TIMERVALUE1_SHIFT) 262f7917c00SJeff Kirsher #define TIMERVALUE1_GET(x) (((x) & TIMERVALUE1_MASK) >> TIMERVALUE1_SHIFT) 263f7917c00SJeff Kirsher 264f7917c00SJeff Kirsher #define SGE_TIMER_VALUE_2_AND_3 0x10bc 26552367a76SVipul Pandya #define TIMERVALUE2_MASK 0xffff0000U 26652367a76SVipul Pandya #define TIMERVALUE2_SHIFT 16 26752367a76SVipul Pandya #define TIMERVALUE2(x) ((x) << TIMERVALUE2_SHIFT) 26852367a76SVipul Pandya #define TIMERVALUE2_GET(x) (((x) & TIMERVALUE2_MASK) >> TIMERVALUE2_SHIFT) 26952367a76SVipul Pandya #define TIMERVALUE3_MASK 0x0000ffffU 27052367a76SVipul Pandya #define TIMERVALUE3_SHIFT 0 27152367a76SVipul Pandya #define TIMERVALUE3(x) ((x) << TIMERVALUE3_SHIFT) 27252367a76SVipul Pandya #define TIMERVALUE3_GET(x) (((x) & TIMERVALUE3_MASK) >> TIMERVALUE3_SHIFT) 27352367a76SVipul Pandya 274f7917c00SJeff Kirsher #define SGE_TIMER_VALUE_4_AND_5 0x10c0 27552367a76SVipul Pandya #define TIMERVALUE4_MASK 0xffff0000U 27652367a76SVipul Pandya #define TIMERVALUE4_SHIFT 16 27752367a76SVipul Pandya #define TIMERVALUE4(x) ((x) << TIMERVALUE4_SHIFT) 27852367a76SVipul Pandya #define TIMERVALUE4_GET(x) (((x) & TIMERVALUE4_MASK) >> TIMERVALUE4_SHIFT) 27952367a76SVipul Pandya #define TIMERVALUE5_MASK 0x0000ffffU 28052367a76SVipul Pandya #define TIMERVALUE5_SHIFT 0 28152367a76SVipul Pandya #define TIMERVALUE5(x) ((x) << TIMERVALUE5_SHIFT) 28252367a76SVipul Pandya #define TIMERVALUE5_GET(x) (((x) & TIMERVALUE5_MASK) >> TIMERVALUE5_SHIFT) 28352367a76SVipul Pandya 284f7917c00SJeff Kirsher #define SGE_DEBUG_INDEX 0x10cc 285f7917c00SJeff Kirsher #define SGE_DEBUG_DATA_HIGH 0x10d0 286f7917c00SJeff Kirsher #define SGE_DEBUG_DATA_LOW 0x10d4 28768bce192SKumar Sanghvi #define SGE_DEBUG_DATA_LOW_INDEX_2 0x12c8 28868bce192SKumar Sanghvi #define SGE_DEBUG_DATA_LOW_INDEX_3 0x12cc 28968bce192SKumar Sanghvi #define SGE_DEBUG_DATA_HIGH_INDEX_10 0x12a8 290f7917c00SJeff Kirsher #define SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4 291f7917c00SJeff Kirsher 2923069ee9bSVipul Pandya #define S_HP_INT_THRESH 28 293840f3000SVipul Pandya #define M_HP_INT_THRESH 0xfU 2943069ee9bSVipul Pandya #define V_HP_INT_THRESH(x) ((x) << S_HP_INT_THRESH) 295b2decaddSSantosh Rastapur #define S_LP_INT_THRESH_T5 18 296b2decaddSSantosh Rastapur #define V_LP_INT_THRESH_T5(x) ((x) << S_LP_INT_THRESH_T5) 297b2decaddSSantosh Rastapur #define M_LP_COUNT_T5 0x3ffffU 298b2decaddSSantosh Rastapur #define G_LP_COUNT_T5(x) (((x) >> S_LP_COUNT) & M_LP_COUNT_T5) 299840f3000SVipul Pandya #define M_HP_COUNT 0x7ffU 300840f3000SVipul Pandya #define S_HP_COUNT 16 301840f3000SVipul Pandya #define G_HP_COUNT(x) (((x) >> S_HP_COUNT) & M_HP_COUNT) 302840f3000SVipul Pandya #define S_LP_INT_THRESH 12 303840f3000SVipul Pandya #define M_LP_INT_THRESH 0xfU 304b2decaddSSantosh Rastapur #define M_LP_INT_THRESH_T5 0xfffU 305840f3000SVipul Pandya #define V_LP_INT_THRESH(x) ((x) << S_LP_INT_THRESH) 306840f3000SVipul Pandya #define M_LP_COUNT 0x7ffU 307840f3000SVipul Pandya #define S_LP_COUNT 0 308840f3000SVipul Pandya #define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT) 3093069ee9bSVipul Pandya #define A_SGE_DBFIFO_STATUS 0x10a4 3103069ee9bSVipul Pandya 311b2decaddSSantosh Rastapur #define SGE_STAT_TOTAL 0x10e4 312b2decaddSSantosh Rastapur #define SGE_STAT_MATCH 0x10e8 313b2decaddSSantosh Rastapur 314b2decaddSSantosh Rastapur #define SGE_STAT_CFG 0x10ec 315b2decaddSSantosh Rastapur #define S_STATSOURCE_T5 9 316b2decaddSSantosh Rastapur #define STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5) 317b2decaddSSantosh Rastapur 318b2decaddSSantosh Rastapur #define SGE_DBFIFO_STATUS2 0x1118 319b2decaddSSantosh Rastapur #define M_HP_COUNT_T5 0x3ffU 320b2decaddSSantosh Rastapur #define G_HP_COUNT_T5(x) ((x) & M_HP_COUNT_T5) 321b2decaddSSantosh Rastapur #define S_HP_INT_THRESH_T5 10 322b2decaddSSantosh Rastapur #define M_HP_INT_THRESH_T5 0xfU 323b2decaddSSantosh Rastapur #define V_HP_INT_THRESH_T5(x) ((x) << S_HP_INT_THRESH_T5) 324b2decaddSSantosh Rastapur 3253069ee9bSVipul Pandya #define S_ENABLE_DROP 13 3263069ee9bSVipul Pandya #define V_ENABLE_DROP(x) ((x) << S_ENABLE_DROP) 3273069ee9bSVipul Pandya #define F_ENABLE_DROP V_ENABLE_DROP(1U) 328840f3000SVipul Pandya #define S_DROPPED_DB 0 329840f3000SVipul Pandya #define V_DROPPED_DB(x) ((x) << S_DROPPED_DB) 330840f3000SVipul Pandya #define F_DROPPED_DB V_DROPPED_DB(1U) 3313069ee9bSVipul Pandya #define A_SGE_DOORBELL_CONTROL 0x10a8 3323069ee9bSVipul Pandya 3333069ee9bSVipul Pandya #define A_SGE_CTXT_CMD 0x11fc 3343069ee9bSVipul Pandya #define A_SGE_DBQ_CTXT_BADDR 0x1084 3353069ee9bSVipul Pandya 336ce91a923SNaresh Kumar Inna #define PCIE_PF_CFG 0x40 337ce91a923SNaresh Kumar Inna #define AIVEC(x) ((x) << 4) 338ce91a923SNaresh Kumar Inna #define AIVEC_MASK 0x3ffU 339ce91a923SNaresh Kumar Inna 340f7917c00SJeff Kirsher #define PCIE_PF_CLI 0x44 341f7917c00SJeff Kirsher #define PCIE_INT_CAUSE 0x3004 342f7917c00SJeff Kirsher #define UNXSPLCPLERR 0x20000000U 343f7917c00SJeff Kirsher #define PCIEPINT 0x10000000U 344f7917c00SJeff Kirsher #define PCIESINT 0x08000000U 345f7917c00SJeff Kirsher #define RPLPERR 0x04000000U 346f7917c00SJeff Kirsher #define RXWRPERR 0x02000000U 347f7917c00SJeff Kirsher #define RXCPLPERR 0x01000000U 348f7917c00SJeff Kirsher #define PIOTAGPERR 0x00800000U 349f7917c00SJeff Kirsher #define MATAGPERR 0x00400000U 350f7917c00SJeff Kirsher #define INTXCLRPERR 0x00200000U 351f7917c00SJeff Kirsher #define FIDPERR 0x00100000U 352f7917c00SJeff Kirsher #define CFGSNPPERR 0x00080000U 353f7917c00SJeff Kirsher #define HRSPPERR 0x00040000U 354f7917c00SJeff Kirsher #define HREQPERR 0x00020000U 355f7917c00SJeff Kirsher #define HCNTPERR 0x00010000U 356f7917c00SJeff Kirsher #define DRSPPERR 0x00008000U 357f7917c00SJeff Kirsher #define DREQPERR 0x00004000U 358f7917c00SJeff Kirsher #define DCNTPERR 0x00002000U 359f7917c00SJeff Kirsher #define CRSPPERR 0x00001000U 360f7917c00SJeff Kirsher #define CREQPERR 0x00000800U 361f7917c00SJeff Kirsher #define CCNTPERR 0x00000400U 362f7917c00SJeff Kirsher #define TARTAGPERR 0x00000200U 363f7917c00SJeff Kirsher #define PIOREQPERR 0x00000100U 364f7917c00SJeff Kirsher #define PIOCPLPERR 0x00000080U 365f7917c00SJeff Kirsher #define MSIXDIPERR 0x00000040U 366f7917c00SJeff Kirsher #define MSIXDATAPERR 0x00000020U 367f7917c00SJeff Kirsher #define MSIXADDRHPERR 0x00000010U 368f7917c00SJeff Kirsher #define MSIXADDRLPERR 0x00000008U 369f7917c00SJeff Kirsher #define MSIDATAPERR 0x00000004U 370f7917c00SJeff Kirsher #define MSIADDRHPERR 0x00000002U 371f7917c00SJeff Kirsher #define MSIADDRLPERR 0x00000001U 372f7917c00SJeff Kirsher 373b2decaddSSantosh Rastapur #define READRSPERR 0x20000000U 374b2decaddSSantosh Rastapur #define TRGT1GRPPERR 0x10000000U 375b2decaddSSantosh Rastapur #define IPSOTPERR 0x08000000U 376b2decaddSSantosh Rastapur #define IPRXDATAGRPPERR 0x02000000U 377b2decaddSSantosh Rastapur #define IPRXHDRGRPPERR 0x01000000U 378b2decaddSSantosh Rastapur #define MAGRPPERR 0x00400000U 379b2decaddSSantosh Rastapur #define VFIDPERR 0x00200000U 380b2decaddSSantosh Rastapur #define HREQWRPERR 0x00010000U 381b2decaddSSantosh Rastapur #define DREQWRPERR 0x00002000U 382b2decaddSSantosh Rastapur #define MSTTAGQPERR 0x00000400U 383b2decaddSSantosh Rastapur #define PIOREQGRPPERR 0x00000100U 384b2decaddSSantosh Rastapur #define PIOCPLGRPPERR 0x00000080U 385b2decaddSSantosh Rastapur #define MSIXSTIPERR 0x00000004U 386b2decaddSSantosh Rastapur #define MSTTIMEOUTPERR 0x00000002U 387b2decaddSSantosh Rastapur #define MSTGRPPERR 0x00000001U 388b2decaddSSantosh Rastapur 389f7917c00SJeff Kirsher #define PCIE_NONFAT_ERR 0x3010 390f7917c00SJeff Kirsher #define PCIE_MEM_ACCESS_BASE_WIN 0x3068 391b2decaddSSantosh Rastapur #define S_PCIEOFST 10 392b2decaddSSantosh Rastapur #define M_PCIEOFST 0x3fffffU 393b2decaddSSantosh Rastapur #define GET_PCIEOFST(x) (((x) >> S_PCIEOFST) & M_PCIEOFST) 394f7917c00SJeff Kirsher #define PCIEOFST_MASK 0xfffffc00U 395f7917c00SJeff Kirsher #define BIR_MASK 0x00000300U 396f7917c00SJeff Kirsher #define BIR_SHIFT 8 397f7917c00SJeff Kirsher #define BIR(x) ((x) << BIR_SHIFT) 398f7917c00SJeff Kirsher #define WINDOW_MASK 0x000000ffU 399f7917c00SJeff Kirsher #define WINDOW_SHIFT 0 400f7917c00SJeff Kirsher #define WINDOW(x) ((x) << WINDOW_SHIFT) 401f7917c00SJeff Kirsher #define PCIE_MEM_ACCESS_OFFSET 0x306c 402f7917c00SJeff Kirsher 403b2decaddSSantosh Rastapur #define S_PFNUM 0 404b2decaddSSantosh Rastapur #define V_PFNUM(x) ((x) << S_PFNUM) 405b2decaddSSantosh Rastapur 40626f7cbc0SVipul Pandya #define PCIE_FW 0x30b8 407ce91a923SNaresh Kumar Inna #define PCIE_FW_ERR 0x80000000U 408ce91a923SNaresh Kumar Inna #define PCIE_FW_INIT 0x40000000U 409ce91a923SNaresh Kumar Inna #define PCIE_FW_HALT 0x20000000U 410ce91a923SNaresh Kumar Inna #define PCIE_FW_MASTER_VLD 0x00008000U 411ce91a923SNaresh Kumar Inna #define PCIE_FW_MASTER(x) ((x) << 12) 412ce91a923SNaresh Kumar Inna #define PCIE_FW_MASTER_MASK 0x7 413ce91a923SNaresh Kumar Inna #define PCIE_FW_MASTER_GET(x) (((x) >> 12) & PCIE_FW_MASTER_MASK) 41426f7cbc0SVipul Pandya 415f7917c00SJeff Kirsher #define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS 0x5908 416f7917c00SJeff Kirsher #define RNPP 0x80000000U 417f7917c00SJeff Kirsher #define RPCP 0x20000000U 418f7917c00SJeff Kirsher #define RCIP 0x08000000U 419f7917c00SJeff Kirsher #define RCCP 0x04000000U 420f7917c00SJeff Kirsher #define RFTP 0x00800000U 421f7917c00SJeff Kirsher #define PTRP 0x00100000U 422f7917c00SJeff Kirsher 423f7917c00SJeff Kirsher #define PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS 0x59a4 424f7917c00SJeff Kirsher #define TPCP 0x40000000U 425f7917c00SJeff Kirsher #define TNPP 0x20000000U 426f7917c00SJeff Kirsher #define TFTP 0x10000000U 427f7917c00SJeff Kirsher #define TCAP 0x08000000U 428f7917c00SJeff Kirsher #define TCIP 0x04000000U 429f7917c00SJeff Kirsher #define RCAP 0x02000000U 430f7917c00SJeff Kirsher #define PLUP 0x00800000U 431f7917c00SJeff Kirsher #define PLDN 0x00400000U 432f7917c00SJeff Kirsher #define OTDD 0x00200000U 433f7917c00SJeff Kirsher #define GTRP 0x00100000U 434f7917c00SJeff Kirsher #define RDPE 0x00040000U 435f7917c00SJeff Kirsher #define TDCE 0x00020000U 436f7917c00SJeff Kirsher #define TDUE 0x00010000U 437f7917c00SJeff Kirsher 438f7917c00SJeff Kirsher #define MC_INT_CAUSE 0x7518 439f7917c00SJeff Kirsher #define ECC_UE_INT_CAUSE 0x00000004U 440f7917c00SJeff Kirsher #define ECC_CE_INT_CAUSE 0x00000002U 441f7917c00SJeff Kirsher #define PERR_INT_CAUSE 0x00000001U 442f7917c00SJeff Kirsher 443f7917c00SJeff Kirsher #define MC_ECC_STATUS 0x751c 444f7917c00SJeff Kirsher #define ECC_CECNT_MASK 0xffff0000U 445f7917c00SJeff Kirsher #define ECC_CECNT_SHIFT 16 446f7917c00SJeff Kirsher #define ECC_CECNT(x) ((x) << ECC_CECNT_SHIFT) 447f7917c00SJeff Kirsher #define ECC_CECNT_GET(x) (((x) & ECC_CECNT_MASK) >> ECC_CECNT_SHIFT) 448f7917c00SJeff Kirsher #define ECC_UECNT_MASK 0x0000ffffU 449f7917c00SJeff Kirsher #define ECC_UECNT_SHIFT 0 450f7917c00SJeff Kirsher #define ECC_UECNT(x) ((x) << ECC_UECNT_SHIFT) 451f7917c00SJeff Kirsher #define ECC_UECNT_GET(x) (((x) & ECC_UECNT_MASK) >> ECC_UECNT_SHIFT) 452f7917c00SJeff Kirsher 453f7917c00SJeff Kirsher #define MC_BIST_CMD 0x7600 454f7917c00SJeff Kirsher #define START_BIST 0x80000000U 455f7917c00SJeff Kirsher #define BIST_CMD_GAP_MASK 0x0000ff00U 456f7917c00SJeff Kirsher #define BIST_CMD_GAP_SHIFT 8 457f7917c00SJeff Kirsher #define BIST_CMD_GAP(x) ((x) << BIST_CMD_GAP_SHIFT) 458f7917c00SJeff Kirsher #define BIST_OPCODE_MASK 0x00000003U 459f7917c00SJeff Kirsher #define BIST_OPCODE_SHIFT 0 460f7917c00SJeff Kirsher #define BIST_OPCODE(x) ((x) << BIST_OPCODE_SHIFT) 461f7917c00SJeff Kirsher 462f7917c00SJeff Kirsher #define MC_BIST_CMD_ADDR 0x7604 463f7917c00SJeff Kirsher #define MC_BIST_CMD_LEN 0x7608 464f7917c00SJeff Kirsher #define MC_BIST_DATA_PATTERN 0x760c 465f7917c00SJeff Kirsher #define BIST_DATA_TYPE_MASK 0x0000000fU 466f7917c00SJeff Kirsher #define BIST_DATA_TYPE_SHIFT 0 467f7917c00SJeff Kirsher #define BIST_DATA_TYPE(x) ((x) << BIST_DATA_TYPE_SHIFT) 468f7917c00SJeff Kirsher 469f7917c00SJeff Kirsher #define MC_BIST_STATUS_RDATA 0x7688 470f7917c00SJeff Kirsher 471b2decaddSSantosh Rastapur #define MA_EDRAM0_BAR 0x77c0 472b2decaddSSantosh Rastapur #define MA_EDRAM1_BAR 0x77c4 473b2decaddSSantosh Rastapur #define EDRAM_SIZE_MASK 0xfffU 474b2decaddSSantosh Rastapur #define EDRAM_SIZE_GET(x) ((x) & EDRAM_SIZE_MASK) 475b2decaddSSantosh Rastapur 476f7917c00SJeff Kirsher #define MA_EXT_MEMORY_BAR 0x77c8 477f7917c00SJeff Kirsher #define EXT_MEM_SIZE_MASK 0x00000fffU 478f7917c00SJeff Kirsher #define EXT_MEM_SIZE_SHIFT 0 479f7917c00SJeff Kirsher #define EXT_MEM_SIZE_GET(x) (((x) & EXT_MEM_SIZE_MASK) >> EXT_MEM_SIZE_SHIFT) 480f7917c00SJeff Kirsher 481f7917c00SJeff Kirsher #define MA_TARGET_MEM_ENABLE 0x77d8 482b2decaddSSantosh Rastapur #define EXT_MEM1_ENABLE 0x00000010U 483f7917c00SJeff Kirsher #define EXT_MEM_ENABLE 0x00000004U 484f7917c00SJeff Kirsher #define EDRAM1_ENABLE 0x00000002U 485f7917c00SJeff Kirsher #define EDRAM0_ENABLE 0x00000001U 486f7917c00SJeff Kirsher 487f7917c00SJeff Kirsher #define MA_INT_CAUSE 0x77e0 488f7917c00SJeff Kirsher #define MEM_PERR_INT_CAUSE 0x00000002U 489f7917c00SJeff Kirsher #define MEM_WRAP_INT_CAUSE 0x00000001U 490f7917c00SJeff Kirsher 491f7917c00SJeff Kirsher #define MA_INT_WRAP_STATUS 0x77e4 492f7917c00SJeff Kirsher #define MEM_WRAP_ADDRESS_MASK 0xfffffff0U 493f7917c00SJeff Kirsher #define MEM_WRAP_ADDRESS_SHIFT 4 494f7917c00SJeff Kirsher #define MEM_WRAP_ADDRESS_GET(x) (((x) & MEM_WRAP_ADDRESS_MASK) >> MEM_WRAP_ADDRESS_SHIFT) 495f7917c00SJeff Kirsher #define MEM_WRAP_CLIENT_NUM_MASK 0x0000000fU 496f7917c00SJeff Kirsher #define MEM_WRAP_CLIENT_NUM_SHIFT 0 497f7917c00SJeff Kirsher #define MEM_WRAP_CLIENT_NUM_GET(x) (((x) & MEM_WRAP_CLIENT_NUM_MASK) >> MEM_WRAP_CLIENT_NUM_SHIFT) 498636f9d37SVipul Pandya #define MA_PCIE_FW 0x30b8 499f7917c00SJeff Kirsher #define MA_PARITY_ERROR_STATUS 0x77f4 500f7917c00SJeff Kirsher 501b2decaddSSantosh Rastapur #define MA_EXT_MEMORY1_BAR 0x7808 502f7917c00SJeff Kirsher #define EDC_0_BASE_ADDR 0x7900 503f7917c00SJeff Kirsher 504f7917c00SJeff Kirsher #define EDC_BIST_CMD 0x7904 505f7917c00SJeff Kirsher #define EDC_BIST_CMD_ADDR 0x7908 506f7917c00SJeff Kirsher #define EDC_BIST_CMD_LEN 0x790c 507f7917c00SJeff Kirsher #define EDC_BIST_DATA_PATTERN 0x7910 508f7917c00SJeff Kirsher #define EDC_BIST_STATUS_RDATA 0x7928 509f7917c00SJeff Kirsher #define EDC_INT_CAUSE 0x7978 510f7917c00SJeff Kirsher #define ECC_UE_PAR 0x00000020U 511f7917c00SJeff Kirsher #define ECC_CE_PAR 0x00000010U 512f7917c00SJeff Kirsher #define PERR_PAR_CAUSE 0x00000008U 513f7917c00SJeff Kirsher 514f7917c00SJeff Kirsher #define EDC_ECC_STATUS 0x797c 515f7917c00SJeff Kirsher 516f7917c00SJeff Kirsher #define EDC_1_BASE_ADDR 0x7980 517f7917c00SJeff Kirsher 518f7917c00SJeff Kirsher #define CIM_BOOT_CFG 0x7b00 519f7917c00SJeff Kirsher #define BOOTADDR_MASK 0xffffff00U 52026f7cbc0SVipul Pandya #define UPCRST 0x1U 521f7917c00SJeff Kirsher 522f7917c00SJeff Kirsher #define CIM_PF_MAILBOX_DATA 0x240 523f7917c00SJeff Kirsher #define CIM_PF_MAILBOX_CTRL 0x280 524f7917c00SJeff Kirsher #define MBMSGVALID 0x00000008U 525f7917c00SJeff Kirsher #define MBINTREQ 0x00000004U 526f7917c00SJeff Kirsher #define MBOWNER_MASK 0x00000003U 527f7917c00SJeff Kirsher #define MBOWNER_SHIFT 0 528f7917c00SJeff Kirsher #define MBOWNER(x) ((x) << MBOWNER_SHIFT) 529f7917c00SJeff Kirsher #define MBOWNER_GET(x) (((x) & MBOWNER_MASK) >> MBOWNER_SHIFT) 530f7917c00SJeff Kirsher 531ce91a923SNaresh Kumar Inna #define CIM_PF_HOST_INT_ENABLE 0x288 532ce91a923SNaresh Kumar Inna #define MBMSGRDYINTEN(x) ((x) << 19) 533ce91a923SNaresh Kumar Inna 534f7917c00SJeff Kirsher #define CIM_PF_HOST_INT_CAUSE 0x28c 535f7917c00SJeff Kirsher #define MBMSGRDYINT 0x00080000U 536f7917c00SJeff Kirsher 537f7917c00SJeff Kirsher #define CIM_HOST_INT_CAUSE 0x7b2c 538f7917c00SJeff Kirsher #define TIEQOUTPARERRINT 0x00100000U 539f7917c00SJeff Kirsher #define TIEQINPARERRINT 0x00080000U 540f7917c00SJeff Kirsher #define MBHOSTPARERR 0x00040000U 541f7917c00SJeff Kirsher #define MBUPPARERR 0x00020000U 542f7917c00SJeff Kirsher #define IBQPARERR 0x0001f800U 543f7917c00SJeff Kirsher #define IBQTP0PARERR 0x00010000U 544f7917c00SJeff Kirsher #define IBQTP1PARERR 0x00008000U 545f7917c00SJeff Kirsher #define IBQULPPARERR 0x00004000U 546f7917c00SJeff Kirsher #define IBQSGELOPARERR 0x00002000U 547f7917c00SJeff Kirsher #define IBQSGEHIPARERR 0x00001000U 548f7917c00SJeff Kirsher #define IBQNCSIPARERR 0x00000800U 549f7917c00SJeff Kirsher #define OBQPARERR 0x000007e0U 550f7917c00SJeff Kirsher #define OBQULP0PARERR 0x00000400U 551f7917c00SJeff Kirsher #define OBQULP1PARERR 0x00000200U 552f7917c00SJeff Kirsher #define OBQULP2PARERR 0x00000100U 553f7917c00SJeff Kirsher #define OBQULP3PARERR 0x00000080U 554f7917c00SJeff Kirsher #define OBQSGEPARERR 0x00000040U 555f7917c00SJeff Kirsher #define OBQNCSIPARERR 0x00000020U 556f7917c00SJeff Kirsher #define PREFDROPINT 0x00000002U 557f7917c00SJeff Kirsher #define UPACCNONZERO 0x00000001U 558f7917c00SJeff Kirsher 559f7917c00SJeff Kirsher #define CIM_HOST_UPACC_INT_CAUSE 0x7b34 560f7917c00SJeff Kirsher #define EEPROMWRINT 0x40000000U 561f7917c00SJeff Kirsher #define TIMEOUTMAINT 0x20000000U 562f7917c00SJeff Kirsher #define TIMEOUTINT 0x10000000U 563f7917c00SJeff Kirsher #define RSPOVRLOOKUPINT 0x08000000U 564f7917c00SJeff Kirsher #define REQOVRLOOKUPINT 0x04000000U 565f7917c00SJeff Kirsher #define BLKWRPLINT 0x02000000U 566f7917c00SJeff Kirsher #define BLKRDPLINT 0x01000000U 567f7917c00SJeff Kirsher #define SGLWRPLINT 0x00800000U 568f7917c00SJeff Kirsher #define SGLRDPLINT 0x00400000U 569f7917c00SJeff Kirsher #define BLKWRCTLINT 0x00200000U 570f7917c00SJeff Kirsher #define BLKRDCTLINT 0x00100000U 571f7917c00SJeff Kirsher #define SGLWRCTLINT 0x00080000U 572f7917c00SJeff Kirsher #define SGLRDCTLINT 0x00040000U 573f7917c00SJeff Kirsher #define BLKWREEPROMINT 0x00020000U 574f7917c00SJeff Kirsher #define BLKRDEEPROMINT 0x00010000U 575f7917c00SJeff Kirsher #define SGLWREEPROMINT 0x00008000U 576f7917c00SJeff Kirsher #define SGLRDEEPROMINT 0x00004000U 577f7917c00SJeff Kirsher #define BLKWRFLASHINT 0x00002000U 578f7917c00SJeff Kirsher #define BLKRDFLASHINT 0x00001000U 579f7917c00SJeff Kirsher #define SGLWRFLASHINT 0x00000800U 580f7917c00SJeff Kirsher #define SGLRDFLASHINT 0x00000400U 581f7917c00SJeff Kirsher #define BLKWRBOOTINT 0x00000200U 582f7917c00SJeff Kirsher #define BLKRDBOOTINT 0x00000100U 583f7917c00SJeff Kirsher #define SGLWRBOOTINT 0x00000080U 584f7917c00SJeff Kirsher #define SGLRDBOOTINT 0x00000040U 585f7917c00SJeff Kirsher #define ILLWRBEINT 0x00000020U 586f7917c00SJeff Kirsher #define ILLRDBEINT 0x00000010U 587f7917c00SJeff Kirsher #define ILLRDINT 0x00000008U 588f7917c00SJeff Kirsher #define ILLWRINT 0x00000004U 589f7917c00SJeff Kirsher #define ILLTRANSINT 0x00000002U 590f7917c00SJeff Kirsher #define RSVDSPACEINT 0x00000001U 591f7917c00SJeff Kirsher 592f7917c00SJeff Kirsher #define TP_OUT_CONFIG 0x7d04 593f7917c00SJeff Kirsher #define VLANEXTENABLE_MASK 0x0000f000U 594f7917c00SJeff Kirsher #define VLANEXTENABLE_SHIFT 12 595f7917c00SJeff Kirsher 59613ee15d3SVipul Pandya #define TP_GLOBAL_CONFIG 0x7d08 59713ee15d3SVipul Pandya #define FIVETUPLELOOKUP_SHIFT 17 59813ee15d3SVipul Pandya #define FIVETUPLELOOKUP_MASK 0x00060000U 59913ee15d3SVipul Pandya #define FIVETUPLELOOKUP(x) ((x) << FIVETUPLELOOKUP_SHIFT) 60013ee15d3SVipul Pandya #define FIVETUPLELOOKUP_GET(x) (((x) & FIVETUPLELOOKUP_MASK) >> \ 60113ee15d3SVipul Pandya FIVETUPLELOOKUP_SHIFT) 60213ee15d3SVipul Pandya 603f7917c00SJeff Kirsher #define TP_PARA_REG2 0x7d68 604f7917c00SJeff Kirsher #define MAXRXDATA_MASK 0xffff0000U 605f7917c00SJeff Kirsher #define MAXRXDATA_SHIFT 16 606f7917c00SJeff Kirsher #define MAXRXDATA_GET(x) (((x) & MAXRXDATA_MASK) >> MAXRXDATA_SHIFT) 607f7917c00SJeff Kirsher 608f7917c00SJeff Kirsher #define TP_TIMER_RESOLUTION 0x7d90 609f7917c00SJeff Kirsher #define TIMERRESOLUTION_MASK 0x00ff0000U 610f7917c00SJeff Kirsher #define TIMERRESOLUTION_SHIFT 16 611f7917c00SJeff Kirsher #define TIMERRESOLUTION_GET(x) (((x) & TIMERRESOLUTION_MASK) >> TIMERRESOLUTION_SHIFT) 612636f9d37SVipul Pandya #define DELAYEDACKRESOLUTION_MASK 0x000000ffU 613636f9d37SVipul Pandya #define DELAYEDACKRESOLUTION_SHIFT 0 614636f9d37SVipul Pandya #define DELAYEDACKRESOLUTION_GET(x) \ 615636f9d37SVipul Pandya (((x) & DELAYEDACKRESOLUTION_MASK) >> DELAYEDACKRESOLUTION_SHIFT) 616f7917c00SJeff Kirsher 617f7917c00SJeff Kirsher #define TP_SHIFT_CNT 0x7dc0 61813ee15d3SVipul Pandya #define SYNSHIFTMAX_SHIFT 24 61913ee15d3SVipul Pandya #define SYNSHIFTMAX_MASK 0xff000000U 62013ee15d3SVipul Pandya #define SYNSHIFTMAX(x) ((x) << SYNSHIFTMAX_SHIFT) 62113ee15d3SVipul Pandya #define SYNSHIFTMAX_GET(x) (((x) & SYNSHIFTMAX_MASK) >> \ 62213ee15d3SVipul Pandya SYNSHIFTMAX_SHIFT) 62313ee15d3SVipul Pandya #define RXTSHIFTMAXR1_SHIFT 20 62413ee15d3SVipul Pandya #define RXTSHIFTMAXR1_MASK 0x00f00000U 62513ee15d3SVipul Pandya #define RXTSHIFTMAXR1(x) ((x) << RXTSHIFTMAXR1_SHIFT) 62613ee15d3SVipul Pandya #define RXTSHIFTMAXR1_GET(x) (((x) & RXTSHIFTMAXR1_MASK) >> \ 62713ee15d3SVipul Pandya RXTSHIFTMAXR1_SHIFT) 62813ee15d3SVipul Pandya #define RXTSHIFTMAXR2_SHIFT 16 62913ee15d3SVipul Pandya #define RXTSHIFTMAXR2_MASK 0x000f0000U 63013ee15d3SVipul Pandya #define RXTSHIFTMAXR2(x) ((x) << RXTSHIFTMAXR2_SHIFT) 63113ee15d3SVipul Pandya #define RXTSHIFTMAXR2_GET(x) (((x) & RXTSHIFTMAXR2_MASK) >> \ 63213ee15d3SVipul Pandya RXTSHIFTMAXR2_SHIFT) 63313ee15d3SVipul Pandya #define PERSHIFTBACKOFFMAX_SHIFT 12 63413ee15d3SVipul Pandya #define PERSHIFTBACKOFFMAX_MASK 0x0000f000U 63513ee15d3SVipul Pandya #define PERSHIFTBACKOFFMAX(x) ((x) << PERSHIFTBACKOFFMAX_SHIFT) 63613ee15d3SVipul Pandya #define PERSHIFTBACKOFFMAX_GET(x) (((x) & PERSHIFTBACKOFFMAX_MASK) >> \ 63713ee15d3SVipul Pandya PERSHIFTBACKOFFMAX_SHIFT) 63813ee15d3SVipul Pandya #define PERSHIFTMAX_SHIFT 8 63913ee15d3SVipul Pandya #define PERSHIFTMAX_MASK 0x00000f00U 64013ee15d3SVipul Pandya #define PERSHIFTMAX(x) ((x) << PERSHIFTMAX_SHIFT) 64113ee15d3SVipul Pandya #define PERSHIFTMAX_GET(x) (((x) & PERSHIFTMAX_MASK) >> \ 64213ee15d3SVipul Pandya PERSHIFTMAX_SHIFT) 64313ee15d3SVipul Pandya #define KEEPALIVEMAXR1_SHIFT 4 64413ee15d3SVipul Pandya #define KEEPALIVEMAXR1_MASK 0x000000f0U 64513ee15d3SVipul Pandya #define KEEPALIVEMAXR1(x) ((x) << KEEPALIVEMAXR1_SHIFT) 64613ee15d3SVipul Pandya #define KEEPALIVEMAXR1_GET(x) (((x) & KEEPALIVEMAXR1_MASK) >> \ 64713ee15d3SVipul Pandya KEEPALIVEMAXR1_SHIFT) 64813ee15d3SVipul Pandya #define KEEPALIVEMAXR2_SHIFT 0 64913ee15d3SVipul Pandya #define KEEPALIVEMAXR2_MASK 0x0000000fU 65013ee15d3SVipul Pandya #define KEEPALIVEMAXR2(x) ((x) << KEEPALIVEMAXR2_SHIFT) 65113ee15d3SVipul Pandya #define KEEPALIVEMAXR2_GET(x) (((x) & KEEPALIVEMAXR2_MASK) >> \ 65213ee15d3SVipul Pandya KEEPALIVEMAXR2_SHIFT) 653f7917c00SJeff Kirsher 654f7917c00SJeff Kirsher #define TP_CCTRL_TABLE 0x7ddc 655f7917c00SJeff Kirsher #define TP_MTU_TABLE 0x7de4 656f7917c00SJeff Kirsher #define MTUINDEX_MASK 0xff000000U 657f7917c00SJeff Kirsher #define MTUINDEX_SHIFT 24 658f7917c00SJeff Kirsher #define MTUINDEX(x) ((x) << MTUINDEX_SHIFT) 659f7917c00SJeff Kirsher #define MTUWIDTH_MASK 0x000f0000U 660f7917c00SJeff Kirsher #define MTUWIDTH_SHIFT 16 661f7917c00SJeff Kirsher #define MTUWIDTH(x) ((x) << MTUWIDTH_SHIFT) 662f7917c00SJeff Kirsher #define MTUWIDTH_GET(x) (((x) & MTUWIDTH_MASK) >> MTUWIDTH_SHIFT) 663f7917c00SJeff Kirsher #define MTUVALUE_MASK 0x00003fffU 664f7917c00SJeff Kirsher #define MTUVALUE_SHIFT 0 665f7917c00SJeff Kirsher #define MTUVALUE(x) ((x) << MTUVALUE_SHIFT) 666f7917c00SJeff Kirsher #define MTUVALUE_GET(x) (((x) & MTUVALUE_MASK) >> MTUVALUE_SHIFT) 667f7917c00SJeff Kirsher 668f7917c00SJeff Kirsher #define TP_RSS_LKP_TABLE 0x7dec 669f7917c00SJeff Kirsher #define LKPTBLROWVLD 0x80000000U 670f7917c00SJeff Kirsher #define LKPTBLQUEUE1_MASK 0x000ffc00U 671f7917c00SJeff Kirsher #define LKPTBLQUEUE1_SHIFT 10 672f7917c00SJeff Kirsher #define LKPTBLQUEUE1(x) ((x) << LKPTBLQUEUE1_SHIFT) 673f7917c00SJeff Kirsher #define LKPTBLQUEUE1_GET(x) (((x) & LKPTBLQUEUE1_MASK) >> LKPTBLQUEUE1_SHIFT) 674f7917c00SJeff Kirsher #define LKPTBLQUEUE0_MASK 0x000003ffU 675f7917c00SJeff Kirsher #define LKPTBLQUEUE0_SHIFT 0 676f7917c00SJeff Kirsher #define LKPTBLQUEUE0(x) ((x) << LKPTBLQUEUE0_SHIFT) 677f7917c00SJeff Kirsher #define LKPTBLQUEUE0_GET(x) (((x) & LKPTBLQUEUE0_MASK) >> LKPTBLQUEUE0_SHIFT) 678f7917c00SJeff Kirsher 679f7917c00SJeff Kirsher #define TP_PIO_ADDR 0x7e40 680f7917c00SJeff Kirsher #define TP_PIO_DATA 0x7e44 681f7917c00SJeff Kirsher #define TP_MIB_INDEX 0x7e50 682f7917c00SJeff Kirsher #define TP_MIB_DATA 0x7e54 683f7917c00SJeff Kirsher #define TP_INT_CAUSE 0x7e74 684f7917c00SJeff Kirsher #define FLMTXFLSTEMPTY 0x40000000U 685f7917c00SJeff Kirsher 68613ee15d3SVipul Pandya #define TP_VLAN_PRI_MAP 0x140 68713ee15d3SVipul Pandya #define FRAGMENTATION_SHIFT 9 68813ee15d3SVipul Pandya #define FRAGMENTATION_MASK 0x00000200U 68913ee15d3SVipul Pandya #define MPSHITTYPE_MASK 0x00000100U 69013ee15d3SVipul Pandya #define MACMATCH_MASK 0x00000080U 69113ee15d3SVipul Pandya #define ETHERTYPE_MASK 0x00000040U 69213ee15d3SVipul Pandya #define PROTOCOL_MASK 0x00000020U 69313ee15d3SVipul Pandya #define TOS_MASK 0x00000010U 69413ee15d3SVipul Pandya #define VLAN_MASK 0x00000008U 69513ee15d3SVipul Pandya #define VNIC_ID_MASK 0x00000004U 69613ee15d3SVipul Pandya #define PORT_MASK 0x00000002U 69713ee15d3SVipul Pandya #define FCOE_SHIFT 0 69813ee15d3SVipul Pandya #define FCOE_MASK 0x00000001U 69913ee15d3SVipul Pandya 700f7917c00SJeff Kirsher #define TP_INGRESS_CONFIG 0x141 701f7917c00SJeff Kirsher #define VNIC 0x00000800U 702f7917c00SJeff Kirsher #define CSUM_HAS_PSEUDO_HDR 0x00000400U 703f7917c00SJeff Kirsher #define RM_OVLAN 0x00000200U 704f7917c00SJeff Kirsher #define LOOKUPEVERYPKT 0x00000100U 705f7917c00SJeff Kirsher 706f7917c00SJeff Kirsher #define TP_MIB_MAC_IN_ERR_0 0x0 707f7917c00SJeff Kirsher #define TP_MIB_TCP_OUT_RST 0xc 708f7917c00SJeff Kirsher #define TP_MIB_TCP_IN_SEG_HI 0x10 709f7917c00SJeff Kirsher #define TP_MIB_TCP_IN_SEG_LO 0x11 710f7917c00SJeff Kirsher #define TP_MIB_TCP_OUT_SEG_HI 0x12 711f7917c00SJeff Kirsher #define TP_MIB_TCP_OUT_SEG_LO 0x13 712f7917c00SJeff Kirsher #define TP_MIB_TCP_RXT_SEG_HI 0x14 713f7917c00SJeff Kirsher #define TP_MIB_TCP_RXT_SEG_LO 0x15 714f7917c00SJeff Kirsher #define TP_MIB_TNL_CNG_DROP_0 0x18 715f7917c00SJeff Kirsher #define TP_MIB_TCP_V6IN_ERR_0 0x28 716f7917c00SJeff Kirsher #define TP_MIB_TCP_V6OUT_RST 0x2c 717f7917c00SJeff Kirsher #define TP_MIB_OFD_ARP_DROP 0x36 718f7917c00SJeff Kirsher #define TP_MIB_TNL_DROP_0 0x44 719f7917c00SJeff Kirsher #define TP_MIB_OFD_VLN_DROP_0 0x58 720f7917c00SJeff Kirsher 721f7917c00SJeff Kirsher #define ULP_TX_INT_CAUSE 0x8dcc 722f7917c00SJeff Kirsher #define PBL_BOUND_ERR_CH3 0x80000000U 723f7917c00SJeff Kirsher #define PBL_BOUND_ERR_CH2 0x40000000U 724f7917c00SJeff Kirsher #define PBL_BOUND_ERR_CH1 0x20000000U 725f7917c00SJeff Kirsher #define PBL_BOUND_ERR_CH0 0x10000000U 726f7917c00SJeff Kirsher 727f7917c00SJeff Kirsher #define PM_RX_INT_CAUSE 0x8fdc 728f7917c00SJeff Kirsher #define ZERO_E_CMD_ERROR 0x00400000U 729f7917c00SJeff Kirsher #define PMRX_FRAMING_ERROR 0x003ffff0U 730f7917c00SJeff Kirsher #define OCSPI_PAR_ERROR 0x00000008U 731f7917c00SJeff Kirsher #define DB_OPTIONS_PAR_ERROR 0x00000004U 732f7917c00SJeff Kirsher #define IESPI_PAR_ERROR 0x00000002U 733f7917c00SJeff Kirsher #define E_PCMD_PAR_ERROR 0x00000001U 734f7917c00SJeff Kirsher 735f7917c00SJeff Kirsher #define PM_TX_INT_CAUSE 0x8ffc 736f7917c00SJeff Kirsher #define PCMD_LEN_OVFL0 0x80000000U 737f7917c00SJeff Kirsher #define PCMD_LEN_OVFL1 0x40000000U 738f7917c00SJeff Kirsher #define PCMD_LEN_OVFL2 0x20000000U 739f7917c00SJeff Kirsher #define ZERO_C_CMD_ERROR 0x10000000U 740f7917c00SJeff Kirsher #define PMTX_FRAMING_ERROR 0x0ffffff0U 741f7917c00SJeff Kirsher #define OESPI_PAR_ERROR 0x00000008U 742f7917c00SJeff Kirsher #define ICSPI_PAR_ERROR 0x00000002U 743f7917c00SJeff Kirsher #define C_PCMD_PAR_ERROR 0x00000001U 744f7917c00SJeff Kirsher 745f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_BYTES_L 0x400 746f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_BYTES_H 0x404 747f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408 748f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c 749f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_BCAST_L 0x410 750f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_BCAST_H 0x414 751f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_MCAST_L 0x418 752f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c 753f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_UCAST_L 0x420 754f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_UCAST_H 0x424 755f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_ERROR_L 0x428 756f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c 757f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_64B_L 0x430 758f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_64B_H 0x434 759f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438 760f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c 761f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440 762f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444 763f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448 764f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c 765f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450 766f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454 767f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458 768f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c 769f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460 770f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464 771f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_DROP_L 0x468 772f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_DROP_H 0x46c 773f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470 774f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474 775f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PPP0_L 0x478 776f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c 777f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PPP1_L 0x480 778f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PPP1_H 0x484 779f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PPP2_L 0x488 780f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c 781f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PPP3_L 0x490 782f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PPP3_H 0x494 783f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PPP4_L 0x498 784f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c 785f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0 786f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4 787f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8 788f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac 789f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0 790f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4 791f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0 792f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4 793f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8 794f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc 795f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0 796f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4 797f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8 798f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc 799f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0 800f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4 801f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8 802f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec 803f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_64B_L 0x4f0 804f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_64B_H 0x4f4 805f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8 806f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc 807f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500 808f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504 809f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508 810f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c 811f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510 812f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514 813f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518 814f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c 815f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520 816f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524 817f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528 818f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_BYTES_L 0x540 819f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_BYTES_H 0x544 820f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548 821f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c 822f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_BCAST_L 0x550 823f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_BCAST_H 0x554 824f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_MCAST_L 0x558 825f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c 826f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_UCAST_L 0x560 827f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_UCAST_H 0x564 828f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568 829f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c 830f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570 831f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574 832f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578 833f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c 834f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580 835f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584 836f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588 837f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c 838f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_64B_L 0x590 839f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_64B_H 0x594 840f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598 841f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c 842f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0 843f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4 844f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8 845f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac 846f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0 847f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4 848f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8 849f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc 850f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0 851f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4 852f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8 853f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc 854f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0 855f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4 856f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8 857f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc 858f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0 859f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4 860f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8 861f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec 862f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0 863f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4 864f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8 865f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc 866f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PPP6_L 0x600 867f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PPP6_H 0x604 868f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PPP7_L 0x608 869f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c 870f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610 871f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614 872b2decaddSSantosh Rastapur #define MAC_PORT_CFG2 0x818 873b2decaddSSantosh Rastapur #define MAC_PORT_MAGIC_MACID_LO 0x824 874b2decaddSSantosh Rastapur #define MAC_PORT_MAGIC_MACID_HI 0x828 875b2decaddSSantosh Rastapur #define MAC_PORT_EPIO_DATA0 0x8c0 876b2decaddSSantosh Rastapur #define MAC_PORT_EPIO_DATA1 0x8c4 877b2decaddSSantosh Rastapur #define MAC_PORT_EPIO_DATA2 0x8c8 878b2decaddSSantosh Rastapur #define MAC_PORT_EPIO_DATA3 0x8cc 879b2decaddSSantosh Rastapur #define MAC_PORT_EPIO_OP 0x8d0 880b2decaddSSantosh Rastapur 881f7917c00SJeff Kirsher #define MPS_CMN_CTL 0x9000 882f7917c00SJeff Kirsher #define NUMPORTS_MASK 0x00000003U 883f7917c00SJeff Kirsher #define NUMPORTS_SHIFT 0 884f7917c00SJeff Kirsher #define NUMPORTS_GET(x) (((x) & NUMPORTS_MASK) >> NUMPORTS_SHIFT) 885f7917c00SJeff Kirsher 886f7917c00SJeff Kirsher #define MPS_INT_CAUSE 0x9008 887f7917c00SJeff Kirsher #define STATINT 0x00000020U 888f7917c00SJeff Kirsher #define TXINT 0x00000010U 889f7917c00SJeff Kirsher #define RXINT 0x00000008U 890f7917c00SJeff Kirsher #define TRCINT 0x00000004U 891f7917c00SJeff Kirsher #define CLSINT 0x00000002U 892f7917c00SJeff Kirsher #define PLINT 0x00000001U 893f7917c00SJeff Kirsher 894f7917c00SJeff Kirsher #define MPS_TX_INT_CAUSE 0x9408 895f7917c00SJeff Kirsher #define PORTERR 0x00010000U 896f7917c00SJeff Kirsher #define FRMERR 0x00008000U 897f7917c00SJeff Kirsher #define SECNTERR 0x00004000U 898f7917c00SJeff Kirsher #define BUBBLE 0x00002000U 899f7917c00SJeff Kirsher #define TXDESCFIFO 0x00001e00U 900f7917c00SJeff Kirsher #define TXDATAFIFO 0x000001e0U 901f7917c00SJeff Kirsher #define NCSIFIFO 0x00000010U 902f7917c00SJeff Kirsher #define TPFIFO 0x0000000fU 903f7917c00SJeff Kirsher 904f7917c00SJeff Kirsher #define MPS_STAT_PERR_INT_CAUSE_SRAM 0x9614 905f7917c00SJeff Kirsher #define MPS_STAT_PERR_INT_CAUSE_TX_FIFO 0x9620 906f7917c00SJeff Kirsher #define MPS_STAT_PERR_INT_CAUSE_RX_FIFO 0x962c 907f7917c00SJeff Kirsher 908f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640 909f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644 910f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648 911f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c 912f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650 913f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654 914f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658 915f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c 916f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660 917f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664 918f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668 919f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c 920f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670 921f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674 922f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678 923f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c 924f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680 925f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684 926f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688 927f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c 928f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690 929f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694 930f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698 931f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c 932f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0 933f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4 934f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8 935f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac 936f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0 937f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4 938f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8 939f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc 940f7917c00SJeff Kirsher #define MPS_TRC_CFG 0x9800 941f7917c00SJeff Kirsher #define TRCFIFOEMPTY 0x00000010U 942f7917c00SJeff Kirsher #define TRCIGNOREDROPINPUT 0x00000008U 943f7917c00SJeff Kirsher #define TRCKEEPDUPLICATES 0x00000004U 944f7917c00SJeff Kirsher #define TRCEN 0x00000002U 945f7917c00SJeff Kirsher #define TRCMULTIFILTER 0x00000001U 946f7917c00SJeff Kirsher 947f7917c00SJeff Kirsher #define MPS_TRC_RSS_CONTROL 0x9808 948f7917c00SJeff Kirsher #define RSSCONTROL_MASK 0x00ff0000U 949f7917c00SJeff Kirsher #define RSSCONTROL_SHIFT 16 950f7917c00SJeff Kirsher #define RSSCONTROL(x) ((x) << RSSCONTROL_SHIFT) 951f7917c00SJeff Kirsher #define QUEUENUMBER_MASK 0x0000ffffU 952f7917c00SJeff Kirsher #define QUEUENUMBER_SHIFT 0 953f7917c00SJeff Kirsher #define QUEUENUMBER(x) ((x) << QUEUENUMBER_SHIFT) 954f7917c00SJeff Kirsher 955f7917c00SJeff Kirsher #define MPS_TRC_FILTER_MATCH_CTL_A 0x9810 956f7917c00SJeff Kirsher #define TFINVERTMATCH 0x01000000U 957f7917c00SJeff Kirsher #define TFPKTTOOLARGE 0x00800000U 958f7917c00SJeff Kirsher #define TFEN 0x00400000U 959f7917c00SJeff Kirsher #define TFPORT_MASK 0x003c0000U 960f7917c00SJeff Kirsher #define TFPORT_SHIFT 18 961f7917c00SJeff Kirsher #define TFPORT(x) ((x) << TFPORT_SHIFT) 962f7917c00SJeff Kirsher #define TFPORT_GET(x) (((x) & TFPORT_MASK) >> TFPORT_SHIFT) 963f7917c00SJeff Kirsher #define TFDROP 0x00020000U 964f7917c00SJeff Kirsher #define TFSOPEOPERR 0x00010000U 965f7917c00SJeff Kirsher #define TFLENGTH_MASK 0x00001f00U 966f7917c00SJeff Kirsher #define TFLENGTH_SHIFT 8 967f7917c00SJeff Kirsher #define TFLENGTH(x) ((x) << TFLENGTH_SHIFT) 968f7917c00SJeff Kirsher #define TFLENGTH_GET(x) (((x) & TFLENGTH_MASK) >> TFLENGTH_SHIFT) 969f7917c00SJeff Kirsher #define TFOFFSET_MASK 0x0000001fU 970f7917c00SJeff Kirsher #define TFOFFSET_SHIFT 0 971f7917c00SJeff Kirsher #define TFOFFSET(x) ((x) << TFOFFSET_SHIFT) 972f7917c00SJeff Kirsher #define TFOFFSET_GET(x) (((x) & TFOFFSET_MASK) >> TFOFFSET_SHIFT) 973f7917c00SJeff Kirsher 974f7917c00SJeff Kirsher #define MPS_TRC_FILTER_MATCH_CTL_B 0x9820 975f7917c00SJeff Kirsher #define TFMINPKTSIZE_MASK 0x01ff0000U 976f7917c00SJeff Kirsher #define TFMINPKTSIZE_SHIFT 16 977f7917c00SJeff Kirsher #define TFMINPKTSIZE(x) ((x) << TFMINPKTSIZE_SHIFT) 978f7917c00SJeff Kirsher #define TFMINPKTSIZE_GET(x) (((x) & TFMINPKTSIZE_MASK) >> TFMINPKTSIZE_SHIFT) 979f7917c00SJeff Kirsher #define TFCAPTUREMAX_MASK 0x00003fffU 980f7917c00SJeff Kirsher #define TFCAPTUREMAX_SHIFT 0 981f7917c00SJeff Kirsher #define TFCAPTUREMAX(x) ((x) << TFCAPTUREMAX_SHIFT) 982f7917c00SJeff Kirsher #define TFCAPTUREMAX_GET(x) (((x) & TFCAPTUREMAX_MASK) >> TFCAPTUREMAX_SHIFT) 983f7917c00SJeff Kirsher 984f7917c00SJeff Kirsher #define MPS_TRC_INT_CAUSE 0x985c 985f7917c00SJeff Kirsher #define MISCPERR 0x00000100U 986f7917c00SJeff Kirsher #define PKTFIFO 0x000000f0U 987f7917c00SJeff Kirsher #define FILTMEM 0x0000000fU 988f7917c00SJeff Kirsher 989f7917c00SJeff Kirsher #define MPS_TRC_FILTER0_MATCH 0x9c00 990f7917c00SJeff Kirsher #define MPS_TRC_FILTER0_DONT_CARE 0x9c80 991f7917c00SJeff Kirsher #define MPS_TRC_FILTER1_MATCH 0x9d00 992f7917c00SJeff Kirsher #define MPS_CLS_INT_CAUSE 0xd028 993f7917c00SJeff Kirsher #define PLERRENB 0x00000008U 994f7917c00SJeff Kirsher #define HASHSRAM 0x00000004U 995f7917c00SJeff Kirsher #define MATCHTCAM 0x00000002U 996f7917c00SJeff Kirsher #define MATCHSRAM 0x00000001U 997f7917c00SJeff Kirsher 998f7917c00SJeff Kirsher #define MPS_RX_PERR_INT_CAUSE 0x11074 999f7917c00SJeff Kirsher 1000f7917c00SJeff Kirsher #define CPL_INTR_CAUSE 0x19054 1001f7917c00SJeff Kirsher #define CIM_OP_MAP_PERR 0x00000020U 1002f7917c00SJeff Kirsher #define CIM_OVFL_ERROR 0x00000010U 1003f7917c00SJeff Kirsher #define TP_FRAMING_ERROR 0x00000008U 1004f7917c00SJeff Kirsher #define SGE_FRAMING_ERROR 0x00000004U 1005f7917c00SJeff Kirsher #define CIM_FRAMING_ERROR 0x00000002U 1006f7917c00SJeff Kirsher #define ZERO_SWITCH_ERROR 0x00000001U 1007f7917c00SJeff Kirsher 1008f7917c00SJeff Kirsher #define SMB_INT_CAUSE 0x19090 1009f7917c00SJeff Kirsher #define MSTTXFIFOPARINT 0x00200000U 1010f7917c00SJeff Kirsher #define MSTRXFIFOPARINT 0x00100000U 1011f7917c00SJeff Kirsher #define SLVFIFOPARINT 0x00080000U 1012f7917c00SJeff Kirsher 1013f7917c00SJeff Kirsher #define ULP_RX_INT_CAUSE 0x19158 1014f7917c00SJeff Kirsher #define ULP_RX_ISCSI_TAGMASK 0x19164 1015f7917c00SJeff Kirsher #define ULP_RX_ISCSI_PSZ 0x19168 1016f7917c00SJeff Kirsher #define HPZ3_MASK 0x0f000000U 1017f7917c00SJeff Kirsher #define HPZ3_SHIFT 24 1018f7917c00SJeff Kirsher #define HPZ3(x) ((x) << HPZ3_SHIFT) 1019f7917c00SJeff Kirsher #define HPZ2_MASK 0x000f0000U 1020f7917c00SJeff Kirsher #define HPZ2_SHIFT 16 1021f7917c00SJeff Kirsher #define HPZ2(x) ((x) << HPZ2_SHIFT) 1022f7917c00SJeff Kirsher #define HPZ1_MASK 0x00000f00U 1023f7917c00SJeff Kirsher #define HPZ1_SHIFT 8 1024f7917c00SJeff Kirsher #define HPZ1(x) ((x) << HPZ1_SHIFT) 1025f7917c00SJeff Kirsher #define HPZ0_MASK 0x0000000fU 1026f7917c00SJeff Kirsher #define HPZ0_SHIFT 0 1027f7917c00SJeff Kirsher #define HPZ0(x) ((x) << HPZ0_SHIFT) 1028f7917c00SJeff Kirsher 1029f7917c00SJeff Kirsher #define ULP_RX_TDDP_PSZ 0x19178 1030f7917c00SJeff Kirsher 1031f7917c00SJeff Kirsher #define SF_DATA 0x193f8 1032f7917c00SJeff Kirsher #define SF_OP 0x193fc 1033ce91a923SNaresh Kumar Inna #define SF_BUSY 0x80000000U 1034f7917c00SJeff Kirsher #define SF_LOCK 0x00000010U 1035f7917c00SJeff Kirsher #define SF_CONT 0x00000008U 1036f7917c00SJeff Kirsher #define BYTECNT_MASK 0x00000006U 1037f7917c00SJeff Kirsher #define BYTECNT_SHIFT 1 1038f7917c00SJeff Kirsher #define BYTECNT(x) ((x) << BYTECNT_SHIFT) 1039f7917c00SJeff Kirsher #define OP_WR 0x00000001U 1040f7917c00SJeff Kirsher 1041f7917c00SJeff Kirsher #define PL_PF_INT_CAUSE 0x3c0 1042f7917c00SJeff Kirsher #define PFSW 0x00000008U 1043f7917c00SJeff Kirsher #define PFSGE 0x00000004U 1044f7917c00SJeff Kirsher #define PFCIM 0x00000002U 1045f7917c00SJeff Kirsher #define PFMPS 0x00000001U 1046f7917c00SJeff Kirsher 1047f7917c00SJeff Kirsher #define PL_PF_INT_ENABLE 0x3c4 1048f7917c00SJeff Kirsher #define PL_PF_CTL 0x3c8 1049f7917c00SJeff Kirsher #define SWINT 0x00000001U 1050f7917c00SJeff Kirsher 1051f7917c00SJeff Kirsher #define PL_WHOAMI 0x19400 1052f7917c00SJeff Kirsher #define SOURCEPF_MASK 0x00000700U 1053f7917c00SJeff Kirsher #define SOURCEPF_SHIFT 8 1054f7917c00SJeff Kirsher #define SOURCEPF(x) ((x) << SOURCEPF_SHIFT) 1055f7917c00SJeff Kirsher #define SOURCEPF_GET(x) (((x) & SOURCEPF_MASK) >> SOURCEPF_SHIFT) 1056f7917c00SJeff Kirsher #define ISVF 0x00000080U 1057f7917c00SJeff Kirsher #define VFID_MASK 0x0000007fU 1058f7917c00SJeff Kirsher #define VFID_SHIFT 0 1059f7917c00SJeff Kirsher #define VFID(x) ((x) << VFID_SHIFT) 1060f7917c00SJeff Kirsher #define VFID_GET(x) (((x) & VFID_MASK) >> VFID_SHIFT) 1061f7917c00SJeff Kirsher 1062f7917c00SJeff Kirsher #define PL_INT_CAUSE 0x1940c 1063f7917c00SJeff Kirsher #define ULP_TX 0x08000000U 1064f7917c00SJeff Kirsher #define SGE 0x04000000U 1065f7917c00SJeff Kirsher #define HMA 0x02000000U 1066f7917c00SJeff Kirsher #define CPL_SWITCH 0x01000000U 1067f7917c00SJeff Kirsher #define ULP_RX 0x00800000U 1068f7917c00SJeff Kirsher #define PM_RX 0x00400000U 1069f7917c00SJeff Kirsher #define PM_TX 0x00200000U 1070f7917c00SJeff Kirsher #define MA 0x00100000U 1071f7917c00SJeff Kirsher #define TP 0x00080000U 1072f7917c00SJeff Kirsher #define LE 0x00040000U 1073f7917c00SJeff Kirsher #define EDC1 0x00020000U 1074f7917c00SJeff Kirsher #define EDC0 0x00010000U 1075f7917c00SJeff Kirsher #define MC 0x00008000U 1076f7917c00SJeff Kirsher #define PCIE 0x00004000U 1077f7917c00SJeff Kirsher #define PMU 0x00002000U 1078f7917c00SJeff Kirsher #define XGMAC_KR1 0x00001000U 1079f7917c00SJeff Kirsher #define XGMAC_KR0 0x00000800U 1080f7917c00SJeff Kirsher #define XGMAC1 0x00000400U 1081f7917c00SJeff Kirsher #define XGMAC0 0x00000200U 1082f7917c00SJeff Kirsher #define SMB 0x00000100U 1083f7917c00SJeff Kirsher #define SF 0x00000080U 1084f7917c00SJeff Kirsher #define PL 0x00000040U 1085f7917c00SJeff Kirsher #define NCSI 0x00000020U 1086f7917c00SJeff Kirsher #define MPS 0x00000010U 1087f7917c00SJeff Kirsher #define MI 0x00000008U 1088f7917c00SJeff Kirsher #define DBG 0x00000004U 1089f7917c00SJeff Kirsher #define I2CM 0x00000002U 1090f7917c00SJeff Kirsher #define CIM 0x00000001U 1091f7917c00SJeff Kirsher 1092ce91a923SNaresh Kumar Inna #define PL_INT_ENABLE 0x19410 1093f7917c00SJeff Kirsher #define PL_INT_MAP0 0x19414 1094f7917c00SJeff Kirsher #define PL_RST 0x19428 1095f7917c00SJeff Kirsher #define PIORST 0x00000002U 1096f7917c00SJeff Kirsher #define PIORSTMODE 0x00000001U 1097f7917c00SJeff Kirsher 1098f7917c00SJeff Kirsher #define PL_PL_INT_CAUSE 0x19430 1099f7917c00SJeff Kirsher #define FATALPERR 0x00000010U 1100f7917c00SJeff Kirsher #define PERRVFID 0x00000001U 1101f7917c00SJeff Kirsher 1102f7917c00SJeff Kirsher #define PL_REV 0x1943c 1103f7917c00SJeff Kirsher 1104d14807ddSHariprasad Shenai #define S_REV 0 1105d14807ddSHariprasad Shenai #define M_REV 0xfU 1106d14807ddSHariprasad Shenai #define V_REV(x) ((x) << S_REV) 1107d14807ddSHariprasad Shenai #define G_REV(x) (((x) >> S_REV) & M_REV) 1108d14807ddSHariprasad Shenai 1109f7917c00SJeff Kirsher #define LE_DB_CONFIG 0x19c04 1110f7917c00SJeff Kirsher #define HASHEN 0x00100000U 1111f7917c00SJeff Kirsher 1112f7917c00SJeff Kirsher #define LE_DB_SERVER_INDEX 0x19c18 1113f7917c00SJeff Kirsher #define LE_DB_ACT_CNT_IPV4 0x19c20 1114f7917c00SJeff Kirsher #define LE_DB_ACT_CNT_IPV6 0x19c24 1115f7917c00SJeff Kirsher 1116f7917c00SJeff Kirsher #define LE_DB_INT_CAUSE 0x19c3c 1117f7917c00SJeff Kirsher #define REQQPARERR 0x00010000U 1118f7917c00SJeff Kirsher #define UNKNOWNCMD 0x00008000U 1119f7917c00SJeff Kirsher #define PARITYERR 0x00000040U 1120f7917c00SJeff Kirsher #define LIPMISS 0x00000020U 1121f7917c00SJeff Kirsher #define LIP0 0x00000010U 1122f7917c00SJeff Kirsher 1123f7917c00SJeff Kirsher #define LE_DB_TID_HASHBASE 0x19df8 1124f7917c00SJeff Kirsher 1125f7917c00SJeff Kirsher #define NCSI_INT_CAUSE 0x1a0d8 1126f7917c00SJeff Kirsher #define CIM_DM_PRTY_ERR 0x00000100U 1127f7917c00SJeff Kirsher #define MPS_DM_PRTY_ERR 0x00000080U 1128f7917c00SJeff Kirsher #define TXFIFO_PRTY_ERR 0x00000002U 1129f7917c00SJeff Kirsher #define RXFIFO_PRTY_ERR 0x00000001U 1130f7917c00SJeff Kirsher 1131f7917c00SJeff Kirsher #define XGMAC_PORT_CFG2 0x1018 1132f7917c00SJeff Kirsher #define PATEN 0x00040000U 1133f7917c00SJeff Kirsher #define MAGICEN 0x00020000U 1134f7917c00SJeff Kirsher 1135f7917c00SJeff Kirsher #define XGMAC_PORT_MAGIC_MACID_LO 0x1024 1136f7917c00SJeff Kirsher #define XGMAC_PORT_MAGIC_MACID_HI 0x1028 1137f7917c00SJeff Kirsher 1138f7917c00SJeff Kirsher #define XGMAC_PORT_EPIO_DATA0 0x10c0 1139f7917c00SJeff Kirsher #define XGMAC_PORT_EPIO_DATA1 0x10c4 1140f7917c00SJeff Kirsher #define XGMAC_PORT_EPIO_DATA2 0x10c8 1141f7917c00SJeff Kirsher #define XGMAC_PORT_EPIO_DATA3 0x10cc 1142f7917c00SJeff Kirsher #define XGMAC_PORT_EPIO_OP 0x10d0 1143f7917c00SJeff Kirsher #define EPIOWR 0x00000100U 1144f7917c00SJeff Kirsher #define ADDRESS_MASK 0x000000ffU 1145f7917c00SJeff Kirsher #define ADDRESS_SHIFT 0 1146f7917c00SJeff Kirsher #define ADDRESS(x) ((x) << ADDRESS_SHIFT) 1147f7917c00SJeff Kirsher 1148b2decaddSSantosh Rastapur #define MAC_PORT_INT_CAUSE 0x8dc 1149f7917c00SJeff Kirsher #define XGMAC_PORT_INT_CAUSE 0x10dc 1150dca4faebSVipul Pandya 1151dca4faebSVipul Pandya #define A_TP_TX_MOD_QUEUE_REQ_MAP 0x7e28 1152dca4faebSVipul Pandya 1153dca4faebSVipul Pandya #define A_TP_TX_MOD_CHANNEL_WEIGHT 0x7e34 1154dca4faebSVipul Pandya 1155dca4faebSVipul Pandya #define S_TX_MOD_QUEUE_REQ_MAP 0 1156dca4faebSVipul Pandya #define M_TX_MOD_QUEUE_REQ_MAP 0xffffU 1157dca4faebSVipul Pandya #define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP) 1158dca4faebSVipul Pandya 1159dca4faebSVipul Pandya #define A_TP_TX_MOD_QUEUE_WEIGHT0 0x7e30 1160dca4faebSVipul Pandya 1161dca4faebSVipul Pandya #define S_TX_MODQ_WEIGHT3 24 1162dca4faebSVipul Pandya #define M_TX_MODQ_WEIGHT3 0xffU 1163dca4faebSVipul Pandya #define V_TX_MODQ_WEIGHT3(x) ((x) << S_TX_MODQ_WEIGHT3) 1164dca4faebSVipul Pandya 1165dca4faebSVipul Pandya #define S_TX_MODQ_WEIGHT2 16 1166dca4faebSVipul Pandya #define M_TX_MODQ_WEIGHT2 0xffU 1167dca4faebSVipul Pandya #define V_TX_MODQ_WEIGHT2(x) ((x) << S_TX_MODQ_WEIGHT2) 1168dca4faebSVipul Pandya 1169dca4faebSVipul Pandya #define S_TX_MODQ_WEIGHT1 8 1170dca4faebSVipul Pandya #define M_TX_MODQ_WEIGHT1 0xffU 1171dca4faebSVipul Pandya #define V_TX_MODQ_WEIGHT1(x) ((x) << S_TX_MODQ_WEIGHT1) 1172dca4faebSVipul Pandya 1173dca4faebSVipul Pandya #define S_TX_MODQ_WEIGHT0 0 1174dca4faebSVipul Pandya #define M_TX_MODQ_WEIGHT0 0xffU 1175dca4faebSVipul Pandya #define V_TX_MODQ_WEIGHT0(x) ((x) << S_TX_MODQ_WEIGHT0) 1176dca4faebSVipul Pandya 1177dca4faebSVipul Pandya #define A_TP_TX_SCHED_HDR 0x23 1178dca4faebSVipul Pandya 1179dca4faebSVipul Pandya #define A_TP_TX_SCHED_FIFO 0x24 1180dca4faebSVipul Pandya 1181dca4faebSVipul Pandya #define A_TP_TX_SCHED_PCMD 0x25 1182dca4faebSVipul Pandya 1183dcf7b6f5SKumar Sanghvi #define S_VNIC 11 1184dcf7b6f5SKumar Sanghvi #define V_VNIC(x) ((x) << S_VNIC) 1185dcf7b6f5SKumar Sanghvi #define F_VNIC V_VNIC(1U) 1186dcf7b6f5SKumar Sanghvi 1187dcf7b6f5SKumar Sanghvi #define S_FRAGMENTATION 9 1188dcf7b6f5SKumar Sanghvi #define V_FRAGMENTATION(x) ((x) << S_FRAGMENTATION) 1189dcf7b6f5SKumar Sanghvi #define F_FRAGMENTATION V_FRAGMENTATION(1U) 1190dcf7b6f5SKumar Sanghvi 1191dcf7b6f5SKumar Sanghvi #define S_MPSHITTYPE 8 1192dcf7b6f5SKumar Sanghvi #define V_MPSHITTYPE(x) ((x) << S_MPSHITTYPE) 1193dcf7b6f5SKumar Sanghvi #define F_MPSHITTYPE V_MPSHITTYPE(1U) 1194dcf7b6f5SKumar Sanghvi 1195dcf7b6f5SKumar Sanghvi #define S_MACMATCH 7 1196dcf7b6f5SKumar Sanghvi #define V_MACMATCH(x) ((x) << S_MACMATCH) 1197dcf7b6f5SKumar Sanghvi #define F_MACMATCH V_MACMATCH(1U) 1198dcf7b6f5SKumar Sanghvi 1199dcf7b6f5SKumar Sanghvi #define S_ETHERTYPE 6 1200dcf7b6f5SKumar Sanghvi #define V_ETHERTYPE(x) ((x) << S_ETHERTYPE) 1201dcf7b6f5SKumar Sanghvi #define F_ETHERTYPE V_ETHERTYPE(1U) 1202dcf7b6f5SKumar Sanghvi 12037c89e555SKumar Sanghvi #define S_PROTOCOL 5 12047c89e555SKumar Sanghvi #define V_PROTOCOL(x) ((x) << S_PROTOCOL) 12057c89e555SKumar Sanghvi #define F_PROTOCOL V_PROTOCOL(1U) 12067c89e555SKumar Sanghvi 1207dcf7b6f5SKumar Sanghvi #define S_TOS 4 1208dcf7b6f5SKumar Sanghvi #define V_TOS(x) ((x) << S_TOS) 1209dcf7b6f5SKumar Sanghvi #define F_TOS V_TOS(1U) 1210dcf7b6f5SKumar Sanghvi 1211dcf7b6f5SKumar Sanghvi #define S_VLAN 3 1212dcf7b6f5SKumar Sanghvi #define V_VLAN(x) ((x) << S_VLAN) 1213dcf7b6f5SKumar Sanghvi #define F_VLAN V_VLAN(1U) 1214dcf7b6f5SKumar Sanghvi 1215dcf7b6f5SKumar Sanghvi #define S_VNIC_ID 2 1216dcf7b6f5SKumar Sanghvi #define V_VNIC_ID(x) ((x) << S_VNIC_ID) 1217dcf7b6f5SKumar Sanghvi #define F_VNIC_ID V_VNIC_ID(1U) 1218dcf7b6f5SKumar Sanghvi 12195be78ee9SVipul Pandya #define S_PORT 1 1220793dad94SVipul Pandya #define V_PORT(x) ((x) << S_PORT) 1221793dad94SVipul Pandya #define F_PORT V_PORT(1U) 12225be78ee9SVipul Pandya 1223dcf7b6f5SKumar Sanghvi #define S_FCOE 0 1224dcf7b6f5SKumar Sanghvi #define V_FCOE(x) ((x) << S_FCOE) 1225dcf7b6f5SKumar Sanghvi #define F_FCOE V_FCOE(1U) 1226dcf7b6f5SKumar Sanghvi 1227b2decaddSSantosh Rastapur #define NUM_MPS_CLS_SRAM_L_INSTANCES 336 1228b2decaddSSantosh Rastapur #define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512 1229b2decaddSSantosh Rastapur 1230b2decaddSSantosh Rastapur #define T5_PORT0_BASE 0x30000 1231b2decaddSSantosh Rastapur #define T5_PORT_STRIDE 0x4000 1232b2decaddSSantosh Rastapur #define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE) 1233b2decaddSSantosh Rastapur #define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg)) 1234b2decaddSSantosh Rastapur 1235b2decaddSSantosh Rastapur #define MC_0_BASE_ADDR 0x40000 1236b2decaddSSantosh Rastapur #define MC_1_BASE_ADDR 0x48000 1237b2decaddSSantosh Rastapur #define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR) 1238b2decaddSSantosh Rastapur #define MC_REG(reg, idx) (reg + MC_STRIDE * idx) 1239b2decaddSSantosh Rastapur 1240b2decaddSSantosh Rastapur #define MC_P_BIST_CMD 0x41400 1241b2decaddSSantosh Rastapur #define MC_P_BIST_CMD_ADDR 0x41404 1242b2decaddSSantosh Rastapur #define MC_P_BIST_CMD_LEN 0x41408 1243b2decaddSSantosh Rastapur #define MC_P_BIST_DATA_PATTERN 0x4140c 1244b2decaddSSantosh Rastapur #define MC_P_BIST_STATUS_RDATA 0x41488 1245b2decaddSSantosh Rastapur #define EDC_T50_BASE_ADDR 0x50000 1246b2decaddSSantosh Rastapur #define EDC_H_BIST_CMD 0x50004 1247b2decaddSSantosh Rastapur #define EDC_H_BIST_CMD_ADDR 0x50008 1248b2decaddSSantosh Rastapur #define EDC_H_BIST_CMD_LEN 0x5000c 1249b2decaddSSantosh Rastapur #define EDC_H_BIST_DATA_PATTERN 0x50010 1250b2decaddSSantosh Rastapur #define EDC_H_BIST_STATUS_RDATA 0x50028 1251b2decaddSSantosh Rastapur 1252b2decaddSSantosh Rastapur #define EDC_T51_BASE_ADDR 0x50800 1253b2decaddSSantosh Rastapur #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) 1254b2decaddSSantosh Rastapur #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx) 1255b2decaddSSantosh Rastapur 125670ee3666SHariprasad Shenai #define A_PL_VF_REV 0x4 125770ee3666SHariprasad Shenai #define A_PL_VF_WHOAMI 0x0 125870ee3666SHariprasad Shenai #define A_PL_VF_REVISION 0x8 125970ee3666SHariprasad Shenai 126070ee3666SHariprasad Shenai #define S_CHIPID 4 126170ee3666SHariprasad Shenai #define M_CHIPID 0xfU 126270ee3666SHariprasad Shenai #define V_CHIPID(x) ((x) << S_CHIPID) 126370ee3666SHariprasad Shenai #define G_CHIPID(x) (((x) >> S_CHIPID) & M_CHIPID) 126470ee3666SHariprasad Shenai 1265dcf7b6f5SKumar Sanghvi /* TP_VLAN_PRI_MAP controls which subset of fields will be present in the 1266dcf7b6f5SKumar Sanghvi * Compressed Filter Tuple for LE filters. Each bit set in TP_VLAN_PRI_MAP 1267dcf7b6f5SKumar Sanghvi * selects for a particular field being present. These fields, when present 1268dcf7b6f5SKumar Sanghvi * in the Compressed Filter Tuple, have the following widths in bits. 1269dcf7b6f5SKumar Sanghvi */ 1270dcf7b6f5SKumar Sanghvi #define W_FT_FCOE 1 1271dcf7b6f5SKumar Sanghvi #define W_FT_PORT 3 1272dcf7b6f5SKumar Sanghvi #define W_FT_VNIC_ID 17 1273dcf7b6f5SKumar Sanghvi #define W_FT_VLAN 17 1274dcf7b6f5SKumar Sanghvi #define W_FT_TOS 8 1275dcf7b6f5SKumar Sanghvi #define W_FT_PROTOCOL 8 1276dcf7b6f5SKumar Sanghvi #define W_FT_ETHERTYPE 16 1277dcf7b6f5SKumar Sanghvi #define W_FT_MACMATCH 9 1278dcf7b6f5SKumar Sanghvi #define W_FT_MPSHITTYPE 3 1279dcf7b6f5SKumar Sanghvi #define W_FT_FRAGMENTATION 1 1280dcf7b6f5SKumar Sanghvi 1281dcf7b6f5SKumar Sanghvi /* Some of the Compressed Filter Tuple fields have internal structure. These 1282dcf7b6f5SKumar Sanghvi * bit shifts/masks describe those structures. All shifts are relative to the 1283dcf7b6f5SKumar Sanghvi * base position of the fields within the Compressed Filter Tuple 1284dcf7b6f5SKumar Sanghvi */ 1285dcf7b6f5SKumar Sanghvi #define S_FT_VLAN_VLD 16 1286dcf7b6f5SKumar Sanghvi #define V_FT_VLAN_VLD(x) ((x) << S_FT_VLAN_VLD) 1287dcf7b6f5SKumar Sanghvi #define F_FT_VLAN_VLD V_FT_VLAN_VLD(1U) 1288dcf7b6f5SKumar Sanghvi 1289dcf7b6f5SKumar Sanghvi #define S_FT_VNID_ID_VF 0 1290dcf7b6f5SKumar Sanghvi #define V_FT_VNID_ID_VF(x) ((x) << S_FT_VNID_ID_VF) 1291dcf7b6f5SKumar Sanghvi 1292dcf7b6f5SKumar Sanghvi #define S_FT_VNID_ID_PF 7 1293dcf7b6f5SKumar Sanghvi #define V_FT_VNID_ID_PF(x) ((x) << S_FT_VNID_ID_PF) 1294dcf7b6f5SKumar Sanghvi 1295dcf7b6f5SKumar Sanghvi #define S_FT_VNID_ID_VLD 16 1296dcf7b6f5SKumar Sanghvi #define V_FT_VNID_ID_VLD(x) ((x) << S_FT_VNID_ID_VLD) 1297dcf7b6f5SKumar Sanghvi 1298f7917c00SJeff Kirsher #endif /* __T4_REGS_H */ 1299