1f7917c00SJeff Kirsher /* 2f7917c00SJeff Kirsher * This file is part of the Chelsio T4 Ethernet driver for Linux. 3f7917c00SJeff Kirsher * 4f7917c00SJeff Kirsher * Copyright (c) 2010 Chelsio Communications, Inc. All rights reserved. 5f7917c00SJeff Kirsher * 6f7917c00SJeff Kirsher * This software is available to you under a choice of one of two 7f7917c00SJeff Kirsher * licenses. You may choose to be licensed under the terms of the GNU 8f7917c00SJeff Kirsher * General Public License (GPL) Version 2, available from the file 9f7917c00SJeff Kirsher * COPYING in the main directory of this source tree, or the 10f7917c00SJeff Kirsher * OpenIB.org BSD license below: 11f7917c00SJeff Kirsher * 12f7917c00SJeff Kirsher * Redistribution and use in source and binary forms, with or 13f7917c00SJeff Kirsher * without modification, are permitted provided that the following 14f7917c00SJeff Kirsher * conditions are met: 15f7917c00SJeff Kirsher * 16f7917c00SJeff Kirsher * - Redistributions of source code must retain the above 17f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 18f7917c00SJeff Kirsher * disclaimer. 19f7917c00SJeff Kirsher * 20f7917c00SJeff Kirsher * - Redistributions in binary form must reproduce the above 21f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 22f7917c00SJeff Kirsher * disclaimer in the documentation and/or other materials 23f7917c00SJeff Kirsher * provided with the distribution. 24f7917c00SJeff Kirsher * 25f7917c00SJeff Kirsher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26f7917c00SJeff Kirsher * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27f7917c00SJeff Kirsher * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28f7917c00SJeff Kirsher * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29f7917c00SJeff Kirsher * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30f7917c00SJeff Kirsher * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31f7917c00SJeff Kirsher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32f7917c00SJeff Kirsher * SOFTWARE. 33f7917c00SJeff Kirsher */ 34f7917c00SJeff Kirsher 35f7917c00SJeff Kirsher #ifndef __T4_REGS_H 36f7917c00SJeff Kirsher #define __T4_REGS_H 37f7917c00SJeff Kirsher 38f7917c00SJeff Kirsher #define MYPF_BASE 0x1b000 39f7917c00SJeff Kirsher #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr)) 40f7917c00SJeff Kirsher 41f7917c00SJeff Kirsher #define PF0_BASE 0x1e000 42f7917c00SJeff Kirsher #define PF0_REG(reg_addr) (PF0_BASE + (reg_addr)) 43f7917c00SJeff Kirsher 44f7917c00SJeff Kirsher #define PF_STRIDE 0x400 45f7917c00SJeff Kirsher #define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE) 46f7917c00SJeff Kirsher #define PF_REG(idx, reg) (PF_BASE(idx) + (reg)) 47f7917c00SJeff Kirsher 48f7917c00SJeff Kirsher #define MYPORT_BASE 0x1c000 49f7917c00SJeff Kirsher #define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr)) 50f7917c00SJeff Kirsher 51f7917c00SJeff Kirsher #define PORT0_BASE 0x20000 52f7917c00SJeff Kirsher #define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr)) 53f7917c00SJeff Kirsher 54f7917c00SJeff Kirsher #define PORT_STRIDE 0x2000 55f7917c00SJeff Kirsher #define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE) 56f7917c00SJeff Kirsher #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg)) 57f7917c00SJeff Kirsher 58f7917c00SJeff Kirsher #define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR) 59f7917c00SJeff Kirsher #define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx) 60f7917c00SJeff Kirsher 61f7917c00SJeff Kirsher #define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) 62f7917c00SJeff Kirsher #define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) 63f7917c00SJeff Kirsher #define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) 64f7917c00SJeff Kirsher #define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) 65f7917c00SJeff Kirsher 66f7917c00SJeff Kirsher #define SGE_PF_KDOORBELL 0x0 67f7917c00SJeff Kirsher #define QID_MASK 0xffff8000U 68f7917c00SJeff Kirsher #define QID_SHIFT 15 69f7917c00SJeff Kirsher #define QID(x) ((x) << QID_SHIFT) 70f7917c00SJeff Kirsher #define DBPRIO 0x00004000U 71f7917c00SJeff Kirsher #define PIDX_MASK 0x00003fffU 72f7917c00SJeff Kirsher #define PIDX_SHIFT 0 73f7917c00SJeff Kirsher #define PIDX(x) ((x) << PIDX_SHIFT) 74f7917c00SJeff Kirsher 75f7917c00SJeff Kirsher #define SGE_PF_GTS 0x4 76f7917c00SJeff Kirsher #define INGRESSQID_MASK 0xffff0000U 77f7917c00SJeff Kirsher #define INGRESSQID_SHIFT 16 78f7917c00SJeff Kirsher #define INGRESSQID(x) ((x) << INGRESSQID_SHIFT) 79f7917c00SJeff Kirsher #define TIMERREG_MASK 0x0000e000U 80f7917c00SJeff Kirsher #define TIMERREG_SHIFT 13 81f7917c00SJeff Kirsher #define TIMERREG(x) ((x) << TIMERREG_SHIFT) 82f7917c00SJeff Kirsher #define SEINTARM_MASK 0x00001000U 83f7917c00SJeff Kirsher #define SEINTARM_SHIFT 12 84f7917c00SJeff Kirsher #define SEINTARM(x) ((x) << SEINTARM_SHIFT) 85f7917c00SJeff Kirsher #define CIDXINC_MASK 0x00000fffU 86f7917c00SJeff Kirsher #define CIDXINC_SHIFT 0 87f7917c00SJeff Kirsher #define CIDXINC(x) ((x) << CIDXINC_SHIFT) 88f7917c00SJeff Kirsher 89f7917c00SJeff Kirsher #define SGE_CONTROL 0x1008 90f7917c00SJeff Kirsher #define DCASYSTYPE 0x00080000U 91f7917c00SJeff Kirsher #define RXPKTCPLMODE 0x00040000U 92f7917c00SJeff Kirsher #define EGRSTATUSPAGESIZE 0x00020000U 93f7917c00SJeff Kirsher #define PKTSHIFT_MASK 0x00001c00U 94f7917c00SJeff Kirsher #define PKTSHIFT_SHIFT 10 95f7917c00SJeff Kirsher #define PKTSHIFT(x) ((x) << PKTSHIFT_SHIFT) 96f7917c00SJeff Kirsher #define PKTSHIFT_GET(x) (((x) & PKTSHIFT_MASK) >> PKTSHIFT_SHIFT) 97f7917c00SJeff Kirsher #define INGPCIEBOUNDARY_MASK 0x00000380U 98f7917c00SJeff Kirsher #define INGPCIEBOUNDARY_SHIFT 7 99f7917c00SJeff Kirsher #define INGPCIEBOUNDARY(x) ((x) << INGPCIEBOUNDARY_SHIFT) 100f7917c00SJeff Kirsher #define INGPADBOUNDARY_MASK 0x00000070U 101f7917c00SJeff Kirsher #define INGPADBOUNDARY_SHIFT 4 102f7917c00SJeff Kirsher #define INGPADBOUNDARY(x) ((x) << INGPADBOUNDARY_SHIFT) 103f7917c00SJeff Kirsher #define INGPADBOUNDARY_GET(x) (((x) & INGPADBOUNDARY_MASK) \ 104f7917c00SJeff Kirsher >> INGPADBOUNDARY_SHIFT) 105f7917c00SJeff Kirsher #define EGRPCIEBOUNDARY_MASK 0x0000000eU 106f7917c00SJeff Kirsher #define EGRPCIEBOUNDARY_SHIFT 1 107f7917c00SJeff Kirsher #define EGRPCIEBOUNDARY(x) ((x) << EGRPCIEBOUNDARY_SHIFT) 108f7917c00SJeff Kirsher #define GLOBALENABLE 0x00000001U 109f7917c00SJeff Kirsher 110f7917c00SJeff Kirsher #define SGE_HOST_PAGE_SIZE 0x100c 111f7917c00SJeff Kirsher #define HOSTPAGESIZEPF0_MASK 0x0000000fU 112f7917c00SJeff Kirsher #define HOSTPAGESIZEPF0_SHIFT 0 113f7917c00SJeff Kirsher #define HOSTPAGESIZEPF0(x) ((x) << HOSTPAGESIZEPF0_SHIFT) 114f7917c00SJeff Kirsher 115f7917c00SJeff Kirsher #define SGE_EGRESS_QUEUES_PER_PAGE_PF 0x1010 116f7917c00SJeff Kirsher #define QUEUESPERPAGEPF0_MASK 0x0000000fU 117f7917c00SJeff Kirsher #define QUEUESPERPAGEPF0_GET(x) ((x) & QUEUESPERPAGEPF0_MASK) 118f7917c00SJeff Kirsher 119f7917c00SJeff Kirsher #define SGE_INT_CAUSE1 0x1024 120f7917c00SJeff Kirsher #define SGE_INT_CAUSE2 0x1030 121f7917c00SJeff Kirsher #define SGE_INT_CAUSE3 0x103c 122f7917c00SJeff Kirsher #define ERR_FLM_DBP 0x80000000U 123f7917c00SJeff Kirsher #define ERR_FLM_IDMA1 0x40000000U 124f7917c00SJeff Kirsher #define ERR_FLM_IDMA0 0x20000000U 125f7917c00SJeff Kirsher #define ERR_FLM_HINT 0x10000000U 126f7917c00SJeff Kirsher #define ERR_PCIE_ERROR3 0x08000000U 127f7917c00SJeff Kirsher #define ERR_PCIE_ERROR2 0x04000000U 128f7917c00SJeff Kirsher #define ERR_PCIE_ERROR1 0x02000000U 129f7917c00SJeff Kirsher #define ERR_PCIE_ERROR0 0x01000000U 130f7917c00SJeff Kirsher #define ERR_TIMER_ABOVE_MAX_QID 0x00800000U 131f7917c00SJeff Kirsher #define ERR_CPL_EXCEED_IQE_SIZE 0x00400000U 132f7917c00SJeff Kirsher #define ERR_INVALID_CIDX_INC 0x00200000U 133f7917c00SJeff Kirsher #define ERR_ITP_TIME_PAUSED 0x00100000U 134f7917c00SJeff Kirsher #define ERR_CPL_OPCODE_0 0x00080000U 135f7917c00SJeff Kirsher #define ERR_DROPPED_DB 0x00040000U 136f7917c00SJeff Kirsher #define ERR_DATA_CPL_ON_HIGH_QID1 0x00020000U 137f7917c00SJeff Kirsher #define ERR_DATA_CPL_ON_HIGH_QID0 0x00010000U 138f7917c00SJeff Kirsher #define ERR_BAD_DB_PIDX3 0x00008000U 139f7917c00SJeff Kirsher #define ERR_BAD_DB_PIDX2 0x00004000U 140f7917c00SJeff Kirsher #define ERR_BAD_DB_PIDX1 0x00002000U 141f7917c00SJeff Kirsher #define ERR_BAD_DB_PIDX0 0x00001000U 142f7917c00SJeff Kirsher #define ERR_ING_PCIE_CHAN 0x00000800U 143f7917c00SJeff Kirsher #define ERR_ING_CTXT_PRIO 0x00000400U 144f7917c00SJeff Kirsher #define ERR_EGR_CTXT_PRIO 0x00000200U 145f7917c00SJeff Kirsher #define DBFIFO_HP_INT 0x00000100U 146f7917c00SJeff Kirsher #define DBFIFO_LP_INT 0x00000080U 147f7917c00SJeff Kirsher #define REG_ADDRESS_ERR 0x00000040U 148f7917c00SJeff Kirsher #define INGRESS_SIZE_ERR 0x00000020U 149f7917c00SJeff Kirsher #define EGRESS_SIZE_ERR 0x00000010U 150f7917c00SJeff Kirsher #define ERR_INV_CTXT3 0x00000008U 151f7917c00SJeff Kirsher #define ERR_INV_CTXT2 0x00000004U 152f7917c00SJeff Kirsher #define ERR_INV_CTXT1 0x00000002U 153f7917c00SJeff Kirsher #define ERR_INV_CTXT0 0x00000001U 154f7917c00SJeff Kirsher 155f7917c00SJeff Kirsher #define SGE_INT_ENABLE3 0x1040 156f7917c00SJeff Kirsher #define SGE_FL_BUFFER_SIZE0 0x1044 157f7917c00SJeff Kirsher #define SGE_FL_BUFFER_SIZE1 0x1048 158f7917c00SJeff Kirsher #define SGE_INGRESS_RX_THRESHOLD 0x10a0 159f7917c00SJeff Kirsher #define THRESHOLD_0_MASK 0x3f000000U 160f7917c00SJeff Kirsher #define THRESHOLD_0_SHIFT 24 161f7917c00SJeff Kirsher #define THRESHOLD_0(x) ((x) << THRESHOLD_0_SHIFT) 162f7917c00SJeff Kirsher #define THRESHOLD_0_GET(x) (((x) & THRESHOLD_0_MASK) >> THRESHOLD_0_SHIFT) 163f7917c00SJeff Kirsher #define THRESHOLD_1_MASK 0x003f0000U 164f7917c00SJeff Kirsher #define THRESHOLD_1_SHIFT 16 165f7917c00SJeff Kirsher #define THRESHOLD_1(x) ((x) << THRESHOLD_1_SHIFT) 166f7917c00SJeff Kirsher #define THRESHOLD_1_GET(x) (((x) & THRESHOLD_1_MASK) >> THRESHOLD_1_SHIFT) 167f7917c00SJeff Kirsher #define THRESHOLD_2_MASK 0x00003f00U 168f7917c00SJeff Kirsher #define THRESHOLD_2_SHIFT 8 169f7917c00SJeff Kirsher #define THRESHOLD_2(x) ((x) << THRESHOLD_2_SHIFT) 170f7917c00SJeff Kirsher #define THRESHOLD_2_GET(x) (((x) & THRESHOLD_2_MASK) >> THRESHOLD_2_SHIFT) 171f7917c00SJeff Kirsher #define THRESHOLD_3_MASK 0x0000003fU 172f7917c00SJeff Kirsher #define THRESHOLD_3_SHIFT 0 173f7917c00SJeff Kirsher #define THRESHOLD_3(x) ((x) << THRESHOLD_3_SHIFT) 174f7917c00SJeff Kirsher #define THRESHOLD_3_GET(x) (((x) & THRESHOLD_3_MASK) >> THRESHOLD_3_SHIFT) 175f7917c00SJeff Kirsher 176f7917c00SJeff Kirsher #define SGE_TIMER_VALUE_0_AND_1 0x10b8 177f7917c00SJeff Kirsher #define TIMERVALUE0_MASK 0xffff0000U 178f7917c00SJeff Kirsher #define TIMERVALUE0_SHIFT 16 179f7917c00SJeff Kirsher #define TIMERVALUE0(x) ((x) << TIMERVALUE0_SHIFT) 180f7917c00SJeff Kirsher #define TIMERVALUE0_GET(x) (((x) & TIMERVALUE0_MASK) >> TIMERVALUE0_SHIFT) 181f7917c00SJeff Kirsher #define TIMERVALUE1_MASK 0x0000ffffU 182f7917c00SJeff Kirsher #define TIMERVALUE1_SHIFT 0 183f7917c00SJeff Kirsher #define TIMERVALUE1(x) ((x) << TIMERVALUE1_SHIFT) 184f7917c00SJeff Kirsher #define TIMERVALUE1_GET(x) (((x) & TIMERVALUE1_MASK) >> TIMERVALUE1_SHIFT) 185f7917c00SJeff Kirsher 186f7917c00SJeff Kirsher #define SGE_TIMER_VALUE_2_AND_3 0x10bc 187f7917c00SJeff Kirsher #define SGE_TIMER_VALUE_4_AND_5 0x10c0 188f7917c00SJeff Kirsher #define SGE_DEBUG_INDEX 0x10cc 189f7917c00SJeff Kirsher #define SGE_DEBUG_DATA_HIGH 0x10d0 190f7917c00SJeff Kirsher #define SGE_DEBUG_DATA_LOW 0x10d4 191f7917c00SJeff Kirsher #define SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4 192f7917c00SJeff Kirsher 1933069ee9bSVipul Pandya #define S_LP_INT_THRESH 12 1943069ee9bSVipul Pandya #define V_LP_INT_THRESH(x) ((x) << S_LP_INT_THRESH) 1953069ee9bSVipul Pandya #define S_HP_INT_THRESH 28 1963069ee9bSVipul Pandya #define V_HP_INT_THRESH(x) ((x) << S_HP_INT_THRESH) 1973069ee9bSVipul Pandya #define A_SGE_DBFIFO_STATUS 0x10a4 1983069ee9bSVipul Pandya 1993069ee9bSVipul Pandya #define S_ENABLE_DROP 13 2003069ee9bSVipul Pandya #define V_ENABLE_DROP(x) ((x) << S_ENABLE_DROP) 2013069ee9bSVipul Pandya #define F_ENABLE_DROP V_ENABLE_DROP(1U) 2023069ee9bSVipul Pandya #define A_SGE_DOORBELL_CONTROL 0x10a8 2033069ee9bSVipul Pandya 2043069ee9bSVipul Pandya #define A_SGE_CTXT_CMD 0x11fc 2053069ee9bSVipul Pandya #define A_SGE_DBQ_CTXT_BADDR 0x1084 2063069ee9bSVipul Pandya 2073069ee9bSVipul Pandya #define A_SGE_PF_KDOORBELL 0x0 2083069ee9bSVipul Pandya 2093069ee9bSVipul Pandya #define S_QID 15 2103069ee9bSVipul Pandya #define V_QID(x) ((x) << S_QID) 2113069ee9bSVipul Pandya 2123069ee9bSVipul Pandya #define S_PIDX 0 2133069ee9bSVipul Pandya #define V_PIDX(x) ((x) << S_PIDX) 2143069ee9bSVipul Pandya 2153069ee9bSVipul Pandya #define M_LP_COUNT 0x7ffU 2163069ee9bSVipul Pandya #define S_LP_COUNT 0 2173069ee9bSVipul Pandya #define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT) 2183069ee9bSVipul Pandya 2193069ee9bSVipul Pandya #define M_HP_COUNT 0x7ffU 2203069ee9bSVipul Pandya #define S_HP_COUNT 16 2213069ee9bSVipul Pandya #define G_HP_COUNT(x) (((x) >> S_HP_COUNT) & M_HP_COUNT) 2223069ee9bSVipul Pandya 2233069ee9bSVipul Pandya #define A_SGE_INT_ENABLE3 0x1040 2243069ee9bSVipul Pandya 2253069ee9bSVipul Pandya #define S_DBFIFO_HP_INT 8 2263069ee9bSVipul Pandya #define V_DBFIFO_HP_INT(x) ((x) << S_DBFIFO_HP_INT) 2273069ee9bSVipul Pandya #define F_DBFIFO_HP_INT V_DBFIFO_HP_INT(1U) 2283069ee9bSVipul Pandya 2293069ee9bSVipul Pandya #define S_DBFIFO_LP_INT 7 2303069ee9bSVipul Pandya #define V_DBFIFO_LP_INT(x) ((x) << S_DBFIFO_LP_INT) 2313069ee9bSVipul Pandya #define F_DBFIFO_LP_INT V_DBFIFO_LP_INT(1U) 2323069ee9bSVipul Pandya 2333069ee9bSVipul Pandya #define S_DROPPED_DB 0 2343069ee9bSVipul Pandya #define V_DROPPED_DB(x) ((x) << S_DROPPED_DB) 2353069ee9bSVipul Pandya #define F_DROPPED_DB V_DROPPED_DB(1U) 2363069ee9bSVipul Pandya 2373069ee9bSVipul Pandya #define S_ERR_DROPPED_DB 18 2383069ee9bSVipul Pandya #define V_ERR_DROPPED_DB(x) ((x) << S_ERR_DROPPED_DB) 2393069ee9bSVipul Pandya #define F_ERR_DROPPED_DB V_ERR_DROPPED_DB(1U) 2403069ee9bSVipul Pandya 2413069ee9bSVipul Pandya #define A_PCIE_MEM_ACCESS_OFFSET 0x306c 2423069ee9bSVipul Pandya 2433069ee9bSVipul Pandya #define M_HP_INT_THRESH 0xfU 2443069ee9bSVipul Pandya #define M_LP_INT_THRESH 0xfU 2453069ee9bSVipul Pandya 246f7917c00SJeff Kirsher #define PCIE_PF_CLI 0x44 247f7917c00SJeff Kirsher #define PCIE_INT_CAUSE 0x3004 248f7917c00SJeff Kirsher #define UNXSPLCPLERR 0x20000000U 249f7917c00SJeff Kirsher #define PCIEPINT 0x10000000U 250f7917c00SJeff Kirsher #define PCIESINT 0x08000000U 251f7917c00SJeff Kirsher #define RPLPERR 0x04000000U 252f7917c00SJeff Kirsher #define RXWRPERR 0x02000000U 253f7917c00SJeff Kirsher #define RXCPLPERR 0x01000000U 254f7917c00SJeff Kirsher #define PIOTAGPERR 0x00800000U 255f7917c00SJeff Kirsher #define MATAGPERR 0x00400000U 256f7917c00SJeff Kirsher #define INTXCLRPERR 0x00200000U 257f7917c00SJeff Kirsher #define FIDPERR 0x00100000U 258f7917c00SJeff Kirsher #define CFGSNPPERR 0x00080000U 259f7917c00SJeff Kirsher #define HRSPPERR 0x00040000U 260f7917c00SJeff Kirsher #define HREQPERR 0x00020000U 261f7917c00SJeff Kirsher #define HCNTPERR 0x00010000U 262f7917c00SJeff Kirsher #define DRSPPERR 0x00008000U 263f7917c00SJeff Kirsher #define DREQPERR 0x00004000U 264f7917c00SJeff Kirsher #define DCNTPERR 0x00002000U 265f7917c00SJeff Kirsher #define CRSPPERR 0x00001000U 266f7917c00SJeff Kirsher #define CREQPERR 0x00000800U 267f7917c00SJeff Kirsher #define CCNTPERR 0x00000400U 268f7917c00SJeff Kirsher #define TARTAGPERR 0x00000200U 269f7917c00SJeff Kirsher #define PIOREQPERR 0x00000100U 270f7917c00SJeff Kirsher #define PIOCPLPERR 0x00000080U 271f7917c00SJeff Kirsher #define MSIXDIPERR 0x00000040U 272f7917c00SJeff Kirsher #define MSIXDATAPERR 0x00000020U 273f7917c00SJeff Kirsher #define MSIXADDRHPERR 0x00000010U 274f7917c00SJeff Kirsher #define MSIXADDRLPERR 0x00000008U 275f7917c00SJeff Kirsher #define MSIDATAPERR 0x00000004U 276f7917c00SJeff Kirsher #define MSIADDRHPERR 0x00000002U 277f7917c00SJeff Kirsher #define MSIADDRLPERR 0x00000001U 278f7917c00SJeff Kirsher 279f7917c00SJeff Kirsher #define PCIE_NONFAT_ERR 0x3010 280f7917c00SJeff Kirsher #define PCIE_MEM_ACCESS_BASE_WIN 0x3068 281f7917c00SJeff Kirsher #define PCIEOFST_MASK 0xfffffc00U 282f7917c00SJeff Kirsher #define BIR_MASK 0x00000300U 283f7917c00SJeff Kirsher #define BIR_SHIFT 8 284f7917c00SJeff Kirsher #define BIR(x) ((x) << BIR_SHIFT) 285f7917c00SJeff Kirsher #define WINDOW_MASK 0x000000ffU 286f7917c00SJeff Kirsher #define WINDOW_SHIFT 0 287f7917c00SJeff Kirsher #define WINDOW(x) ((x) << WINDOW_SHIFT) 288f7917c00SJeff Kirsher #define PCIE_MEM_ACCESS_OFFSET 0x306c 289f7917c00SJeff Kirsher 290f7917c00SJeff Kirsher #define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS 0x5908 291f7917c00SJeff Kirsher #define RNPP 0x80000000U 292f7917c00SJeff Kirsher #define RPCP 0x20000000U 293f7917c00SJeff Kirsher #define RCIP 0x08000000U 294f7917c00SJeff Kirsher #define RCCP 0x04000000U 295f7917c00SJeff Kirsher #define RFTP 0x00800000U 296f7917c00SJeff Kirsher #define PTRP 0x00100000U 297f7917c00SJeff Kirsher 298f7917c00SJeff Kirsher #define PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS 0x59a4 299f7917c00SJeff Kirsher #define TPCP 0x40000000U 300f7917c00SJeff Kirsher #define TNPP 0x20000000U 301f7917c00SJeff Kirsher #define TFTP 0x10000000U 302f7917c00SJeff Kirsher #define TCAP 0x08000000U 303f7917c00SJeff Kirsher #define TCIP 0x04000000U 304f7917c00SJeff Kirsher #define RCAP 0x02000000U 305f7917c00SJeff Kirsher #define PLUP 0x00800000U 306f7917c00SJeff Kirsher #define PLDN 0x00400000U 307f7917c00SJeff Kirsher #define OTDD 0x00200000U 308f7917c00SJeff Kirsher #define GTRP 0x00100000U 309f7917c00SJeff Kirsher #define RDPE 0x00040000U 310f7917c00SJeff Kirsher #define TDCE 0x00020000U 311f7917c00SJeff Kirsher #define TDUE 0x00010000U 312f7917c00SJeff Kirsher 313f7917c00SJeff Kirsher #define MC_INT_CAUSE 0x7518 314f7917c00SJeff Kirsher #define ECC_UE_INT_CAUSE 0x00000004U 315f7917c00SJeff Kirsher #define ECC_CE_INT_CAUSE 0x00000002U 316f7917c00SJeff Kirsher #define PERR_INT_CAUSE 0x00000001U 317f7917c00SJeff Kirsher 318f7917c00SJeff Kirsher #define MC_ECC_STATUS 0x751c 319f7917c00SJeff Kirsher #define ECC_CECNT_MASK 0xffff0000U 320f7917c00SJeff Kirsher #define ECC_CECNT_SHIFT 16 321f7917c00SJeff Kirsher #define ECC_CECNT(x) ((x) << ECC_CECNT_SHIFT) 322f7917c00SJeff Kirsher #define ECC_CECNT_GET(x) (((x) & ECC_CECNT_MASK) >> ECC_CECNT_SHIFT) 323f7917c00SJeff Kirsher #define ECC_UECNT_MASK 0x0000ffffU 324f7917c00SJeff Kirsher #define ECC_UECNT_SHIFT 0 325f7917c00SJeff Kirsher #define ECC_UECNT(x) ((x) << ECC_UECNT_SHIFT) 326f7917c00SJeff Kirsher #define ECC_UECNT_GET(x) (((x) & ECC_UECNT_MASK) >> ECC_UECNT_SHIFT) 327f7917c00SJeff Kirsher 328f7917c00SJeff Kirsher #define MC_BIST_CMD 0x7600 329f7917c00SJeff Kirsher #define START_BIST 0x80000000U 330f7917c00SJeff Kirsher #define BIST_CMD_GAP_MASK 0x0000ff00U 331f7917c00SJeff Kirsher #define BIST_CMD_GAP_SHIFT 8 332f7917c00SJeff Kirsher #define BIST_CMD_GAP(x) ((x) << BIST_CMD_GAP_SHIFT) 333f7917c00SJeff Kirsher #define BIST_OPCODE_MASK 0x00000003U 334f7917c00SJeff Kirsher #define BIST_OPCODE_SHIFT 0 335f7917c00SJeff Kirsher #define BIST_OPCODE(x) ((x) << BIST_OPCODE_SHIFT) 336f7917c00SJeff Kirsher 337f7917c00SJeff Kirsher #define MC_BIST_CMD_ADDR 0x7604 338f7917c00SJeff Kirsher #define MC_BIST_CMD_LEN 0x7608 339f7917c00SJeff Kirsher #define MC_BIST_DATA_PATTERN 0x760c 340f7917c00SJeff Kirsher #define BIST_DATA_TYPE_MASK 0x0000000fU 341f7917c00SJeff Kirsher #define BIST_DATA_TYPE_SHIFT 0 342f7917c00SJeff Kirsher #define BIST_DATA_TYPE(x) ((x) << BIST_DATA_TYPE_SHIFT) 343f7917c00SJeff Kirsher 344f7917c00SJeff Kirsher #define MC_BIST_STATUS_RDATA 0x7688 345f7917c00SJeff Kirsher 346f7917c00SJeff Kirsher #define MA_EXT_MEMORY_BAR 0x77c8 347f7917c00SJeff Kirsher #define EXT_MEM_SIZE_MASK 0x00000fffU 348f7917c00SJeff Kirsher #define EXT_MEM_SIZE_SHIFT 0 349f7917c00SJeff Kirsher #define EXT_MEM_SIZE_GET(x) (((x) & EXT_MEM_SIZE_MASK) >> EXT_MEM_SIZE_SHIFT) 350f7917c00SJeff Kirsher 351f7917c00SJeff Kirsher #define MA_TARGET_MEM_ENABLE 0x77d8 352f7917c00SJeff Kirsher #define EXT_MEM_ENABLE 0x00000004U 353f7917c00SJeff Kirsher #define EDRAM1_ENABLE 0x00000002U 354f7917c00SJeff Kirsher #define EDRAM0_ENABLE 0x00000001U 355f7917c00SJeff Kirsher 356f7917c00SJeff Kirsher #define MA_INT_CAUSE 0x77e0 357f7917c00SJeff Kirsher #define MEM_PERR_INT_CAUSE 0x00000002U 358f7917c00SJeff Kirsher #define MEM_WRAP_INT_CAUSE 0x00000001U 359f7917c00SJeff Kirsher 360f7917c00SJeff Kirsher #define MA_INT_WRAP_STATUS 0x77e4 361f7917c00SJeff Kirsher #define MEM_WRAP_ADDRESS_MASK 0xfffffff0U 362f7917c00SJeff Kirsher #define MEM_WRAP_ADDRESS_SHIFT 4 363f7917c00SJeff Kirsher #define MEM_WRAP_ADDRESS_GET(x) (((x) & MEM_WRAP_ADDRESS_MASK) >> MEM_WRAP_ADDRESS_SHIFT) 364f7917c00SJeff Kirsher #define MEM_WRAP_CLIENT_NUM_MASK 0x0000000fU 365f7917c00SJeff Kirsher #define MEM_WRAP_CLIENT_NUM_SHIFT 0 366f7917c00SJeff Kirsher #define MEM_WRAP_CLIENT_NUM_GET(x) (((x) & MEM_WRAP_CLIENT_NUM_MASK) >> MEM_WRAP_CLIENT_NUM_SHIFT) 367f7917c00SJeff Kirsher 368f7917c00SJeff Kirsher #define MA_PARITY_ERROR_STATUS 0x77f4 369f7917c00SJeff Kirsher 370f7917c00SJeff Kirsher #define EDC_0_BASE_ADDR 0x7900 371f7917c00SJeff Kirsher 372f7917c00SJeff Kirsher #define EDC_BIST_CMD 0x7904 373f7917c00SJeff Kirsher #define EDC_BIST_CMD_ADDR 0x7908 374f7917c00SJeff Kirsher #define EDC_BIST_CMD_LEN 0x790c 375f7917c00SJeff Kirsher #define EDC_BIST_DATA_PATTERN 0x7910 376f7917c00SJeff Kirsher #define EDC_BIST_STATUS_RDATA 0x7928 377f7917c00SJeff Kirsher #define EDC_INT_CAUSE 0x7978 378f7917c00SJeff Kirsher #define ECC_UE_PAR 0x00000020U 379f7917c00SJeff Kirsher #define ECC_CE_PAR 0x00000010U 380f7917c00SJeff Kirsher #define PERR_PAR_CAUSE 0x00000008U 381f7917c00SJeff Kirsher 382f7917c00SJeff Kirsher #define EDC_ECC_STATUS 0x797c 383f7917c00SJeff Kirsher 384f7917c00SJeff Kirsher #define EDC_1_BASE_ADDR 0x7980 385f7917c00SJeff Kirsher 386f7917c00SJeff Kirsher #define CIM_BOOT_CFG 0x7b00 387f7917c00SJeff Kirsher #define BOOTADDR_MASK 0xffffff00U 388f7917c00SJeff Kirsher 389f7917c00SJeff Kirsher #define CIM_PF_MAILBOX_DATA 0x240 390f7917c00SJeff Kirsher #define CIM_PF_MAILBOX_CTRL 0x280 391f7917c00SJeff Kirsher #define MBMSGVALID 0x00000008U 392f7917c00SJeff Kirsher #define MBINTREQ 0x00000004U 393f7917c00SJeff Kirsher #define MBOWNER_MASK 0x00000003U 394f7917c00SJeff Kirsher #define MBOWNER_SHIFT 0 395f7917c00SJeff Kirsher #define MBOWNER(x) ((x) << MBOWNER_SHIFT) 396f7917c00SJeff Kirsher #define MBOWNER_GET(x) (((x) & MBOWNER_MASK) >> MBOWNER_SHIFT) 397f7917c00SJeff Kirsher 398f7917c00SJeff Kirsher #define CIM_PF_HOST_INT_CAUSE 0x28c 399f7917c00SJeff Kirsher #define MBMSGRDYINT 0x00080000U 400f7917c00SJeff Kirsher 401f7917c00SJeff Kirsher #define CIM_HOST_INT_CAUSE 0x7b2c 402f7917c00SJeff Kirsher #define TIEQOUTPARERRINT 0x00100000U 403f7917c00SJeff Kirsher #define TIEQINPARERRINT 0x00080000U 404f7917c00SJeff Kirsher #define MBHOSTPARERR 0x00040000U 405f7917c00SJeff Kirsher #define MBUPPARERR 0x00020000U 406f7917c00SJeff Kirsher #define IBQPARERR 0x0001f800U 407f7917c00SJeff Kirsher #define IBQTP0PARERR 0x00010000U 408f7917c00SJeff Kirsher #define IBQTP1PARERR 0x00008000U 409f7917c00SJeff Kirsher #define IBQULPPARERR 0x00004000U 410f7917c00SJeff Kirsher #define IBQSGELOPARERR 0x00002000U 411f7917c00SJeff Kirsher #define IBQSGEHIPARERR 0x00001000U 412f7917c00SJeff Kirsher #define IBQNCSIPARERR 0x00000800U 413f7917c00SJeff Kirsher #define OBQPARERR 0x000007e0U 414f7917c00SJeff Kirsher #define OBQULP0PARERR 0x00000400U 415f7917c00SJeff Kirsher #define OBQULP1PARERR 0x00000200U 416f7917c00SJeff Kirsher #define OBQULP2PARERR 0x00000100U 417f7917c00SJeff Kirsher #define OBQULP3PARERR 0x00000080U 418f7917c00SJeff Kirsher #define OBQSGEPARERR 0x00000040U 419f7917c00SJeff Kirsher #define OBQNCSIPARERR 0x00000020U 420f7917c00SJeff Kirsher #define PREFDROPINT 0x00000002U 421f7917c00SJeff Kirsher #define UPACCNONZERO 0x00000001U 422f7917c00SJeff Kirsher 423f7917c00SJeff Kirsher #define CIM_HOST_UPACC_INT_CAUSE 0x7b34 424f7917c00SJeff Kirsher #define EEPROMWRINT 0x40000000U 425f7917c00SJeff Kirsher #define TIMEOUTMAINT 0x20000000U 426f7917c00SJeff Kirsher #define TIMEOUTINT 0x10000000U 427f7917c00SJeff Kirsher #define RSPOVRLOOKUPINT 0x08000000U 428f7917c00SJeff Kirsher #define REQOVRLOOKUPINT 0x04000000U 429f7917c00SJeff Kirsher #define BLKWRPLINT 0x02000000U 430f7917c00SJeff Kirsher #define BLKRDPLINT 0x01000000U 431f7917c00SJeff Kirsher #define SGLWRPLINT 0x00800000U 432f7917c00SJeff Kirsher #define SGLRDPLINT 0x00400000U 433f7917c00SJeff Kirsher #define BLKWRCTLINT 0x00200000U 434f7917c00SJeff Kirsher #define BLKRDCTLINT 0x00100000U 435f7917c00SJeff Kirsher #define SGLWRCTLINT 0x00080000U 436f7917c00SJeff Kirsher #define SGLRDCTLINT 0x00040000U 437f7917c00SJeff Kirsher #define BLKWREEPROMINT 0x00020000U 438f7917c00SJeff Kirsher #define BLKRDEEPROMINT 0x00010000U 439f7917c00SJeff Kirsher #define SGLWREEPROMINT 0x00008000U 440f7917c00SJeff Kirsher #define SGLRDEEPROMINT 0x00004000U 441f7917c00SJeff Kirsher #define BLKWRFLASHINT 0x00002000U 442f7917c00SJeff Kirsher #define BLKRDFLASHINT 0x00001000U 443f7917c00SJeff Kirsher #define SGLWRFLASHINT 0x00000800U 444f7917c00SJeff Kirsher #define SGLRDFLASHINT 0x00000400U 445f7917c00SJeff Kirsher #define BLKWRBOOTINT 0x00000200U 446f7917c00SJeff Kirsher #define BLKRDBOOTINT 0x00000100U 447f7917c00SJeff Kirsher #define SGLWRBOOTINT 0x00000080U 448f7917c00SJeff Kirsher #define SGLRDBOOTINT 0x00000040U 449f7917c00SJeff Kirsher #define ILLWRBEINT 0x00000020U 450f7917c00SJeff Kirsher #define ILLRDBEINT 0x00000010U 451f7917c00SJeff Kirsher #define ILLRDINT 0x00000008U 452f7917c00SJeff Kirsher #define ILLWRINT 0x00000004U 453f7917c00SJeff Kirsher #define ILLTRANSINT 0x00000002U 454f7917c00SJeff Kirsher #define RSVDSPACEINT 0x00000001U 455f7917c00SJeff Kirsher 456f7917c00SJeff Kirsher #define TP_OUT_CONFIG 0x7d04 457f7917c00SJeff Kirsher #define VLANEXTENABLE_MASK 0x0000f000U 458f7917c00SJeff Kirsher #define VLANEXTENABLE_SHIFT 12 459f7917c00SJeff Kirsher 460f7917c00SJeff Kirsher #define TP_PARA_REG2 0x7d68 461f7917c00SJeff Kirsher #define MAXRXDATA_MASK 0xffff0000U 462f7917c00SJeff Kirsher #define MAXRXDATA_SHIFT 16 463f7917c00SJeff Kirsher #define MAXRXDATA_GET(x) (((x) & MAXRXDATA_MASK) >> MAXRXDATA_SHIFT) 464f7917c00SJeff Kirsher 465f7917c00SJeff Kirsher #define TP_TIMER_RESOLUTION 0x7d90 466f7917c00SJeff Kirsher #define TIMERRESOLUTION_MASK 0x00ff0000U 467f7917c00SJeff Kirsher #define TIMERRESOLUTION_SHIFT 16 468f7917c00SJeff Kirsher #define TIMERRESOLUTION_GET(x) (((x) & TIMERRESOLUTION_MASK) >> TIMERRESOLUTION_SHIFT) 469f7917c00SJeff Kirsher 470f7917c00SJeff Kirsher #define TP_SHIFT_CNT 0x7dc0 471f7917c00SJeff Kirsher 472f7917c00SJeff Kirsher #define TP_CCTRL_TABLE 0x7ddc 473f7917c00SJeff Kirsher #define TP_MTU_TABLE 0x7de4 474f7917c00SJeff Kirsher #define MTUINDEX_MASK 0xff000000U 475f7917c00SJeff Kirsher #define MTUINDEX_SHIFT 24 476f7917c00SJeff Kirsher #define MTUINDEX(x) ((x) << MTUINDEX_SHIFT) 477f7917c00SJeff Kirsher #define MTUWIDTH_MASK 0x000f0000U 478f7917c00SJeff Kirsher #define MTUWIDTH_SHIFT 16 479f7917c00SJeff Kirsher #define MTUWIDTH(x) ((x) << MTUWIDTH_SHIFT) 480f7917c00SJeff Kirsher #define MTUWIDTH_GET(x) (((x) & MTUWIDTH_MASK) >> MTUWIDTH_SHIFT) 481f7917c00SJeff Kirsher #define MTUVALUE_MASK 0x00003fffU 482f7917c00SJeff Kirsher #define MTUVALUE_SHIFT 0 483f7917c00SJeff Kirsher #define MTUVALUE(x) ((x) << MTUVALUE_SHIFT) 484f7917c00SJeff Kirsher #define MTUVALUE_GET(x) (((x) & MTUVALUE_MASK) >> MTUVALUE_SHIFT) 485f7917c00SJeff Kirsher 486f7917c00SJeff Kirsher #define TP_RSS_LKP_TABLE 0x7dec 487f7917c00SJeff Kirsher #define LKPTBLROWVLD 0x80000000U 488f7917c00SJeff Kirsher #define LKPTBLQUEUE1_MASK 0x000ffc00U 489f7917c00SJeff Kirsher #define LKPTBLQUEUE1_SHIFT 10 490f7917c00SJeff Kirsher #define LKPTBLQUEUE1(x) ((x) << LKPTBLQUEUE1_SHIFT) 491f7917c00SJeff Kirsher #define LKPTBLQUEUE1_GET(x) (((x) & LKPTBLQUEUE1_MASK) >> LKPTBLQUEUE1_SHIFT) 492f7917c00SJeff Kirsher #define LKPTBLQUEUE0_MASK 0x000003ffU 493f7917c00SJeff Kirsher #define LKPTBLQUEUE0_SHIFT 0 494f7917c00SJeff Kirsher #define LKPTBLQUEUE0(x) ((x) << LKPTBLQUEUE0_SHIFT) 495f7917c00SJeff Kirsher #define LKPTBLQUEUE0_GET(x) (((x) & LKPTBLQUEUE0_MASK) >> LKPTBLQUEUE0_SHIFT) 496f7917c00SJeff Kirsher 497f7917c00SJeff Kirsher #define TP_PIO_ADDR 0x7e40 498f7917c00SJeff Kirsher #define TP_PIO_DATA 0x7e44 499f7917c00SJeff Kirsher #define TP_MIB_INDEX 0x7e50 500f7917c00SJeff Kirsher #define TP_MIB_DATA 0x7e54 501f7917c00SJeff Kirsher #define TP_INT_CAUSE 0x7e74 502f7917c00SJeff Kirsher #define FLMTXFLSTEMPTY 0x40000000U 503f7917c00SJeff Kirsher 504f7917c00SJeff Kirsher #define TP_INGRESS_CONFIG 0x141 505f7917c00SJeff Kirsher #define VNIC 0x00000800U 506f7917c00SJeff Kirsher #define CSUM_HAS_PSEUDO_HDR 0x00000400U 507f7917c00SJeff Kirsher #define RM_OVLAN 0x00000200U 508f7917c00SJeff Kirsher #define LOOKUPEVERYPKT 0x00000100U 509f7917c00SJeff Kirsher 510f7917c00SJeff Kirsher #define TP_MIB_MAC_IN_ERR_0 0x0 511f7917c00SJeff Kirsher #define TP_MIB_TCP_OUT_RST 0xc 512f7917c00SJeff Kirsher #define TP_MIB_TCP_IN_SEG_HI 0x10 513f7917c00SJeff Kirsher #define TP_MIB_TCP_IN_SEG_LO 0x11 514f7917c00SJeff Kirsher #define TP_MIB_TCP_OUT_SEG_HI 0x12 515f7917c00SJeff Kirsher #define TP_MIB_TCP_OUT_SEG_LO 0x13 516f7917c00SJeff Kirsher #define TP_MIB_TCP_RXT_SEG_HI 0x14 517f7917c00SJeff Kirsher #define TP_MIB_TCP_RXT_SEG_LO 0x15 518f7917c00SJeff Kirsher #define TP_MIB_TNL_CNG_DROP_0 0x18 519f7917c00SJeff Kirsher #define TP_MIB_TCP_V6IN_ERR_0 0x28 520f7917c00SJeff Kirsher #define TP_MIB_TCP_V6OUT_RST 0x2c 521f7917c00SJeff Kirsher #define TP_MIB_OFD_ARP_DROP 0x36 522f7917c00SJeff Kirsher #define TP_MIB_TNL_DROP_0 0x44 523f7917c00SJeff Kirsher #define TP_MIB_OFD_VLN_DROP_0 0x58 524f7917c00SJeff Kirsher 525f7917c00SJeff Kirsher #define ULP_TX_INT_CAUSE 0x8dcc 526f7917c00SJeff Kirsher #define PBL_BOUND_ERR_CH3 0x80000000U 527f7917c00SJeff Kirsher #define PBL_BOUND_ERR_CH2 0x40000000U 528f7917c00SJeff Kirsher #define PBL_BOUND_ERR_CH1 0x20000000U 529f7917c00SJeff Kirsher #define PBL_BOUND_ERR_CH0 0x10000000U 530f7917c00SJeff Kirsher 531f7917c00SJeff Kirsher #define PM_RX_INT_CAUSE 0x8fdc 532f7917c00SJeff Kirsher #define ZERO_E_CMD_ERROR 0x00400000U 533f7917c00SJeff Kirsher #define PMRX_FRAMING_ERROR 0x003ffff0U 534f7917c00SJeff Kirsher #define OCSPI_PAR_ERROR 0x00000008U 535f7917c00SJeff Kirsher #define DB_OPTIONS_PAR_ERROR 0x00000004U 536f7917c00SJeff Kirsher #define IESPI_PAR_ERROR 0x00000002U 537f7917c00SJeff Kirsher #define E_PCMD_PAR_ERROR 0x00000001U 538f7917c00SJeff Kirsher 539f7917c00SJeff Kirsher #define PM_TX_INT_CAUSE 0x8ffc 540f7917c00SJeff Kirsher #define PCMD_LEN_OVFL0 0x80000000U 541f7917c00SJeff Kirsher #define PCMD_LEN_OVFL1 0x40000000U 542f7917c00SJeff Kirsher #define PCMD_LEN_OVFL2 0x20000000U 543f7917c00SJeff Kirsher #define ZERO_C_CMD_ERROR 0x10000000U 544f7917c00SJeff Kirsher #define PMTX_FRAMING_ERROR 0x0ffffff0U 545f7917c00SJeff Kirsher #define OESPI_PAR_ERROR 0x00000008U 546f7917c00SJeff Kirsher #define ICSPI_PAR_ERROR 0x00000002U 547f7917c00SJeff Kirsher #define C_PCMD_PAR_ERROR 0x00000001U 548f7917c00SJeff Kirsher 549f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_BYTES_L 0x400 550f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_BYTES_H 0x404 551f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408 552f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c 553f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_BCAST_L 0x410 554f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_BCAST_H 0x414 555f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_MCAST_L 0x418 556f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c 557f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_UCAST_L 0x420 558f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_UCAST_H 0x424 559f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_ERROR_L 0x428 560f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c 561f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_64B_L 0x430 562f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_64B_H 0x434 563f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438 564f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c 565f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440 566f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444 567f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448 568f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c 569f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450 570f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454 571f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458 572f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c 573f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460 574f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464 575f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_DROP_L 0x468 576f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_DROP_H 0x46c 577f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470 578f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474 579f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PPP0_L 0x478 580f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c 581f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PPP1_L 0x480 582f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PPP1_H 0x484 583f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PPP2_L 0x488 584f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c 585f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PPP3_L 0x490 586f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PPP3_H 0x494 587f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PPP4_L 0x498 588f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c 589f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0 590f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4 591f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8 592f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac 593f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0 594f7917c00SJeff Kirsher #define MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4 595f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0 596f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4 597f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8 598f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc 599f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0 600f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4 601f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8 602f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc 603f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0 604f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4 605f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8 606f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec 607f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_64B_L 0x4f0 608f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_64B_H 0x4f4 609f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8 610f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc 611f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500 612f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504 613f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508 614f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c 615f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510 616f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514 617f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518 618f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c 619f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520 620f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524 621f7917c00SJeff Kirsher #define MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528 622f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_BYTES_L 0x540 623f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_BYTES_H 0x544 624f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548 625f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c 626f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_BCAST_L 0x550 627f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_BCAST_H 0x554 628f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_MCAST_L 0x558 629f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c 630f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_UCAST_L 0x560 631f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_UCAST_H 0x564 632f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568 633f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c 634f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570 635f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574 636f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578 637f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c 638f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580 639f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584 640f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588 641f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c 642f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_64B_L 0x590 643f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_64B_H 0x594 644f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598 645f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c 646f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0 647f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4 648f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8 649f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac 650f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0 651f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4 652f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8 653f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc 654f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0 655f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4 656f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8 657f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc 658f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0 659f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4 660f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8 661f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc 662f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0 663f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4 664f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8 665f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec 666f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0 667f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4 668f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8 669f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc 670f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PPP6_L 0x600 671f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PPP6_H 0x604 672f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PPP7_L 0x608 673f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c 674f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610 675f7917c00SJeff Kirsher #define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614 676f7917c00SJeff Kirsher #define MPS_CMN_CTL 0x9000 677f7917c00SJeff Kirsher #define NUMPORTS_MASK 0x00000003U 678f7917c00SJeff Kirsher #define NUMPORTS_SHIFT 0 679f7917c00SJeff Kirsher #define NUMPORTS_GET(x) (((x) & NUMPORTS_MASK) >> NUMPORTS_SHIFT) 680f7917c00SJeff Kirsher 681f7917c00SJeff Kirsher #define MPS_INT_CAUSE 0x9008 682f7917c00SJeff Kirsher #define STATINT 0x00000020U 683f7917c00SJeff Kirsher #define TXINT 0x00000010U 684f7917c00SJeff Kirsher #define RXINT 0x00000008U 685f7917c00SJeff Kirsher #define TRCINT 0x00000004U 686f7917c00SJeff Kirsher #define CLSINT 0x00000002U 687f7917c00SJeff Kirsher #define PLINT 0x00000001U 688f7917c00SJeff Kirsher 689f7917c00SJeff Kirsher #define MPS_TX_INT_CAUSE 0x9408 690f7917c00SJeff Kirsher #define PORTERR 0x00010000U 691f7917c00SJeff Kirsher #define FRMERR 0x00008000U 692f7917c00SJeff Kirsher #define SECNTERR 0x00004000U 693f7917c00SJeff Kirsher #define BUBBLE 0x00002000U 694f7917c00SJeff Kirsher #define TXDESCFIFO 0x00001e00U 695f7917c00SJeff Kirsher #define TXDATAFIFO 0x000001e0U 696f7917c00SJeff Kirsher #define NCSIFIFO 0x00000010U 697f7917c00SJeff Kirsher #define TPFIFO 0x0000000fU 698f7917c00SJeff Kirsher 699f7917c00SJeff Kirsher #define MPS_STAT_PERR_INT_CAUSE_SRAM 0x9614 700f7917c00SJeff Kirsher #define MPS_STAT_PERR_INT_CAUSE_TX_FIFO 0x9620 701f7917c00SJeff Kirsher #define MPS_STAT_PERR_INT_CAUSE_RX_FIFO 0x962c 702f7917c00SJeff Kirsher 703f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640 704f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644 705f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648 706f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c 707f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650 708f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654 709f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658 710f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c 711f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660 712f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664 713f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668 714f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c 715f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670 716f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674 717f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678 718f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c 719f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680 720f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684 721f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688 722f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c 723f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690 724f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694 725f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698 726f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c 727f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0 728f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4 729f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8 730f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac 731f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0 732f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4 733f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8 734f7917c00SJeff Kirsher #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc 735f7917c00SJeff Kirsher #define MPS_TRC_CFG 0x9800 736f7917c00SJeff Kirsher #define TRCFIFOEMPTY 0x00000010U 737f7917c00SJeff Kirsher #define TRCIGNOREDROPINPUT 0x00000008U 738f7917c00SJeff Kirsher #define TRCKEEPDUPLICATES 0x00000004U 739f7917c00SJeff Kirsher #define TRCEN 0x00000002U 740f7917c00SJeff Kirsher #define TRCMULTIFILTER 0x00000001U 741f7917c00SJeff Kirsher 742f7917c00SJeff Kirsher #define MPS_TRC_RSS_CONTROL 0x9808 743f7917c00SJeff Kirsher #define RSSCONTROL_MASK 0x00ff0000U 744f7917c00SJeff Kirsher #define RSSCONTROL_SHIFT 16 745f7917c00SJeff Kirsher #define RSSCONTROL(x) ((x) << RSSCONTROL_SHIFT) 746f7917c00SJeff Kirsher #define QUEUENUMBER_MASK 0x0000ffffU 747f7917c00SJeff Kirsher #define QUEUENUMBER_SHIFT 0 748f7917c00SJeff Kirsher #define QUEUENUMBER(x) ((x) << QUEUENUMBER_SHIFT) 749f7917c00SJeff Kirsher 750f7917c00SJeff Kirsher #define MPS_TRC_FILTER_MATCH_CTL_A 0x9810 751f7917c00SJeff Kirsher #define TFINVERTMATCH 0x01000000U 752f7917c00SJeff Kirsher #define TFPKTTOOLARGE 0x00800000U 753f7917c00SJeff Kirsher #define TFEN 0x00400000U 754f7917c00SJeff Kirsher #define TFPORT_MASK 0x003c0000U 755f7917c00SJeff Kirsher #define TFPORT_SHIFT 18 756f7917c00SJeff Kirsher #define TFPORT(x) ((x) << TFPORT_SHIFT) 757f7917c00SJeff Kirsher #define TFPORT_GET(x) (((x) & TFPORT_MASK) >> TFPORT_SHIFT) 758f7917c00SJeff Kirsher #define TFDROP 0x00020000U 759f7917c00SJeff Kirsher #define TFSOPEOPERR 0x00010000U 760f7917c00SJeff Kirsher #define TFLENGTH_MASK 0x00001f00U 761f7917c00SJeff Kirsher #define TFLENGTH_SHIFT 8 762f7917c00SJeff Kirsher #define TFLENGTH(x) ((x) << TFLENGTH_SHIFT) 763f7917c00SJeff Kirsher #define TFLENGTH_GET(x) (((x) & TFLENGTH_MASK) >> TFLENGTH_SHIFT) 764f7917c00SJeff Kirsher #define TFOFFSET_MASK 0x0000001fU 765f7917c00SJeff Kirsher #define TFOFFSET_SHIFT 0 766f7917c00SJeff Kirsher #define TFOFFSET(x) ((x) << TFOFFSET_SHIFT) 767f7917c00SJeff Kirsher #define TFOFFSET_GET(x) (((x) & TFOFFSET_MASK) >> TFOFFSET_SHIFT) 768f7917c00SJeff Kirsher 769f7917c00SJeff Kirsher #define MPS_TRC_FILTER_MATCH_CTL_B 0x9820 770f7917c00SJeff Kirsher #define TFMINPKTSIZE_MASK 0x01ff0000U 771f7917c00SJeff Kirsher #define TFMINPKTSIZE_SHIFT 16 772f7917c00SJeff Kirsher #define TFMINPKTSIZE(x) ((x) << TFMINPKTSIZE_SHIFT) 773f7917c00SJeff Kirsher #define TFMINPKTSIZE_GET(x) (((x) & TFMINPKTSIZE_MASK) >> TFMINPKTSIZE_SHIFT) 774f7917c00SJeff Kirsher #define TFCAPTUREMAX_MASK 0x00003fffU 775f7917c00SJeff Kirsher #define TFCAPTUREMAX_SHIFT 0 776f7917c00SJeff Kirsher #define TFCAPTUREMAX(x) ((x) << TFCAPTUREMAX_SHIFT) 777f7917c00SJeff Kirsher #define TFCAPTUREMAX_GET(x) (((x) & TFCAPTUREMAX_MASK) >> TFCAPTUREMAX_SHIFT) 778f7917c00SJeff Kirsher 779f7917c00SJeff Kirsher #define MPS_TRC_INT_CAUSE 0x985c 780f7917c00SJeff Kirsher #define MISCPERR 0x00000100U 781f7917c00SJeff Kirsher #define PKTFIFO 0x000000f0U 782f7917c00SJeff Kirsher #define FILTMEM 0x0000000fU 783f7917c00SJeff Kirsher 784f7917c00SJeff Kirsher #define MPS_TRC_FILTER0_MATCH 0x9c00 785f7917c00SJeff Kirsher #define MPS_TRC_FILTER0_DONT_CARE 0x9c80 786f7917c00SJeff Kirsher #define MPS_TRC_FILTER1_MATCH 0x9d00 787f7917c00SJeff Kirsher #define MPS_CLS_INT_CAUSE 0xd028 788f7917c00SJeff Kirsher #define PLERRENB 0x00000008U 789f7917c00SJeff Kirsher #define HASHSRAM 0x00000004U 790f7917c00SJeff Kirsher #define MATCHTCAM 0x00000002U 791f7917c00SJeff Kirsher #define MATCHSRAM 0x00000001U 792f7917c00SJeff Kirsher 793f7917c00SJeff Kirsher #define MPS_RX_PERR_INT_CAUSE 0x11074 794f7917c00SJeff Kirsher 795f7917c00SJeff Kirsher #define CPL_INTR_CAUSE 0x19054 796f7917c00SJeff Kirsher #define CIM_OP_MAP_PERR 0x00000020U 797f7917c00SJeff Kirsher #define CIM_OVFL_ERROR 0x00000010U 798f7917c00SJeff Kirsher #define TP_FRAMING_ERROR 0x00000008U 799f7917c00SJeff Kirsher #define SGE_FRAMING_ERROR 0x00000004U 800f7917c00SJeff Kirsher #define CIM_FRAMING_ERROR 0x00000002U 801f7917c00SJeff Kirsher #define ZERO_SWITCH_ERROR 0x00000001U 802f7917c00SJeff Kirsher 803f7917c00SJeff Kirsher #define SMB_INT_CAUSE 0x19090 804f7917c00SJeff Kirsher #define MSTTXFIFOPARINT 0x00200000U 805f7917c00SJeff Kirsher #define MSTRXFIFOPARINT 0x00100000U 806f7917c00SJeff Kirsher #define SLVFIFOPARINT 0x00080000U 807f7917c00SJeff Kirsher 808f7917c00SJeff Kirsher #define ULP_RX_INT_CAUSE 0x19158 809f7917c00SJeff Kirsher #define ULP_RX_ISCSI_TAGMASK 0x19164 810f7917c00SJeff Kirsher #define ULP_RX_ISCSI_PSZ 0x19168 811f7917c00SJeff Kirsher #define HPZ3_MASK 0x0f000000U 812f7917c00SJeff Kirsher #define HPZ3_SHIFT 24 813f7917c00SJeff Kirsher #define HPZ3(x) ((x) << HPZ3_SHIFT) 814f7917c00SJeff Kirsher #define HPZ2_MASK 0x000f0000U 815f7917c00SJeff Kirsher #define HPZ2_SHIFT 16 816f7917c00SJeff Kirsher #define HPZ2(x) ((x) << HPZ2_SHIFT) 817f7917c00SJeff Kirsher #define HPZ1_MASK 0x00000f00U 818f7917c00SJeff Kirsher #define HPZ1_SHIFT 8 819f7917c00SJeff Kirsher #define HPZ1(x) ((x) << HPZ1_SHIFT) 820f7917c00SJeff Kirsher #define HPZ0_MASK 0x0000000fU 821f7917c00SJeff Kirsher #define HPZ0_SHIFT 0 822f7917c00SJeff Kirsher #define HPZ0(x) ((x) << HPZ0_SHIFT) 823f7917c00SJeff Kirsher 824f7917c00SJeff Kirsher #define ULP_RX_TDDP_PSZ 0x19178 825f7917c00SJeff Kirsher 826f7917c00SJeff Kirsher #define SF_DATA 0x193f8 827f7917c00SJeff Kirsher #define SF_OP 0x193fc 828f7917c00SJeff Kirsher #define BUSY 0x80000000U 829f7917c00SJeff Kirsher #define SF_LOCK 0x00000010U 830f7917c00SJeff Kirsher #define SF_CONT 0x00000008U 831f7917c00SJeff Kirsher #define BYTECNT_MASK 0x00000006U 832f7917c00SJeff Kirsher #define BYTECNT_SHIFT 1 833f7917c00SJeff Kirsher #define BYTECNT(x) ((x) << BYTECNT_SHIFT) 834f7917c00SJeff Kirsher #define OP_WR 0x00000001U 835f7917c00SJeff Kirsher 836f7917c00SJeff Kirsher #define PL_PF_INT_CAUSE 0x3c0 837f7917c00SJeff Kirsher #define PFSW 0x00000008U 838f7917c00SJeff Kirsher #define PFSGE 0x00000004U 839f7917c00SJeff Kirsher #define PFCIM 0x00000002U 840f7917c00SJeff Kirsher #define PFMPS 0x00000001U 841f7917c00SJeff Kirsher 842f7917c00SJeff Kirsher #define PL_PF_INT_ENABLE 0x3c4 843f7917c00SJeff Kirsher #define PL_PF_CTL 0x3c8 844f7917c00SJeff Kirsher #define SWINT 0x00000001U 845f7917c00SJeff Kirsher 846f7917c00SJeff Kirsher #define PL_WHOAMI 0x19400 847f7917c00SJeff Kirsher #define SOURCEPF_MASK 0x00000700U 848f7917c00SJeff Kirsher #define SOURCEPF_SHIFT 8 849f7917c00SJeff Kirsher #define SOURCEPF(x) ((x) << SOURCEPF_SHIFT) 850f7917c00SJeff Kirsher #define SOURCEPF_GET(x) (((x) & SOURCEPF_MASK) >> SOURCEPF_SHIFT) 851f7917c00SJeff Kirsher #define ISVF 0x00000080U 852f7917c00SJeff Kirsher #define VFID_MASK 0x0000007fU 853f7917c00SJeff Kirsher #define VFID_SHIFT 0 854f7917c00SJeff Kirsher #define VFID(x) ((x) << VFID_SHIFT) 855f7917c00SJeff Kirsher #define VFID_GET(x) (((x) & VFID_MASK) >> VFID_SHIFT) 856f7917c00SJeff Kirsher 857f7917c00SJeff Kirsher #define PL_INT_CAUSE 0x1940c 858f7917c00SJeff Kirsher #define ULP_TX 0x08000000U 859f7917c00SJeff Kirsher #define SGE 0x04000000U 860f7917c00SJeff Kirsher #define HMA 0x02000000U 861f7917c00SJeff Kirsher #define CPL_SWITCH 0x01000000U 862f7917c00SJeff Kirsher #define ULP_RX 0x00800000U 863f7917c00SJeff Kirsher #define PM_RX 0x00400000U 864f7917c00SJeff Kirsher #define PM_TX 0x00200000U 865f7917c00SJeff Kirsher #define MA 0x00100000U 866f7917c00SJeff Kirsher #define TP 0x00080000U 867f7917c00SJeff Kirsher #define LE 0x00040000U 868f7917c00SJeff Kirsher #define EDC1 0x00020000U 869f7917c00SJeff Kirsher #define EDC0 0x00010000U 870f7917c00SJeff Kirsher #define MC 0x00008000U 871f7917c00SJeff Kirsher #define PCIE 0x00004000U 872f7917c00SJeff Kirsher #define PMU 0x00002000U 873f7917c00SJeff Kirsher #define XGMAC_KR1 0x00001000U 874f7917c00SJeff Kirsher #define XGMAC_KR0 0x00000800U 875f7917c00SJeff Kirsher #define XGMAC1 0x00000400U 876f7917c00SJeff Kirsher #define XGMAC0 0x00000200U 877f7917c00SJeff Kirsher #define SMB 0x00000100U 878f7917c00SJeff Kirsher #define SF 0x00000080U 879f7917c00SJeff Kirsher #define PL 0x00000040U 880f7917c00SJeff Kirsher #define NCSI 0x00000020U 881f7917c00SJeff Kirsher #define MPS 0x00000010U 882f7917c00SJeff Kirsher #define MI 0x00000008U 883f7917c00SJeff Kirsher #define DBG 0x00000004U 884f7917c00SJeff Kirsher #define I2CM 0x00000002U 885f7917c00SJeff Kirsher #define CIM 0x00000001U 886f7917c00SJeff Kirsher 887f7917c00SJeff Kirsher #define PL_INT_MAP0 0x19414 888f7917c00SJeff Kirsher #define PL_RST 0x19428 889f7917c00SJeff Kirsher #define PIORST 0x00000002U 890f7917c00SJeff Kirsher #define PIORSTMODE 0x00000001U 891f7917c00SJeff Kirsher 892f7917c00SJeff Kirsher #define PL_PL_INT_CAUSE 0x19430 893f7917c00SJeff Kirsher #define FATALPERR 0x00000010U 894f7917c00SJeff Kirsher #define PERRVFID 0x00000001U 895f7917c00SJeff Kirsher 896f7917c00SJeff Kirsher #define PL_REV 0x1943c 897f7917c00SJeff Kirsher 898f7917c00SJeff Kirsher #define LE_DB_CONFIG 0x19c04 899f7917c00SJeff Kirsher #define HASHEN 0x00100000U 900f7917c00SJeff Kirsher 901f7917c00SJeff Kirsher #define LE_DB_SERVER_INDEX 0x19c18 902f7917c00SJeff Kirsher #define LE_DB_ACT_CNT_IPV4 0x19c20 903f7917c00SJeff Kirsher #define LE_DB_ACT_CNT_IPV6 0x19c24 904f7917c00SJeff Kirsher 905f7917c00SJeff Kirsher #define LE_DB_INT_CAUSE 0x19c3c 906f7917c00SJeff Kirsher #define REQQPARERR 0x00010000U 907f7917c00SJeff Kirsher #define UNKNOWNCMD 0x00008000U 908f7917c00SJeff Kirsher #define PARITYERR 0x00000040U 909f7917c00SJeff Kirsher #define LIPMISS 0x00000020U 910f7917c00SJeff Kirsher #define LIP0 0x00000010U 911f7917c00SJeff Kirsher 912f7917c00SJeff Kirsher #define LE_DB_TID_HASHBASE 0x19df8 913f7917c00SJeff Kirsher 914f7917c00SJeff Kirsher #define NCSI_INT_CAUSE 0x1a0d8 915f7917c00SJeff Kirsher #define CIM_DM_PRTY_ERR 0x00000100U 916f7917c00SJeff Kirsher #define MPS_DM_PRTY_ERR 0x00000080U 917f7917c00SJeff Kirsher #define TXFIFO_PRTY_ERR 0x00000002U 918f7917c00SJeff Kirsher #define RXFIFO_PRTY_ERR 0x00000001U 919f7917c00SJeff Kirsher 920f7917c00SJeff Kirsher #define XGMAC_PORT_CFG2 0x1018 921f7917c00SJeff Kirsher #define PATEN 0x00040000U 922f7917c00SJeff Kirsher #define MAGICEN 0x00020000U 923f7917c00SJeff Kirsher 924f7917c00SJeff Kirsher #define XGMAC_PORT_MAGIC_MACID_LO 0x1024 925f7917c00SJeff Kirsher #define XGMAC_PORT_MAGIC_MACID_HI 0x1028 926f7917c00SJeff Kirsher 927f7917c00SJeff Kirsher #define XGMAC_PORT_EPIO_DATA0 0x10c0 928f7917c00SJeff Kirsher #define XGMAC_PORT_EPIO_DATA1 0x10c4 929f7917c00SJeff Kirsher #define XGMAC_PORT_EPIO_DATA2 0x10c8 930f7917c00SJeff Kirsher #define XGMAC_PORT_EPIO_DATA3 0x10cc 931f7917c00SJeff Kirsher #define XGMAC_PORT_EPIO_OP 0x10d0 932f7917c00SJeff Kirsher #define EPIOWR 0x00000100U 933f7917c00SJeff Kirsher #define ADDRESS_MASK 0x000000ffU 934f7917c00SJeff Kirsher #define ADDRESS_SHIFT 0 935f7917c00SJeff Kirsher #define ADDRESS(x) ((x) << ADDRESS_SHIFT) 936f7917c00SJeff Kirsher 937f7917c00SJeff Kirsher #define XGMAC_PORT_INT_CAUSE 0x10dc 938f7917c00SJeff Kirsher #endif /* __T4_REGS_H */ 939