1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __T4_MSG_H 36 #define __T4_MSG_H 37 38 #include <linux/types.h> 39 40 enum { 41 CPL_PASS_OPEN_REQ = 0x1, 42 CPL_PASS_ACCEPT_RPL = 0x2, 43 CPL_ACT_OPEN_REQ = 0x3, 44 CPL_SET_TCB_FIELD = 0x5, 45 CPL_GET_TCB = 0x6, 46 CPL_CLOSE_CON_REQ = 0x8, 47 CPL_CLOSE_LISTSRV_REQ = 0x9, 48 CPL_ABORT_REQ = 0xA, 49 CPL_ABORT_RPL = 0xB, 50 CPL_RX_DATA_ACK = 0xD, 51 CPL_TX_PKT = 0xE, 52 CPL_L2T_WRITE_REQ = 0x12, 53 CPL_TID_RELEASE = 0x1A, 54 55 CPL_CLOSE_LISTSRV_RPL = 0x20, 56 CPL_L2T_WRITE_RPL = 0x23, 57 CPL_PASS_OPEN_RPL = 0x24, 58 CPL_ACT_OPEN_RPL = 0x25, 59 CPL_PEER_CLOSE = 0x26, 60 CPL_ABORT_REQ_RSS = 0x2B, 61 CPL_ABORT_RPL_RSS = 0x2D, 62 63 CPL_CLOSE_CON_RPL = 0x32, 64 CPL_ISCSI_HDR = 0x33, 65 CPL_RDMA_CQE = 0x35, 66 CPL_RDMA_CQE_READ_RSP = 0x36, 67 CPL_RDMA_CQE_ERR = 0x37, 68 CPL_RX_DATA = 0x39, 69 CPL_SET_TCB_RPL = 0x3A, 70 CPL_RX_PKT = 0x3B, 71 CPL_RX_DDP_COMPLETE = 0x3F, 72 73 CPL_ACT_ESTABLISH = 0x40, 74 CPL_PASS_ESTABLISH = 0x41, 75 CPL_RX_DATA_DDP = 0x42, 76 CPL_PASS_ACCEPT_REQ = 0x44, 77 CPL_TRACE_PKT_T5 = 0x48, 78 CPL_RX_ISCSI_DDP = 0x49, 79 80 CPL_RDMA_READ_REQ = 0x60, 81 82 CPL_PASS_OPEN_REQ6 = 0x81, 83 CPL_ACT_OPEN_REQ6 = 0x83, 84 85 CPL_RDMA_TERMINATE = 0xA2, 86 CPL_RDMA_WRITE = 0xA4, 87 CPL_SGE_EGR_UPDATE = 0xA5, 88 89 CPL_TRACE_PKT = 0xB0, 90 CPL_ISCSI_DATA = 0xB2, 91 92 CPL_FW4_MSG = 0xC0, 93 CPL_FW4_PLD = 0xC1, 94 CPL_FW4_ACK = 0xC3, 95 96 CPL_FW6_MSG = 0xE0, 97 CPL_FW6_PLD = 0xE1, 98 CPL_TX_PKT_LSO = 0xED, 99 CPL_TX_PKT_XT = 0xEE, 100 101 NUM_CPL_CMDS 102 }; 103 104 enum CPL_error { 105 CPL_ERR_NONE = 0, 106 CPL_ERR_TCAM_FULL = 3, 107 CPL_ERR_BAD_LENGTH = 15, 108 CPL_ERR_BAD_ROUTE = 18, 109 CPL_ERR_CONN_RESET = 20, 110 CPL_ERR_CONN_EXIST_SYNRECV = 21, 111 CPL_ERR_CONN_EXIST = 22, 112 CPL_ERR_ARP_MISS = 23, 113 CPL_ERR_BAD_SYN = 24, 114 CPL_ERR_CONN_TIMEDOUT = 30, 115 CPL_ERR_XMIT_TIMEDOUT = 31, 116 CPL_ERR_PERSIST_TIMEDOUT = 32, 117 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 118 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 119 CPL_ERR_RTX_NEG_ADVICE = 35, 120 CPL_ERR_PERSIST_NEG_ADVICE = 36, 121 CPL_ERR_KEEPALV_NEG_ADVICE = 37, 122 CPL_ERR_ABORT_FAILED = 42, 123 CPL_ERR_IWARP_FLM = 50, 124 }; 125 126 enum { 127 ULP_MODE_NONE = 0, 128 ULP_MODE_ISCSI = 2, 129 ULP_MODE_RDMA = 4, 130 ULP_MODE_TCPDDP = 5, 131 ULP_MODE_FCOE = 6, 132 }; 133 134 enum { 135 ULP_CRC_HEADER = 1 << 0, 136 ULP_CRC_DATA = 1 << 1 137 }; 138 139 enum { 140 CPL_ABORT_SEND_RST = 0, 141 CPL_ABORT_NO_RST, 142 }; 143 144 enum { /* TX_PKT_XT checksum types */ 145 TX_CSUM_TCP = 0, 146 TX_CSUM_UDP = 1, 147 TX_CSUM_CRC16 = 4, 148 TX_CSUM_CRC32 = 5, 149 TX_CSUM_CRC32C = 6, 150 TX_CSUM_FCOE = 7, 151 TX_CSUM_TCPIP = 8, 152 TX_CSUM_UDPIP = 9, 153 TX_CSUM_TCPIP6 = 10, 154 TX_CSUM_UDPIP6 = 11, 155 TX_CSUM_IP = 12, 156 }; 157 158 union opcode_tid { 159 __be32 opcode_tid; 160 u8 opcode; 161 }; 162 163 #define CPL_OPCODE(x) ((x) << 24) 164 #define G_CPL_OPCODE(x) (((x) >> 24) & 0xFF) 165 #define MK_OPCODE_TID(opcode, tid) (CPL_OPCODE(opcode) | (tid)) 166 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 167 #define GET_TID(cmd) (ntohl(OPCODE_TID(cmd)) & 0xFFFFFF) 168 169 /* partitioning of TID fields that also carry a queue id */ 170 #define GET_TID_TID(x) ((x) & 0x3fff) 171 #define GET_TID_QID(x) (((x) >> 14) & 0x3ff) 172 #define TID_QID(x) ((x) << 14) 173 174 struct rss_header { 175 u8 opcode; 176 #if defined(__LITTLE_ENDIAN_BITFIELD) 177 u8 channel:2; 178 u8 filter_hit:1; 179 u8 filter_tid:1; 180 u8 hash_type:2; 181 u8 ipv6:1; 182 u8 send2fw:1; 183 #else 184 u8 send2fw:1; 185 u8 ipv6:1; 186 u8 hash_type:2; 187 u8 filter_tid:1; 188 u8 filter_hit:1; 189 u8 channel:2; 190 #endif 191 __be16 qid; 192 __be32 hash_val; 193 }; 194 195 struct work_request_hdr { 196 __be32 wr_hi; 197 __be32 wr_mid; 198 __be64 wr_lo; 199 }; 200 201 /* wr_hi fields */ 202 #define S_WR_OP 24 203 #define V_WR_OP(x) ((__u64)(x) << S_WR_OP) 204 205 #define WR_HDR struct work_request_hdr wr 206 207 /* option 0 fields */ 208 #define TX_CHAN_S 2 209 #define TX_CHAN_V(x) ((x) << TX_CHAN_S) 210 211 #define ULP_MODE_S 8 212 #define ULP_MODE_V(x) ((x) << ULP_MODE_S) 213 214 #define RCV_BUFSIZ_S 12 215 #define RCV_BUFSIZ_M 0x3FFU 216 #define RCV_BUFSIZ_V(x) ((x) << RCV_BUFSIZ_S) 217 218 #define SMAC_SEL_S 28 219 #define SMAC_SEL_V(x) ((__u64)(x) << SMAC_SEL_S) 220 221 #define L2T_IDX_S 36 222 #define L2T_IDX_V(x) ((__u64)(x) << L2T_IDX_S) 223 224 #define WND_SCALE_S 50 225 #define WND_SCALE_V(x) ((__u64)(x) << WND_SCALE_S) 226 227 #define KEEP_ALIVE_S 54 228 #define KEEP_ALIVE_V(x) ((__u64)(x) << KEEP_ALIVE_S) 229 #define KEEP_ALIVE_F KEEP_ALIVE_V(1ULL) 230 231 #define MSS_IDX_S 60 232 #define MSS_IDX_M 0xF 233 #define MSS_IDX_V(x) ((__u64)(x) << MSS_IDX_S) 234 #define MSS_IDX_G(x) (((x) >> MSS_IDX_S) & MSS_IDX_M) 235 236 /* option 2 fields */ 237 #define RSS_QUEUE_S 0 238 #define RSS_QUEUE_M 0x3FF 239 #define RSS_QUEUE_V(x) ((x) << RSS_QUEUE_S) 240 #define RSS_QUEUE_G(x) (((x) >> RSS_QUEUE_S) & RSS_QUEUE_M) 241 242 #define RSS_QUEUE_VALID_S 10 243 #define RSS_QUEUE_VALID_V(x) ((x) << RSS_QUEUE_VALID_S) 244 #define RSS_QUEUE_VALID_F RSS_QUEUE_VALID_V(1U) 245 246 #define RX_FC_DISABLE_S 20 247 #define RX_FC_DISABLE_V(x) ((x) << RX_FC_DISABLE_S) 248 #define RX_FC_DISABLE_F RX_FC_DISABLE_V(1U) 249 250 #define RX_FC_VALID_S 22 251 #define RX_FC_VALID_V(x) ((x) << RX_FC_VALID_S) 252 #define RX_FC_VALID_F RX_FC_VALID_V(1U) 253 254 #define RX_CHANNEL_S 26 255 #define RX_CHANNEL_V(x) ((x) << RX_CHANNEL_S) 256 257 #define WND_SCALE_EN_S 28 258 #define WND_SCALE_EN_V(x) ((x) << WND_SCALE_EN_S) 259 #define WND_SCALE_EN_F WND_SCALE_EN_V(1U) 260 261 #define T5_OPT_2_VALID_S 31 262 #define T5_OPT_2_VALID_V(x) ((x) << T5_OPT_2_VALID_S) 263 #define T5_OPT_2_VALID_F T5_OPT_2_VALID_V(1U) 264 265 struct cpl_pass_open_req { 266 WR_HDR; 267 union opcode_tid ot; 268 __be16 local_port; 269 __be16 peer_port; 270 __be32 local_ip; 271 __be32 peer_ip; 272 __be64 opt0; 273 #define NO_CONG(x) ((x) << 4) 274 #define DELACK(x) ((x) << 5) 275 #define DSCP(x) ((x) << 22) 276 #define TCAM_BYPASS(x) ((u64)(x) << 48) 277 #define NAGLE(x) ((u64)(x) << 49) 278 __be64 opt1; 279 #define SYN_RSS_ENABLE (1 << 0) 280 #define SYN_RSS_QUEUE(x) ((x) << 2) 281 #define CONN_POLICY_ASK (1 << 22) 282 }; 283 284 struct cpl_pass_open_req6 { 285 WR_HDR; 286 union opcode_tid ot; 287 __be16 local_port; 288 __be16 peer_port; 289 __be64 local_ip_hi; 290 __be64 local_ip_lo; 291 __be64 peer_ip_hi; 292 __be64 peer_ip_lo; 293 __be64 opt0; 294 __be64 opt1; 295 }; 296 297 struct cpl_pass_open_rpl { 298 union opcode_tid ot; 299 u8 rsvd[3]; 300 u8 status; 301 }; 302 303 struct cpl_pass_accept_rpl { 304 WR_HDR; 305 union opcode_tid ot; 306 __be32 opt2; 307 #define RX_COALESCE_VALID(x) ((x) << 11) 308 #define RX_COALESCE(x) ((x) << 12) 309 #define PACE(x) ((x) << 16) 310 #define TX_QUEUE(x) ((x) << 23) 311 #define CCTRL_ECN(x) ((x) << 27) 312 #define TSTAMPS_EN(x) ((x) << 29) 313 #define SACK_EN(x) ((x) << 30) 314 __be64 opt0; 315 }; 316 317 struct cpl_t5_pass_accept_rpl { 318 WR_HDR; 319 union opcode_tid ot; 320 __be32 opt2; 321 __be64 opt0; 322 __be32 iss; 323 __be32 rsvd; 324 }; 325 326 struct cpl_act_open_req { 327 WR_HDR; 328 union opcode_tid ot; 329 __be16 local_port; 330 __be16 peer_port; 331 __be32 local_ip; 332 __be32 peer_ip; 333 __be64 opt0; 334 __be32 params; 335 __be32 opt2; 336 }; 337 338 #define FILTER_TUPLE_S 24 339 #define FILTER_TUPLE_M 0xFFFFFFFFFF 340 #define FILTER_TUPLE_V(x) ((x) << FILTER_TUPLE_S) 341 #define FILTER_TUPLE_G(x) (((x) >> FILTER_TUPLE_S) & FILTER_TUPLE_M) 342 struct cpl_t5_act_open_req { 343 WR_HDR; 344 union opcode_tid ot; 345 __be16 local_port; 346 __be16 peer_port; 347 __be32 local_ip; 348 __be32 peer_ip; 349 __be64 opt0; 350 __be32 rsvd; 351 __be32 opt2; 352 __be64 params; 353 }; 354 355 struct cpl_act_open_req6 { 356 WR_HDR; 357 union opcode_tid ot; 358 __be16 local_port; 359 __be16 peer_port; 360 __be64 local_ip_hi; 361 __be64 local_ip_lo; 362 __be64 peer_ip_hi; 363 __be64 peer_ip_lo; 364 __be64 opt0; 365 __be32 params; 366 __be32 opt2; 367 }; 368 369 struct cpl_t5_act_open_req6 { 370 WR_HDR; 371 union opcode_tid ot; 372 __be16 local_port; 373 __be16 peer_port; 374 __be64 local_ip_hi; 375 __be64 local_ip_lo; 376 __be64 peer_ip_hi; 377 __be64 peer_ip_lo; 378 __be64 opt0; 379 __be32 rsvd; 380 __be32 opt2; 381 __be64 params; 382 }; 383 384 struct cpl_act_open_rpl { 385 union opcode_tid ot; 386 __be32 atid_status; 387 #define GET_AOPEN_STATUS(x) ((x) & 0xff) 388 #define GET_AOPEN_ATID(x) (((x) >> 8) & 0xffffff) 389 }; 390 391 struct cpl_pass_establish { 392 union opcode_tid ot; 393 __be32 rsvd; 394 __be32 tos_stid; 395 #define PASS_OPEN_TID(x) ((x) << 0) 396 #define PASS_OPEN_TOS(x) ((x) << 24) 397 #define GET_PASS_OPEN_TID(x) (((x) >> 0) & 0xFFFFFF) 398 #define GET_POPEN_TID(x) ((x) & 0xffffff) 399 #define GET_POPEN_TOS(x) (((x) >> 24) & 0xff) 400 __be16 mac_idx; 401 __be16 tcp_opt; 402 #define GET_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1) 403 #define GET_TCPOPT_SACK(x) (((x) >> 6) & 1) 404 #define GET_TCPOPT_TSTAMP(x) (((x) >> 7) & 1) 405 #define GET_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf) 406 #define GET_TCPOPT_MSS(x) (((x) >> 12) & 0xf) 407 __be32 snd_isn; 408 __be32 rcv_isn; 409 }; 410 411 struct cpl_act_establish { 412 union opcode_tid ot; 413 __be32 rsvd; 414 __be32 tos_atid; 415 __be16 mac_idx; 416 __be16 tcp_opt; 417 __be32 snd_isn; 418 __be32 rcv_isn; 419 }; 420 421 struct cpl_get_tcb { 422 WR_HDR; 423 union opcode_tid ot; 424 __be16 reply_ctrl; 425 #define QUEUENO(x) ((x) << 0) 426 #define REPLY_CHAN(x) ((x) << 14) 427 #define NO_REPLY(x) ((x) << 15) 428 __be16 cookie; 429 }; 430 431 struct cpl_set_tcb_field { 432 WR_HDR; 433 union opcode_tid ot; 434 __be16 reply_ctrl; 435 __be16 word_cookie; 436 #define TCB_WORD(x) ((x) << 0) 437 #define TCB_COOKIE(x) ((x) << 5) 438 #define GET_TCB_COOKIE(x) (((x) >> 5) & 7) 439 __be64 mask; 440 __be64 val; 441 }; 442 443 struct cpl_set_tcb_rpl { 444 union opcode_tid ot; 445 __be16 rsvd; 446 u8 cookie; 447 u8 status; 448 __be64 oldval; 449 }; 450 451 struct cpl_close_con_req { 452 WR_HDR; 453 union opcode_tid ot; 454 __be32 rsvd; 455 }; 456 457 struct cpl_close_con_rpl { 458 union opcode_tid ot; 459 u8 rsvd[3]; 460 u8 status; 461 __be32 snd_nxt; 462 __be32 rcv_nxt; 463 }; 464 465 struct cpl_close_listsvr_req { 466 WR_HDR; 467 union opcode_tid ot; 468 __be16 reply_ctrl; 469 #define LISTSVR_IPV6(x) ((x) << 14) 470 __be16 rsvd; 471 }; 472 473 struct cpl_close_listsvr_rpl { 474 union opcode_tid ot; 475 u8 rsvd[3]; 476 u8 status; 477 }; 478 479 struct cpl_abort_req_rss { 480 union opcode_tid ot; 481 u8 rsvd[3]; 482 u8 status; 483 }; 484 485 struct cpl_abort_req { 486 WR_HDR; 487 union opcode_tid ot; 488 __be32 rsvd0; 489 u8 rsvd1; 490 u8 cmd; 491 u8 rsvd2[6]; 492 }; 493 494 struct cpl_abort_rpl_rss { 495 union opcode_tid ot; 496 u8 rsvd[3]; 497 u8 status; 498 }; 499 500 struct cpl_abort_rpl { 501 WR_HDR; 502 union opcode_tid ot; 503 __be32 rsvd0; 504 u8 rsvd1; 505 u8 cmd; 506 u8 rsvd2[6]; 507 }; 508 509 struct cpl_peer_close { 510 union opcode_tid ot; 511 __be32 rcv_nxt; 512 }; 513 514 struct cpl_tid_release { 515 WR_HDR; 516 union opcode_tid ot; 517 __be32 rsvd; 518 }; 519 520 struct cpl_tx_pkt_core { 521 __be32 ctrl0; 522 #define TXPKT_VF(x) ((x) << 0) 523 #define TXPKT_PF(x) ((x) << 8) 524 #define TXPKT_VF_VLD (1 << 11) 525 #define TXPKT_OVLAN_IDX(x) ((x) << 12) 526 #define TXPKT_INTF(x) ((x) << 16) 527 #define TXPKT_INS_OVLAN (1 << 21) 528 #define TXPKT_OPCODE(x) ((x) << 24) 529 __be16 pack; 530 __be16 len; 531 __be64 ctrl1; 532 #define TXPKT_CSUM_END(x) ((x) << 12) 533 #define TXPKT_CSUM_START(x) ((x) << 20) 534 #define TXPKT_IPHDR_LEN(x) ((u64)(x) << 20) 535 #define TXPKT_CSUM_LOC(x) ((u64)(x) << 30) 536 #define TXPKT_ETHHDR_LEN(x) ((u64)(x) << 34) 537 #define TXPKT_CSUM_TYPE(x) ((u64)(x) << 40) 538 #define TXPKT_VLAN(x) ((u64)(x) << 44) 539 #define TXPKT_VLAN_VLD (1ULL << 60) 540 #define TXPKT_IPCSUM_DIS (1ULL << 62) 541 #define TXPKT_L4CSUM_DIS (1ULL << 63) 542 }; 543 544 struct cpl_tx_pkt { 545 WR_HDR; 546 struct cpl_tx_pkt_core c; 547 }; 548 549 #define cpl_tx_pkt_xt cpl_tx_pkt 550 551 struct cpl_tx_pkt_lso_core { 552 __be32 lso_ctrl; 553 #define LSO_TCPHDR_LEN(x) ((x) << 0) 554 #define LSO_IPHDR_LEN(x) ((x) << 4) 555 #define LSO_ETHHDR_LEN(x) ((x) << 16) 556 #define LSO_IPV6(x) ((x) << 20) 557 #define LSO_LAST_SLICE (1 << 22) 558 #define LSO_FIRST_SLICE (1 << 23) 559 #define LSO_OPCODE(x) ((x) << 24) 560 #define LSO_T5_XFER_SIZE(x) ((x) << 0) 561 __be16 ipid_ofst; 562 __be16 mss; 563 __be32 seqno_offset; 564 __be32 len; 565 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 566 }; 567 568 struct cpl_tx_pkt_lso { 569 WR_HDR; 570 struct cpl_tx_pkt_lso_core c; 571 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 572 }; 573 574 struct cpl_iscsi_hdr { 575 union opcode_tid ot; 576 __be16 pdu_len_ddp; 577 #define ISCSI_PDU_LEN(x) ((x) & 0x7FFF) 578 #define ISCSI_DDP (1 << 15) 579 __be16 len; 580 __be32 seq; 581 __be16 urg; 582 u8 rsvd; 583 u8 status; 584 }; 585 586 struct cpl_rx_data { 587 union opcode_tid ot; 588 __be16 rsvd; 589 __be16 len; 590 __be32 seq; 591 __be16 urg; 592 #if defined(__LITTLE_ENDIAN_BITFIELD) 593 u8 dack_mode:2; 594 u8 psh:1; 595 u8 heartbeat:1; 596 u8 ddp_off:1; 597 u8 :3; 598 #else 599 u8 :3; 600 u8 ddp_off:1; 601 u8 heartbeat:1; 602 u8 psh:1; 603 u8 dack_mode:2; 604 #endif 605 u8 status; 606 }; 607 608 struct cpl_rx_data_ack { 609 WR_HDR; 610 union opcode_tid ot; 611 __be32 credit_dack; 612 }; 613 614 /* cpl_rx_data_ack.ack_seq fields */ 615 #define RX_CREDITS_S 0 616 #define RX_CREDITS_V(x) ((x) << RX_CREDITS_S) 617 618 #define RX_FORCE_ACK_S 28 619 #define RX_FORCE_ACK_V(x) ((x) << RX_FORCE_ACK_S) 620 #define RX_FORCE_ACK_F RX_FORCE_ACK_V(1U) 621 622 struct cpl_rx_pkt { 623 struct rss_header rsshdr; 624 u8 opcode; 625 #if defined(__LITTLE_ENDIAN_BITFIELD) 626 u8 iff:4; 627 u8 csum_calc:1; 628 u8 ipmi_pkt:1; 629 u8 vlan_ex:1; 630 u8 ip_frag:1; 631 #else 632 u8 ip_frag:1; 633 u8 vlan_ex:1; 634 u8 ipmi_pkt:1; 635 u8 csum_calc:1; 636 u8 iff:4; 637 #endif 638 __be16 csum; 639 __be16 vlan; 640 __be16 len; 641 __be32 l2info; 642 #define RXF_UDP (1 << 22) 643 #define RXF_TCP (1 << 23) 644 #define RXF_IP (1 << 24) 645 #define RXF_IP6 (1 << 25) 646 __be16 hdr_len; 647 __be16 err_vec; 648 }; 649 650 /* rx_pkt.l2info fields */ 651 #define S_RX_ETHHDR_LEN 0 652 #define M_RX_ETHHDR_LEN 0x1F 653 #define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN) 654 #define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN) 655 656 #define S_RX_T5_ETHHDR_LEN 0 657 #define M_RX_T5_ETHHDR_LEN 0x3F 658 #define V_RX_T5_ETHHDR_LEN(x) ((x) << S_RX_T5_ETHHDR_LEN) 659 #define G_RX_T5_ETHHDR_LEN(x) (((x) >> S_RX_T5_ETHHDR_LEN) & M_RX_T5_ETHHDR_LEN) 660 661 #define S_RX_MACIDX 8 662 #define M_RX_MACIDX 0x1FF 663 #define V_RX_MACIDX(x) ((x) << S_RX_MACIDX) 664 #define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX) 665 666 #define S_RXF_SYN 21 667 #define V_RXF_SYN(x) ((x) << S_RXF_SYN) 668 #define F_RXF_SYN V_RXF_SYN(1U) 669 670 #define S_RX_CHAN 28 671 #define M_RX_CHAN 0xF 672 #define V_RX_CHAN(x) ((x) << S_RX_CHAN) 673 #define G_RX_CHAN(x) (((x) >> S_RX_CHAN) & M_RX_CHAN) 674 675 /* rx_pkt.hdr_len fields */ 676 #define S_RX_TCPHDR_LEN 0 677 #define M_RX_TCPHDR_LEN 0x3F 678 #define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN) 679 #define G_RX_TCPHDR_LEN(x) (((x) >> S_RX_TCPHDR_LEN) & M_RX_TCPHDR_LEN) 680 681 #define S_RX_IPHDR_LEN 6 682 #define M_RX_IPHDR_LEN 0x3FF 683 #define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN) 684 #define G_RX_IPHDR_LEN(x) (((x) >> S_RX_IPHDR_LEN) & M_RX_IPHDR_LEN) 685 686 struct cpl_trace_pkt { 687 u8 opcode; 688 u8 intf; 689 #if defined(__LITTLE_ENDIAN_BITFIELD) 690 u8 runt:4; 691 u8 filter_hit:4; 692 u8 :6; 693 u8 err:1; 694 u8 trunc:1; 695 #else 696 u8 filter_hit:4; 697 u8 runt:4; 698 u8 trunc:1; 699 u8 err:1; 700 u8 :6; 701 #endif 702 __be16 rsvd; 703 __be16 len; 704 __be64 tstamp; 705 }; 706 707 struct cpl_t5_trace_pkt { 708 __u8 opcode; 709 __u8 intf; 710 #if defined(__LITTLE_ENDIAN_BITFIELD) 711 __u8 runt:4; 712 __u8 filter_hit:4; 713 __u8:6; 714 __u8 err:1; 715 __u8 trunc:1; 716 #else 717 __u8 filter_hit:4; 718 __u8 runt:4; 719 __u8 trunc:1; 720 __u8 err:1; 721 __u8:6; 722 #endif 723 __be16 rsvd; 724 __be16 len; 725 __be64 tstamp; 726 __be64 rsvd1; 727 }; 728 729 struct cpl_l2t_write_req { 730 WR_HDR; 731 union opcode_tid ot; 732 __be16 params; 733 #define L2T_W_INFO(x) ((x) << 2) 734 #define L2T_W_PORT(x) ((x) << 8) 735 #define L2T_W_NOREPLY(x) ((x) << 15) 736 __be16 l2t_idx; 737 __be16 vlan; 738 u8 dst_mac[6]; 739 }; 740 741 struct cpl_l2t_write_rpl { 742 union opcode_tid ot; 743 u8 status; 744 u8 rsvd[3]; 745 }; 746 747 struct cpl_rdma_terminate { 748 union opcode_tid ot; 749 __be16 rsvd; 750 __be16 len; 751 }; 752 753 struct cpl_sge_egr_update { 754 __be32 opcode_qid; 755 #define EGR_QID(x) ((x) & 0x1FFFF) 756 __be16 cidx; 757 __be16 pidx; 758 }; 759 760 /* cpl_fw*.type values */ 761 enum { 762 FW_TYPE_CMD_RPL = 0, 763 FW_TYPE_WR_RPL = 1, 764 FW_TYPE_CQE = 2, 765 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3, 766 FW_TYPE_RSSCPL = 4, 767 }; 768 769 struct cpl_fw4_pld { 770 u8 opcode; 771 u8 rsvd0[3]; 772 u8 type; 773 u8 rsvd1; 774 __be16 len; 775 __be64 data; 776 __be64 rsvd2; 777 }; 778 779 struct cpl_fw6_pld { 780 u8 opcode; 781 u8 rsvd[5]; 782 __be16 len; 783 __be64 data[4]; 784 }; 785 786 struct cpl_fw4_msg { 787 u8 opcode; 788 u8 type; 789 __be16 rsvd0; 790 __be32 rsvd1; 791 __be64 data[2]; 792 }; 793 794 struct cpl_fw4_ack { 795 union opcode_tid ot; 796 u8 credits; 797 u8 rsvd0[2]; 798 u8 seq_vld; 799 __be32 snd_nxt; 800 __be32 snd_una; 801 __be64 rsvd1; 802 }; 803 804 struct cpl_fw6_msg { 805 u8 opcode; 806 u8 type; 807 __be16 rsvd0; 808 __be32 rsvd1; 809 __be64 data[4]; 810 }; 811 812 /* cpl_fw6_msg.type values */ 813 enum { 814 FW6_TYPE_CMD_RPL = 0, 815 FW6_TYPE_WR_RPL = 1, 816 FW6_TYPE_CQE = 2, 817 FW6_TYPE_OFLD_CONNECTION_WR_RPL = 3, 818 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL, 819 }; 820 821 struct cpl_fw6_msg_ofld_connection_wr_rpl { 822 __u64 cookie; 823 __be32 tid; /* or atid in case of active failure */ 824 __u8 t_state; 825 __u8 retval; 826 __u8 rsvd[2]; 827 }; 828 829 enum { 830 ULP_TX_MEM_READ = 2, 831 ULP_TX_MEM_WRITE = 3, 832 ULP_TX_PKT = 4 833 }; 834 835 enum { 836 ULP_TX_SC_NOOP = 0x80, 837 ULP_TX_SC_IMM = 0x81, 838 ULP_TX_SC_DSGL = 0x82, 839 ULP_TX_SC_ISGL = 0x83 840 }; 841 842 #define ULPTX_CMD_S 24 843 #define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S) 844 845 struct ulptx_sge_pair { 846 __be32 len[2]; 847 __be64 addr[2]; 848 }; 849 850 struct ulptx_sgl { 851 __be32 cmd_nsge; 852 #define ULPTX_NSGE(x) ((x) << 0) 853 #define ULPTX_MORE (1U << 23) 854 __be32 len0; 855 __be64 addr0; 856 struct ulptx_sge_pair sge[0]; 857 }; 858 859 struct ulp_mem_io { 860 WR_HDR; 861 __be32 cmd; 862 __be32 len16; /* command length */ 863 __be32 dlen; /* data length in 32-byte units */ 864 __be32 lock_addr; 865 #define ULP_MEMIO_LOCK(x) ((x) << 31) 866 }; 867 868 /* additional ulp_mem_io.cmd fields */ 869 #define ULP_MEMIO_ORDER_S 23 870 #define ULP_MEMIO_ORDER_V(x) ((x) << ULP_MEMIO_ORDER_S) 871 #define ULP_MEMIO_ORDER_F ULP_MEMIO_ORDER_V(1U) 872 873 #define T5_ULP_MEMIO_IMM_S 23 874 #define T5_ULP_MEMIO_IMM_V(x) ((x) << T5_ULP_MEMIO_IMM_S) 875 #define T5_ULP_MEMIO_IMM_F T5_ULP_MEMIO_IMM_V(1U) 876 877 #define S_T5_ULP_MEMIO_IMM 23 878 #define V_T5_ULP_MEMIO_IMM(x) ((x) << S_T5_ULP_MEMIO_IMM) 879 #define F_T5_ULP_MEMIO_IMM V_T5_ULP_MEMIO_IMM(1U) 880 881 #define S_T5_ULP_MEMIO_ORDER 22 882 #define V_T5_ULP_MEMIO_ORDER(x) ((x) << S_T5_ULP_MEMIO_ORDER) 883 #define F_T5_ULP_MEMIO_ORDER V_T5_ULP_MEMIO_ORDER(1U) 884 885 /* ulp_mem_io.lock_addr fields */ 886 #define ULP_MEMIO_ADDR_S 0 887 #define ULP_MEMIO_ADDR_V(x) ((x) << ULP_MEMIO_ADDR_S) 888 889 /* ulp_mem_io.dlen fields */ 890 #define ULP_MEMIO_DATA_LEN_S 0 891 #define ULP_MEMIO_DATA_LEN_V(x) ((x) << ULP_MEMIO_DATA_LEN_S) 892 893 #endif /* __T4_MSG_H */ 894