1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __T4_MSG_H 36 #define __T4_MSG_H 37 38 #include <linux/types.h> 39 40 enum { 41 CPL_PASS_OPEN_REQ = 0x1, 42 CPL_PASS_ACCEPT_RPL = 0x2, 43 CPL_ACT_OPEN_REQ = 0x3, 44 CPL_SET_TCB_FIELD = 0x5, 45 CPL_GET_TCB = 0x6, 46 CPL_CLOSE_CON_REQ = 0x8, 47 CPL_CLOSE_LISTSRV_REQ = 0x9, 48 CPL_ABORT_REQ = 0xA, 49 CPL_ABORT_RPL = 0xB, 50 CPL_RX_DATA_ACK = 0xD, 51 CPL_TX_PKT = 0xE, 52 CPL_L2T_WRITE_REQ = 0x12, 53 CPL_TID_RELEASE = 0x1A, 54 CPL_TX_DATA_ISO = 0x1F, 55 56 CPL_CLOSE_LISTSRV_RPL = 0x20, 57 CPL_L2T_WRITE_RPL = 0x23, 58 CPL_PASS_OPEN_RPL = 0x24, 59 CPL_ACT_OPEN_RPL = 0x25, 60 CPL_PEER_CLOSE = 0x26, 61 CPL_ABORT_REQ_RSS = 0x2B, 62 CPL_ABORT_RPL_RSS = 0x2D, 63 64 CPL_CLOSE_CON_RPL = 0x32, 65 CPL_ISCSI_HDR = 0x33, 66 CPL_RDMA_CQE = 0x35, 67 CPL_RDMA_CQE_READ_RSP = 0x36, 68 CPL_RDMA_CQE_ERR = 0x37, 69 CPL_RX_DATA = 0x39, 70 CPL_SET_TCB_RPL = 0x3A, 71 CPL_RX_PKT = 0x3B, 72 CPL_RX_DDP_COMPLETE = 0x3F, 73 74 CPL_ACT_ESTABLISH = 0x40, 75 CPL_PASS_ESTABLISH = 0x41, 76 CPL_RX_DATA_DDP = 0x42, 77 CPL_PASS_ACCEPT_REQ = 0x44, 78 CPL_TRACE_PKT_T5 = 0x48, 79 CPL_RX_ISCSI_DDP = 0x49, 80 81 CPL_RDMA_READ_REQ = 0x60, 82 83 CPL_PASS_OPEN_REQ6 = 0x81, 84 CPL_ACT_OPEN_REQ6 = 0x83, 85 86 CPL_RDMA_TERMINATE = 0xA2, 87 CPL_RDMA_WRITE = 0xA4, 88 CPL_SGE_EGR_UPDATE = 0xA5, 89 90 CPL_TRACE_PKT = 0xB0, 91 CPL_ISCSI_DATA = 0xB2, 92 93 CPL_FW4_MSG = 0xC0, 94 CPL_FW4_PLD = 0xC1, 95 CPL_FW4_ACK = 0xC3, 96 97 CPL_FW6_MSG = 0xE0, 98 CPL_FW6_PLD = 0xE1, 99 CPL_TX_PKT_LSO = 0xED, 100 CPL_TX_PKT_XT = 0xEE, 101 102 NUM_CPL_CMDS 103 }; 104 105 enum CPL_error { 106 CPL_ERR_NONE = 0, 107 CPL_ERR_TCAM_PARITY = 1, 108 CPL_ERR_TCAM_MISS = 2, 109 CPL_ERR_TCAM_FULL = 3, 110 CPL_ERR_BAD_LENGTH = 15, 111 CPL_ERR_BAD_ROUTE = 18, 112 CPL_ERR_CONN_RESET = 20, 113 CPL_ERR_CONN_EXIST_SYNRECV = 21, 114 CPL_ERR_CONN_EXIST = 22, 115 CPL_ERR_ARP_MISS = 23, 116 CPL_ERR_BAD_SYN = 24, 117 CPL_ERR_CONN_TIMEDOUT = 30, 118 CPL_ERR_XMIT_TIMEDOUT = 31, 119 CPL_ERR_PERSIST_TIMEDOUT = 32, 120 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 121 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 122 CPL_ERR_RTX_NEG_ADVICE = 35, 123 CPL_ERR_PERSIST_NEG_ADVICE = 36, 124 CPL_ERR_KEEPALV_NEG_ADVICE = 37, 125 CPL_ERR_ABORT_FAILED = 42, 126 CPL_ERR_IWARP_FLM = 50, 127 }; 128 129 enum { 130 CPL_CONN_POLICY_AUTO = 0, 131 CPL_CONN_POLICY_ASK = 1, 132 CPL_CONN_POLICY_FILTER = 2, 133 CPL_CONN_POLICY_DENY = 3 134 }; 135 136 enum { 137 ULP_MODE_NONE = 0, 138 ULP_MODE_ISCSI = 2, 139 ULP_MODE_RDMA = 4, 140 ULP_MODE_TCPDDP = 5, 141 ULP_MODE_FCOE = 6, 142 }; 143 144 enum { 145 ULP_CRC_HEADER = 1 << 0, 146 ULP_CRC_DATA = 1 << 1 147 }; 148 149 enum { 150 CPL_ABORT_SEND_RST = 0, 151 CPL_ABORT_NO_RST, 152 }; 153 154 enum { /* TX_PKT_XT checksum types */ 155 TX_CSUM_TCP = 0, 156 TX_CSUM_UDP = 1, 157 TX_CSUM_CRC16 = 4, 158 TX_CSUM_CRC32 = 5, 159 TX_CSUM_CRC32C = 6, 160 TX_CSUM_FCOE = 7, 161 TX_CSUM_TCPIP = 8, 162 TX_CSUM_UDPIP = 9, 163 TX_CSUM_TCPIP6 = 10, 164 TX_CSUM_UDPIP6 = 11, 165 TX_CSUM_IP = 12, 166 }; 167 168 union opcode_tid { 169 __be32 opcode_tid; 170 u8 opcode; 171 }; 172 173 #define CPL_OPCODE_S 24 174 #define CPL_OPCODE_V(x) ((x) << CPL_OPCODE_S) 175 #define CPL_OPCODE_G(x) (((x) >> CPL_OPCODE_S) & 0xFF) 176 #define TID_G(x) ((x) & 0xFFFFFF) 177 178 /* tid is assumed to be 24-bits */ 179 #define MK_OPCODE_TID(opcode, tid) (CPL_OPCODE_V(opcode) | (tid)) 180 181 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 182 183 /* extract the TID from a CPL command */ 184 #define GET_TID(cmd) (TID_G(be32_to_cpu(OPCODE_TID(cmd)))) 185 186 /* partitioning of TID fields that also carry a queue id */ 187 #define TID_TID_S 0 188 #define TID_TID_M 0x3fff 189 #define TID_TID_G(x) (((x) >> TID_TID_S) & TID_TID_M) 190 191 #define TID_QID_S 14 192 #define TID_QID_M 0x3ff 193 #define TID_QID_V(x) ((x) << TID_QID_S) 194 #define TID_QID_G(x) (((x) >> TID_QID_S) & TID_QID_M) 195 196 struct rss_header { 197 u8 opcode; 198 #if defined(__LITTLE_ENDIAN_BITFIELD) 199 u8 channel:2; 200 u8 filter_hit:1; 201 u8 filter_tid:1; 202 u8 hash_type:2; 203 u8 ipv6:1; 204 u8 send2fw:1; 205 #else 206 u8 send2fw:1; 207 u8 ipv6:1; 208 u8 hash_type:2; 209 u8 filter_tid:1; 210 u8 filter_hit:1; 211 u8 channel:2; 212 #endif 213 __be16 qid; 214 __be32 hash_val; 215 }; 216 217 struct work_request_hdr { 218 __be32 wr_hi; 219 __be32 wr_mid; 220 __be64 wr_lo; 221 }; 222 223 /* wr_hi fields */ 224 #define WR_OP_S 24 225 #define WR_OP_V(x) ((__u64)(x) << WR_OP_S) 226 227 #define WR_HDR struct work_request_hdr wr 228 229 /* option 0 fields */ 230 #define TX_CHAN_S 2 231 #define TX_CHAN_V(x) ((x) << TX_CHAN_S) 232 233 #define ULP_MODE_S 8 234 #define ULP_MODE_V(x) ((x) << ULP_MODE_S) 235 236 #define RCV_BUFSIZ_S 12 237 #define RCV_BUFSIZ_M 0x3FFU 238 #define RCV_BUFSIZ_V(x) ((x) << RCV_BUFSIZ_S) 239 240 #define SMAC_SEL_S 28 241 #define SMAC_SEL_V(x) ((__u64)(x) << SMAC_SEL_S) 242 243 #define L2T_IDX_S 36 244 #define L2T_IDX_V(x) ((__u64)(x) << L2T_IDX_S) 245 246 #define WND_SCALE_S 50 247 #define WND_SCALE_V(x) ((__u64)(x) << WND_SCALE_S) 248 249 #define KEEP_ALIVE_S 54 250 #define KEEP_ALIVE_V(x) ((__u64)(x) << KEEP_ALIVE_S) 251 #define KEEP_ALIVE_F KEEP_ALIVE_V(1ULL) 252 253 #define MSS_IDX_S 60 254 #define MSS_IDX_M 0xF 255 #define MSS_IDX_V(x) ((__u64)(x) << MSS_IDX_S) 256 #define MSS_IDX_G(x) (((x) >> MSS_IDX_S) & MSS_IDX_M) 257 258 /* option 2 fields */ 259 #define RSS_QUEUE_S 0 260 #define RSS_QUEUE_M 0x3FF 261 #define RSS_QUEUE_V(x) ((x) << RSS_QUEUE_S) 262 #define RSS_QUEUE_G(x) (((x) >> RSS_QUEUE_S) & RSS_QUEUE_M) 263 264 #define RSS_QUEUE_VALID_S 10 265 #define RSS_QUEUE_VALID_V(x) ((x) << RSS_QUEUE_VALID_S) 266 #define RSS_QUEUE_VALID_F RSS_QUEUE_VALID_V(1U) 267 268 #define RX_FC_DISABLE_S 20 269 #define RX_FC_DISABLE_V(x) ((x) << RX_FC_DISABLE_S) 270 #define RX_FC_DISABLE_F RX_FC_DISABLE_V(1U) 271 272 #define RX_FC_VALID_S 22 273 #define RX_FC_VALID_V(x) ((x) << RX_FC_VALID_S) 274 #define RX_FC_VALID_F RX_FC_VALID_V(1U) 275 276 #define RX_CHANNEL_S 26 277 #define RX_CHANNEL_V(x) ((x) << RX_CHANNEL_S) 278 279 #define WND_SCALE_EN_S 28 280 #define WND_SCALE_EN_V(x) ((x) << WND_SCALE_EN_S) 281 #define WND_SCALE_EN_F WND_SCALE_EN_V(1U) 282 283 #define T5_OPT_2_VALID_S 31 284 #define T5_OPT_2_VALID_V(x) ((x) << T5_OPT_2_VALID_S) 285 #define T5_OPT_2_VALID_F T5_OPT_2_VALID_V(1U) 286 287 struct cpl_pass_open_req { 288 WR_HDR; 289 union opcode_tid ot; 290 __be16 local_port; 291 __be16 peer_port; 292 __be32 local_ip; 293 __be32 peer_ip; 294 __be64 opt0; 295 __be64 opt1; 296 }; 297 298 /* option 0 fields */ 299 #define NO_CONG_S 4 300 #define NO_CONG_V(x) ((x) << NO_CONG_S) 301 #define NO_CONG_F NO_CONG_V(1U) 302 303 #define DELACK_S 5 304 #define DELACK_V(x) ((x) << DELACK_S) 305 #define DELACK_F DELACK_V(1U) 306 307 #define DSCP_S 22 308 #define DSCP_M 0x3F 309 #define DSCP_V(x) ((x) << DSCP_S) 310 #define DSCP_G(x) (((x) >> DSCP_S) & DSCP_M) 311 312 #define TCAM_BYPASS_S 48 313 #define TCAM_BYPASS_V(x) ((__u64)(x) << TCAM_BYPASS_S) 314 #define TCAM_BYPASS_F TCAM_BYPASS_V(1ULL) 315 316 #define NAGLE_S 49 317 #define NAGLE_V(x) ((__u64)(x) << NAGLE_S) 318 #define NAGLE_F NAGLE_V(1ULL) 319 320 /* option 1 fields */ 321 #define SYN_RSS_ENABLE_S 0 322 #define SYN_RSS_ENABLE_V(x) ((x) << SYN_RSS_ENABLE_S) 323 #define SYN_RSS_ENABLE_F SYN_RSS_ENABLE_V(1U) 324 325 #define SYN_RSS_QUEUE_S 2 326 #define SYN_RSS_QUEUE_V(x) ((x) << SYN_RSS_QUEUE_S) 327 328 #define CONN_POLICY_S 22 329 #define CONN_POLICY_V(x) ((x) << CONN_POLICY_S) 330 331 struct cpl_pass_open_req6 { 332 WR_HDR; 333 union opcode_tid ot; 334 __be16 local_port; 335 __be16 peer_port; 336 __be64 local_ip_hi; 337 __be64 local_ip_lo; 338 __be64 peer_ip_hi; 339 __be64 peer_ip_lo; 340 __be64 opt0; 341 __be64 opt1; 342 }; 343 344 struct cpl_pass_open_rpl { 345 union opcode_tid ot; 346 u8 rsvd[3]; 347 u8 status; 348 }; 349 350 struct tcp_options { 351 __be16 mss; 352 __u8 wsf; 353 #if defined(__LITTLE_ENDIAN_BITFIELD) 354 __u8:4; 355 __u8 unknown:1; 356 __u8:1; 357 __u8 sack:1; 358 __u8 tstamp:1; 359 #else 360 __u8 tstamp:1; 361 __u8 sack:1; 362 __u8:1; 363 __u8 unknown:1; 364 __u8:4; 365 #endif 366 }; 367 368 struct cpl_pass_accept_req { 369 union opcode_tid ot; 370 __be16 rsvd; 371 __be16 len; 372 __be32 hdr_len; 373 __be16 vlan; 374 __be16 l2info; 375 __be32 tos_stid; 376 struct tcp_options tcpopt; 377 }; 378 379 /* cpl_pass_accept_req.hdr_len fields */ 380 #define SYN_RX_CHAN_S 0 381 #define SYN_RX_CHAN_M 0xF 382 #define SYN_RX_CHAN_V(x) ((x) << SYN_RX_CHAN_S) 383 #define SYN_RX_CHAN_G(x) (((x) >> SYN_RX_CHAN_S) & SYN_RX_CHAN_M) 384 385 #define TCP_HDR_LEN_S 10 386 #define TCP_HDR_LEN_M 0x3F 387 #define TCP_HDR_LEN_V(x) ((x) << TCP_HDR_LEN_S) 388 #define TCP_HDR_LEN_G(x) (((x) >> TCP_HDR_LEN_S) & TCP_HDR_LEN_M) 389 390 #define IP_HDR_LEN_S 16 391 #define IP_HDR_LEN_M 0x3FF 392 #define IP_HDR_LEN_V(x) ((x) << IP_HDR_LEN_S) 393 #define IP_HDR_LEN_G(x) (((x) >> IP_HDR_LEN_S) & IP_HDR_LEN_M) 394 395 #define ETH_HDR_LEN_S 26 396 #define ETH_HDR_LEN_M 0x1F 397 #define ETH_HDR_LEN_V(x) ((x) << ETH_HDR_LEN_S) 398 #define ETH_HDR_LEN_G(x) (((x) >> ETH_HDR_LEN_S) & ETH_HDR_LEN_M) 399 400 /* cpl_pass_accept_req.l2info fields */ 401 #define SYN_MAC_IDX_S 0 402 #define SYN_MAC_IDX_M 0x1FF 403 #define SYN_MAC_IDX_V(x) ((x) << SYN_MAC_IDX_S) 404 #define SYN_MAC_IDX_G(x) (((x) >> SYN_MAC_IDX_S) & SYN_MAC_IDX_M) 405 406 #define SYN_XACT_MATCH_S 9 407 #define SYN_XACT_MATCH_V(x) ((x) << SYN_XACT_MATCH_S) 408 #define SYN_XACT_MATCH_F SYN_XACT_MATCH_V(1U) 409 410 #define SYN_INTF_S 12 411 #define SYN_INTF_M 0xF 412 #define SYN_INTF_V(x) ((x) << SYN_INTF_S) 413 #define SYN_INTF_G(x) (((x) >> SYN_INTF_S) & SYN_INTF_M) 414 415 enum { /* TCP congestion control algorithms */ 416 CONG_ALG_RENO, 417 CONG_ALG_TAHOE, 418 CONG_ALG_NEWRENO, 419 CONG_ALG_HIGHSPEED 420 }; 421 422 #define CONG_CNTRL_S 14 423 #define CONG_CNTRL_M 0x3 424 #define CONG_CNTRL_V(x) ((x) << CONG_CNTRL_S) 425 #define CONG_CNTRL_G(x) (((x) >> CONG_CNTRL_S) & CONG_CNTRL_M) 426 427 #define T5_ISS_S 18 428 #define T5_ISS_V(x) ((x) << T5_ISS_S) 429 #define T5_ISS_F T5_ISS_V(1U) 430 431 struct cpl_pass_accept_rpl { 432 WR_HDR; 433 union opcode_tid ot; 434 __be32 opt2; 435 __be64 opt0; 436 }; 437 438 /* option 2 fields */ 439 #define RX_COALESCE_VALID_S 11 440 #define RX_COALESCE_VALID_V(x) ((x) << RX_COALESCE_VALID_S) 441 #define RX_COALESCE_VALID_F RX_COALESCE_VALID_V(1U) 442 443 #define RX_COALESCE_S 12 444 #define RX_COALESCE_V(x) ((x) << RX_COALESCE_S) 445 446 #define PACE_S 16 447 #define PACE_V(x) ((x) << PACE_S) 448 449 #define TX_QUEUE_S 23 450 #define TX_QUEUE_M 0x7 451 #define TX_QUEUE_V(x) ((x) << TX_QUEUE_S) 452 #define TX_QUEUE_G(x) (((x) >> TX_QUEUE_S) & TX_QUEUE_M) 453 454 #define CCTRL_ECN_S 27 455 #define CCTRL_ECN_V(x) ((x) << CCTRL_ECN_S) 456 #define CCTRL_ECN_F CCTRL_ECN_V(1U) 457 458 #define TSTAMPS_EN_S 29 459 #define TSTAMPS_EN_V(x) ((x) << TSTAMPS_EN_S) 460 #define TSTAMPS_EN_F TSTAMPS_EN_V(1U) 461 462 #define SACK_EN_S 30 463 #define SACK_EN_V(x) ((x) << SACK_EN_S) 464 #define SACK_EN_F SACK_EN_V(1U) 465 466 struct cpl_t5_pass_accept_rpl { 467 WR_HDR; 468 union opcode_tid ot; 469 __be32 opt2; 470 __be64 opt0; 471 __be32 iss; 472 __be32 rsvd; 473 }; 474 475 struct cpl_act_open_req { 476 WR_HDR; 477 union opcode_tid ot; 478 __be16 local_port; 479 __be16 peer_port; 480 __be32 local_ip; 481 __be32 peer_ip; 482 __be64 opt0; 483 __be32 params; 484 __be32 opt2; 485 }; 486 487 #define FILTER_TUPLE_S 24 488 #define FILTER_TUPLE_M 0xFFFFFFFFFF 489 #define FILTER_TUPLE_V(x) ((x) << FILTER_TUPLE_S) 490 #define FILTER_TUPLE_G(x) (((x) >> FILTER_TUPLE_S) & FILTER_TUPLE_M) 491 struct cpl_t5_act_open_req { 492 WR_HDR; 493 union opcode_tid ot; 494 __be16 local_port; 495 __be16 peer_port; 496 __be32 local_ip; 497 __be32 peer_ip; 498 __be64 opt0; 499 __be32 rsvd; 500 __be32 opt2; 501 __be64 params; 502 }; 503 504 struct cpl_t6_act_open_req { 505 WR_HDR; 506 union opcode_tid ot; 507 __be16 local_port; 508 __be16 peer_port; 509 __be32 local_ip; 510 __be32 peer_ip; 511 __be64 opt0; 512 __be32 rsvd; 513 __be32 opt2; 514 __be64 params; 515 __be32 rsvd2; 516 __be32 opt3; 517 }; 518 519 struct cpl_act_open_req6 { 520 WR_HDR; 521 union opcode_tid ot; 522 __be16 local_port; 523 __be16 peer_port; 524 __be64 local_ip_hi; 525 __be64 local_ip_lo; 526 __be64 peer_ip_hi; 527 __be64 peer_ip_lo; 528 __be64 opt0; 529 __be32 params; 530 __be32 opt2; 531 }; 532 533 struct cpl_t5_act_open_req6 { 534 WR_HDR; 535 union opcode_tid ot; 536 __be16 local_port; 537 __be16 peer_port; 538 __be64 local_ip_hi; 539 __be64 local_ip_lo; 540 __be64 peer_ip_hi; 541 __be64 peer_ip_lo; 542 __be64 opt0; 543 __be32 rsvd; 544 __be32 opt2; 545 __be64 params; 546 }; 547 548 struct cpl_t6_act_open_req6 { 549 WR_HDR; 550 union opcode_tid ot; 551 __be16 local_port; 552 __be16 peer_port; 553 __be64 local_ip_hi; 554 __be64 local_ip_lo; 555 __be64 peer_ip_hi; 556 __be64 peer_ip_lo; 557 __be64 opt0; 558 __be32 rsvd; 559 __be32 opt2; 560 __be64 params; 561 __be32 rsvd2; 562 __be32 opt3; 563 }; 564 565 struct cpl_act_open_rpl { 566 union opcode_tid ot; 567 __be32 atid_status; 568 }; 569 570 /* cpl_act_open_rpl.atid_status fields */ 571 #define AOPEN_STATUS_S 0 572 #define AOPEN_STATUS_M 0xFF 573 #define AOPEN_STATUS_G(x) (((x) >> AOPEN_STATUS_S) & AOPEN_STATUS_M) 574 575 #define AOPEN_ATID_S 8 576 #define AOPEN_ATID_M 0xFFFFFF 577 #define AOPEN_ATID_G(x) (((x) >> AOPEN_ATID_S) & AOPEN_ATID_M) 578 579 struct cpl_pass_establish { 580 union opcode_tid ot; 581 __be32 rsvd; 582 __be32 tos_stid; 583 __be16 mac_idx; 584 __be16 tcp_opt; 585 __be32 snd_isn; 586 __be32 rcv_isn; 587 }; 588 589 /* cpl_pass_establish.tos_stid fields */ 590 #define PASS_OPEN_TID_S 0 591 #define PASS_OPEN_TID_M 0xFFFFFF 592 #define PASS_OPEN_TID_V(x) ((x) << PASS_OPEN_TID_S) 593 #define PASS_OPEN_TID_G(x) (((x) >> PASS_OPEN_TID_S) & PASS_OPEN_TID_M) 594 595 #define PASS_OPEN_TOS_S 24 596 #define PASS_OPEN_TOS_M 0xFF 597 #define PASS_OPEN_TOS_V(x) ((x) << PASS_OPEN_TOS_S) 598 #define PASS_OPEN_TOS_G(x) (((x) >> PASS_OPEN_TOS_S) & PASS_OPEN_TOS_M) 599 600 /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */ 601 #define TCPOPT_WSCALE_OK_S 5 602 #define TCPOPT_WSCALE_OK_M 0x1 603 #define TCPOPT_WSCALE_OK_G(x) \ 604 (((x) >> TCPOPT_WSCALE_OK_S) & TCPOPT_WSCALE_OK_M) 605 606 #define TCPOPT_SACK_S 6 607 #define TCPOPT_SACK_M 0x1 608 #define TCPOPT_SACK_G(x) (((x) >> TCPOPT_SACK_S) & TCPOPT_SACK_M) 609 610 #define TCPOPT_TSTAMP_S 7 611 #define TCPOPT_TSTAMP_M 0x1 612 #define TCPOPT_TSTAMP_G(x) (((x) >> TCPOPT_TSTAMP_S) & TCPOPT_TSTAMP_M) 613 614 #define TCPOPT_SND_WSCALE_S 8 615 #define TCPOPT_SND_WSCALE_M 0xF 616 #define TCPOPT_SND_WSCALE_G(x) \ 617 (((x) >> TCPOPT_SND_WSCALE_S) & TCPOPT_SND_WSCALE_M) 618 619 #define TCPOPT_MSS_S 12 620 #define TCPOPT_MSS_M 0xF 621 #define TCPOPT_MSS_G(x) (((x) >> TCPOPT_MSS_S) & TCPOPT_MSS_M) 622 623 #define T6_TCP_HDR_LEN_S 8 624 #define T6_TCP_HDR_LEN_V(x) ((x) << T6_TCP_HDR_LEN_S) 625 #define T6_TCP_HDR_LEN_G(x) (((x) >> T6_TCP_HDR_LEN_S) & TCP_HDR_LEN_M) 626 627 #define T6_IP_HDR_LEN_S 14 628 #define T6_IP_HDR_LEN_V(x) ((x) << T6_IP_HDR_LEN_S) 629 #define T6_IP_HDR_LEN_G(x) (((x) >> T6_IP_HDR_LEN_S) & IP_HDR_LEN_M) 630 631 #define T6_ETH_HDR_LEN_S 24 632 #define T6_ETH_HDR_LEN_M 0xFF 633 #define T6_ETH_HDR_LEN_V(x) ((x) << T6_ETH_HDR_LEN_S) 634 #define T6_ETH_HDR_LEN_G(x) (((x) >> T6_ETH_HDR_LEN_S) & T6_ETH_HDR_LEN_M) 635 636 struct cpl_act_establish { 637 union opcode_tid ot; 638 __be32 rsvd; 639 __be32 tos_atid; 640 __be16 mac_idx; 641 __be16 tcp_opt; 642 __be32 snd_isn; 643 __be32 rcv_isn; 644 }; 645 646 struct cpl_get_tcb { 647 WR_HDR; 648 union opcode_tid ot; 649 __be16 reply_ctrl; 650 __be16 cookie; 651 }; 652 653 /* cpl_get_tcb.reply_ctrl fields */ 654 #define QUEUENO_S 0 655 #define QUEUENO_V(x) ((x) << QUEUENO_S) 656 657 #define REPLY_CHAN_S 14 658 #define REPLY_CHAN_V(x) ((x) << REPLY_CHAN_S) 659 #define REPLY_CHAN_F REPLY_CHAN_V(1U) 660 661 #define NO_REPLY_S 15 662 #define NO_REPLY_V(x) ((x) << NO_REPLY_S) 663 #define NO_REPLY_F NO_REPLY_V(1U) 664 665 struct cpl_set_tcb_field { 666 WR_HDR; 667 union opcode_tid ot; 668 __be16 reply_ctrl; 669 __be16 word_cookie; 670 __be64 mask; 671 __be64 val; 672 }; 673 674 /* cpl_set_tcb_field.word_cookie fields */ 675 #define TCB_WORD_S 0 676 #define TCB_WORD(x) ((x) << TCB_WORD_S) 677 678 #define TCB_COOKIE_S 5 679 #define TCB_COOKIE_M 0x7 680 #define TCB_COOKIE_V(x) ((x) << TCB_COOKIE_S) 681 #define TCB_COOKIE_G(x) (((x) >> TCB_COOKIE_S) & TCB_COOKIE_M) 682 683 struct cpl_set_tcb_rpl { 684 union opcode_tid ot; 685 __be16 rsvd; 686 u8 cookie; 687 u8 status; 688 __be64 oldval; 689 }; 690 691 struct cpl_close_con_req { 692 WR_HDR; 693 union opcode_tid ot; 694 __be32 rsvd; 695 }; 696 697 struct cpl_close_con_rpl { 698 union opcode_tid ot; 699 u8 rsvd[3]; 700 u8 status; 701 __be32 snd_nxt; 702 __be32 rcv_nxt; 703 }; 704 705 struct cpl_close_listsvr_req { 706 WR_HDR; 707 union opcode_tid ot; 708 __be16 reply_ctrl; 709 __be16 rsvd; 710 }; 711 712 /* additional cpl_close_listsvr_req.reply_ctrl field */ 713 #define LISTSVR_IPV6_S 14 714 #define LISTSVR_IPV6_V(x) ((x) << LISTSVR_IPV6_S) 715 #define LISTSVR_IPV6_F LISTSVR_IPV6_V(1U) 716 717 struct cpl_close_listsvr_rpl { 718 union opcode_tid ot; 719 u8 rsvd[3]; 720 u8 status; 721 }; 722 723 struct cpl_abort_req_rss { 724 union opcode_tid ot; 725 u8 rsvd[3]; 726 u8 status; 727 }; 728 729 struct cpl_abort_req { 730 WR_HDR; 731 union opcode_tid ot; 732 __be32 rsvd0; 733 u8 rsvd1; 734 u8 cmd; 735 u8 rsvd2[6]; 736 }; 737 738 struct cpl_abort_rpl_rss { 739 union opcode_tid ot; 740 u8 rsvd[3]; 741 u8 status; 742 }; 743 744 struct cpl_abort_rpl { 745 WR_HDR; 746 union opcode_tid ot; 747 __be32 rsvd0; 748 u8 rsvd1; 749 u8 cmd; 750 u8 rsvd2[6]; 751 }; 752 753 struct cpl_peer_close { 754 union opcode_tid ot; 755 __be32 rcv_nxt; 756 }; 757 758 struct cpl_tid_release { 759 WR_HDR; 760 union opcode_tid ot; 761 __be32 rsvd; 762 }; 763 764 struct cpl_tx_pkt_core { 765 __be32 ctrl0; 766 __be16 pack; 767 __be16 len; 768 __be64 ctrl1; 769 }; 770 771 struct cpl_tx_pkt { 772 WR_HDR; 773 struct cpl_tx_pkt_core c; 774 }; 775 776 #define cpl_tx_pkt_xt cpl_tx_pkt 777 778 /* cpl_tx_pkt_core.ctrl0 fields */ 779 #define TXPKT_VF_S 0 780 #define TXPKT_VF_V(x) ((x) << TXPKT_VF_S) 781 782 #define TXPKT_PF_S 8 783 #define TXPKT_PF_V(x) ((x) << TXPKT_PF_S) 784 785 #define TXPKT_VF_VLD_S 11 786 #define TXPKT_VF_VLD_V(x) ((x) << TXPKT_VF_VLD_S) 787 #define TXPKT_VF_VLD_F TXPKT_VF_VLD_V(1U) 788 789 #define TXPKT_OVLAN_IDX_S 12 790 #define TXPKT_OVLAN_IDX_V(x) ((x) << TXPKT_OVLAN_IDX_S) 791 792 #define TXPKT_T5_OVLAN_IDX_S 12 793 #define TXPKT_T5_OVLAN_IDX_V(x) ((x) << TXPKT_T5_OVLAN_IDX_S) 794 795 #define TXPKT_INTF_S 16 796 #define TXPKT_INTF_V(x) ((x) << TXPKT_INTF_S) 797 798 #define TXPKT_INS_OVLAN_S 21 799 #define TXPKT_INS_OVLAN_V(x) ((x) << TXPKT_INS_OVLAN_S) 800 #define TXPKT_INS_OVLAN_F TXPKT_INS_OVLAN_V(1U) 801 802 #define TXPKT_OPCODE_S 24 803 #define TXPKT_OPCODE_V(x) ((x) << TXPKT_OPCODE_S) 804 805 /* cpl_tx_pkt_core.ctrl1 fields */ 806 #define TXPKT_CSUM_END_S 12 807 #define TXPKT_CSUM_END_V(x) ((x) << TXPKT_CSUM_END_S) 808 809 #define TXPKT_CSUM_START_S 20 810 #define TXPKT_CSUM_START_V(x) ((x) << TXPKT_CSUM_START_S) 811 812 #define TXPKT_IPHDR_LEN_S 20 813 #define TXPKT_IPHDR_LEN_V(x) ((__u64)(x) << TXPKT_IPHDR_LEN_S) 814 815 #define TXPKT_CSUM_LOC_S 30 816 #define TXPKT_CSUM_LOC_V(x) ((__u64)(x) << TXPKT_CSUM_LOC_S) 817 818 #define TXPKT_ETHHDR_LEN_S 34 819 #define TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << TXPKT_ETHHDR_LEN_S) 820 821 #define T6_TXPKT_ETHHDR_LEN_S 32 822 #define T6_TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << T6_TXPKT_ETHHDR_LEN_S) 823 824 #define TXPKT_CSUM_TYPE_S 40 825 #define TXPKT_CSUM_TYPE_V(x) ((__u64)(x) << TXPKT_CSUM_TYPE_S) 826 827 #define TXPKT_VLAN_S 44 828 #define TXPKT_VLAN_V(x) ((__u64)(x) << TXPKT_VLAN_S) 829 830 #define TXPKT_VLAN_VLD_S 60 831 #define TXPKT_VLAN_VLD_V(x) ((__u64)(x) << TXPKT_VLAN_VLD_S) 832 #define TXPKT_VLAN_VLD_F TXPKT_VLAN_VLD_V(1ULL) 833 834 #define TXPKT_IPCSUM_DIS_S 62 835 #define TXPKT_IPCSUM_DIS_V(x) ((__u64)(x) << TXPKT_IPCSUM_DIS_S) 836 #define TXPKT_IPCSUM_DIS_F TXPKT_IPCSUM_DIS_V(1ULL) 837 838 #define TXPKT_L4CSUM_DIS_S 63 839 #define TXPKT_L4CSUM_DIS_V(x) ((__u64)(x) << TXPKT_L4CSUM_DIS_S) 840 #define TXPKT_L4CSUM_DIS_F TXPKT_L4CSUM_DIS_V(1ULL) 841 842 struct cpl_tx_pkt_lso_core { 843 __be32 lso_ctrl; 844 __be16 ipid_ofst; 845 __be16 mss; 846 __be32 seqno_offset; 847 __be32 len; 848 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 849 }; 850 851 /* cpl_tx_pkt_lso_core.lso_ctrl fields */ 852 #define LSO_TCPHDR_LEN_S 0 853 #define LSO_TCPHDR_LEN_V(x) ((x) << LSO_TCPHDR_LEN_S) 854 855 #define LSO_IPHDR_LEN_S 4 856 #define LSO_IPHDR_LEN_V(x) ((x) << LSO_IPHDR_LEN_S) 857 858 #define LSO_ETHHDR_LEN_S 16 859 #define LSO_ETHHDR_LEN_V(x) ((x) << LSO_ETHHDR_LEN_S) 860 861 #define LSO_IPV6_S 20 862 #define LSO_IPV6_V(x) ((x) << LSO_IPV6_S) 863 #define LSO_IPV6_F LSO_IPV6_V(1U) 864 865 #define LSO_LAST_SLICE_S 22 866 #define LSO_LAST_SLICE_V(x) ((x) << LSO_LAST_SLICE_S) 867 #define LSO_LAST_SLICE_F LSO_LAST_SLICE_V(1U) 868 869 #define LSO_FIRST_SLICE_S 23 870 #define LSO_FIRST_SLICE_V(x) ((x) << LSO_FIRST_SLICE_S) 871 #define LSO_FIRST_SLICE_F LSO_FIRST_SLICE_V(1U) 872 873 #define LSO_OPCODE_S 24 874 #define LSO_OPCODE_V(x) ((x) << LSO_OPCODE_S) 875 876 #define LSO_T5_XFER_SIZE_S 0 877 #define LSO_T5_XFER_SIZE_V(x) ((x) << LSO_T5_XFER_SIZE_S) 878 879 struct cpl_tx_pkt_lso { 880 WR_HDR; 881 struct cpl_tx_pkt_lso_core c; 882 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 883 }; 884 885 struct cpl_iscsi_hdr { 886 union opcode_tid ot; 887 __be16 pdu_len_ddp; 888 __be16 len; 889 __be32 seq; 890 __be16 urg; 891 u8 rsvd; 892 u8 status; 893 }; 894 895 /* cpl_iscsi_hdr.pdu_len_ddp fields */ 896 #define ISCSI_PDU_LEN_S 0 897 #define ISCSI_PDU_LEN_M 0x7FFF 898 #define ISCSI_PDU_LEN_V(x) ((x) << ISCSI_PDU_LEN_S) 899 #define ISCSI_PDU_LEN_G(x) (((x) >> ISCSI_PDU_LEN_S) & ISCSI_PDU_LEN_M) 900 901 #define ISCSI_DDP_S 15 902 #define ISCSI_DDP_V(x) ((x) << ISCSI_DDP_S) 903 #define ISCSI_DDP_F ISCSI_DDP_V(1U) 904 905 struct cpl_rx_data_ddp { 906 union opcode_tid ot; 907 __be16 urg; 908 __be16 len; 909 __be32 seq; 910 union { 911 __be32 nxt_seq; 912 __be32 ddp_report; 913 }; 914 __be32 ulp_crc; 915 __be32 ddpvld; 916 }; 917 918 #define cpl_rx_iscsi_ddp cpl_rx_data_ddp 919 920 struct cpl_iscsi_data { 921 union opcode_tid ot; 922 __u8 rsvd0[2]; 923 __be16 len; 924 __be32 seq; 925 __be16 urg; 926 __u8 rsvd1; 927 __u8 status; 928 }; 929 930 struct cpl_tx_data_iso { 931 __be32 op_to_scsi; 932 __u8 reserved1; 933 __u8 ahs_len; 934 __be16 mpdu; 935 __be32 burst_size; 936 __be32 len; 937 __be32 reserved2_seglen_offset; 938 __be32 datasn_offset; 939 __be32 buffer_offset; 940 __be32 reserved3; 941 942 /* encapsulated CPL_TX_DATA follows here */ 943 }; 944 945 /* cpl_tx_data_iso.op_to_scsi fields */ 946 #define CPL_TX_DATA_ISO_OP_S 24 947 #define CPL_TX_DATA_ISO_OP_M 0xff 948 #define CPL_TX_DATA_ISO_OP_V(x) ((x) << CPL_TX_DATA_ISO_OP_S) 949 #define CPL_TX_DATA_ISO_OP_G(x) \ 950 (((x) >> CPL_TX_DATA_ISO_OP_S) & CPL_TX_DATA_ISO_OP_M) 951 952 #define CPL_TX_DATA_ISO_FIRST_S 23 953 #define CPL_TX_DATA_ISO_FIRST_M 0x1 954 #define CPL_TX_DATA_ISO_FIRST_V(x) ((x) << CPL_TX_DATA_ISO_FIRST_S) 955 #define CPL_TX_DATA_ISO_FIRST_G(x) \ 956 (((x) >> CPL_TX_DATA_ISO_FIRST_S) & CPL_TX_DATA_ISO_FIRST_M) 957 #define CPL_TX_DATA_ISO_FIRST_F CPL_TX_DATA_ISO_FIRST_V(1U) 958 959 #define CPL_TX_DATA_ISO_LAST_S 22 960 #define CPL_TX_DATA_ISO_LAST_M 0x1 961 #define CPL_TX_DATA_ISO_LAST_V(x) ((x) << CPL_TX_DATA_ISO_LAST_S) 962 #define CPL_TX_DATA_ISO_LAST_G(x) \ 963 (((x) >> CPL_TX_DATA_ISO_LAST_S) & CPL_TX_DATA_ISO_LAST_M) 964 #define CPL_TX_DATA_ISO_LAST_F CPL_TX_DATA_ISO_LAST_V(1U) 965 966 #define CPL_TX_DATA_ISO_CPLHDRLEN_S 21 967 #define CPL_TX_DATA_ISO_CPLHDRLEN_M 0x1 968 #define CPL_TX_DATA_ISO_CPLHDRLEN_V(x) ((x) << CPL_TX_DATA_ISO_CPLHDRLEN_S) 969 #define CPL_TX_DATA_ISO_CPLHDRLEN_G(x) \ 970 (((x) >> CPL_TX_DATA_ISO_CPLHDRLEN_S) & CPL_TX_DATA_ISO_CPLHDRLEN_M) 971 #define CPL_TX_DATA_ISO_CPLHDRLEN_F CPL_TX_DATA_ISO_CPLHDRLEN_V(1U) 972 973 #define CPL_TX_DATA_ISO_HDRCRC_S 20 974 #define CPL_TX_DATA_ISO_HDRCRC_M 0x1 975 #define CPL_TX_DATA_ISO_HDRCRC_V(x) ((x) << CPL_TX_DATA_ISO_HDRCRC_S) 976 #define CPL_TX_DATA_ISO_HDRCRC_G(x) \ 977 (((x) >> CPL_TX_DATA_ISO_HDRCRC_S) & CPL_TX_DATA_ISO_HDRCRC_M) 978 #define CPL_TX_DATA_ISO_HDRCRC_F CPL_TX_DATA_ISO_HDRCRC_V(1U) 979 980 #define CPL_TX_DATA_ISO_PLDCRC_S 19 981 #define CPL_TX_DATA_ISO_PLDCRC_M 0x1 982 #define CPL_TX_DATA_ISO_PLDCRC_V(x) ((x) << CPL_TX_DATA_ISO_PLDCRC_S) 983 #define CPL_TX_DATA_ISO_PLDCRC_G(x) \ 984 (((x) >> CPL_TX_DATA_ISO_PLDCRC_S) & CPL_TX_DATA_ISO_PLDCRC_M) 985 #define CPL_TX_DATA_ISO_PLDCRC_F CPL_TX_DATA_ISO_PLDCRC_V(1U) 986 987 #define CPL_TX_DATA_ISO_IMMEDIATE_S 18 988 #define CPL_TX_DATA_ISO_IMMEDIATE_M 0x1 989 #define CPL_TX_DATA_ISO_IMMEDIATE_V(x) ((x) << CPL_TX_DATA_ISO_IMMEDIATE_S) 990 #define CPL_TX_DATA_ISO_IMMEDIATE_G(x) \ 991 (((x) >> CPL_TX_DATA_ISO_IMMEDIATE_S) & CPL_TX_DATA_ISO_IMMEDIATE_M) 992 #define CPL_TX_DATA_ISO_IMMEDIATE_F CPL_TX_DATA_ISO_IMMEDIATE_V(1U) 993 994 #define CPL_TX_DATA_ISO_SCSI_S 16 995 #define CPL_TX_DATA_ISO_SCSI_M 0x3 996 #define CPL_TX_DATA_ISO_SCSI_V(x) ((x) << CPL_TX_DATA_ISO_SCSI_S) 997 #define CPL_TX_DATA_ISO_SCSI_G(x) \ 998 (((x) >> CPL_TX_DATA_ISO_SCSI_S) & CPL_TX_DATA_ISO_SCSI_M) 999 1000 /* cpl_tx_data_iso.reserved2_seglen_offset fields */ 1001 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_S 0 1002 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_M 0xffffff 1003 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_V(x) \ 1004 ((x) << CPL_TX_DATA_ISO_SEGLEN_OFFSET_S) 1005 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_G(x) \ 1006 (((x) >> CPL_TX_DATA_ISO_SEGLEN_OFFSET_S) & \ 1007 CPL_TX_DATA_ISO_SEGLEN_OFFSET_M) 1008 1009 struct cpl_rx_data { 1010 union opcode_tid ot; 1011 __be16 rsvd; 1012 __be16 len; 1013 __be32 seq; 1014 __be16 urg; 1015 #if defined(__LITTLE_ENDIAN_BITFIELD) 1016 u8 dack_mode:2; 1017 u8 psh:1; 1018 u8 heartbeat:1; 1019 u8 ddp_off:1; 1020 u8 :3; 1021 #else 1022 u8 :3; 1023 u8 ddp_off:1; 1024 u8 heartbeat:1; 1025 u8 psh:1; 1026 u8 dack_mode:2; 1027 #endif 1028 u8 status; 1029 }; 1030 1031 struct cpl_rx_data_ack { 1032 WR_HDR; 1033 union opcode_tid ot; 1034 __be32 credit_dack; 1035 }; 1036 1037 /* cpl_rx_data_ack.ack_seq fields */ 1038 #define RX_CREDITS_S 0 1039 #define RX_CREDITS_V(x) ((x) << RX_CREDITS_S) 1040 1041 #define RX_FORCE_ACK_S 28 1042 #define RX_FORCE_ACK_V(x) ((x) << RX_FORCE_ACK_S) 1043 #define RX_FORCE_ACK_F RX_FORCE_ACK_V(1U) 1044 1045 #define RX_DACK_MODE_S 29 1046 #define RX_DACK_MODE_M 0x3 1047 #define RX_DACK_MODE_V(x) ((x) << RX_DACK_MODE_S) 1048 #define RX_DACK_MODE_G(x) (((x) >> RX_DACK_MODE_S) & RX_DACK_MODE_M) 1049 1050 #define RX_DACK_CHANGE_S 31 1051 #define RX_DACK_CHANGE_V(x) ((x) << RX_DACK_CHANGE_S) 1052 #define RX_DACK_CHANGE_F RX_DACK_CHANGE_V(1U) 1053 1054 struct cpl_rx_pkt { 1055 struct rss_header rsshdr; 1056 u8 opcode; 1057 #if defined(__LITTLE_ENDIAN_BITFIELD) 1058 u8 iff:4; 1059 u8 csum_calc:1; 1060 u8 ipmi_pkt:1; 1061 u8 vlan_ex:1; 1062 u8 ip_frag:1; 1063 #else 1064 u8 ip_frag:1; 1065 u8 vlan_ex:1; 1066 u8 ipmi_pkt:1; 1067 u8 csum_calc:1; 1068 u8 iff:4; 1069 #endif 1070 __be16 csum; 1071 __be16 vlan; 1072 __be16 len; 1073 __be32 l2info; 1074 __be16 hdr_len; 1075 __be16 err_vec; 1076 }; 1077 1078 #define RX_T6_ETHHDR_LEN_M 0xFF 1079 #define RX_T6_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_T6_ETHHDR_LEN_M) 1080 1081 #define RXF_PSH_S 20 1082 #define RXF_PSH_V(x) ((x) << RXF_PSH_S) 1083 #define RXF_PSH_F RXF_PSH_V(1U) 1084 1085 #define RXF_SYN_S 21 1086 #define RXF_SYN_V(x) ((x) << RXF_SYN_S) 1087 #define RXF_SYN_F RXF_SYN_V(1U) 1088 1089 #define RXF_UDP_S 22 1090 #define RXF_UDP_V(x) ((x) << RXF_UDP_S) 1091 #define RXF_UDP_F RXF_UDP_V(1U) 1092 1093 #define RXF_TCP_S 23 1094 #define RXF_TCP_V(x) ((x) << RXF_TCP_S) 1095 #define RXF_TCP_F RXF_TCP_V(1U) 1096 1097 #define RXF_IP_S 24 1098 #define RXF_IP_V(x) ((x) << RXF_IP_S) 1099 #define RXF_IP_F RXF_IP_V(1U) 1100 1101 #define RXF_IP6_S 25 1102 #define RXF_IP6_V(x) ((x) << RXF_IP6_S) 1103 #define RXF_IP6_F RXF_IP6_V(1U) 1104 1105 #define RXF_SYN_COOKIE_S 26 1106 #define RXF_SYN_COOKIE_V(x) ((x) << RXF_SYN_COOKIE_S) 1107 #define RXF_SYN_COOKIE_F RXF_SYN_COOKIE_V(1U) 1108 1109 #define RXF_FCOE_S 26 1110 #define RXF_FCOE_V(x) ((x) << RXF_FCOE_S) 1111 #define RXF_FCOE_F RXF_FCOE_V(1U) 1112 1113 #define RXF_LRO_S 27 1114 #define RXF_LRO_V(x) ((x) << RXF_LRO_S) 1115 #define RXF_LRO_F RXF_LRO_V(1U) 1116 1117 /* rx_pkt.l2info fields */ 1118 #define RX_ETHHDR_LEN_S 0 1119 #define RX_ETHHDR_LEN_M 0x1F 1120 #define RX_ETHHDR_LEN_V(x) ((x) << RX_ETHHDR_LEN_S) 1121 #define RX_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_ETHHDR_LEN_M) 1122 1123 #define RX_T5_ETHHDR_LEN_S 0 1124 #define RX_T5_ETHHDR_LEN_M 0x3F 1125 #define RX_T5_ETHHDR_LEN_V(x) ((x) << RX_T5_ETHHDR_LEN_S) 1126 #define RX_T5_ETHHDR_LEN_G(x) (((x) >> RX_T5_ETHHDR_LEN_S) & RX_T5_ETHHDR_LEN_M) 1127 1128 #define RX_MACIDX_S 8 1129 #define RX_MACIDX_M 0x1FF 1130 #define RX_MACIDX_V(x) ((x) << RX_MACIDX_S) 1131 #define RX_MACIDX_G(x) (((x) >> RX_MACIDX_S) & RX_MACIDX_M) 1132 1133 #define RXF_SYN_S 21 1134 #define RXF_SYN_V(x) ((x) << RXF_SYN_S) 1135 #define RXF_SYN_F RXF_SYN_V(1U) 1136 1137 #define RX_CHAN_S 28 1138 #define RX_CHAN_M 0xF 1139 #define RX_CHAN_V(x) ((x) << RX_CHAN_S) 1140 #define RX_CHAN_G(x) (((x) >> RX_CHAN_S) & RX_CHAN_M) 1141 1142 /* rx_pkt.hdr_len fields */ 1143 #define RX_TCPHDR_LEN_S 0 1144 #define RX_TCPHDR_LEN_M 0x3F 1145 #define RX_TCPHDR_LEN_V(x) ((x) << RX_TCPHDR_LEN_S) 1146 #define RX_TCPHDR_LEN_G(x) (((x) >> RX_TCPHDR_LEN_S) & RX_TCPHDR_LEN_M) 1147 1148 #define RX_IPHDR_LEN_S 6 1149 #define RX_IPHDR_LEN_M 0x3FF 1150 #define RX_IPHDR_LEN_V(x) ((x) << RX_IPHDR_LEN_S) 1151 #define RX_IPHDR_LEN_G(x) (((x) >> RX_IPHDR_LEN_S) & RX_IPHDR_LEN_M) 1152 1153 /* rx_pkt.err_vec fields */ 1154 #define RXERR_CSUM_S 13 1155 #define RXERR_CSUM_V(x) ((x) << RXERR_CSUM_S) 1156 #define RXERR_CSUM_F RXERR_CSUM_V(1U) 1157 1158 struct cpl_trace_pkt { 1159 u8 opcode; 1160 u8 intf; 1161 #if defined(__LITTLE_ENDIAN_BITFIELD) 1162 u8 runt:4; 1163 u8 filter_hit:4; 1164 u8 :6; 1165 u8 err:1; 1166 u8 trunc:1; 1167 #else 1168 u8 filter_hit:4; 1169 u8 runt:4; 1170 u8 trunc:1; 1171 u8 err:1; 1172 u8 :6; 1173 #endif 1174 __be16 rsvd; 1175 __be16 len; 1176 __be64 tstamp; 1177 }; 1178 1179 struct cpl_t5_trace_pkt { 1180 __u8 opcode; 1181 __u8 intf; 1182 #if defined(__LITTLE_ENDIAN_BITFIELD) 1183 __u8 runt:4; 1184 __u8 filter_hit:4; 1185 __u8:6; 1186 __u8 err:1; 1187 __u8 trunc:1; 1188 #else 1189 __u8 filter_hit:4; 1190 __u8 runt:4; 1191 __u8 trunc:1; 1192 __u8 err:1; 1193 __u8:6; 1194 #endif 1195 __be16 rsvd; 1196 __be16 len; 1197 __be64 tstamp; 1198 __be64 rsvd1; 1199 }; 1200 1201 struct cpl_l2t_write_req { 1202 WR_HDR; 1203 union opcode_tid ot; 1204 __be16 params; 1205 __be16 l2t_idx; 1206 __be16 vlan; 1207 u8 dst_mac[6]; 1208 }; 1209 1210 /* cpl_l2t_write_req.params fields */ 1211 #define L2T_W_INFO_S 2 1212 #define L2T_W_INFO_V(x) ((x) << L2T_W_INFO_S) 1213 1214 #define L2T_W_PORT_S 8 1215 #define L2T_W_PORT_V(x) ((x) << L2T_W_PORT_S) 1216 1217 #define L2T_W_NOREPLY_S 15 1218 #define L2T_W_NOREPLY_V(x) ((x) << L2T_W_NOREPLY_S) 1219 #define L2T_W_NOREPLY_F L2T_W_NOREPLY_V(1U) 1220 1221 #define CPL_L2T_VLAN_NONE 0xfff 1222 1223 struct cpl_l2t_write_rpl { 1224 union opcode_tid ot; 1225 u8 status; 1226 u8 rsvd[3]; 1227 }; 1228 1229 struct cpl_rdma_terminate { 1230 union opcode_tid ot; 1231 __be16 rsvd; 1232 __be16 len; 1233 }; 1234 1235 struct cpl_sge_egr_update { 1236 __be32 opcode_qid; 1237 __be16 cidx; 1238 __be16 pidx; 1239 }; 1240 1241 /* cpl_sge_egr_update.ot fields */ 1242 #define EGR_QID_S 0 1243 #define EGR_QID_M 0x1FFFF 1244 #define EGR_QID_G(x) (((x) >> EGR_QID_S) & EGR_QID_M) 1245 1246 /* cpl_fw*.type values */ 1247 enum { 1248 FW_TYPE_CMD_RPL = 0, 1249 FW_TYPE_WR_RPL = 1, 1250 FW_TYPE_CQE = 2, 1251 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3, 1252 FW_TYPE_RSSCPL = 4, 1253 }; 1254 1255 struct cpl_fw4_pld { 1256 u8 opcode; 1257 u8 rsvd0[3]; 1258 u8 type; 1259 u8 rsvd1; 1260 __be16 len; 1261 __be64 data; 1262 __be64 rsvd2; 1263 }; 1264 1265 struct cpl_fw6_pld { 1266 u8 opcode; 1267 u8 rsvd[5]; 1268 __be16 len; 1269 __be64 data[4]; 1270 }; 1271 1272 struct cpl_fw4_msg { 1273 u8 opcode; 1274 u8 type; 1275 __be16 rsvd0; 1276 __be32 rsvd1; 1277 __be64 data[2]; 1278 }; 1279 1280 struct cpl_fw4_ack { 1281 union opcode_tid ot; 1282 u8 credits; 1283 u8 rsvd0[2]; 1284 u8 seq_vld; 1285 __be32 snd_nxt; 1286 __be32 snd_una; 1287 __be64 rsvd1; 1288 }; 1289 1290 enum { 1291 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1, /* seqn valid */ 1292 CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */ 1293 CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */ 1294 }; 1295 1296 struct cpl_fw6_msg { 1297 u8 opcode; 1298 u8 type; 1299 __be16 rsvd0; 1300 __be32 rsvd1; 1301 __be64 data[4]; 1302 }; 1303 1304 /* cpl_fw6_msg.type values */ 1305 enum { 1306 FW6_TYPE_CMD_RPL = 0, 1307 FW6_TYPE_WR_RPL = 1, 1308 FW6_TYPE_CQE = 2, 1309 FW6_TYPE_OFLD_CONNECTION_WR_RPL = 3, 1310 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL, 1311 }; 1312 1313 struct cpl_fw6_msg_ofld_connection_wr_rpl { 1314 __u64 cookie; 1315 __be32 tid; /* or atid in case of active failure */ 1316 __u8 t_state; 1317 __u8 retval; 1318 __u8 rsvd[2]; 1319 }; 1320 1321 struct cpl_tx_data { 1322 union opcode_tid ot; 1323 __be32 len; 1324 __be32 rsvd; 1325 __be32 flags; 1326 }; 1327 1328 /* cpl_tx_data.flags field */ 1329 #define TX_FORCE_S 13 1330 #define TX_FORCE_V(x) ((x) << TX_FORCE_S) 1331 1332 enum { 1333 ULP_TX_MEM_READ = 2, 1334 ULP_TX_MEM_WRITE = 3, 1335 ULP_TX_PKT = 4 1336 }; 1337 1338 enum { 1339 ULP_TX_SC_NOOP = 0x80, 1340 ULP_TX_SC_IMM = 0x81, 1341 ULP_TX_SC_DSGL = 0x82, 1342 ULP_TX_SC_ISGL = 0x83 1343 }; 1344 1345 #define ULPTX_CMD_S 24 1346 #define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S) 1347 1348 struct ulptx_sge_pair { 1349 __be32 len[2]; 1350 __be64 addr[2]; 1351 }; 1352 1353 struct ulptx_sgl { 1354 __be32 cmd_nsge; 1355 __be32 len0; 1356 __be64 addr0; 1357 struct ulptx_sge_pair sge[0]; 1358 }; 1359 1360 struct ulptx_idata { 1361 __be32 cmd_more; 1362 __be32 len; 1363 }; 1364 1365 #define ULPTX_NSGE_S 0 1366 #define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S) 1367 1368 #define ULPTX_MORE_S 23 1369 #define ULPTX_MORE_V(x) ((x) << ULPTX_MORE_S) 1370 #define ULPTX_MORE_F ULPTX_MORE_V(1U) 1371 1372 struct ulp_mem_io { 1373 WR_HDR; 1374 __be32 cmd; 1375 __be32 len16; /* command length */ 1376 __be32 dlen; /* data length in 32-byte units */ 1377 __be32 lock_addr; 1378 }; 1379 1380 #define ULP_MEMIO_LOCK_S 31 1381 #define ULP_MEMIO_LOCK_V(x) ((x) << ULP_MEMIO_LOCK_S) 1382 #define ULP_MEMIO_LOCK_F ULP_MEMIO_LOCK_V(1U) 1383 1384 /* additional ulp_mem_io.cmd fields */ 1385 #define ULP_MEMIO_ORDER_S 23 1386 #define ULP_MEMIO_ORDER_V(x) ((x) << ULP_MEMIO_ORDER_S) 1387 #define ULP_MEMIO_ORDER_F ULP_MEMIO_ORDER_V(1U) 1388 1389 #define T5_ULP_MEMIO_IMM_S 23 1390 #define T5_ULP_MEMIO_IMM_V(x) ((x) << T5_ULP_MEMIO_IMM_S) 1391 #define T5_ULP_MEMIO_IMM_F T5_ULP_MEMIO_IMM_V(1U) 1392 1393 #define T5_ULP_MEMIO_ORDER_S 22 1394 #define T5_ULP_MEMIO_ORDER_V(x) ((x) << T5_ULP_MEMIO_ORDER_S) 1395 #define T5_ULP_MEMIO_ORDER_F T5_ULP_MEMIO_ORDER_V(1U) 1396 1397 #define T5_ULP_MEMIO_FID_S 4 1398 #define T5_ULP_MEMIO_FID_M 0x7ff 1399 #define T5_ULP_MEMIO_FID_V(x) ((x) << T5_ULP_MEMIO_FID_S) 1400 1401 /* ulp_mem_io.lock_addr fields */ 1402 #define ULP_MEMIO_ADDR_S 0 1403 #define ULP_MEMIO_ADDR_V(x) ((x) << ULP_MEMIO_ADDR_S) 1404 1405 /* ulp_mem_io.dlen fields */ 1406 #define ULP_MEMIO_DATA_LEN_S 0 1407 #define ULP_MEMIO_DATA_LEN_V(x) ((x) << ULP_MEMIO_DATA_LEN_S) 1408 1409 #endif /* __T4_MSG_H */ 1410