1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __T4_MSG_H 36 #define __T4_MSG_H 37 38 #include <linux/types.h> 39 40 enum { 41 CPL_PASS_OPEN_REQ = 0x1, 42 CPL_PASS_ACCEPT_RPL = 0x2, 43 CPL_ACT_OPEN_REQ = 0x3, 44 CPL_SET_TCB_FIELD = 0x5, 45 CPL_GET_TCB = 0x6, 46 CPL_CLOSE_CON_REQ = 0x8, 47 CPL_CLOSE_LISTSRV_REQ = 0x9, 48 CPL_ABORT_REQ = 0xA, 49 CPL_ABORT_RPL = 0xB, 50 CPL_RX_DATA_ACK = 0xD, 51 CPL_TX_PKT = 0xE, 52 CPL_L2T_WRITE_REQ = 0x12, 53 CPL_SMT_WRITE_REQ = 0x14, 54 CPL_TID_RELEASE = 0x1A, 55 CPL_TX_DATA_ISO = 0x1F, 56 57 CPL_CLOSE_LISTSRV_RPL = 0x20, 58 CPL_L2T_WRITE_RPL = 0x23, 59 CPL_PASS_OPEN_RPL = 0x24, 60 CPL_ACT_OPEN_RPL = 0x25, 61 CPL_PEER_CLOSE = 0x26, 62 CPL_ABORT_REQ_RSS = 0x2B, 63 CPL_ABORT_RPL_RSS = 0x2D, 64 CPL_SMT_WRITE_RPL = 0x2E, 65 66 CPL_RX_PHYS_ADDR = 0x30, 67 CPL_CLOSE_CON_RPL = 0x32, 68 CPL_ISCSI_HDR = 0x33, 69 CPL_RDMA_CQE = 0x35, 70 CPL_RDMA_CQE_READ_RSP = 0x36, 71 CPL_RDMA_CQE_ERR = 0x37, 72 CPL_RX_DATA = 0x39, 73 CPL_SET_TCB_RPL = 0x3A, 74 CPL_RX_PKT = 0x3B, 75 CPL_RX_DDP_COMPLETE = 0x3F, 76 77 CPL_ACT_ESTABLISH = 0x40, 78 CPL_PASS_ESTABLISH = 0x41, 79 CPL_RX_DATA_DDP = 0x42, 80 CPL_PASS_ACCEPT_REQ = 0x44, 81 CPL_RX_ISCSI_CMP = 0x45, 82 CPL_TRACE_PKT_T5 = 0x48, 83 CPL_RX_ISCSI_DDP = 0x49, 84 85 CPL_RDMA_READ_REQ = 0x60, 86 87 CPL_PASS_OPEN_REQ6 = 0x81, 88 CPL_ACT_OPEN_REQ6 = 0x83, 89 90 CPL_TX_TLS_PDU = 0x88, 91 CPL_TX_SEC_PDU = 0x8A, 92 CPL_TX_TLS_ACK = 0x8B, 93 94 CPL_RDMA_TERMINATE = 0xA2, 95 CPL_RDMA_WRITE = 0xA4, 96 CPL_SGE_EGR_UPDATE = 0xA5, 97 CPL_RX_MPS_PKT = 0xAF, 98 99 CPL_TRACE_PKT = 0xB0, 100 CPL_ISCSI_DATA = 0xB2, 101 102 CPL_FW4_MSG = 0xC0, 103 CPL_FW4_PLD = 0xC1, 104 CPL_FW4_ACK = 0xC3, 105 106 CPL_RX_PHYS_DSGL = 0xD0, 107 108 CPL_FW6_MSG = 0xE0, 109 CPL_FW6_PLD = 0xE1, 110 CPL_TX_TNL_LSO = 0xEC, 111 CPL_TX_PKT_LSO = 0xED, 112 CPL_TX_PKT_XT = 0xEE, 113 114 NUM_CPL_CMDS 115 }; 116 117 enum CPL_error { 118 CPL_ERR_NONE = 0, 119 CPL_ERR_TCAM_PARITY = 1, 120 CPL_ERR_TCAM_MISS = 2, 121 CPL_ERR_TCAM_FULL = 3, 122 CPL_ERR_BAD_LENGTH = 15, 123 CPL_ERR_BAD_ROUTE = 18, 124 CPL_ERR_CONN_RESET = 20, 125 CPL_ERR_CONN_EXIST_SYNRECV = 21, 126 CPL_ERR_CONN_EXIST = 22, 127 CPL_ERR_ARP_MISS = 23, 128 CPL_ERR_BAD_SYN = 24, 129 CPL_ERR_CONN_TIMEDOUT = 30, 130 CPL_ERR_XMIT_TIMEDOUT = 31, 131 CPL_ERR_PERSIST_TIMEDOUT = 32, 132 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 133 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 134 CPL_ERR_RTX_NEG_ADVICE = 35, 135 CPL_ERR_PERSIST_NEG_ADVICE = 36, 136 CPL_ERR_KEEPALV_NEG_ADVICE = 37, 137 CPL_ERR_ABORT_FAILED = 42, 138 CPL_ERR_IWARP_FLM = 50, 139 }; 140 141 enum { 142 CPL_CONN_POLICY_AUTO = 0, 143 CPL_CONN_POLICY_ASK = 1, 144 CPL_CONN_POLICY_FILTER = 2, 145 CPL_CONN_POLICY_DENY = 3 146 }; 147 148 enum { 149 ULP_MODE_NONE = 0, 150 ULP_MODE_ISCSI = 2, 151 ULP_MODE_RDMA = 4, 152 ULP_MODE_TCPDDP = 5, 153 ULP_MODE_FCOE = 6, 154 }; 155 156 enum { 157 ULP_CRC_HEADER = 1 << 0, 158 ULP_CRC_DATA = 1 << 1 159 }; 160 161 enum { 162 CPL_ABORT_SEND_RST = 0, 163 CPL_ABORT_NO_RST, 164 }; 165 166 enum { /* TX_PKT_XT checksum types */ 167 TX_CSUM_TCP = 0, 168 TX_CSUM_UDP = 1, 169 TX_CSUM_CRC16 = 4, 170 TX_CSUM_CRC32 = 5, 171 TX_CSUM_CRC32C = 6, 172 TX_CSUM_FCOE = 7, 173 TX_CSUM_TCPIP = 8, 174 TX_CSUM_UDPIP = 9, 175 TX_CSUM_TCPIP6 = 10, 176 TX_CSUM_UDPIP6 = 11, 177 TX_CSUM_IP = 12, 178 }; 179 180 union opcode_tid { 181 __be32 opcode_tid; 182 u8 opcode; 183 }; 184 185 #define CPL_OPCODE_S 24 186 #define CPL_OPCODE_V(x) ((x) << CPL_OPCODE_S) 187 #define CPL_OPCODE_G(x) (((x) >> CPL_OPCODE_S) & 0xFF) 188 #define TID_G(x) ((x) & 0xFFFFFF) 189 190 /* tid is assumed to be 24-bits */ 191 #define MK_OPCODE_TID(opcode, tid) (CPL_OPCODE_V(opcode) | (tid)) 192 193 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 194 195 /* extract the TID from a CPL command */ 196 #define GET_TID(cmd) (TID_G(be32_to_cpu(OPCODE_TID(cmd)))) 197 198 /* partitioning of TID fields that also carry a queue id */ 199 #define TID_TID_S 0 200 #define TID_TID_M 0x3fff 201 #define TID_TID_G(x) (((x) >> TID_TID_S) & TID_TID_M) 202 203 #define TID_QID_S 14 204 #define TID_QID_M 0x3ff 205 #define TID_QID_V(x) ((x) << TID_QID_S) 206 #define TID_QID_G(x) (((x) >> TID_QID_S) & TID_QID_M) 207 208 struct rss_header { 209 u8 opcode; 210 #if defined(__LITTLE_ENDIAN_BITFIELD) 211 u8 channel:2; 212 u8 filter_hit:1; 213 u8 filter_tid:1; 214 u8 hash_type:2; 215 u8 ipv6:1; 216 u8 send2fw:1; 217 #else 218 u8 send2fw:1; 219 u8 ipv6:1; 220 u8 hash_type:2; 221 u8 filter_tid:1; 222 u8 filter_hit:1; 223 u8 channel:2; 224 #endif 225 __be16 qid; 226 __be32 hash_val; 227 }; 228 229 struct work_request_hdr { 230 __be32 wr_hi; 231 __be32 wr_mid; 232 __be64 wr_lo; 233 }; 234 235 /* wr_hi fields */ 236 #define WR_OP_S 24 237 #define WR_OP_V(x) ((__u64)(x) << WR_OP_S) 238 239 #define WR_HDR struct work_request_hdr wr 240 241 /* option 0 fields */ 242 #define TX_CHAN_S 2 243 #define TX_CHAN_V(x) ((x) << TX_CHAN_S) 244 245 #define ULP_MODE_S 8 246 #define ULP_MODE_V(x) ((x) << ULP_MODE_S) 247 248 #define RCV_BUFSIZ_S 12 249 #define RCV_BUFSIZ_M 0x3FFU 250 #define RCV_BUFSIZ_V(x) ((x) << RCV_BUFSIZ_S) 251 252 #define SMAC_SEL_S 28 253 #define SMAC_SEL_V(x) ((__u64)(x) << SMAC_SEL_S) 254 255 #define L2T_IDX_S 36 256 #define L2T_IDX_V(x) ((__u64)(x) << L2T_IDX_S) 257 258 #define WND_SCALE_S 50 259 #define WND_SCALE_V(x) ((__u64)(x) << WND_SCALE_S) 260 261 #define KEEP_ALIVE_S 54 262 #define KEEP_ALIVE_V(x) ((__u64)(x) << KEEP_ALIVE_S) 263 #define KEEP_ALIVE_F KEEP_ALIVE_V(1ULL) 264 265 #define MSS_IDX_S 60 266 #define MSS_IDX_M 0xF 267 #define MSS_IDX_V(x) ((__u64)(x) << MSS_IDX_S) 268 #define MSS_IDX_G(x) (((x) >> MSS_IDX_S) & MSS_IDX_M) 269 270 /* option 2 fields */ 271 #define RSS_QUEUE_S 0 272 #define RSS_QUEUE_M 0x3FF 273 #define RSS_QUEUE_V(x) ((x) << RSS_QUEUE_S) 274 #define RSS_QUEUE_G(x) (((x) >> RSS_QUEUE_S) & RSS_QUEUE_M) 275 276 #define RSS_QUEUE_VALID_S 10 277 #define RSS_QUEUE_VALID_V(x) ((x) << RSS_QUEUE_VALID_S) 278 #define RSS_QUEUE_VALID_F RSS_QUEUE_VALID_V(1U) 279 280 #define RX_FC_DISABLE_S 20 281 #define RX_FC_DISABLE_V(x) ((x) << RX_FC_DISABLE_S) 282 #define RX_FC_DISABLE_F RX_FC_DISABLE_V(1U) 283 284 #define RX_FC_VALID_S 22 285 #define RX_FC_VALID_V(x) ((x) << RX_FC_VALID_S) 286 #define RX_FC_VALID_F RX_FC_VALID_V(1U) 287 288 #define RX_CHANNEL_S 26 289 #define RX_CHANNEL_V(x) ((x) << RX_CHANNEL_S) 290 #define RX_CHANNEL_F RX_CHANNEL_V(1U) 291 292 #define WND_SCALE_EN_S 28 293 #define WND_SCALE_EN_V(x) ((x) << WND_SCALE_EN_S) 294 #define WND_SCALE_EN_F WND_SCALE_EN_V(1U) 295 296 #define T5_OPT_2_VALID_S 31 297 #define T5_OPT_2_VALID_V(x) ((x) << T5_OPT_2_VALID_S) 298 #define T5_OPT_2_VALID_F T5_OPT_2_VALID_V(1U) 299 300 struct cpl_pass_open_req { 301 WR_HDR; 302 union opcode_tid ot; 303 __be16 local_port; 304 __be16 peer_port; 305 __be32 local_ip; 306 __be32 peer_ip; 307 __be64 opt0; 308 __be64 opt1; 309 }; 310 311 /* option 0 fields */ 312 #define NO_CONG_S 4 313 #define NO_CONG_V(x) ((x) << NO_CONG_S) 314 #define NO_CONG_F NO_CONG_V(1U) 315 316 #define DELACK_S 5 317 #define DELACK_V(x) ((x) << DELACK_S) 318 #define DELACK_F DELACK_V(1U) 319 320 #define NON_OFFLOAD_S 7 321 #define NON_OFFLOAD_V(x) ((x) << NON_OFFLOAD_S) 322 #define NON_OFFLOAD_F NON_OFFLOAD_V(1U) 323 324 #define DSCP_S 22 325 #define DSCP_M 0x3F 326 #define DSCP_V(x) ((x) << DSCP_S) 327 #define DSCP_G(x) (((x) >> DSCP_S) & DSCP_M) 328 329 #define TCAM_BYPASS_S 48 330 #define TCAM_BYPASS_V(x) ((__u64)(x) << TCAM_BYPASS_S) 331 #define TCAM_BYPASS_F TCAM_BYPASS_V(1ULL) 332 333 #define NAGLE_S 49 334 #define NAGLE_V(x) ((__u64)(x) << NAGLE_S) 335 #define NAGLE_F NAGLE_V(1ULL) 336 337 /* option 1 fields */ 338 #define SYN_RSS_ENABLE_S 0 339 #define SYN_RSS_ENABLE_V(x) ((x) << SYN_RSS_ENABLE_S) 340 #define SYN_RSS_ENABLE_F SYN_RSS_ENABLE_V(1U) 341 342 #define SYN_RSS_QUEUE_S 2 343 #define SYN_RSS_QUEUE_V(x) ((x) << SYN_RSS_QUEUE_S) 344 345 #define CONN_POLICY_S 22 346 #define CONN_POLICY_V(x) ((x) << CONN_POLICY_S) 347 348 struct cpl_pass_open_req6 { 349 WR_HDR; 350 union opcode_tid ot; 351 __be16 local_port; 352 __be16 peer_port; 353 __be64 local_ip_hi; 354 __be64 local_ip_lo; 355 __be64 peer_ip_hi; 356 __be64 peer_ip_lo; 357 __be64 opt0; 358 __be64 opt1; 359 }; 360 361 struct cpl_pass_open_rpl { 362 union opcode_tid ot; 363 u8 rsvd[3]; 364 u8 status; 365 }; 366 367 struct tcp_options { 368 __be16 mss; 369 __u8 wsf; 370 #if defined(__LITTLE_ENDIAN_BITFIELD) 371 __u8:4; 372 __u8 unknown:1; 373 __u8:1; 374 __u8 sack:1; 375 __u8 tstamp:1; 376 #else 377 __u8 tstamp:1; 378 __u8 sack:1; 379 __u8:1; 380 __u8 unknown:1; 381 __u8:4; 382 #endif 383 }; 384 385 struct cpl_pass_accept_req { 386 union opcode_tid ot; 387 __be16 rsvd; 388 __be16 len; 389 __be32 hdr_len; 390 __be16 vlan; 391 __be16 l2info; 392 __be32 tos_stid; 393 struct tcp_options tcpopt; 394 }; 395 396 /* cpl_pass_accept_req.hdr_len fields */ 397 #define SYN_RX_CHAN_S 0 398 #define SYN_RX_CHAN_M 0xF 399 #define SYN_RX_CHAN_V(x) ((x) << SYN_RX_CHAN_S) 400 #define SYN_RX_CHAN_G(x) (((x) >> SYN_RX_CHAN_S) & SYN_RX_CHAN_M) 401 402 #define TCP_HDR_LEN_S 10 403 #define TCP_HDR_LEN_M 0x3F 404 #define TCP_HDR_LEN_V(x) ((x) << TCP_HDR_LEN_S) 405 #define TCP_HDR_LEN_G(x) (((x) >> TCP_HDR_LEN_S) & TCP_HDR_LEN_M) 406 407 #define IP_HDR_LEN_S 16 408 #define IP_HDR_LEN_M 0x3FF 409 #define IP_HDR_LEN_V(x) ((x) << IP_HDR_LEN_S) 410 #define IP_HDR_LEN_G(x) (((x) >> IP_HDR_LEN_S) & IP_HDR_LEN_M) 411 412 #define ETH_HDR_LEN_S 26 413 #define ETH_HDR_LEN_M 0x1F 414 #define ETH_HDR_LEN_V(x) ((x) << ETH_HDR_LEN_S) 415 #define ETH_HDR_LEN_G(x) (((x) >> ETH_HDR_LEN_S) & ETH_HDR_LEN_M) 416 417 /* cpl_pass_accept_req.l2info fields */ 418 #define SYN_MAC_IDX_S 0 419 #define SYN_MAC_IDX_M 0x1FF 420 #define SYN_MAC_IDX_V(x) ((x) << SYN_MAC_IDX_S) 421 #define SYN_MAC_IDX_G(x) (((x) >> SYN_MAC_IDX_S) & SYN_MAC_IDX_M) 422 423 #define SYN_XACT_MATCH_S 9 424 #define SYN_XACT_MATCH_V(x) ((x) << SYN_XACT_MATCH_S) 425 #define SYN_XACT_MATCH_F SYN_XACT_MATCH_V(1U) 426 427 #define SYN_INTF_S 12 428 #define SYN_INTF_M 0xF 429 #define SYN_INTF_V(x) ((x) << SYN_INTF_S) 430 #define SYN_INTF_G(x) (((x) >> SYN_INTF_S) & SYN_INTF_M) 431 432 enum { /* TCP congestion control algorithms */ 433 CONG_ALG_RENO, 434 CONG_ALG_TAHOE, 435 CONG_ALG_NEWRENO, 436 CONG_ALG_HIGHSPEED 437 }; 438 439 #define CONG_CNTRL_S 14 440 #define CONG_CNTRL_M 0x3 441 #define CONG_CNTRL_V(x) ((x) << CONG_CNTRL_S) 442 #define CONG_CNTRL_G(x) (((x) >> CONG_CNTRL_S) & CONG_CNTRL_M) 443 444 #define T5_ISS_S 18 445 #define T5_ISS_V(x) ((x) << T5_ISS_S) 446 #define T5_ISS_F T5_ISS_V(1U) 447 448 struct cpl_pass_accept_rpl { 449 WR_HDR; 450 union opcode_tid ot; 451 __be32 opt2; 452 __be64 opt0; 453 }; 454 455 /* option 2 fields */ 456 #define RX_COALESCE_VALID_S 11 457 #define RX_COALESCE_VALID_V(x) ((x) << RX_COALESCE_VALID_S) 458 #define RX_COALESCE_VALID_F RX_COALESCE_VALID_V(1U) 459 460 #define RX_COALESCE_S 12 461 #define RX_COALESCE_V(x) ((x) << RX_COALESCE_S) 462 463 #define PACE_S 16 464 #define PACE_V(x) ((x) << PACE_S) 465 466 #define TX_QUEUE_S 23 467 #define TX_QUEUE_M 0x7 468 #define TX_QUEUE_V(x) ((x) << TX_QUEUE_S) 469 #define TX_QUEUE_G(x) (((x) >> TX_QUEUE_S) & TX_QUEUE_M) 470 471 #define CCTRL_ECN_S 27 472 #define CCTRL_ECN_V(x) ((x) << CCTRL_ECN_S) 473 #define CCTRL_ECN_F CCTRL_ECN_V(1U) 474 475 #define TSTAMPS_EN_S 29 476 #define TSTAMPS_EN_V(x) ((x) << TSTAMPS_EN_S) 477 #define TSTAMPS_EN_F TSTAMPS_EN_V(1U) 478 479 #define SACK_EN_S 30 480 #define SACK_EN_V(x) ((x) << SACK_EN_S) 481 #define SACK_EN_F SACK_EN_V(1U) 482 483 struct cpl_t5_pass_accept_rpl { 484 WR_HDR; 485 union opcode_tid ot; 486 __be32 opt2; 487 __be64 opt0; 488 __be32 iss; 489 __be32 rsvd; 490 }; 491 492 struct cpl_act_open_req { 493 WR_HDR; 494 union opcode_tid ot; 495 __be16 local_port; 496 __be16 peer_port; 497 __be32 local_ip; 498 __be32 peer_ip; 499 __be64 opt0; 500 __be32 params; 501 __be32 opt2; 502 }; 503 504 #define FILTER_TUPLE_S 24 505 #define FILTER_TUPLE_M 0xFFFFFFFFFF 506 #define FILTER_TUPLE_V(x) ((x) << FILTER_TUPLE_S) 507 #define FILTER_TUPLE_G(x) (((x) >> FILTER_TUPLE_S) & FILTER_TUPLE_M) 508 struct cpl_t5_act_open_req { 509 WR_HDR; 510 union opcode_tid ot; 511 __be16 local_port; 512 __be16 peer_port; 513 __be32 local_ip; 514 __be32 peer_ip; 515 __be64 opt0; 516 __be32 rsvd; 517 __be32 opt2; 518 __be64 params; 519 }; 520 521 struct cpl_t6_act_open_req { 522 WR_HDR; 523 union opcode_tid ot; 524 __be16 local_port; 525 __be16 peer_port; 526 __be32 local_ip; 527 __be32 peer_ip; 528 __be64 opt0; 529 __be32 rsvd; 530 __be32 opt2; 531 __be64 params; 532 __be32 rsvd2; 533 __be32 opt3; 534 }; 535 536 struct cpl_act_open_req6 { 537 WR_HDR; 538 union opcode_tid ot; 539 __be16 local_port; 540 __be16 peer_port; 541 __be64 local_ip_hi; 542 __be64 local_ip_lo; 543 __be64 peer_ip_hi; 544 __be64 peer_ip_lo; 545 __be64 opt0; 546 __be32 params; 547 __be32 opt2; 548 }; 549 550 struct cpl_t5_act_open_req6 { 551 WR_HDR; 552 union opcode_tid ot; 553 __be16 local_port; 554 __be16 peer_port; 555 __be64 local_ip_hi; 556 __be64 local_ip_lo; 557 __be64 peer_ip_hi; 558 __be64 peer_ip_lo; 559 __be64 opt0; 560 __be32 rsvd; 561 __be32 opt2; 562 __be64 params; 563 }; 564 565 struct cpl_t6_act_open_req6 { 566 WR_HDR; 567 union opcode_tid ot; 568 __be16 local_port; 569 __be16 peer_port; 570 __be64 local_ip_hi; 571 __be64 local_ip_lo; 572 __be64 peer_ip_hi; 573 __be64 peer_ip_lo; 574 __be64 opt0; 575 __be32 rsvd; 576 __be32 opt2; 577 __be64 params; 578 __be32 rsvd2; 579 __be32 opt3; 580 }; 581 582 struct cpl_act_open_rpl { 583 union opcode_tid ot; 584 __be32 atid_status; 585 }; 586 587 /* cpl_act_open_rpl.atid_status fields */ 588 #define AOPEN_STATUS_S 0 589 #define AOPEN_STATUS_M 0xFF 590 #define AOPEN_STATUS_G(x) (((x) >> AOPEN_STATUS_S) & AOPEN_STATUS_M) 591 592 #define AOPEN_ATID_S 8 593 #define AOPEN_ATID_M 0xFFFFFF 594 #define AOPEN_ATID_G(x) (((x) >> AOPEN_ATID_S) & AOPEN_ATID_M) 595 596 struct cpl_pass_establish { 597 union opcode_tid ot; 598 __be32 rsvd; 599 __be32 tos_stid; 600 __be16 mac_idx; 601 __be16 tcp_opt; 602 __be32 snd_isn; 603 __be32 rcv_isn; 604 }; 605 606 /* cpl_pass_establish.tos_stid fields */ 607 #define PASS_OPEN_TID_S 0 608 #define PASS_OPEN_TID_M 0xFFFFFF 609 #define PASS_OPEN_TID_V(x) ((x) << PASS_OPEN_TID_S) 610 #define PASS_OPEN_TID_G(x) (((x) >> PASS_OPEN_TID_S) & PASS_OPEN_TID_M) 611 612 #define PASS_OPEN_TOS_S 24 613 #define PASS_OPEN_TOS_M 0xFF 614 #define PASS_OPEN_TOS_V(x) ((x) << PASS_OPEN_TOS_S) 615 #define PASS_OPEN_TOS_G(x) (((x) >> PASS_OPEN_TOS_S) & PASS_OPEN_TOS_M) 616 617 /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */ 618 #define TCPOPT_WSCALE_OK_S 5 619 #define TCPOPT_WSCALE_OK_M 0x1 620 #define TCPOPT_WSCALE_OK_G(x) \ 621 (((x) >> TCPOPT_WSCALE_OK_S) & TCPOPT_WSCALE_OK_M) 622 623 #define TCPOPT_SACK_S 6 624 #define TCPOPT_SACK_M 0x1 625 #define TCPOPT_SACK_G(x) (((x) >> TCPOPT_SACK_S) & TCPOPT_SACK_M) 626 627 #define TCPOPT_TSTAMP_S 7 628 #define TCPOPT_TSTAMP_M 0x1 629 #define TCPOPT_TSTAMP_G(x) (((x) >> TCPOPT_TSTAMP_S) & TCPOPT_TSTAMP_M) 630 631 #define TCPOPT_SND_WSCALE_S 8 632 #define TCPOPT_SND_WSCALE_M 0xF 633 #define TCPOPT_SND_WSCALE_G(x) \ 634 (((x) >> TCPOPT_SND_WSCALE_S) & TCPOPT_SND_WSCALE_M) 635 636 #define TCPOPT_MSS_S 12 637 #define TCPOPT_MSS_M 0xF 638 #define TCPOPT_MSS_G(x) (((x) >> TCPOPT_MSS_S) & TCPOPT_MSS_M) 639 640 #define T6_TCP_HDR_LEN_S 8 641 #define T6_TCP_HDR_LEN_V(x) ((x) << T6_TCP_HDR_LEN_S) 642 #define T6_TCP_HDR_LEN_G(x) (((x) >> T6_TCP_HDR_LEN_S) & TCP_HDR_LEN_M) 643 644 #define T6_IP_HDR_LEN_S 14 645 #define T6_IP_HDR_LEN_V(x) ((x) << T6_IP_HDR_LEN_S) 646 #define T6_IP_HDR_LEN_G(x) (((x) >> T6_IP_HDR_LEN_S) & IP_HDR_LEN_M) 647 648 #define T6_ETH_HDR_LEN_S 24 649 #define T6_ETH_HDR_LEN_M 0xFF 650 #define T6_ETH_HDR_LEN_V(x) ((x) << T6_ETH_HDR_LEN_S) 651 #define T6_ETH_HDR_LEN_G(x) (((x) >> T6_ETH_HDR_LEN_S) & T6_ETH_HDR_LEN_M) 652 653 struct cpl_act_establish { 654 union opcode_tid ot; 655 __be32 rsvd; 656 __be32 tos_atid; 657 __be16 mac_idx; 658 __be16 tcp_opt; 659 __be32 snd_isn; 660 __be32 rcv_isn; 661 }; 662 663 struct cpl_get_tcb { 664 WR_HDR; 665 union opcode_tid ot; 666 __be16 reply_ctrl; 667 __be16 cookie; 668 }; 669 670 /* cpl_get_tcb.reply_ctrl fields */ 671 #define QUEUENO_S 0 672 #define QUEUENO_V(x) ((x) << QUEUENO_S) 673 674 #define REPLY_CHAN_S 14 675 #define REPLY_CHAN_V(x) ((x) << REPLY_CHAN_S) 676 #define REPLY_CHAN_F REPLY_CHAN_V(1U) 677 678 #define NO_REPLY_S 15 679 #define NO_REPLY_V(x) ((x) << NO_REPLY_S) 680 #define NO_REPLY_F NO_REPLY_V(1U) 681 682 struct cpl_set_tcb_field { 683 WR_HDR; 684 union opcode_tid ot; 685 __be16 reply_ctrl; 686 __be16 word_cookie; 687 __be64 mask; 688 __be64 val; 689 }; 690 691 /* cpl_set_tcb_field.word_cookie fields */ 692 #define TCB_WORD_S 0 693 #define TCB_WORD_V(x) ((x) << TCB_WORD_S) 694 695 #define TCB_COOKIE_S 5 696 #define TCB_COOKIE_M 0x7 697 #define TCB_COOKIE_V(x) ((x) << TCB_COOKIE_S) 698 #define TCB_COOKIE_G(x) (((x) >> TCB_COOKIE_S) & TCB_COOKIE_M) 699 700 struct cpl_set_tcb_rpl { 701 union opcode_tid ot; 702 __be16 rsvd; 703 u8 cookie; 704 u8 status; 705 __be64 oldval; 706 }; 707 708 struct cpl_close_con_req { 709 WR_HDR; 710 union opcode_tid ot; 711 __be32 rsvd; 712 }; 713 714 struct cpl_close_con_rpl { 715 union opcode_tid ot; 716 u8 rsvd[3]; 717 u8 status; 718 __be32 snd_nxt; 719 __be32 rcv_nxt; 720 }; 721 722 struct cpl_close_listsvr_req { 723 WR_HDR; 724 union opcode_tid ot; 725 __be16 reply_ctrl; 726 __be16 rsvd; 727 }; 728 729 /* additional cpl_close_listsvr_req.reply_ctrl field */ 730 #define LISTSVR_IPV6_S 14 731 #define LISTSVR_IPV6_V(x) ((x) << LISTSVR_IPV6_S) 732 #define LISTSVR_IPV6_F LISTSVR_IPV6_V(1U) 733 734 struct cpl_close_listsvr_rpl { 735 union opcode_tid ot; 736 u8 rsvd[3]; 737 u8 status; 738 }; 739 740 struct cpl_abort_req_rss { 741 union opcode_tid ot; 742 u8 rsvd[3]; 743 u8 status; 744 }; 745 746 struct cpl_abort_req { 747 WR_HDR; 748 union opcode_tid ot; 749 __be32 rsvd0; 750 u8 rsvd1; 751 u8 cmd; 752 u8 rsvd2[6]; 753 }; 754 755 struct cpl_abort_rpl_rss { 756 union opcode_tid ot; 757 u8 rsvd[3]; 758 u8 status; 759 }; 760 761 struct cpl_abort_rpl { 762 WR_HDR; 763 union opcode_tid ot; 764 __be32 rsvd0; 765 u8 rsvd1; 766 u8 cmd; 767 u8 rsvd2[6]; 768 }; 769 770 struct cpl_peer_close { 771 union opcode_tid ot; 772 __be32 rcv_nxt; 773 }; 774 775 struct cpl_tid_release { 776 WR_HDR; 777 union opcode_tid ot; 778 __be32 rsvd; 779 }; 780 781 struct cpl_tx_pkt_core { 782 __be32 ctrl0; 783 __be16 pack; 784 __be16 len; 785 __be64 ctrl1; 786 }; 787 788 struct cpl_tx_pkt { 789 WR_HDR; 790 struct cpl_tx_pkt_core c; 791 }; 792 793 #define cpl_tx_pkt_xt cpl_tx_pkt 794 795 /* cpl_tx_pkt_core.ctrl0 fields */ 796 #define TXPKT_VF_S 0 797 #define TXPKT_VF_V(x) ((x) << TXPKT_VF_S) 798 799 #define TXPKT_PF_S 8 800 #define TXPKT_PF_V(x) ((x) << TXPKT_PF_S) 801 802 #define TXPKT_VF_VLD_S 11 803 #define TXPKT_VF_VLD_V(x) ((x) << TXPKT_VF_VLD_S) 804 #define TXPKT_VF_VLD_F TXPKT_VF_VLD_V(1U) 805 806 #define TXPKT_OVLAN_IDX_S 12 807 #define TXPKT_OVLAN_IDX_V(x) ((x) << TXPKT_OVLAN_IDX_S) 808 809 #define TXPKT_T5_OVLAN_IDX_S 12 810 #define TXPKT_T5_OVLAN_IDX_V(x) ((x) << TXPKT_T5_OVLAN_IDX_S) 811 812 #define TXPKT_INTF_S 16 813 #define TXPKT_INTF_V(x) ((x) << TXPKT_INTF_S) 814 815 #define TXPKT_INS_OVLAN_S 21 816 #define TXPKT_INS_OVLAN_V(x) ((x) << TXPKT_INS_OVLAN_S) 817 #define TXPKT_INS_OVLAN_F TXPKT_INS_OVLAN_V(1U) 818 819 #define TXPKT_TSTAMP_S 23 820 #define TXPKT_TSTAMP_V(x) ((x) << TXPKT_TSTAMP_S) 821 #define TXPKT_TSTAMP_F TXPKT_TSTAMP_V(1ULL) 822 823 #define TXPKT_OPCODE_S 24 824 #define TXPKT_OPCODE_V(x) ((x) << TXPKT_OPCODE_S) 825 826 /* cpl_tx_pkt_core.ctrl1 fields */ 827 #define TXPKT_CSUM_END_S 12 828 #define TXPKT_CSUM_END_V(x) ((x) << TXPKT_CSUM_END_S) 829 830 #define TXPKT_CSUM_START_S 20 831 #define TXPKT_CSUM_START_V(x) ((x) << TXPKT_CSUM_START_S) 832 833 #define TXPKT_IPHDR_LEN_S 20 834 #define TXPKT_IPHDR_LEN_V(x) ((__u64)(x) << TXPKT_IPHDR_LEN_S) 835 836 #define TXPKT_CSUM_LOC_S 30 837 #define TXPKT_CSUM_LOC_V(x) ((__u64)(x) << TXPKT_CSUM_LOC_S) 838 839 #define TXPKT_ETHHDR_LEN_S 34 840 #define TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << TXPKT_ETHHDR_LEN_S) 841 842 #define T6_TXPKT_ETHHDR_LEN_S 32 843 #define T6_TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << T6_TXPKT_ETHHDR_LEN_S) 844 845 #define TXPKT_CSUM_TYPE_S 40 846 #define TXPKT_CSUM_TYPE_V(x) ((__u64)(x) << TXPKT_CSUM_TYPE_S) 847 848 #define TXPKT_VLAN_S 44 849 #define TXPKT_VLAN_V(x) ((__u64)(x) << TXPKT_VLAN_S) 850 851 #define TXPKT_VLAN_VLD_S 60 852 #define TXPKT_VLAN_VLD_V(x) ((__u64)(x) << TXPKT_VLAN_VLD_S) 853 #define TXPKT_VLAN_VLD_F TXPKT_VLAN_VLD_V(1ULL) 854 855 #define TXPKT_IPCSUM_DIS_S 62 856 #define TXPKT_IPCSUM_DIS_V(x) ((__u64)(x) << TXPKT_IPCSUM_DIS_S) 857 #define TXPKT_IPCSUM_DIS_F TXPKT_IPCSUM_DIS_V(1ULL) 858 859 #define TXPKT_L4CSUM_DIS_S 63 860 #define TXPKT_L4CSUM_DIS_V(x) ((__u64)(x) << TXPKT_L4CSUM_DIS_S) 861 #define TXPKT_L4CSUM_DIS_F TXPKT_L4CSUM_DIS_V(1ULL) 862 863 struct cpl_tx_pkt_lso_core { 864 __be32 lso_ctrl; 865 __be16 ipid_ofst; 866 __be16 mss; 867 __be32 seqno_offset; 868 __be32 len; 869 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 870 }; 871 872 /* cpl_tx_pkt_lso_core.lso_ctrl fields */ 873 #define LSO_TCPHDR_LEN_S 0 874 #define LSO_TCPHDR_LEN_V(x) ((x) << LSO_TCPHDR_LEN_S) 875 876 #define LSO_IPHDR_LEN_S 4 877 #define LSO_IPHDR_LEN_V(x) ((x) << LSO_IPHDR_LEN_S) 878 879 #define LSO_ETHHDR_LEN_S 16 880 #define LSO_ETHHDR_LEN_V(x) ((x) << LSO_ETHHDR_LEN_S) 881 882 #define LSO_IPV6_S 20 883 #define LSO_IPV6_V(x) ((x) << LSO_IPV6_S) 884 #define LSO_IPV6_F LSO_IPV6_V(1U) 885 886 #define LSO_LAST_SLICE_S 22 887 #define LSO_LAST_SLICE_V(x) ((x) << LSO_LAST_SLICE_S) 888 #define LSO_LAST_SLICE_F LSO_LAST_SLICE_V(1U) 889 890 #define LSO_FIRST_SLICE_S 23 891 #define LSO_FIRST_SLICE_V(x) ((x) << LSO_FIRST_SLICE_S) 892 #define LSO_FIRST_SLICE_F LSO_FIRST_SLICE_V(1U) 893 894 #define LSO_OPCODE_S 24 895 #define LSO_OPCODE_V(x) ((x) << LSO_OPCODE_S) 896 897 #define LSO_T5_XFER_SIZE_S 0 898 #define LSO_T5_XFER_SIZE_V(x) ((x) << LSO_T5_XFER_SIZE_S) 899 900 struct cpl_tx_pkt_lso { 901 WR_HDR; 902 struct cpl_tx_pkt_lso_core c; 903 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 904 }; 905 906 struct cpl_iscsi_hdr { 907 union opcode_tid ot; 908 __be16 pdu_len_ddp; 909 __be16 len; 910 __be32 seq; 911 __be16 urg; 912 u8 rsvd; 913 u8 status; 914 }; 915 916 /* cpl_iscsi_hdr.pdu_len_ddp fields */ 917 #define ISCSI_PDU_LEN_S 0 918 #define ISCSI_PDU_LEN_M 0x7FFF 919 #define ISCSI_PDU_LEN_V(x) ((x) << ISCSI_PDU_LEN_S) 920 #define ISCSI_PDU_LEN_G(x) (((x) >> ISCSI_PDU_LEN_S) & ISCSI_PDU_LEN_M) 921 922 #define ISCSI_DDP_S 15 923 #define ISCSI_DDP_V(x) ((x) << ISCSI_DDP_S) 924 #define ISCSI_DDP_F ISCSI_DDP_V(1U) 925 926 struct cpl_rx_data_ddp { 927 union opcode_tid ot; 928 __be16 urg; 929 __be16 len; 930 __be32 seq; 931 union { 932 __be32 nxt_seq; 933 __be32 ddp_report; 934 }; 935 __be32 ulp_crc; 936 __be32 ddpvld; 937 }; 938 939 #define cpl_rx_iscsi_ddp cpl_rx_data_ddp 940 941 struct cpl_iscsi_data { 942 union opcode_tid ot; 943 __u8 rsvd0[2]; 944 __be16 len; 945 __be32 seq; 946 __be16 urg; 947 __u8 rsvd1; 948 __u8 status; 949 }; 950 951 struct cpl_rx_iscsi_cmp { 952 union opcode_tid ot; 953 __be16 pdu_len_ddp; 954 __be16 len; 955 __be32 seq; 956 __be16 urg; 957 __u8 rsvd; 958 __u8 status; 959 __be32 ulp_crc; 960 __be32 ddpvld; 961 }; 962 963 struct cpl_tx_data_iso { 964 __be32 op_to_scsi; 965 __u8 reserved1; 966 __u8 ahs_len; 967 __be16 mpdu; 968 __be32 burst_size; 969 __be32 len; 970 __be32 reserved2_seglen_offset; 971 __be32 datasn_offset; 972 __be32 buffer_offset; 973 __be32 reserved3; 974 975 /* encapsulated CPL_TX_DATA follows here */ 976 }; 977 978 /* cpl_tx_data_iso.op_to_scsi fields */ 979 #define CPL_TX_DATA_ISO_OP_S 24 980 #define CPL_TX_DATA_ISO_OP_M 0xff 981 #define CPL_TX_DATA_ISO_OP_V(x) ((x) << CPL_TX_DATA_ISO_OP_S) 982 #define CPL_TX_DATA_ISO_OP_G(x) \ 983 (((x) >> CPL_TX_DATA_ISO_OP_S) & CPL_TX_DATA_ISO_OP_M) 984 985 #define CPL_TX_DATA_ISO_FIRST_S 23 986 #define CPL_TX_DATA_ISO_FIRST_M 0x1 987 #define CPL_TX_DATA_ISO_FIRST_V(x) ((x) << CPL_TX_DATA_ISO_FIRST_S) 988 #define CPL_TX_DATA_ISO_FIRST_G(x) \ 989 (((x) >> CPL_TX_DATA_ISO_FIRST_S) & CPL_TX_DATA_ISO_FIRST_M) 990 #define CPL_TX_DATA_ISO_FIRST_F CPL_TX_DATA_ISO_FIRST_V(1U) 991 992 #define CPL_TX_DATA_ISO_LAST_S 22 993 #define CPL_TX_DATA_ISO_LAST_M 0x1 994 #define CPL_TX_DATA_ISO_LAST_V(x) ((x) << CPL_TX_DATA_ISO_LAST_S) 995 #define CPL_TX_DATA_ISO_LAST_G(x) \ 996 (((x) >> CPL_TX_DATA_ISO_LAST_S) & CPL_TX_DATA_ISO_LAST_M) 997 #define CPL_TX_DATA_ISO_LAST_F CPL_TX_DATA_ISO_LAST_V(1U) 998 999 #define CPL_TX_DATA_ISO_CPLHDRLEN_S 21 1000 #define CPL_TX_DATA_ISO_CPLHDRLEN_M 0x1 1001 #define CPL_TX_DATA_ISO_CPLHDRLEN_V(x) ((x) << CPL_TX_DATA_ISO_CPLHDRLEN_S) 1002 #define CPL_TX_DATA_ISO_CPLHDRLEN_G(x) \ 1003 (((x) >> CPL_TX_DATA_ISO_CPLHDRLEN_S) & CPL_TX_DATA_ISO_CPLHDRLEN_M) 1004 #define CPL_TX_DATA_ISO_CPLHDRLEN_F CPL_TX_DATA_ISO_CPLHDRLEN_V(1U) 1005 1006 #define CPL_TX_DATA_ISO_HDRCRC_S 20 1007 #define CPL_TX_DATA_ISO_HDRCRC_M 0x1 1008 #define CPL_TX_DATA_ISO_HDRCRC_V(x) ((x) << CPL_TX_DATA_ISO_HDRCRC_S) 1009 #define CPL_TX_DATA_ISO_HDRCRC_G(x) \ 1010 (((x) >> CPL_TX_DATA_ISO_HDRCRC_S) & CPL_TX_DATA_ISO_HDRCRC_M) 1011 #define CPL_TX_DATA_ISO_HDRCRC_F CPL_TX_DATA_ISO_HDRCRC_V(1U) 1012 1013 #define CPL_TX_DATA_ISO_PLDCRC_S 19 1014 #define CPL_TX_DATA_ISO_PLDCRC_M 0x1 1015 #define CPL_TX_DATA_ISO_PLDCRC_V(x) ((x) << CPL_TX_DATA_ISO_PLDCRC_S) 1016 #define CPL_TX_DATA_ISO_PLDCRC_G(x) \ 1017 (((x) >> CPL_TX_DATA_ISO_PLDCRC_S) & CPL_TX_DATA_ISO_PLDCRC_M) 1018 #define CPL_TX_DATA_ISO_PLDCRC_F CPL_TX_DATA_ISO_PLDCRC_V(1U) 1019 1020 #define CPL_TX_DATA_ISO_IMMEDIATE_S 18 1021 #define CPL_TX_DATA_ISO_IMMEDIATE_M 0x1 1022 #define CPL_TX_DATA_ISO_IMMEDIATE_V(x) ((x) << CPL_TX_DATA_ISO_IMMEDIATE_S) 1023 #define CPL_TX_DATA_ISO_IMMEDIATE_G(x) \ 1024 (((x) >> CPL_TX_DATA_ISO_IMMEDIATE_S) & CPL_TX_DATA_ISO_IMMEDIATE_M) 1025 #define CPL_TX_DATA_ISO_IMMEDIATE_F CPL_TX_DATA_ISO_IMMEDIATE_V(1U) 1026 1027 #define CPL_TX_DATA_ISO_SCSI_S 16 1028 #define CPL_TX_DATA_ISO_SCSI_M 0x3 1029 #define CPL_TX_DATA_ISO_SCSI_V(x) ((x) << CPL_TX_DATA_ISO_SCSI_S) 1030 #define CPL_TX_DATA_ISO_SCSI_G(x) \ 1031 (((x) >> CPL_TX_DATA_ISO_SCSI_S) & CPL_TX_DATA_ISO_SCSI_M) 1032 1033 /* cpl_tx_data_iso.reserved2_seglen_offset fields */ 1034 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_S 0 1035 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_M 0xffffff 1036 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_V(x) \ 1037 ((x) << CPL_TX_DATA_ISO_SEGLEN_OFFSET_S) 1038 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_G(x) \ 1039 (((x) >> CPL_TX_DATA_ISO_SEGLEN_OFFSET_S) & \ 1040 CPL_TX_DATA_ISO_SEGLEN_OFFSET_M) 1041 1042 struct cpl_rx_data { 1043 union opcode_tid ot; 1044 __be16 rsvd; 1045 __be16 len; 1046 __be32 seq; 1047 __be16 urg; 1048 #if defined(__LITTLE_ENDIAN_BITFIELD) 1049 u8 dack_mode:2; 1050 u8 psh:1; 1051 u8 heartbeat:1; 1052 u8 ddp_off:1; 1053 u8 :3; 1054 #else 1055 u8 :3; 1056 u8 ddp_off:1; 1057 u8 heartbeat:1; 1058 u8 psh:1; 1059 u8 dack_mode:2; 1060 #endif 1061 u8 status; 1062 }; 1063 1064 struct cpl_rx_data_ack { 1065 WR_HDR; 1066 union opcode_tid ot; 1067 __be32 credit_dack; 1068 }; 1069 1070 /* cpl_rx_data_ack.ack_seq fields */ 1071 #define RX_CREDITS_S 0 1072 #define RX_CREDITS_V(x) ((x) << RX_CREDITS_S) 1073 1074 #define RX_FORCE_ACK_S 28 1075 #define RX_FORCE_ACK_V(x) ((x) << RX_FORCE_ACK_S) 1076 #define RX_FORCE_ACK_F RX_FORCE_ACK_V(1U) 1077 1078 #define RX_DACK_MODE_S 29 1079 #define RX_DACK_MODE_M 0x3 1080 #define RX_DACK_MODE_V(x) ((x) << RX_DACK_MODE_S) 1081 #define RX_DACK_MODE_G(x) (((x) >> RX_DACK_MODE_S) & RX_DACK_MODE_M) 1082 1083 #define RX_DACK_CHANGE_S 31 1084 #define RX_DACK_CHANGE_V(x) ((x) << RX_DACK_CHANGE_S) 1085 #define RX_DACK_CHANGE_F RX_DACK_CHANGE_V(1U) 1086 1087 struct cpl_rx_pkt { 1088 struct rss_header rsshdr; 1089 u8 opcode; 1090 #if defined(__LITTLE_ENDIAN_BITFIELD) 1091 u8 iff:4; 1092 u8 csum_calc:1; 1093 u8 ipmi_pkt:1; 1094 u8 vlan_ex:1; 1095 u8 ip_frag:1; 1096 #else 1097 u8 ip_frag:1; 1098 u8 vlan_ex:1; 1099 u8 ipmi_pkt:1; 1100 u8 csum_calc:1; 1101 u8 iff:4; 1102 #endif 1103 __be16 csum; 1104 __be16 vlan; 1105 __be16 len; 1106 __be32 l2info; 1107 __be16 hdr_len; 1108 __be16 err_vec; 1109 }; 1110 1111 #define RX_T6_ETHHDR_LEN_M 0xFF 1112 #define RX_T6_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_T6_ETHHDR_LEN_M) 1113 1114 #define RXF_PSH_S 20 1115 #define RXF_PSH_V(x) ((x) << RXF_PSH_S) 1116 #define RXF_PSH_F RXF_PSH_V(1U) 1117 1118 #define RXF_SYN_S 21 1119 #define RXF_SYN_V(x) ((x) << RXF_SYN_S) 1120 #define RXF_SYN_F RXF_SYN_V(1U) 1121 1122 #define RXF_UDP_S 22 1123 #define RXF_UDP_V(x) ((x) << RXF_UDP_S) 1124 #define RXF_UDP_F RXF_UDP_V(1U) 1125 1126 #define RXF_TCP_S 23 1127 #define RXF_TCP_V(x) ((x) << RXF_TCP_S) 1128 #define RXF_TCP_F RXF_TCP_V(1U) 1129 1130 #define RXF_IP_S 24 1131 #define RXF_IP_V(x) ((x) << RXF_IP_S) 1132 #define RXF_IP_F RXF_IP_V(1U) 1133 1134 #define RXF_IP6_S 25 1135 #define RXF_IP6_V(x) ((x) << RXF_IP6_S) 1136 #define RXF_IP6_F RXF_IP6_V(1U) 1137 1138 #define RXF_SYN_COOKIE_S 26 1139 #define RXF_SYN_COOKIE_V(x) ((x) << RXF_SYN_COOKIE_S) 1140 #define RXF_SYN_COOKIE_F RXF_SYN_COOKIE_V(1U) 1141 1142 #define RXF_FCOE_S 26 1143 #define RXF_FCOE_V(x) ((x) << RXF_FCOE_S) 1144 #define RXF_FCOE_F RXF_FCOE_V(1U) 1145 1146 #define RXF_LRO_S 27 1147 #define RXF_LRO_V(x) ((x) << RXF_LRO_S) 1148 #define RXF_LRO_F RXF_LRO_V(1U) 1149 1150 /* rx_pkt.l2info fields */ 1151 #define RX_ETHHDR_LEN_S 0 1152 #define RX_ETHHDR_LEN_M 0x1F 1153 #define RX_ETHHDR_LEN_V(x) ((x) << RX_ETHHDR_LEN_S) 1154 #define RX_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_ETHHDR_LEN_M) 1155 1156 #define RX_T5_ETHHDR_LEN_S 0 1157 #define RX_T5_ETHHDR_LEN_M 0x3F 1158 #define RX_T5_ETHHDR_LEN_V(x) ((x) << RX_T5_ETHHDR_LEN_S) 1159 #define RX_T5_ETHHDR_LEN_G(x) (((x) >> RX_T5_ETHHDR_LEN_S) & RX_T5_ETHHDR_LEN_M) 1160 1161 #define RX_MACIDX_S 8 1162 #define RX_MACIDX_M 0x1FF 1163 #define RX_MACIDX_V(x) ((x) << RX_MACIDX_S) 1164 #define RX_MACIDX_G(x) (((x) >> RX_MACIDX_S) & RX_MACIDX_M) 1165 1166 #define RXF_SYN_S 21 1167 #define RXF_SYN_V(x) ((x) << RXF_SYN_S) 1168 #define RXF_SYN_F RXF_SYN_V(1U) 1169 1170 #define RX_CHAN_S 28 1171 #define RX_CHAN_M 0xF 1172 #define RX_CHAN_V(x) ((x) << RX_CHAN_S) 1173 #define RX_CHAN_G(x) (((x) >> RX_CHAN_S) & RX_CHAN_M) 1174 1175 /* rx_pkt.hdr_len fields */ 1176 #define RX_TCPHDR_LEN_S 0 1177 #define RX_TCPHDR_LEN_M 0x3F 1178 #define RX_TCPHDR_LEN_V(x) ((x) << RX_TCPHDR_LEN_S) 1179 #define RX_TCPHDR_LEN_G(x) (((x) >> RX_TCPHDR_LEN_S) & RX_TCPHDR_LEN_M) 1180 1181 #define RX_IPHDR_LEN_S 6 1182 #define RX_IPHDR_LEN_M 0x3FF 1183 #define RX_IPHDR_LEN_V(x) ((x) << RX_IPHDR_LEN_S) 1184 #define RX_IPHDR_LEN_G(x) (((x) >> RX_IPHDR_LEN_S) & RX_IPHDR_LEN_M) 1185 1186 /* rx_pkt.err_vec fields */ 1187 #define RXERR_CSUM_S 13 1188 #define RXERR_CSUM_V(x) ((x) << RXERR_CSUM_S) 1189 #define RXERR_CSUM_F RXERR_CSUM_V(1U) 1190 1191 #define T6_COMPR_RXERR_LEN_S 1 1192 #define T6_COMPR_RXERR_LEN_V(x) ((x) << T6_COMPR_RXERR_LEN_S) 1193 #define T6_COMPR_RXERR_LEN_F T6_COMPR_RXERR_LEN_V(1U) 1194 1195 #define T6_COMPR_RXERR_VEC_S 0 1196 #define T6_COMPR_RXERR_VEC_M 0x3F 1197 #define T6_COMPR_RXERR_VEC_V(x) ((x) << T6_COMPR_RXERR_LEN_S) 1198 #define T6_COMPR_RXERR_VEC_G(x) \ 1199 (((x) >> T6_COMPR_RXERR_VEC_S) & T6_COMPR_RXERR_VEC_M) 1200 1201 /* Logical OR of RX_ERROR_CSUM, RX_ERROR_CSIP */ 1202 #define T6_COMPR_RXERR_SUM_S 4 1203 #define T6_COMPR_RXERR_SUM_V(x) ((x) << T6_COMPR_RXERR_SUM_S) 1204 #define T6_COMPR_RXERR_SUM_F T6_COMPR_RXERR_SUM_V(1U) 1205 1206 struct cpl_trace_pkt { 1207 u8 opcode; 1208 u8 intf; 1209 #if defined(__LITTLE_ENDIAN_BITFIELD) 1210 u8 runt:4; 1211 u8 filter_hit:4; 1212 u8 :6; 1213 u8 err:1; 1214 u8 trunc:1; 1215 #else 1216 u8 filter_hit:4; 1217 u8 runt:4; 1218 u8 trunc:1; 1219 u8 err:1; 1220 u8 :6; 1221 #endif 1222 __be16 rsvd; 1223 __be16 len; 1224 __be64 tstamp; 1225 }; 1226 1227 struct cpl_t5_trace_pkt { 1228 __u8 opcode; 1229 __u8 intf; 1230 #if defined(__LITTLE_ENDIAN_BITFIELD) 1231 __u8 runt:4; 1232 __u8 filter_hit:4; 1233 __u8:6; 1234 __u8 err:1; 1235 __u8 trunc:1; 1236 #else 1237 __u8 filter_hit:4; 1238 __u8 runt:4; 1239 __u8 trunc:1; 1240 __u8 err:1; 1241 __u8:6; 1242 #endif 1243 __be16 rsvd; 1244 __be16 len; 1245 __be64 tstamp; 1246 __be64 rsvd1; 1247 }; 1248 1249 struct cpl_l2t_write_req { 1250 WR_HDR; 1251 union opcode_tid ot; 1252 __be16 params; 1253 __be16 l2t_idx; 1254 __be16 vlan; 1255 u8 dst_mac[6]; 1256 }; 1257 1258 /* cpl_l2t_write_req.params fields */ 1259 #define L2T_W_INFO_S 2 1260 #define L2T_W_INFO_V(x) ((x) << L2T_W_INFO_S) 1261 1262 #define L2T_W_PORT_S 8 1263 #define L2T_W_PORT_V(x) ((x) << L2T_W_PORT_S) 1264 1265 #define L2T_W_NOREPLY_S 15 1266 #define L2T_W_NOREPLY_V(x) ((x) << L2T_W_NOREPLY_S) 1267 #define L2T_W_NOREPLY_F L2T_W_NOREPLY_V(1U) 1268 1269 #define CPL_L2T_VLAN_NONE 0xfff 1270 1271 struct cpl_l2t_write_rpl { 1272 union opcode_tid ot; 1273 u8 status; 1274 u8 rsvd[3]; 1275 }; 1276 1277 struct cpl_smt_write_req { 1278 WR_HDR; 1279 union opcode_tid ot; 1280 __be32 params; 1281 __be16 pfvf1; 1282 u8 src_mac1[6]; 1283 __be16 pfvf0; 1284 u8 src_mac0[6]; 1285 }; 1286 1287 struct cpl_t6_smt_write_req { 1288 WR_HDR; 1289 union opcode_tid ot; 1290 __be32 params; 1291 __be64 tag; 1292 __be16 pfvf0; 1293 u8 src_mac0[6]; 1294 __be32 local_ip; 1295 __be32 rsvd; 1296 }; 1297 1298 struct cpl_smt_write_rpl { 1299 union opcode_tid ot; 1300 u8 status; 1301 u8 rsvd[3]; 1302 }; 1303 1304 /* cpl_smt_{read,write}_req.params fields */ 1305 #define SMTW_OVLAN_IDX_S 16 1306 #define SMTW_OVLAN_IDX_V(x) ((x) << SMTW_OVLAN_IDX_S) 1307 1308 #define SMTW_IDX_S 20 1309 #define SMTW_IDX_V(x) ((x) << SMTW_IDX_S) 1310 1311 #define SMTW_NORPL_S 31 1312 #define SMTW_NORPL_V(x) ((x) << SMTW_NORPL_S) 1313 #define SMTW_NORPL_F SMTW_NORPL_V(1U) 1314 1315 struct cpl_rdma_terminate { 1316 union opcode_tid ot; 1317 __be16 rsvd; 1318 __be16 len; 1319 }; 1320 1321 struct cpl_sge_egr_update { 1322 __be32 opcode_qid; 1323 __be16 cidx; 1324 __be16 pidx; 1325 }; 1326 1327 /* cpl_sge_egr_update.ot fields */ 1328 #define EGR_QID_S 0 1329 #define EGR_QID_M 0x1FFFF 1330 #define EGR_QID_G(x) (((x) >> EGR_QID_S) & EGR_QID_M) 1331 1332 /* cpl_fw*.type values */ 1333 enum { 1334 FW_TYPE_CMD_RPL = 0, 1335 FW_TYPE_WR_RPL = 1, 1336 FW_TYPE_CQE = 2, 1337 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3, 1338 FW_TYPE_RSSCPL = 4, 1339 }; 1340 1341 struct cpl_fw4_pld { 1342 u8 opcode; 1343 u8 rsvd0[3]; 1344 u8 type; 1345 u8 rsvd1; 1346 __be16 len; 1347 __be64 data; 1348 __be64 rsvd2; 1349 }; 1350 1351 struct cpl_fw6_pld { 1352 u8 opcode; 1353 u8 rsvd[5]; 1354 __be16 len; 1355 __be64 data[4]; 1356 }; 1357 1358 struct cpl_fw4_msg { 1359 u8 opcode; 1360 u8 type; 1361 __be16 rsvd0; 1362 __be32 rsvd1; 1363 __be64 data[2]; 1364 }; 1365 1366 struct cpl_fw4_ack { 1367 union opcode_tid ot; 1368 u8 credits; 1369 u8 rsvd0[2]; 1370 u8 seq_vld; 1371 __be32 snd_nxt; 1372 __be32 snd_una; 1373 __be64 rsvd1; 1374 }; 1375 1376 enum { 1377 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1, /* seqn valid */ 1378 CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */ 1379 CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */ 1380 }; 1381 1382 struct cpl_fw6_msg { 1383 u8 opcode; 1384 u8 type; 1385 __be16 rsvd0; 1386 __be32 rsvd1; 1387 __be64 data[4]; 1388 }; 1389 1390 /* cpl_fw6_msg.type values */ 1391 enum { 1392 FW6_TYPE_CMD_RPL = 0, 1393 FW6_TYPE_WR_RPL = 1, 1394 FW6_TYPE_CQE = 2, 1395 FW6_TYPE_OFLD_CONNECTION_WR_RPL = 3, 1396 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL, 1397 }; 1398 1399 struct cpl_fw6_msg_ofld_connection_wr_rpl { 1400 __u64 cookie; 1401 __be32 tid; /* or atid in case of active failure */ 1402 __u8 t_state; 1403 __u8 retval; 1404 __u8 rsvd[2]; 1405 }; 1406 1407 struct cpl_tx_data { 1408 union opcode_tid ot; 1409 __be32 len; 1410 __be32 rsvd; 1411 __be32 flags; 1412 }; 1413 1414 /* cpl_tx_data.flags field */ 1415 #define TX_FORCE_S 13 1416 #define TX_FORCE_V(x) ((x) << TX_FORCE_S) 1417 1418 #define T6_TX_FORCE_S 20 1419 #define T6_TX_FORCE_V(x) ((x) << T6_TX_FORCE_S) 1420 #define T6_TX_FORCE_F T6_TX_FORCE_V(1U) 1421 1422 enum { 1423 ULP_TX_MEM_READ = 2, 1424 ULP_TX_MEM_WRITE = 3, 1425 ULP_TX_PKT = 4 1426 }; 1427 1428 enum { 1429 ULP_TX_SC_NOOP = 0x80, 1430 ULP_TX_SC_IMM = 0x81, 1431 ULP_TX_SC_DSGL = 0x82, 1432 ULP_TX_SC_ISGL = 0x83 1433 }; 1434 1435 #define ULPTX_CMD_S 24 1436 #define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S) 1437 1438 struct ulptx_sge_pair { 1439 __be32 len[2]; 1440 __be64 addr[2]; 1441 }; 1442 1443 struct ulptx_sgl { 1444 __be32 cmd_nsge; 1445 __be32 len0; 1446 __be64 addr0; 1447 struct ulptx_sge_pair sge[0]; 1448 }; 1449 1450 struct ulptx_idata { 1451 __be32 cmd_more; 1452 __be32 len; 1453 }; 1454 1455 struct ulp_txpkt { 1456 __be32 cmd_dest; 1457 __be32 len; 1458 }; 1459 1460 #define ULPTX_CMD_S 24 1461 #define ULPTX_CMD_M 0xFF 1462 #define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S) 1463 1464 #define ULPTX_NSGE_S 0 1465 #define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S) 1466 1467 #define ULPTX_MORE_S 23 1468 #define ULPTX_MORE_V(x) ((x) << ULPTX_MORE_S) 1469 #define ULPTX_MORE_F ULPTX_MORE_V(1U) 1470 1471 #define ULP_TXPKT_DEST_S 16 1472 #define ULP_TXPKT_DEST_M 0x3 1473 #define ULP_TXPKT_DEST_V(x) ((x) << ULP_TXPKT_DEST_S) 1474 1475 #define ULP_TXPKT_FID_S 4 1476 #define ULP_TXPKT_FID_M 0x7ff 1477 #define ULP_TXPKT_FID_V(x) ((x) << ULP_TXPKT_FID_S) 1478 1479 #define ULP_TXPKT_RO_S 3 1480 #define ULP_TXPKT_RO_V(x) ((x) << ULP_TXPKT_RO_S) 1481 #define ULP_TXPKT_RO_F ULP_TXPKT_RO_V(1U) 1482 1483 enum cpl_tx_tnl_lso_type { 1484 TX_TNL_TYPE_OPAQUE, 1485 TX_TNL_TYPE_NVGRE, 1486 TX_TNL_TYPE_VXLAN, 1487 TX_TNL_TYPE_GENEVE, 1488 }; 1489 1490 struct cpl_tx_tnl_lso { 1491 __be32 op_to_IpIdSplitOut; 1492 __be16 IpIdOffsetOut; 1493 __be16 UdpLenSetOut_to_TnlHdrLen; 1494 __be64 r1; 1495 __be32 Flow_to_TcpHdrLen; 1496 __be16 IpIdOffset; 1497 __be16 IpIdSplit_to_Mss; 1498 __be32 TCPSeqOffset; 1499 __be32 EthLenOffset_Size; 1500 /* encapsulated CPL (TX_PKT_XT) follows here */ 1501 }; 1502 1503 #define CPL_TX_TNL_LSO_OPCODE_S 24 1504 #define CPL_TX_TNL_LSO_OPCODE_M 0xff 1505 #define CPL_TX_TNL_LSO_OPCODE_V(x) ((x) << CPL_TX_TNL_LSO_OPCODE_S) 1506 #define CPL_TX_TNL_LSO_OPCODE_G(x) \ 1507 (((x) >> CPL_TX_TNL_LSO_OPCODE_S) & CPL_TX_TNL_LSO_OPCODE_M) 1508 1509 #define CPL_TX_TNL_LSO_FIRST_S 23 1510 #define CPL_TX_TNL_LSO_FIRST_M 0x1 1511 #define CPL_TX_TNL_LSO_FIRST_V(x) ((x) << CPL_TX_TNL_LSO_FIRST_S) 1512 #define CPL_TX_TNL_LSO_FIRST_G(x) \ 1513 (((x) >> CPL_TX_TNL_LSO_FIRST_S) & CPL_TX_TNL_LSO_FIRST_M) 1514 #define CPL_TX_TNL_LSO_FIRST_F CPL_TX_TNL_LSO_FIRST_V(1U) 1515 1516 #define CPL_TX_TNL_LSO_LAST_S 22 1517 #define CPL_TX_TNL_LSO_LAST_M 0x1 1518 #define CPL_TX_TNL_LSO_LAST_V(x) ((x) << CPL_TX_TNL_LSO_LAST_S) 1519 #define CPL_TX_TNL_LSO_LAST_G(x) \ 1520 (((x) >> CPL_TX_TNL_LSO_LAST_S) & CPL_TX_TNL_LSO_LAST_M) 1521 #define CPL_TX_TNL_LSO_LAST_F CPL_TX_TNL_LSO_LAST_V(1U) 1522 1523 #define CPL_TX_TNL_LSO_ETHHDRLENXOUT_S 21 1524 #define CPL_TX_TNL_LSO_ETHHDRLENXOUT_M 0x1 1525 #define CPL_TX_TNL_LSO_ETHHDRLENXOUT_V(x) \ 1526 ((x) << CPL_TX_TNL_LSO_ETHHDRLENXOUT_S) 1527 #define CPL_TX_TNL_LSO_ETHHDRLENXOUT_G(x) \ 1528 (((x) >> CPL_TX_TNL_LSO_ETHHDRLENXOUT_S) & \ 1529 CPL_TX_TNL_LSO_ETHHDRLENXOUT_M) 1530 #define CPL_TX_TNL_LSO_ETHHDRLENXOUT_F CPL_TX_TNL_LSO_ETHHDRLENXOUT_V(1U) 1531 1532 #define CPL_TX_TNL_LSO_IPV6OUT_S 20 1533 #define CPL_TX_TNL_LSO_IPV6OUT_M 0x1 1534 #define CPL_TX_TNL_LSO_IPV6OUT_V(x) ((x) << CPL_TX_TNL_LSO_IPV6OUT_S) 1535 #define CPL_TX_TNL_LSO_IPV6OUT_G(x) \ 1536 (((x) >> CPL_TX_TNL_LSO_IPV6OUT_S) & CPL_TX_TNL_LSO_IPV6OUT_M) 1537 #define CPL_TX_TNL_LSO_IPV6OUT_F CPL_TX_TNL_LSO_IPV6OUT_V(1U) 1538 1539 #define CPL_TX_TNL_LSO_ETHHDRLEN_S 16 1540 #define CPL_TX_TNL_LSO_ETHHDRLEN_M 0xf 1541 #define CPL_TX_TNL_LSO_ETHHDRLEN_V(x) ((x) << CPL_TX_TNL_LSO_ETHHDRLEN_S) 1542 #define CPL_TX_TNL_LSO_ETHHDRLEN_G(x) \ 1543 (((x) >> CPL_TX_TNL_LSO_ETHHDRLEN_S) & CPL_TX_TNL_LSO_ETHHDRLEN_M) 1544 1545 #define CPL_TX_TNL_LSO_IPHDRLEN_S 4 1546 #define CPL_TX_TNL_LSO_IPHDRLEN_M 0xfff 1547 #define CPL_TX_TNL_LSO_IPHDRLEN_V(x) ((x) << CPL_TX_TNL_LSO_IPHDRLEN_S) 1548 #define CPL_TX_TNL_LSO_IPHDRLEN_G(x) \ 1549 (((x) >> CPL_TX_TNL_LSO_IPHDRLEN_S) & CPL_TX_TNL_LSO_IPHDRLEN_M) 1550 1551 #define CPL_TX_TNL_LSO_TCPHDRLEN_S 0 1552 #define CPL_TX_TNL_LSO_TCPHDRLEN_M 0xf 1553 #define CPL_TX_TNL_LSO_TCPHDRLEN_V(x) ((x) << CPL_TX_TNL_LSO_TCPHDRLEN_S) 1554 #define CPL_TX_TNL_LSO_TCPHDRLEN_G(x) \ 1555 (((x) >> CPL_TX_TNL_LSO_TCPHDRLEN_S) & CPL_TX_TNL_LSO_TCPHDRLEN_M) 1556 1557 #define CPL_TX_TNL_LSO_MSS_S 0 1558 #define CPL_TX_TNL_LSO_MSS_M 0x3fff 1559 #define CPL_TX_TNL_LSO_MSS_V(x) ((x) << CPL_TX_TNL_LSO_MSS_S) 1560 #define CPL_TX_TNL_LSO_MSS_G(x) \ 1561 (((x) >> CPL_TX_TNL_LSO_MSS_S) & CPL_TX_TNL_LSO_MSS_M) 1562 1563 #define CPL_TX_TNL_LSO_SIZE_S 0 1564 #define CPL_TX_TNL_LSO_SIZE_M 0xfffffff 1565 #define CPL_TX_TNL_LSO_SIZE_V(x) ((x) << CPL_TX_TNL_LSO_SIZE_S) 1566 #define CPL_TX_TNL_LSO_SIZE_G(x) \ 1567 (((x) >> CPL_TX_TNL_LSO_SIZE_S) & CPL_TX_TNL_LSO_SIZE_M) 1568 1569 #define CPL_TX_TNL_LSO_ETHHDRLENOUT_S 16 1570 #define CPL_TX_TNL_LSO_ETHHDRLENOUT_M 0xf 1571 #define CPL_TX_TNL_LSO_ETHHDRLENOUT_V(x) \ 1572 ((x) << CPL_TX_TNL_LSO_ETHHDRLENOUT_S) 1573 #define CPL_TX_TNL_LSO_ETHHDRLENOUT_G(x) \ 1574 (((x) >> CPL_TX_TNL_LSO_ETHHDRLENOUT_S) & CPL_TX_TNL_LSO_ETHHDRLENOUT_M) 1575 1576 #define CPL_TX_TNL_LSO_IPHDRLENOUT_S 4 1577 #define CPL_TX_TNL_LSO_IPHDRLENOUT_M 0xfff 1578 #define CPL_TX_TNL_LSO_IPHDRLENOUT_V(x) ((x) << CPL_TX_TNL_LSO_IPHDRLENOUT_S) 1579 #define CPL_TX_TNL_LSO_IPHDRLENOUT_G(x) \ 1580 (((x) >> CPL_TX_TNL_LSO_IPHDRLENOUT_S) & CPL_TX_TNL_LSO_IPHDRLENOUT_M) 1581 1582 #define CPL_TX_TNL_LSO_IPHDRCHKOUT_S 3 1583 #define CPL_TX_TNL_LSO_IPHDRCHKOUT_M 0x1 1584 #define CPL_TX_TNL_LSO_IPHDRCHKOUT_V(x) ((x) << CPL_TX_TNL_LSO_IPHDRCHKOUT_S) 1585 #define CPL_TX_TNL_LSO_IPHDRCHKOUT_G(x) \ 1586 (((x) >> CPL_TX_TNL_LSO_IPHDRCHKOUT_S) & CPL_TX_TNL_LSO_IPHDRCHKOUT_M) 1587 #define CPL_TX_TNL_LSO_IPHDRCHKOUT_F CPL_TX_TNL_LSO_IPHDRCHKOUT_V(1U) 1588 1589 #define CPL_TX_TNL_LSO_IPLENSETOUT_S 2 1590 #define CPL_TX_TNL_LSO_IPLENSETOUT_M 0x1 1591 #define CPL_TX_TNL_LSO_IPLENSETOUT_V(x) ((x) << CPL_TX_TNL_LSO_IPLENSETOUT_S) 1592 #define CPL_TX_TNL_LSO_IPLENSETOUT_G(x) \ 1593 (((x) >> CPL_TX_TNL_LSO_IPLENSETOUT_S) & CPL_TX_TNL_LSO_IPLENSETOUT_M) 1594 #define CPL_TX_TNL_LSO_IPLENSETOUT_F CPL_TX_TNL_LSO_IPLENSETOUT_V(1U) 1595 1596 #define CPL_TX_TNL_LSO_IPIDINCOUT_S 1 1597 #define CPL_TX_TNL_LSO_IPIDINCOUT_M 0x1 1598 #define CPL_TX_TNL_LSO_IPIDINCOUT_V(x) ((x) << CPL_TX_TNL_LSO_IPIDINCOUT_S) 1599 #define CPL_TX_TNL_LSO_IPIDINCOUT_G(x) \ 1600 (((x) >> CPL_TX_TNL_LSO_IPIDINCOUT_S) & CPL_TX_TNL_LSO_IPIDINCOUT_M) 1601 #define CPL_TX_TNL_LSO_IPIDINCOUT_F CPL_TX_TNL_LSO_IPIDINCOUT_V(1U) 1602 1603 #define CPL_TX_TNL_LSO_UDPCHKCLROUT_S 14 1604 #define CPL_TX_TNL_LSO_UDPCHKCLROUT_M 0x1 1605 #define CPL_TX_TNL_LSO_UDPCHKCLROUT_V(x) \ 1606 ((x) << CPL_TX_TNL_LSO_UDPCHKCLROUT_S) 1607 #define CPL_TX_TNL_LSO_UDPCHKCLROUT_G(x) \ 1608 (((x) >> CPL_TX_TNL_LSO_UDPCHKCLROUT_S) & \ 1609 CPL_TX_TNL_LSO_UDPCHKCLROUT_M) 1610 #define CPL_TX_TNL_LSO_UDPCHKCLROUT_F CPL_TX_TNL_LSO_UDPCHKCLROUT_V(1U) 1611 1612 #define CPL_TX_TNL_LSO_UDPLENSETOUT_S 15 1613 #define CPL_TX_TNL_LSO_UDPLENSETOUT_M 0x1 1614 #define CPL_TX_TNL_LSO_UDPLENSETOUT_V(x) \ 1615 ((x) << CPL_TX_TNL_LSO_UDPLENSETOUT_S) 1616 #define CPL_TX_TNL_LSO_UDPLENSETOUT_G(x) \ 1617 (((x) >> CPL_TX_TNL_LSO_UDPLENSETOUT_S) & \ 1618 CPL_TX_TNL_LSO_UDPLENSETOUT_M) 1619 #define CPL_TX_TNL_LSO_UDPLENSETOUT_F CPL_TX_TNL_LSO_UDPLENSETOUT_V(1U) 1620 1621 #define CPL_TX_TNL_LSO_TNLTYPE_S 12 1622 #define CPL_TX_TNL_LSO_TNLTYPE_M 0x3 1623 #define CPL_TX_TNL_LSO_TNLTYPE_V(x) ((x) << CPL_TX_TNL_LSO_TNLTYPE_S) 1624 #define CPL_TX_TNL_LSO_TNLTYPE_G(x) \ 1625 (((x) >> CPL_TX_TNL_LSO_TNLTYPE_S) & CPL_TX_TNL_LSO_TNLTYPE_M) 1626 1627 #define S_CPL_TX_TNL_LSO_ETHHDRLEN 16 1628 #define M_CPL_TX_TNL_LSO_ETHHDRLEN 0xf 1629 #define V_CPL_TX_TNL_LSO_ETHHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_ETHHDRLEN) 1630 #define G_CPL_TX_TNL_LSO_ETHHDRLEN(x) \ 1631 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLEN) & M_CPL_TX_TNL_LSO_ETHHDRLEN) 1632 1633 #define CPL_TX_TNL_LSO_TNLHDRLEN_S 0 1634 #define CPL_TX_TNL_LSO_TNLHDRLEN_M 0xfff 1635 #define CPL_TX_TNL_LSO_TNLHDRLEN_V(x) ((x) << CPL_TX_TNL_LSO_TNLHDRLEN_S) 1636 #define CPL_TX_TNL_LSO_TNLHDRLEN_G(x) \ 1637 (((x) >> CPL_TX_TNL_LSO_TNLHDRLEN_S) & CPL_TX_TNL_LSO_TNLHDRLEN_M) 1638 1639 #define CPL_TX_TNL_LSO_IPV6_S 20 1640 #define CPL_TX_TNL_LSO_IPV6_M 0x1 1641 #define CPL_TX_TNL_LSO_IPV6_V(x) ((x) << CPL_TX_TNL_LSO_IPV6_S) 1642 #define CPL_TX_TNL_LSO_IPV6_G(x) \ 1643 (((x) >> CPL_TX_TNL_LSO_IPV6_S) & CPL_TX_TNL_LSO_IPV6_M) 1644 #define CPL_TX_TNL_LSO_IPV6_F CPL_TX_TNL_LSO_IPV6_V(1U) 1645 1646 #define ULP_TX_SC_MORE_S 23 1647 #define ULP_TX_SC_MORE_V(x) ((x) << ULP_TX_SC_MORE_S) 1648 #define ULP_TX_SC_MORE_F ULP_TX_SC_MORE_V(1U) 1649 1650 struct ulp_mem_io { 1651 WR_HDR; 1652 __be32 cmd; 1653 __be32 len16; /* command length */ 1654 __be32 dlen; /* data length in 32-byte units */ 1655 __be32 lock_addr; 1656 }; 1657 1658 #define ULP_MEMIO_LOCK_S 31 1659 #define ULP_MEMIO_LOCK_V(x) ((x) << ULP_MEMIO_LOCK_S) 1660 #define ULP_MEMIO_LOCK_F ULP_MEMIO_LOCK_V(1U) 1661 1662 /* additional ulp_mem_io.cmd fields */ 1663 #define ULP_MEMIO_ORDER_S 23 1664 #define ULP_MEMIO_ORDER_V(x) ((x) << ULP_MEMIO_ORDER_S) 1665 #define ULP_MEMIO_ORDER_F ULP_MEMIO_ORDER_V(1U) 1666 1667 #define T5_ULP_MEMIO_IMM_S 23 1668 #define T5_ULP_MEMIO_IMM_V(x) ((x) << T5_ULP_MEMIO_IMM_S) 1669 #define T5_ULP_MEMIO_IMM_F T5_ULP_MEMIO_IMM_V(1U) 1670 1671 #define T5_ULP_MEMIO_ORDER_S 22 1672 #define T5_ULP_MEMIO_ORDER_V(x) ((x) << T5_ULP_MEMIO_ORDER_S) 1673 #define T5_ULP_MEMIO_ORDER_F T5_ULP_MEMIO_ORDER_V(1U) 1674 1675 #define T5_ULP_MEMIO_FID_S 4 1676 #define T5_ULP_MEMIO_FID_M 0x7ff 1677 #define T5_ULP_MEMIO_FID_V(x) ((x) << T5_ULP_MEMIO_FID_S) 1678 1679 /* ulp_mem_io.lock_addr fields */ 1680 #define ULP_MEMIO_ADDR_S 0 1681 #define ULP_MEMIO_ADDR_V(x) ((x) << ULP_MEMIO_ADDR_S) 1682 1683 /* ulp_mem_io.dlen fields */ 1684 #define ULP_MEMIO_DATA_LEN_S 0 1685 #define ULP_MEMIO_DATA_LEN_V(x) ((x) << ULP_MEMIO_DATA_LEN_S) 1686 1687 #define ULPTX_NSGE_S 0 1688 #define ULPTX_NSGE_M 0xFFFF 1689 #define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S) 1690 #define ULPTX_NSGE_G(x) (((x) >> ULPTX_NSGE_S) & ULPTX_NSGE_M) 1691 1692 struct ulptx_sc_memrd { 1693 __be32 cmd_to_len; 1694 __be32 addr; 1695 }; 1696 1697 #define ULP_TXPKT_DATAMODIFY_S 23 1698 #define ULP_TXPKT_DATAMODIFY_M 0x1 1699 #define ULP_TXPKT_DATAMODIFY_V(x) ((x) << ULP_TXPKT_DATAMODIFY_S) 1700 #define ULP_TXPKT_DATAMODIFY_G(x) \ 1701 (((x) >> ULP_TXPKT_DATAMODIFY_S) & ULP_TXPKT_DATAMODIFY__M) 1702 #define ULP_TXPKT_DATAMODIFY_F ULP_TXPKT_DATAMODIFY_V(1U) 1703 1704 #define ULP_TXPKT_CHANNELID_S 22 1705 #define ULP_TXPKT_CHANNELID_M 0x1 1706 #define ULP_TXPKT_CHANNELID_V(x) ((x) << ULP_TXPKT_CHANNELID_S) 1707 #define ULP_TXPKT_CHANNELID_G(x) \ 1708 (((x) >> ULP_TXPKT_CHANNELID_S) & ULP_TXPKT_CHANNELID_M) 1709 #define ULP_TXPKT_CHANNELID_F ULP_TXPKT_CHANNELID_V(1U) 1710 1711 #define SCMD_SEQ_NO_CTRL_S 29 1712 #define SCMD_SEQ_NO_CTRL_M 0x3 1713 #define SCMD_SEQ_NO_CTRL_V(x) ((x) << SCMD_SEQ_NO_CTRL_S) 1714 #define SCMD_SEQ_NO_CTRL_G(x) \ 1715 (((x) >> SCMD_SEQ_NO_CTRL_S) & SCMD_SEQ_NO_CTRL_M) 1716 1717 /* StsFieldPrsnt- Status field at the end of the TLS PDU */ 1718 #define SCMD_STATUS_PRESENT_S 28 1719 #define SCMD_STATUS_PRESENT_M 0x1 1720 #define SCMD_STATUS_PRESENT_V(x) ((x) << SCMD_STATUS_PRESENT_S) 1721 #define SCMD_STATUS_PRESENT_G(x) \ 1722 (((x) >> SCMD_STATUS_PRESENT_S) & SCMD_STATUS_PRESENT_M) 1723 #define SCMD_STATUS_PRESENT_F SCMD_STATUS_PRESENT_V(1U) 1724 1725 /* ProtoVersion - Protocol Version 0: 1.2, 1:1.1, 2:DTLS, 3:Generic, 1726 * 3-15: Reserved. 1727 */ 1728 #define SCMD_PROTO_VERSION_S 24 1729 #define SCMD_PROTO_VERSION_M 0xf 1730 #define SCMD_PROTO_VERSION_V(x) ((x) << SCMD_PROTO_VERSION_S) 1731 #define SCMD_PROTO_VERSION_G(x) \ 1732 (((x) >> SCMD_PROTO_VERSION_S) & SCMD_PROTO_VERSION_M) 1733 1734 /* EncDecCtrl - Encryption/Decryption Control. 0: Encrypt, 1: Decrypt */ 1735 #define SCMD_ENC_DEC_CTRL_S 23 1736 #define SCMD_ENC_DEC_CTRL_M 0x1 1737 #define SCMD_ENC_DEC_CTRL_V(x) ((x) << SCMD_ENC_DEC_CTRL_S) 1738 #define SCMD_ENC_DEC_CTRL_G(x) \ 1739 (((x) >> SCMD_ENC_DEC_CTRL_S) & SCMD_ENC_DEC_CTRL_M) 1740 #define SCMD_ENC_DEC_CTRL_F SCMD_ENC_DEC_CTRL_V(1U) 1741 1742 /* CipherAuthSeqCtrl - Cipher Authentication Sequence Control. */ 1743 #define SCMD_CIPH_AUTH_SEQ_CTRL_S 22 1744 #define SCMD_CIPH_AUTH_SEQ_CTRL_M 0x1 1745 #define SCMD_CIPH_AUTH_SEQ_CTRL_V(x) \ 1746 ((x) << SCMD_CIPH_AUTH_SEQ_CTRL_S) 1747 #define SCMD_CIPH_AUTH_SEQ_CTRL_G(x) \ 1748 (((x) >> SCMD_CIPH_AUTH_SEQ_CTRL_S) & SCMD_CIPH_AUTH_SEQ_CTRL_M) 1749 #define SCMD_CIPH_AUTH_SEQ_CTRL_F SCMD_CIPH_AUTH_SEQ_CTRL_V(1U) 1750 1751 /* CiphMode - Cipher Mode. 0: NOP, 1:AES-CBC, 2:AES-GCM, 3:AES-CTR, 1752 * 4:Generic-AES, 5-15: Reserved. 1753 */ 1754 #define SCMD_CIPH_MODE_S 18 1755 #define SCMD_CIPH_MODE_M 0xf 1756 #define SCMD_CIPH_MODE_V(x) ((x) << SCMD_CIPH_MODE_S) 1757 #define SCMD_CIPH_MODE_G(x) \ 1758 (((x) >> SCMD_CIPH_MODE_S) & SCMD_CIPH_MODE_M) 1759 1760 /* AuthMode - Auth Mode. 0: NOP, 1:SHA1, 2:SHA2-224, 3:SHA2-256 1761 * 4-15: Reserved 1762 */ 1763 #define SCMD_AUTH_MODE_S 14 1764 #define SCMD_AUTH_MODE_M 0xf 1765 #define SCMD_AUTH_MODE_V(x) ((x) << SCMD_AUTH_MODE_S) 1766 #define SCMD_AUTH_MODE_G(x) \ 1767 (((x) >> SCMD_AUTH_MODE_S) & SCMD_AUTH_MODE_M) 1768 1769 /* HmacCtrl - HMAC Control. 0:NOP, 1:No truncation, 2:Support HMAC Truncation 1770 * per RFC 4366, 3:IPSec 96 bits, 4-7:Reserved 1771 */ 1772 #define SCMD_HMAC_CTRL_S 11 1773 #define SCMD_HMAC_CTRL_M 0x7 1774 #define SCMD_HMAC_CTRL_V(x) ((x) << SCMD_HMAC_CTRL_S) 1775 #define SCMD_HMAC_CTRL_G(x) \ 1776 (((x) >> SCMD_HMAC_CTRL_S) & SCMD_HMAC_CTRL_M) 1777 1778 /* IvSize - IV size in units of 2 bytes */ 1779 #define SCMD_IV_SIZE_S 7 1780 #define SCMD_IV_SIZE_M 0xf 1781 #define SCMD_IV_SIZE_V(x) ((x) << SCMD_IV_SIZE_S) 1782 #define SCMD_IV_SIZE_G(x) \ 1783 (((x) >> SCMD_IV_SIZE_S) & SCMD_IV_SIZE_M) 1784 1785 /* NumIVs - Number of IVs */ 1786 #define SCMD_NUM_IVS_S 0 1787 #define SCMD_NUM_IVS_M 0x7f 1788 #define SCMD_NUM_IVS_V(x) ((x) << SCMD_NUM_IVS_S) 1789 #define SCMD_NUM_IVS_G(x) \ 1790 (((x) >> SCMD_NUM_IVS_S) & SCMD_NUM_IVS_M) 1791 1792 /* EnbDbgId - If this is enabled upper 20 (63:44) bits if SeqNumber 1793 * (below) are used as Cid (connection id for debug status), these 1794 * bits are padded to zero for forming the 64 bit 1795 * sequence number for TLS 1796 */ 1797 #define SCMD_ENB_DBGID_S 31 1798 #define SCMD_ENB_DBGID_M 0x1 1799 #define SCMD_ENB_DBGID_V(x) ((x) << SCMD_ENB_DBGID_S) 1800 #define SCMD_ENB_DBGID_G(x) \ 1801 (((x) >> SCMD_ENB_DBGID_S) & SCMD_ENB_DBGID_M) 1802 1803 /* IV generation in SW. */ 1804 #define SCMD_IV_GEN_CTRL_S 30 1805 #define SCMD_IV_GEN_CTRL_M 0x1 1806 #define SCMD_IV_GEN_CTRL_V(x) ((x) << SCMD_IV_GEN_CTRL_S) 1807 #define SCMD_IV_GEN_CTRL_G(x) \ 1808 (((x) >> SCMD_IV_GEN_CTRL_S) & SCMD_IV_GEN_CTRL_M) 1809 #define SCMD_IV_GEN_CTRL_F SCMD_IV_GEN_CTRL_V(1U) 1810 1811 /* More frags */ 1812 #define SCMD_MORE_FRAGS_S 20 1813 #define SCMD_MORE_FRAGS_M 0x1 1814 #define SCMD_MORE_FRAGS_V(x) ((x) << SCMD_MORE_FRAGS_S) 1815 #define SCMD_MORE_FRAGS_G(x) (((x) >> SCMD_MORE_FRAGS_S) & SCMD_MORE_FRAGS_M) 1816 1817 /*last frag */ 1818 #define SCMD_LAST_FRAG_S 19 1819 #define SCMD_LAST_FRAG_M 0x1 1820 #define SCMD_LAST_FRAG_V(x) ((x) << SCMD_LAST_FRAG_S) 1821 #define SCMD_LAST_FRAG_G(x) (((x) >> SCMD_LAST_FRAG_S) & SCMD_LAST_FRAG_M) 1822 1823 /* TlsCompPdu */ 1824 #define SCMD_TLS_COMPPDU_S 18 1825 #define SCMD_TLS_COMPPDU_M 0x1 1826 #define SCMD_TLS_COMPPDU_V(x) ((x) << SCMD_TLS_COMPPDU_S) 1827 #define SCMD_TLS_COMPPDU_G(x) (((x) >> SCMD_TLS_COMPPDU_S) & SCMD_TLS_COMPPDU_M) 1828 1829 /* KeyCntxtInline - Key context inline after the scmd OR PayloadOnly*/ 1830 #define SCMD_KEY_CTX_INLINE_S 17 1831 #define SCMD_KEY_CTX_INLINE_M 0x1 1832 #define SCMD_KEY_CTX_INLINE_V(x) ((x) << SCMD_KEY_CTX_INLINE_S) 1833 #define SCMD_KEY_CTX_INLINE_G(x) \ 1834 (((x) >> SCMD_KEY_CTX_INLINE_S) & SCMD_KEY_CTX_INLINE_M) 1835 #define SCMD_KEY_CTX_INLINE_F SCMD_KEY_CTX_INLINE_V(1U) 1836 1837 /* TLSFragEnable - 0: Host created TLS PDUs, 1: TLS Framgmentation in ASIC */ 1838 #define SCMD_TLS_FRAG_ENABLE_S 16 1839 #define SCMD_TLS_FRAG_ENABLE_M 0x1 1840 #define SCMD_TLS_FRAG_ENABLE_V(x) ((x) << SCMD_TLS_FRAG_ENABLE_S) 1841 #define SCMD_TLS_FRAG_ENABLE_G(x) \ 1842 (((x) >> SCMD_TLS_FRAG_ENABLE_S) & SCMD_TLS_FRAG_ENABLE_M) 1843 #define SCMD_TLS_FRAG_ENABLE_F SCMD_TLS_FRAG_ENABLE_V(1U) 1844 1845 /* MacOnly - Only send the MAC and discard PDU. This is valid for hash only 1846 * modes, in this case TLS_TX will drop the PDU and only 1847 * send back the MAC bytes. 1848 */ 1849 #define SCMD_MAC_ONLY_S 15 1850 #define SCMD_MAC_ONLY_M 0x1 1851 #define SCMD_MAC_ONLY_V(x) ((x) << SCMD_MAC_ONLY_S) 1852 #define SCMD_MAC_ONLY_G(x) \ 1853 (((x) >> SCMD_MAC_ONLY_S) & SCMD_MAC_ONLY_M) 1854 #define SCMD_MAC_ONLY_F SCMD_MAC_ONLY_V(1U) 1855 1856 /* AadIVDrop - Drop the AAD and IV fields. Useful in protocols 1857 * which have complex AAD and IV formations Eg:AES-CCM 1858 */ 1859 #define SCMD_AADIVDROP_S 14 1860 #define SCMD_AADIVDROP_M 0x1 1861 #define SCMD_AADIVDROP_V(x) ((x) << SCMD_AADIVDROP_S) 1862 #define SCMD_AADIVDROP_G(x) \ 1863 (((x) >> SCMD_AADIVDROP_S) & SCMD_AADIVDROP_M) 1864 #define SCMD_AADIVDROP_F SCMD_AADIVDROP_V(1U) 1865 1866 /* HdrLength - Length of all headers excluding TLS header 1867 * present before start of crypto PDU/payload. 1868 */ 1869 #define SCMD_HDR_LEN_S 0 1870 #define SCMD_HDR_LEN_M 0x3fff 1871 #define SCMD_HDR_LEN_V(x) ((x) << SCMD_HDR_LEN_S) 1872 #define SCMD_HDR_LEN_G(x) \ 1873 (((x) >> SCMD_HDR_LEN_S) & SCMD_HDR_LEN_M) 1874 1875 struct cpl_tx_sec_pdu { 1876 __be32 op_ivinsrtofst; 1877 __be32 pldlen; 1878 __be32 aadstart_cipherstop_hi; 1879 __be32 cipherstop_lo_authinsert; 1880 __be32 seqno_numivs; 1881 __be32 ivgen_hdrlen; 1882 __be64 scmd1; 1883 }; 1884 1885 #define CPL_TX_SEC_PDU_OPCODE_S 24 1886 #define CPL_TX_SEC_PDU_OPCODE_M 0xff 1887 #define CPL_TX_SEC_PDU_OPCODE_V(x) ((x) << CPL_TX_SEC_PDU_OPCODE_S) 1888 #define CPL_TX_SEC_PDU_OPCODE_G(x) \ 1889 (((x) >> CPL_TX_SEC_PDU_OPCODE_S) & CPL_TX_SEC_PDU_OPCODE_M) 1890 1891 /* RX Channel Id */ 1892 #define CPL_TX_SEC_PDU_RXCHID_S 22 1893 #define CPL_TX_SEC_PDU_RXCHID_M 0x1 1894 #define CPL_TX_SEC_PDU_RXCHID_V(x) ((x) << CPL_TX_SEC_PDU_RXCHID_S) 1895 #define CPL_TX_SEC_PDU_RXCHID_G(x) \ 1896 (((x) >> CPL_TX_SEC_PDU_RXCHID_S) & CPL_TX_SEC_PDU_RXCHID_M) 1897 #define CPL_TX_SEC_PDU_RXCHID_F CPL_TX_SEC_PDU_RXCHID_V(1U) 1898 1899 /* Ack Follows */ 1900 #define CPL_TX_SEC_PDU_ACKFOLLOWS_S 21 1901 #define CPL_TX_SEC_PDU_ACKFOLLOWS_M 0x1 1902 #define CPL_TX_SEC_PDU_ACKFOLLOWS_V(x) ((x) << CPL_TX_SEC_PDU_ACKFOLLOWS_S) 1903 #define CPL_TX_SEC_PDU_ACKFOLLOWS_G(x) \ 1904 (((x) >> CPL_TX_SEC_PDU_ACKFOLLOWS_S) & CPL_TX_SEC_PDU_ACKFOLLOWS_M) 1905 #define CPL_TX_SEC_PDU_ACKFOLLOWS_F CPL_TX_SEC_PDU_ACKFOLLOWS_V(1U) 1906 1907 /* Loopback bit in cpl_tx_sec_pdu */ 1908 #define CPL_TX_SEC_PDU_ULPTXLPBK_S 20 1909 #define CPL_TX_SEC_PDU_ULPTXLPBK_M 0x1 1910 #define CPL_TX_SEC_PDU_ULPTXLPBK_V(x) ((x) << CPL_TX_SEC_PDU_ULPTXLPBK_S) 1911 #define CPL_TX_SEC_PDU_ULPTXLPBK_G(x) \ 1912 (((x) >> CPL_TX_SEC_PDU_ULPTXLPBK_S) & CPL_TX_SEC_PDU_ULPTXLPBK_M) 1913 #define CPL_TX_SEC_PDU_ULPTXLPBK_F CPL_TX_SEC_PDU_ULPTXLPBK_V(1U) 1914 1915 /* Length of cpl header encapsulated */ 1916 #define CPL_TX_SEC_PDU_CPLLEN_S 16 1917 #define CPL_TX_SEC_PDU_CPLLEN_M 0xf 1918 #define CPL_TX_SEC_PDU_CPLLEN_V(x) ((x) << CPL_TX_SEC_PDU_CPLLEN_S) 1919 #define CPL_TX_SEC_PDU_CPLLEN_G(x) \ 1920 (((x) >> CPL_TX_SEC_PDU_CPLLEN_S) & CPL_TX_SEC_PDU_CPLLEN_M) 1921 1922 /* PlaceHolder */ 1923 #define CPL_TX_SEC_PDU_PLACEHOLDER_S 10 1924 #define CPL_TX_SEC_PDU_PLACEHOLDER_M 0x1 1925 #define CPL_TX_SEC_PDU_PLACEHOLDER_V(x) ((x) << CPL_TX_SEC_PDU_PLACEHOLDER_S) 1926 #define CPL_TX_SEC_PDU_PLACEHOLDER_G(x) \ 1927 (((x) >> CPL_TX_SEC_PDU_PLACEHOLDER_S) & \ 1928 CPL_TX_SEC_PDU_PLACEHOLDER_M) 1929 1930 /* IvInsrtOffset: Insertion location for IV */ 1931 #define CPL_TX_SEC_PDU_IVINSRTOFST_S 0 1932 #define CPL_TX_SEC_PDU_IVINSRTOFST_M 0x3ff 1933 #define CPL_TX_SEC_PDU_IVINSRTOFST_V(x) ((x) << CPL_TX_SEC_PDU_IVINSRTOFST_S) 1934 #define CPL_TX_SEC_PDU_IVINSRTOFST_G(x) \ 1935 (((x) >> CPL_TX_SEC_PDU_IVINSRTOFST_S) & \ 1936 CPL_TX_SEC_PDU_IVINSRTOFST_M) 1937 1938 /* AadStartOffset: Offset in bytes for AAD start from 1939 * the first byte following the pkt headers (0-255 bytes) 1940 */ 1941 #define CPL_TX_SEC_PDU_AADSTART_S 24 1942 #define CPL_TX_SEC_PDU_AADSTART_M 0xff 1943 #define CPL_TX_SEC_PDU_AADSTART_V(x) ((x) << CPL_TX_SEC_PDU_AADSTART_S) 1944 #define CPL_TX_SEC_PDU_AADSTART_G(x) \ 1945 (((x) >> CPL_TX_SEC_PDU_AADSTART_S) & \ 1946 CPL_TX_SEC_PDU_AADSTART_M) 1947 1948 /* AadStopOffset: offset in bytes for AAD stop/end from the first byte following 1949 * the pkt headers (0-511 bytes) 1950 */ 1951 #define CPL_TX_SEC_PDU_AADSTOP_S 15 1952 #define CPL_TX_SEC_PDU_AADSTOP_M 0x1ff 1953 #define CPL_TX_SEC_PDU_AADSTOP_V(x) ((x) << CPL_TX_SEC_PDU_AADSTOP_S) 1954 #define CPL_TX_SEC_PDU_AADSTOP_G(x) \ 1955 (((x) >> CPL_TX_SEC_PDU_AADSTOP_S) & CPL_TX_SEC_PDU_AADSTOP_M) 1956 1957 /* CipherStartOffset: offset in bytes for encryption/decryption start from the 1958 * first byte following the pkt headers (0-1023 bytes) 1959 */ 1960 #define CPL_TX_SEC_PDU_CIPHERSTART_S 5 1961 #define CPL_TX_SEC_PDU_CIPHERSTART_M 0x3ff 1962 #define CPL_TX_SEC_PDU_CIPHERSTART_V(x) ((x) << CPL_TX_SEC_PDU_CIPHERSTART_S) 1963 #define CPL_TX_SEC_PDU_CIPHERSTART_G(x) \ 1964 (((x) >> CPL_TX_SEC_PDU_CIPHERSTART_S) & \ 1965 CPL_TX_SEC_PDU_CIPHERSTART_M) 1966 1967 /* CipherStopOffset: offset in bytes for encryption/decryption end 1968 * from end of the payload of this command (0-511 bytes) 1969 */ 1970 #define CPL_TX_SEC_PDU_CIPHERSTOP_HI_S 0 1971 #define CPL_TX_SEC_PDU_CIPHERSTOP_HI_M 0x1f 1972 #define CPL_TX_SEC_PDU_CIPHERSTOP_HI_V(x) \ 1973 ((x) << CPL_TX_SEC_PDU_CIPHERSTOP_HI_S) 1974 #define CPL_TX_SEC_PDU_CIPHERSTOP_HI_G(x) \ 1975 (((x) >> CPL_TX_SEC_PDU_CIPHERSTOP_HI_S) & \ 1976 CPL_TX_SEC_PDU_CIPHERSTOP_HI_M) 1977 1978 #define CPL_TX_SEC_PDU_CIPHERSTOP_LO_S 28 1979 #define CPL_TX_SEC_PDU_CIPHERSTOP_LO_M 0xf 1980 #define CPL_TX_SEC_PDU_CIPHERSTOP_LO_V(x) \ 1981 ((x) << CPL_TX_SEC_PDU_CIPHERSTOP_LO_S) 1982 #define CPL_TX_SEC_PDU_CIPHERSTOP_LO_G(x) \ 1983 (((x) >> CPL_TX_SEC_PDU_CIPHERSTOP_LO_S) & \ 1984 CPL_TX_SEC_PDU_CIPHERSTOP_LO_M) 1985 1986 /* AuthStartOffset: offset in bytes for authentication start from 1987 * the first byte following the pkt headers (0-1023) 1988 */ 1989 #define CPL_TX_SEC_PDU_AUTHSTART_S 18 1990 #define CPL_TX_SEC_PDU_AUTHSTART_M 0x3ff 1991 #define CPL_TX_SEC_PDU_AUTHSTART_V(x) ((x) << CPL_TX_SEC_PDU_AUTHSTART_S) 1992 #define CPL_TX_SEC_PDU_AUTHSTART_G(x) \ 1993 (((x) >> CPL_TX_SEC_PDU_AUTHSTART_S) & \ 1994 CPL_TX_SEC_PDU_AUTHSTART_M) 1995 1996 /* AuthStopOffset: offset in bytes for authentication 1997 * end from end of the payload of this command (0-511 Bytes) 1998 */ 1999 #define CPL_TX_SEC_PDU_AUTHSTOP_S 9 2000 #define CPL_TX_SEC_PDU_AUTHSTOP_M 0x1ff 2001 #define CPL_TX_SEC_PDU_AUTHSTOP_V(x) ((x) << CPL_TX_SEC_PDU_AUTHSTOP_S) 2002 #define CPL_TX_SEC_PDU_AUTHSTOP_G(x) \ 2003 (((x) >> CPL_TX_SEC_PDU_AUTHSTOP_S) & \ 2004 CPL_TX_SEC_PDU_AUTHSTOP_M) 2005 2006 /* AuthInsrtOffset: offset in bytes for authentication insertion 2007 * from end of the payload of this command (0-511 bytes) 2008 */ 2009 #define CPL_TX_SEC_PDU_AUTHINSERT_S 0 2010 #define CPL_TX_SEC_PDU_AUTHINSERT_M 0x1ff 2011 #define CPL_TX_SEC_PDU_AUTHINSERT_V(x) ((x) << CPL_TX_SEC_PDU_AUTHINSERT_S) 2012 #define CPL_TX_SEC_PDU_AUTHINSERT_G(x) \ 2013 (((x) >> CPL_TX_SEC_PDU_AUTHINSERT_S) & \ 2014 CPL_TX_SEC_PDU_AUTHINSERT_M) 2015 2016 struct cpl_rx_phys_dsgl { 2017 __be32 op_to_tid; 2018 __be32 pcirlxorder_to_noofsgentr; 2019 struct rss_header rss_hdr_int; 2020 }; 2021 2022 #define CPL_RX_PHYS_DSGL_OPCODE_S 24 2023 #define CPL_RX_PHYS_DSGL_OPCODE_M 0xff 2024 #define CPL_RX_PHYS_DSGL_OPCODE_V(x) ((x) << CPL_RX_PHYS_DSGL_OPCODE_S) 2025 #define CPL_RX_PHYS_DSGL_OPCODE_G(x) \ 2026 (((x) >> CPL_RX_PHYS_DSGL_OPCODE_S) & CPL_RX_PHYS_DSGL_OPCODE_M) 2027 2028 #define CPL_RX_PHYS_DSGL_ISRDMA_S 23 2029 #define CPL_RX_PHYS_DSGL_ISRDMA_M 0x1 2030 #define CPL_RX_PHYS_DSGL_ISRDMA_V(x) ((x) << CPL_RX_PHYS_DSGL_ISRDMA_S) 2031 #define CPL_RX_PHYS_DSGL_ISRDMA_G(x) \ 2032 (((x) >> CPL_RX_PHYS_DSGL_ISRDMA_S) & CPL_RX_PHYS_DSGL_ISRDMA_M) 2033 #define CPL_RX_PHYS_DSGL_ISRDMA_F CPL_RX_PHYS_DSGL_ISRDMA_V(1U) 2034 2035 #define CPL_RX_PHYS_DSGL_RSVD1_S 20 2036 #define CPL_RX_PHYS_DSGL_RSVD1_M 0x7 2037 #define CPL_RX_PHYS_DSGL_RSVD1_V(x) ((x) << CPL_RX_PHYS_DSGL_RSVD1_S) 2038 #define CPL_RX_PHYS_DSGL_RSVD1_G(x) \ 2039 (((x) >> CPL_RX_PHYS_DSGL_RSVD1_S) & \ 2040 CPL_RX_PHYS_DSGL_RSVD1_M) 2041 2042 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_S 31 2043 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_M 0x1 2044 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_V(x) \ 2045 ((x) << CPL_RX_PHYS_DSGL_PCIRLXORDER_S) 2046 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_G(x) \ 2047 (((x) >> CPL_RX_PHYS_DSGL_PCIRLXORDER_S) & \ 2048 CPL_RX_PHYS_DSGL_PCIRLXORDER_M) 2049 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_F CPL_RX_PHYS_DSGL_PCIRLXORDER_V(1U) 2050 2051 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_S 30 2052 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_M 0x1 2053 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_V(x) \ 2054 ((x) << CPL_RX_PHYS_DSGL_PCINOSNOOP_S) 2055 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_G(x) \ 2056 (((x) >> CPL_RX_PHYS_DSGL_PCINOSNOOP_S) & \ 2057 CPL_RX_PHYS_DSGL_PCINOSNOOP_M) 2058 2059 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_F CPL_RX_PHYS_DSGL_PCINOSNOOP_V(1U) 2060 2061 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_S 29 2062 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_M 0x1 2063 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_V(x) \ 2064 ((x) << CPL_RX_PHYS_DSGL_PCITPHNTENB_S) 2065 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_G(x) \ 2066 (((x) >> CPL_RX_PHYS_DSGL_PCITPHNTENB_S) & \ 2067 CPL_RX_PHYS_DSGL_PCITPHNTENB_M) 2068 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_F CPL_RX_PHYS_DSGL_PCITPHNTENB_V(1U) 2069 2070 #define CPL_RX_PHYS_DSGL_PCITPHNT_S 27 2071 #define CPL_RX_PHYS_DSGL_PCITPHNT_M 0x3 2072 #define CPL_RX_PHYS_DSGL_PCITPHNT_V(x) ((x) << CPL_RX_PHYS_DSGL_PCITPHNT_S) 2073 #define CPL_RX_PHYS_DSGL_PCITPHNT_G(x) \ 2074 (((x) >> CPL_RX_PHYS_DSGL_PCITPHNT_S) & \ 2075 CPL_RX_PHYS_DSGL_PCITPHNT_M) 2076 2077 #define CPL_RX_PHYS_DSGL_DCAID_S 16 2078 #define CPL_RX_PHYS_DSGL_DCAID_M 0x7ff 2079 #define CPL_RX_PHYS_DSGL_DCAID_V(x) ((x) << CPL_RX_PHYS_DSGL_DCAID_S) 2080 #define CPL_RX_PHYS_DSGL_DCAID_G(x) \ 2081 (((x) >> CPL_RX_PHYS_DSGL_DCAID_S) & \ 2082 CPL_RX_PHYS_DSGL_DCAID_M) 2083 2084 #define CPL_RX_PHYS_DSGL_NOOFSGENTR_S 0 2085 #define CPL_RX_PHYS_DSGL_NOOFSGENTR_M 0xffff 2086 #define CPL_RX_PHYS_DSGL_NOOFSGENTR_V(x) \ 2087 ((x) << CPL_RX_PHYS_DSGL_NOOFSGENTR_S) 2088 #define CPL_RX_PHYS_DSGL_NOOFSGENTR_G(x) \ 2089 (((x) >> CPL_RX_PHYS_DSGL_NOOFSGENTR_S) & \ 2090 CPL_RX_PHYS_DSGL_NOOFSGENTR_M) 2091 2092 struct cpl_rx_mps_pkt { 2093 __be32 op_to_r1_hi; 2094 __be32 r1_lo_length; 2095 }; 2096 2097 #define CPL_RX_MPS_PKT_OP_S 24 2098 #define CPL_RX_MPS_PKT_OP_M 0xff 2099 #define CPL_RX_MPS_PKT_OP_V(x) ((x) << CPL_RX_MPS_PKT_OP_S) 2100 #define CPL_RX_MPS_PKT_OP_G(x) \ 2101 (((x) >> CPL_RX_MPS_PKT_OP_S) & CPL_RX_MPS_PKT_OP_M) 2102 2103 #define CPL_RX_MPS_PKT_TYPE_S 20 2104 #define CPL_RX_MPS_PKT_TYPE_M 0xf 2105 #define CPL_RX_MPS_PKT_TYPE_V(x) ((x) << CPL_RX_MPS_PKT_TYPE_S) 2106 #define CPL_RX_MPS_PKT_TYPE_G(x) \ 2107 (((x) >> CPL_RX_MPS_PKT_TYPE_S) & CPL_RX_MPS_PKT_TYPE_M) 2108 2109 enum { 2110 X_CPL_RX_MPS_PKT_TYPE_PAUSE = 1 << 0, 2111 X_CPL_RX_MPS_PKT_TYPE_PPP = 1 << 1, 2112 X_CPL_RX_MPS_PKT_TYPE_QFC = 1 << 2, 2113 X_CPL_RX_MPS_PKT_TYPE_PTP = 1 << 3 2114 }; 2115 #endif /* __T4_MSG_H */ 2116