1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __T4_MSG_H 36 #define __T4_MSG_H 37 38 #include <linux/types.h> 39 40 enum { 41 CPL_PASS_OPEN_REQ = 0x1, 42 CPL_PASS_ACCEPT_RPL = 0x2, 43 CPL_ACT_OPEN_REQ = 0x3, 44 CPL_SET_TCB_FIELD = 0x5, 45 CPL_GET_TCB = 0x6, 46 CPL_CLOSE_CON_REQ = 0x8, 47 CPL_CLOSE_LISTSRV_REQ = 0x9, 48 CPL_ABORT_REQ = 0xA, 49 CPL_ABORT_RPL = 0xB, 50 CPL_RX_DATA_ACK = 0xD, 51 CPL_TX_PKT = 0xE, 52 CPL_L2T_WRITE_REQ = 0x12, 53 CPL_TID_RELEASE = 0x1A, 54 55 CPL_CLOSE_LISTSRV_RPL = 0x20, 56 CPL_L2T_WRITE_RPL = 0x23, 57 CPL_PASS_OPEN_RPL = 0x24, 58 CPL_ACT_OPEN_RPL = 0x25, 59 CPL_PEER_CLOSE = 0x26, 60 CPL_ABORT_REQ_RSS = 0x2B, 61 CPL_ABORT_RPL_RSS = 0x2D, 62 63 CPL_CLOSE_CON_RPL = 0x32, 64 CPL_ISCSI_HDR = 0x33, 65 CPL_RDMA_CQE = 0x35, 66 CPL_RDMA_CQE_READ_RSP = 0x36, 67 CPL_RDMA_CQE_ERR = 0x37, 68 CPL_RX_DATA = 0x39, 69 CPL_SET_TCB_RPL = 0x3A, 70 CPL_RX_PKT = 0x3B, 71 CPL_RX_DDP_COMPLETE = 0x3F, 72 73 CPL_ACT_ESTABLISH = 0x40, 74 CPL_PASS_ESTABLISH = 0x41, 75 CPL_RX_DATA_DDP = 0x42, 76 CPL_PASS_ACCEPT_REQ = 0x44, 77 CPL_TRACE_PKT_T5 = 0x48, 78 79 CPL_RDMA_READ_REQ = 0x60, 80 81 CPL_PASS_OPEN_REQ6 = 0x81, 82 CPL_ACT_OPEN_REQ6 = 0x83, 83 84 CPL_RDMA_TERMINATE = 0xA2, 85 CPL_RDMA_WRITE = 0xA4, 86 CPL_SGE_EGR_UPDATE = 0xA5, 87 88 CPL_TRACE_PKT = 0xB0, 89 90 CPL_FW4_MSG = 0xC0, 91 CPL_FW4_PLD = 0xC1, 92 CPL_FW4_ACK = 0xC3, 93 94 CPL_FW6_MSG = 0xE0, 95 CPL_FW6_PLD = 0xE1, 96 CPL_TX_PKT_LSO = 0xED, 97 CPL_TX_PKT_XT = 0xEE, 98 99 NUM_CPL_CMDS 100 }; 101 102 enum CPL_error { 103 CPL_ERR_NONE = 0, 104 CPL_ERR_TCAM_FULL = 3, 105 CPL_ERR_BAD_LENGTH = 15, 106 CPL_ERR_BAD_ROUTE = 18, 107 CPL_ERR_CONN_RESET = 20, 108 CPL_ERR_CONN_EXIST_SYNRECV = 21, 109 CPL_ERR_CONN_EXIST = 22, 110 CPL_ERR_ARP_MISS = 23, 111 CPL_ERR_BAD_SYN = 24, 112 CPL_ERR_CONN_TIMEDOUT = 30, 113 CPL_ERR_XMIT_TIMEDOUT = 31, 114 CPL_ERR_PERSIST_TIMEDOUT = 32, 115 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 116 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 117 CPL_ERR_RTX_NEG_ADVICE = 35, 118 CPL_ERR_PERSIST_NEG_ADVICE = 36, 119 CPL_ERR_KEEPALV_NEG_ADVICE = 37, 120 CPL_ERR_ABORT_FAILED = 42, 121 CPL_ERR_IWARP_FLM = 50, 122 }; 123 124 enum { 125 ULP_MODE_NONE = 0, 126 ULP_MODE_ISCSI = 2, 127 ULP_MODE_RDMA = 4, 128 ULP_MODE_TCPDDP = 5, 129 ULP_MODE_FCOE = 6, 130 }; 131 132 enum { 133 ULP_CRC_HEADER = 1 << 0, 134 ULP_CRC_DATA = 1 << 1 135 }; 136 137 enum { 138 CPL_ABORT_SEND_RST = 0, 139 CPL_ABORT_NO_RST, 140 }; 141 142 enum { /* TX_PKT_XT checksum types */ 143 TX_CSUM_TCP = 0, 144 TX_CSUM_UDP = 1, 145 TX_CSUM_CRC16 = 4, 146 TX_CSUM_CRC32 = 5, 147 TX_CSUM_CRC32C = 6, 148 TX_CSUM_FCOE = 7, 149 TX_CSUM_TCPIP = 8, 150 TX_CSUM_UDPIP = 9, 151 TX_CSUM_TCPIP6 = 10, 152 TX_CSUM_UDPIP6 = 11, 153 TX_CSUM_IP = 12, 154 }; 155 156 union opcode_tid { 157 __be32 opcode_tid; 158 u8 opcode; 159 }; 160 161 #define CPL_OPCODE(x) ((x) << 24) 162 #define G_CPL_OPCODE(x) (((x) >> 24) & 0xFF) 163 #define MK_OPCODE_TID(opcode, tid) (CPL_OPCODE(opcode) | (tid)) 164 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 165 #define GET_TID(cmd) (ntohl(OPCODE_TID(cmd)) & 0xFFFFFF) 166 167 /* partitioning of TID fields that also carry a queue id */ 168 #define GET_TID_TID(x) ((x) & 0x3fff) 169 #define GET_TID_QID(x) (((x) >> 14) & 0x3ff) 170 #define TID_QID(x) ((x) << 14) 171 172 struct rss_header { 173 u8 opcode; 174 #if defined(__LITTLE_ENDIAN_BITFIELD) 175 u8 channel:2; 176 u8 filter_hit:1; 177 u8 filter_tid:1; 178 u8 hash_type:2; 179 u8 ipv6:1; 180 u8 send2fw:1; 181 #else 182 u8 send2fw:1; 183 u8 ipv6:1; 184 u8 hash_type:2; 185 u8 filter_tid:1; 186 u8 filter_hit:1; 187 u8 channel:2; 188 #endif 189 __be16 qid; 190 __be32 hash_val; 191 }; 192 193 struct work_request_hdr { 194 __be32 wr_hi; 195 __be32 wr_mid; 196 __be64 wr_lo; 197 }; 198 199 /* wr_hi fields */ 200 #define S_WR_OP 24 201 #define V_WR_OP(x) ((__u64)(x) << S_WR_OP) 202 203 #define WR_HDR struct work_request_hdr wr 204 205 /* option 0 fields */ 206 #define S_MSS_IDX 60 207 #define M_MSS_IDX 0xF 208 #define V_MSS_IDX(x) ((__u64)(x) << S_MSS_IDX) 209 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX) 210 211 /* option 2 fields */ 212 #define S_RSS_QUEUE 0 213 #define M_RSS_QUEUE 0x3FF 214 #define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE) 215 #define G_RSS_QUEUE(x) (((x) >> S_RSS_QUEUE) & M_RSS_QUEUE) 216 217 struct cpl_pass_open_req { 218 WR_HDR; 219 union opcode_tid ot; 220 __be16 local_port; 221 __be16 peer_port; 222 __be32 local_ip; 223 __be32 peer_ip; 224 __be64 opt0; 225 #define TX_CHAN(x) ((x) << 2) 226 #define NO_CONG(x) ((x) << 4) 227 #define DELACK(x) ((x) << 5) 228 #define ULP_MODE(x) ((x) << 8) 229 #define RCV_BUFSIZ(x) ((x) << 12) 230 #define DSCP(x) ((x) << 22) 231 #define SMAC_SEL(x) ((u64)(x) << 28) 232 #define L2T_IDX(x) ((u64)(x) << 36) 233 #define TCAM_BYPASS(x) ((u64)(x) << 48) 234 #define NAGLE(x) ((u64)(x) << 49) 235 #define WND_SCALE(x) ((u64)(x) << 50) 236 #define KEEP_ALIVE(x) ((u64)(x) << 54) 237 #define MSS_IDX(x) ((u64)(x) << 60) 238 __be64 opt1; 239 #define SYN_RSS_ENABLE (1 << 0) 240 #define SYN_RSS_QUEUE(x) ((x) << 2) 241 #define CONN_POLICY_ASK (1 << 22) 242 }; 243 244 struct cpl_pass_open_req6 { 245 WR_HDR; 246 union opcode_tid ot; 247 __be16 local_port; 248 __be16 peer_port; 249 __be64 local_ip_hi; 250 __be64 local_ip_lo; 251 __be64 peer_ip_hi; 252 __be64 peer_ip_lo; 253 __be64 opt0; 254 __be64 opt1; 255 }; 256 257 struct cpl_pass_open_rpl { 258 union opcode_tid ot; 259 u8 rsvd[3]; 260 u8 status; 261 }; 262 263 struct cpl_pass_accept_rpl { 264 WR_HDR; 265 union opcode_tid ot; 266 __be32 opt2; 267 #define RSS_QUEUE(x) ((x) << 0) 268 #define RSS_QUEUE_VALID (1 << 10) 269 #define RX_COALESCE_VALID(x) ((x) << 11) 270 #define RX_COALESCE(x) ((x) << 12) 271 #define PACE(x) ((x) << 16) 272 #define TX_QUEUE(x) ((x) << 23) 273 #define RX_CHANNEL(x) ((x) << 26) 274 #define CCTRL_ECN(x) ((x) << 27) 275 #define WND_SCALE_EN(x) ((x) << 28) 276 #define TSTAMPS_EN(x) ((x) << 29) 277 #define SACK_EN(x) ((x) << 30) 278 __be64 opt0; 279 }; 280 281 struct cpl_act_open_req { 282 WR_HDR; 283 union opcode_tid ot; 284 __be16 local_port; 285 __be16 peer_port; 286 __be32 local_ip; 287 __be32 peer_ip; 288 __be64 opt0; 289 __be32 params; 290 __be32 opt2; 291 }; 292 293 #define S_FILTER_TUPLE 24 294 #define M_FILTER_TUPLE 0xFFFFFFFFFF 295 #define V_FILTER_TUPLE(x) ((x) << S_FILTER_TUPLE) 296 #define G_FILTER_TUPLE(x) (((x) >> S_FILTER_TUPLE) & M_FILTER_TUPLE) 297 struct cpl_t5_act_open_req { 298 WR_HDR; 299 union opcode_tid ot; 300 __be16 local_port; 301 __be16 peer_port; 302 __be32 local_ip; 303 __be32 peer_ip; 304 __be64 opt0; 305 __be32 rsvd; 306 __be32 opt2; 307 __be64 params; 308 }; 309 310 struct cpl_act_open_req6 { 311 WR_HDR; 312 union opcode_tid ot; 313 __be16 local_port; 314 __be16 peer_port; 315 __be64 local_ip_hi; 316 __be64 local_ip_lo; 317 __be64 peer_ip_hi; 318 __be64 peer_ip_lo; 319 __be64 opt0; 320 __be32 params; 321 __be32 opt2; 322 }; 323 324 struct cpl_t5_act_open_req6 { 325 WR_HDR; 326 union opcode_tid ot; 327 __be16 local_port; 328 __be16 peer_port; 329 __be64 local_ip_hi; 330 __be64 local_ip_lo; 331 __be64 peer_ip_hi; 332 __be64 peer_ip_lo; 333 __be64 opt0; 334 __be32 rsvd; 335 __be32 opt2; 336 __be64 params; 337 }; 338 339 struct cpl_act_open_rpl { 340 union opcode_tid ot; 341 __be32 atid_status; 342 #define GET_AOPEN_STATUS(x) ((x) & 0xff) 343 #define GET_AOPEN_ATID(x) (((x) >> 8) & 0xffffff) 344 }; 345 346 struct cpl_pass_establish { 347 union opcode_tid ot; 348 __be32 rsvd; 349 __be32 tos_stid; 350 #define PASS_OPEN_TID(x) ((x) << 0) 351 #define PASS_OPEN_TOS(x) ((x) << 24) 352 #define GET_PASS_OPEN_TID(x) (((x) >> 0) & 0xFFFFFF) 353 #define GET_POPEN_TID(x) ((x) & 0xffffff) 354 #define GET_POPEN_TOS(x) (((x) >> 24) & 0xff) 355 __be16 mac_idx; 356 __be16 tcp_opt; 357 #define GET_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1) 358 #define GET_TCPOPT_SACK(x) (((x) >> 6) & 1) 359 #define GET_TCPOPT_TSTAMP(x) (((x) >> 7) & 1) 360 #define GET_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf) 361 #define GET_TCPOPT_MSS(x) (((x) >> 12) & 0xf) 362 __be32 snd_isn; 363 __be32 rcv_isn; 364 }; 365 366 struct cpl_act_establish { 367 union opcode_tid ot; 368 __be32 rsvd; 369 __be32 tos_atid; 370 __be16 mac_idx; 371 __be16 tcp_opt; 372 __be32 snd_isn; 373 __be32 rcv_isn; 374 }; 375 376 struct cpl_get_tcb { 377 WR_HDR; 378 union opcode_tid ot; 379 __be16 reply_ctrl; 380 #define QUEUENO(x) ((x) << 0) 381 #define REPLY_CHAN(x) ((x) << 14) 382 #define NO_REPLY(x) ((x) << 15) 383 __be16 cookie; 384 }; 385 386 struct cpl_set_tcb_field { 387 WR_HDR; 388 union opcode_tid ot; 389 __be16 reply_ctrl; 390 __be16 word_cookie; 391 #define TCB_WORD(x) ((x) << 0) 392 #define TCB_COOKIE(x) ((x) << 5) 393 #define GET_TCB_COOKIE(x) (((x) >> 5) & 7) 394 __be64 mask; 395 __be64 val; 396 }; 397 398 struct cpl_set_tcb_rpl { 399 union opcode_tid ot; 400 __be16 rsvd; 401 u8 cookie; 402 u8 status; 403 __be64 oldval; 404 }; 405 406 struct cpl_close_con_req { 407 WR_HDR; 408 union opcode_tid ot; 409 __be32 rsvd; 410 }; 411 412 struct cpl_close_con_rpl { 413 union opcode_tid ot; 414 u8 rsvd[3]; 415 u8 status; 416 __be32 snd_nxt; 417 __be32 rcv_nxt; 418 }; 419 420 struct cpl_close_listsvr_req { 421 WR_HDR; 422 union opcode_tid ot; 423 __be16 reply_ctrl; 424 #define LISTSVR_IPV6(x) ((x) << 14) 425 __be16 rsvd; 426 }; 427 428 struct cpl_close_listsvr_rpl { 429 union opcode_tid ot; 430 u8 rsvd[3]; 431 u8 status; 432 }; 433 434 struct cpl_abort_req_rss { 435 union opcode_tid ot; 436 u8 rsvd[3]; 437 u8 status; 438 }; 439 440 struct cpl_abort_req { 441 WR_HDR; 442 union opcode_tid ot; 443 __be32 rsvd0; 444 u8 rsvd1; 445 u8 cmd; 446 u8 rsvd2[6]; 447 }; 448 449 struct cpl_abort_rpl_rss { 450 union opcode_tid ot; 451 u8 rsvd[3]; 452 u8 status; 453 }; 454 455 struct cpl_abort_rpl { 456 WR_HDR; 457 union opcode_tid ot; 458 __be32 rsvd0; 459 u8 rsvd1; 460 u8 cmd; 461 u8 rsvd2[6]; 462 }; 463 464 struct cpl_peer_close { 465 union opcode_tid ot; 466 __be32 rcv_nxt; 467 }; 468 469 struct cpl_tid_release { 470 WR_HDR; 471 union opcode_tid ot; 472 __be32 rsvd; 473 }; 474 475 struct cpl_tx_pkt_core { 476 __be32 ctrl0; 477 #define TXPKT_VF(x) ((x) << 0) 478 #define TXPKT_PF(x) ((x) << 8) 479 #define TXPKT_VF_VLD (1 << 11) 480 #define TXPKT_OVLAN_IDX(x) ((x) << 12) 481 #define TXPKT_INTF(x) ((x) << 16) 482 #define TXPKT_INS_OVLAN (1 << 21) 483 #define TXPKT_OPCODE(x) ((x) << 24) 484 __be16 pack; 485 __be16 len; 486 __be64 ctrl1; 487 #define TXPKT_CSUM_END(x) ((x) << 12) 488 #define TXPKT_CSUM_START(x) ((x) << 20) 489 #define TXPKT_IPHDR_LEN(x) ((u64)(x) << 20) 490 #define TXPKT_CSUM_LOC(x) ((u64)(x) << 30) 491 #define TXPKT_ETHHDR_LEN(x) ((u64)(x) << 34) 492 #define TXPKT_CSUM_TYPE(x) ((u64)(x) << 40) 493 #define TXPKT_VLAN(x) ((u64)(x) << 44) 494 #define TXPKT_VLAN_VLD (1ULL << 60) 495 #define TXPKT_IPCSUM_DIS (1ULL << 62) 496 #define TXPKT_L4CSUM_DIS (1ULL << 63) 497 }; 498 499 struct cpl_tx_pkt { 500 WR_HDR; 501 struct cpl_tx_pkt_core c; 502 }; 503 504 #define cpl_tx_pkt_xt cpl_tx_pkt 505 506 struct cpl_tx_pkt_lso_core { 507 __be32 lso_ctrl; 508 #define LSO_TCPHDR_LEN(x) ((x) << 0) 509 #define LSO_IPHDR_LEN(x) ((x) << 4) 510 #define LSO_ETHHDR_LEN(x) ((x) << 16) 511 #define LSO_IPV6(x) ((x) << 20) 512 #define LSO_LAST_SLICE (1 << 22) 513 #define LSO_FIRST_SLICE (1 << 23) 514 #define LSO_OPCODE(x) ((x) << 24) 515 __be16 ipid_ofst; 516 __be16 mss; 517 __be32 seqno_offset; 518 __be32 len; 519 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 520 }; 521 522 struct cpl_tx_pkt_lso { 523 WR_HDR; 524 struct cpl_tx_pkt_lso_core c; 525 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 526 }; 527 528 struct cpl_iscsi_hdr { 529 union opcode_tid ot; 530 __be16 pdu_len_ddp; 531 #define ISCSI_PDU_LEN(x) ((x) & 0x7FFF) 532 #define ISCSI_DDP (1 << 15) 533 __be16 len; 534 __be32 seq; 535 __be16 urg; 536 u8 rsvd; 537 u8 status; 538 }; 539 540 struct cpl_rx_data { 541 union opcode_tid ot; 542 __be16 rsvd; 543 __be16 len; 544 __be32 seq; 545 __be16 urg; 546 #if defined(__LITTLE_ENDIAN_BITFIELD) 547 u8 dack_mode:2; 548 u8 psh:1; 549 u8 heartbeat:1; 550 u8 ddp_off:1; 551 u8 :3; 552 #else 553 u8 :3; 554 u8 ddp_off:1; 555 u8 heartbeat:1; 556 u8 psh:1; 557 u8 dack_mode:2; 558 #endif 559 u8 status; 560 }; 561 562 struct cpl_rx_data_ack { 563 WR_HDR; 564 union opcode_tid ot; 565 __be32 credit_dack; 566 #define RX_CREDITS(x) ((x) << 0) 567 #define RX_FORCE_ACK(x) ((x) << 28) 568 }; 569 570 struct cpl_rx_pkt { 571 struct rss_header rsshdr; 572 u8 opcode; 573 #if defined(__LITTLE_ENDIAN_BITFIELD) 574 u8 iff:4; 575 u8 csum_calc:1; 576 u8 ipmi_pkt:1; 577 u8 vlan_ex:1; 578 u8 ip_frag:1; 579 #else 580 u8 ip_frag:1; 581 u8 vlan_ex:1; 582 u8 ipmi_pkt:1; 583 u8 csum_calc:1; 584 u8 iff:4; 585 #endif 586 __be16 csum; 587 __be16 vlan; 588 __be16 len; 589 __be32 l2info; 590 #define RXF_UDP (1 << 22) 591 #define RXF_TCP (1 << 23) 592 #define RXF_IP (1 << 24) 593 #define RXF_IP6 (1 << 25) 594 __be16 hdr_len; 595 __be16 err_vec; 596 }; 597 598 /* rx_pkt.l2info fields */ 599 #define S_RX_ETHHDR_LEN 0 600 #define M_RX_ETHHDR_LEN 0x1F 601 #define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN) 602 #define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN) 603 604 #define S_RX_T5_ETHHDR_LEN 0 605 #define M_RX_T5_ETHHDR_LEN 0x3F 606 #define V_RX_T5_ETHHDR_LEN(x) ((x) << S_RX_T5_ETHHDR_LEN) 607 #define G_RX_T5_ETHHDR_LEN(x) (((x) >> S_RX_T5_ETHHDR_LEN) & M_RX_T5_ETHHDR_LEN) 608 609 #define S_RX_MACIDX 8 610 #define M_RX_MACIDX 0x1FF 611 #define V_RX_MACIDX(x) ((x) << S_RX_MACIDX) 612 #define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX) 613 614 #define S_RXF_SYN 21 615 #define V_RXF_SYN(x) ((x) << S_RXF_SYN) 616 #define F_RXF_SYN V_RXF_SYN(1U) 617 618 #define S_RX_CHAN 28 619 #define M_RX_CHAN 0xF 620 #define V_RX_CHAN(x) ((x) << S_RX_CHAN) 621 #define G_RX_CHAN(x) (((x) >> S_RX_CHAN) & M_RX_CHAN) 622 623 /* rx_pkt.hdr_len fields */ 624 #define S_RX_TCPHDR_LEN 0 625 #define M_RX_TCPHDR_LEN 0x3F 626 #define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN) 627 #define G_RX_TCPHDR_LEN(x) (((x) >> S_RX_TCPHDR_LEN) & M_RX_TCPHDR_LEN) 628 629 #define S_RX_IPHDR_LEN 6 630 #define M_RX_IPHDR_LEN 0x3FF 631 #define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN) 632 #define G_RX_IPHDR_LEN(x) (((x) >> S_RX_IPHDR_LEN) & M_RX_IPHDR_LEN) 633 634 struct cpl_trace_pkt { 635 u8 opcode; 636 u8 intf; 637 #if defined(__LITTLE_ENDIAN_BITFIELD) 638 u8 runt:4; 639 u8 filter_hit:4; 640 u8 :6; 641 u8 err:1; 642 u8 trunc:1; 643 #else 644 u8 filter_hit:4; 645 u8 runt:4; 646 u8 trunc:1; 647 u8 err:1; 648 u8 :6; 649 #endif 650 __be16 rsvd; 651 __be16 len; 652 __be64 tstamp; 653 }; 654 655 struct cpl_t5_trace_pkt { 656 __u8 opcode; 657 __u8 intf; 658 #if defined(__LITTLE_ENDIAN_BITFIELD) 659 __u8 runt:4; 660 __u8 filter_hit:4; 661 __u8:6; 662 __u8 err:1; 663 __u8 trunc:1; 664 #else 665 __u8 filter_hit:4; 666 __u8 runt:4; 667 __u8 trunc:1; 668 __u8 err:1; 669 __u8:6; 670 #endif 671 __be16 rsvd; 672 __be16 len; 673 __be64 tstamp; 674 __be64 rsvd1; 675 }; 676 677 struct cpl_l2t_write_req { 678 WR_HDR; 679 union opcode_tid ot; 680 __be16 params; 681 #define L2T_W_INFO(x) ((x) << 2) 682 #define L2T_W_PORT(x) ((x) << 8) 683 #define L2T_W_NOREPLY(x) ((x) << 15) 684 __be16 l2t_idx; 685 __be16 vlan; 686 u8 dst_mac[6]; 687 }; 688 689 struct cpl_l2t_write_rpl { 690 union opcode_tid ot; 691 u8 status; 692 u8 rsvd[3]; 693 }; 694 695 struct cpl_rdma_terminate { 696 union opcode_tid ot; 697 __be16 rsvd; 698 __be16 len; 699 }; 700 701 struct cpl_sge_egr_update { 702 __be32 opcode_qid; 703 #define EGR_QID(x) ((x) & 0x1FFFF) 704 __be16 cidx; 705 __be16 pidx; 706 }; 707 708 /* cpl_fw*.type values */ 709 enum { 710 FW_TYPE_CMD_RPL = 0, 711 FW_TYPE_WR_RPL = 1, 712 FW_TYPE_CQE = 2, 713 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3, 714 FW_TYPE_RSSCPL = 4, 715 }; 716 717 struct cpl_fw4_pld { 718 u8 opcode; 719 u8 rsvd0[3]; 720 u8 type; 721 u8 rsvd1; 722 __be16 len; 723 __be64 data; 724 __be64 rsvd2; 725 }; 726 727 struct cpl_fw6_pld { 728 u8 opcode; 729 u8 rsvd[5]; 730 __be16 len; 731 __be64 data[4]; 732 }; 733 734 struct cpl_fw4_msg { 735 u8 opcode; 736 u8 type; 737 __be16 rsvd0; 738 __be32 rsvd1; 739 __be64 data[2]; 740 }; 741 742 struct cpl_fw4_ack { 743 union opcode_tid ot; 744 u8 credits; 745 u8 rsvd0[2]; 746 u8 seq_vld; 747 __be32 snd_nxt; 748 __be32 snd_una; 749 __be64 rsvd1; 750 }; 751 752 struct cpl_fw6_msg { 753 u8 opcode; 754 u8 type; 755 __be16 rsvd0; 756 __be32 rsvd1; 757 __be64 data[4]; 758 }; 759 760 /* cpl_fw6_msg.type values */ 761 enum { 762 FW6_TYPE_CMD_RPL = 0, 763 FW6_TYPE_WR_RPL = 1, 764 FW6_TYPE_CQE = 2, 765 FW6_TYPE_OFLD_CONNECTION_WR_RPL = 3, 766 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL, 767 }; 768 769 struct cpl_fw6_msg_ofld_connection_wr_rpl { 770 __u64 cookie; 771 __be32 tid; /* or atid in case of active failure */ 772 __u8 t_state; 773 __u8 retval; 774 __u8 rsvd[2]; 775 }; 776 777 enum { 778 ULP_TX_MEM_READ = 2, 779 ULP_TX_MEM_WRITE = 3, 780 ULP_TX_PKT = 4 781 }; 782 783 enum { 784 ULP_TX_SC_NOOP = 0x80, 785 ULP_TX_SC_IMM = 0x81, 786 ULP_TX_SC_DSGL = 0x82, 787 ULP_TX_SC_ISGL = 0x83 788 }; 789 790 struct ulptx_sge_pair { 791 __be32 len[2]; 792 __be64 addr[2]; 793 }; 794 795 struct ulptx_sgl { 796 __be32 cmd_nsge; 797 #define ULPTX_CMD(x) ((x) << 24) 798 #define ULPTX_NSGE(x) ((x) << 0) 799 #define ULPTX_MORE (1U << 23) 800 __be32 len0; 801 __be64 addr0; 802 struct ulptx_sge_pair sge[0]; 803 }; 804 805 struct ulp_mem_io { 806 WR_HDR; 807 __be32 cmd; 808 #define ULP_MEMIO_ORDER(x) ((x) << 23) 809 __be32 len16; /* command length */ 810 __be32 dlen; /* data length in 32-byte units */ 811 #define ULP_MEMIO_DATA_LEN(x) ((x) << 0) 812 __be32 lock_addr; 813 #define ULP_MEMIO_ADDR(x) ((x) << 0) 814 #define ULP_MEMIO_LOCK(x) ((x) << 31) 815 }; 816 817 #define S_T5_ULP_MEMIO_IMM 23 818 #define V_T5_ULP_MEMIO_IMM(x) ((x) << S_T5_ULP_MEMIO_IMM) 819 #define F_T5_ULP_MEMIO_IMM V_T5_ULP_MEMIO_IMM(1U) 820 821 #define S_T5_ULP_MEMIO_ORDER 22 822 #define V_T5_ULP_MEMIO_ORDER(x) ((x) << S_T5_ULP_MEMIO_ORDER) 823 #define F_T5_ULP_MEMIO_ORDER V_T5_ULP_MEMIO_ORDER(1U) 824 825 #endif /* __T4_MSG_H */ 826