1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __T4_MSG_H 36 #define __T4_MSG_H 37 38 #include <linux/types.h> 39 40 enum { 41 CPL_PASS_OPEN_REQ = 0x1, 42 CPL_PASS_ACCEPT_RPL = 0x2, 43 CPL_ACT_OPEN_REQ = 0x3, 44 CPL_SET_TCB_FIELD = 0x5, 45 CPL_GET_TCB = 0x6, 46 CPL_CLOSE_CON_REQ = 0x8, 47 CPL_CLOSE_LISTSRV_REQ = 0x9, 48 CPL_ABORT_REQ = 0xA, 49 CPL_ABORT_RPL = 0xB, 50 CPL_RX_DATA_ACK = 0xD, 51 CPL_TX_PKT = 0xE, 52 CPL_L2T_WRITE_REQ = 0x12, 53 CPL_SMT_WRITE_REQ = 0x14, 54 CPL_TID_RELEASE = 0x1A, 55 CPL_TX_DATA_ISO = 0x1F, 56 57 CPL_CLOSE_LISTSRV_RPL = 0x20, 58 CPL_L2T_WRITE_RPL = 0x23, 59 CPL_PASS_OPEN_RPL = 0x24, 60 CPL_ACT_OPEN_RPL = 0x25, 61 CPL_PEER_CLOSE = 0x26, 62 CPL_ABORT_REQ_RSS = 0x2B, 63 CPL_ABORT_RPL_RSS = 0x2D, 64 CPL_SMT_WRITE_RPL = 0x2E, 65 66 CPL_RX_PHYS_ADDR = 0x30, 67 CPL_CLOSE_CON_RPL = 0x32, 68 CPL_ISCSI_HDR = 0x33, 69 CPL_RDMA_CQE = 0x35, 70 CPL_RDMA_CQE_READ_RSP = 0x36, 71 CPL_RDMA_CQE_ERR = 0x37, 72 CPL_RX_DATA = 0x39, 73 CPL_SET_TCB_RPL = 0x3A, 74 CPL_RX_PKT = 0x3B, 75 CPL_RX_DDP_COMPLETE = 0x3F, 76 77 CPL_ACT_ESTABLISH = 0x40, 78 CPL_PASS_ESTABLISH = 0x41, 79 CPL_RX_DATA_DDP = 0x42, 80 CPL_PASS_ACCEPT_REQ = 0x44, 81 CPL_RX_ISCSI_CMP = 0x45, 82 CPL_TRACE_PKT_T5 = 0x48, 83 CPL_RX_ISCSI_DDP = 0x49, 84 85 CPL_RDMA_READ_REQ = 0x60, 86 87 CPL_PASS_OPEN_REQ6 = 0x81, 88 CPL_ACT_OPEN_REQ6 = 0x83, 89 90 CPL_TX_TLS_PDU = 0x88, 91 CPL_TX_SEC_PDU = 0x8A, 92 CPL_TX_TLS_ACK = 0x8B, 93 94 CPL_RDMA_TERMINATE = 0xA2, 95 CPL_RDMA_WRITE = 0xA4, 96 CPL_SGE_EGR_UPDATE = 0xA5, 97 CPL_RX_MPS_PKT = 0xAF, 98 99 CPL_TRACE_PKT = 0xB0, 100 CPL_ISCSI_DATA = 0xB2, 101 102 CPL_FW4_MSG = 0xC0, 103 CPL_FW4_PLD = 0xC1, 104 CPL_FW4_ACK = 0xC3, 105 106 CPL_RX_PHYS_DSGL = 0xD0, 107 108 CPL_FW6_MSG = 0xE0, 109 CPL_FW6_PLD = 0xE1, 110 CPL_TX_PKT_LSO = 0xED, 111 CPL_TX_PKT_XT = 0xEE, 112 113 NUM_CPL_CMDS 114 }; 115 116 enum CPL_error { 117 CPL_ERR_NONE = 0, 118 CPL_ERR_TCAM_PARITY = 1, 119 CPL_ERR_TCAM_MISS = 2, 120 CPL_ERR_TCAM_FULL = 3, 121 CPL_ERR_BAD_LENGTH = 15, 122 CPL_ERR_BAD_ROUTE = 18, 123 CPL_ERR_CONN_RESET = 20, 124 CPL_ERR_CONN_EXIST_SYNRECV = 21, 125 CPL_ERR_CONN_EXIST = 22, 126 CPL_ERR_ARP_MISS = 23, 127 CPL_ERR_BAD_SYN = 24, 128 CPL_ERR_CONN_TIMEDOUT = 30, 129 CPL_ERR_XMIT_TIMEDOUT = 31, 130 CPL_ERR_PERSIST_TIMEDOUT = 32, 131 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 132 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 133 CPL_ERR_RTX_NEG_ADVICE = 35, 134 CPL_ERR_PERSIST_NEG_ADVICE = 36, 135 CPL_ERR_KEEPALV_NEG_ADVICE = 37, 136 CPL_ERR_ABORT_FAILED = 42, 137 CPL_ERR_IWARP_FLM = 50, 138 }; 139 140 enum { 141 CPL_CONN_POLICY_AUTO = 0, 142 CPL_CONN_POLICY_ASK = 1, 143 CPL_CONN_POLICY_FILTER = 2, 144 CPL_CONN_POLICY_DENY = 3 145 }; 146 147 enum { 148 ULP_MODE_NONE = 0, 149 ULP_MODE_ISCSI = 2, 150 ULP_MODE_RDMA = 4, 151 ULP_MODE_TCPDDP = 5, 152 ULP_MODE_FCOE = 6, 153 }; 154 155 enum { 156 ULP_CRC_HEADER = 1 << 0, 157 ULP_CRC_DATA = 1 << 1 158 }; 159 160 enum { 161 CPL_ABORT_SEND_RST = 0, 162 CPL_ABORT_NO_RST, 163 }; 164 165 enum { /* TX_PKT_XT checksum types */ 166 TX_CSUM_TCP = 0, 167 TX_CSUM_UDP = 1, 168 TX_CSUM_CRC16 = 4, 169 TX_CSUM_CRC32 = 5, 170 TX_CSUM_CRC32C = 6, 171 TX_CSUM_FCOE = 7, 172 TX_CSUM_TCPIP = 8, 173 TX_CSUM_UDPIP = 9, 174 TX_CSUM_TCPIP6 = 10, 175 TX_CSUM_UDPIP6 = 11, 176 TX_CSUM_IP = 12, 177 }; 178 179 union opcode_tid { 180 __be32 opcode_tid; 181 u8 opcode; 182 }; 183 184 #define CPL_OPCODE_S 24 185 #define CPL_OPCODE_V(x) ((x) << CPL_OPCODE_S) 186 #define CPL_OPCODE_G(x) (((x) >> CPL_OPCODE_S) & 0xFF) 187 #define TID_G(x) ((x) & 0xFFFFFF) 188 189 /* tid is assumed to be 24-bits */ 190 #define MK_OPCODE_TID(opcode, tid) (CPL_OPCODE_V(opcode) | (tid)) 191 192 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 193 194 /* extract the TID from a CPL command */ 195 #define GET_TID(cmd) (TID_G(be32_to_cpu(OPCODE_TID(cmd)))) 196 197 /* partitioning of TID fields that also carry a queue id */ 198 #define TID_TID_S 0 199 #define TID_TID_M 0x3fff 200 #define TID_TID_G(x) (((x) >> TID_TID_S) & TID_TID_M) 201 202 #define TID_QID_S 14 203 #define TID_QID_M 0x3ff 204 #define TID_QID_V(x) ((x) << TID_QID_S) 205 #define TID_QID_G(x) (((x) >> TID_QID_S) & TID_QID_M) 206 207 struct rss_header { 208 u8 opcode; 209 #if defined(__LITTLE_ENDIAN_BITFIELD) 210 u8 channel:2; 211 u8 filter_hit:1; 212 u8 filter_tid:1; 213 u8 hash_type:2; 214 u8 ipv6:1; 215 u8 send2fw:1; 216 #else 217 u8 send2fw:1; 218 u8 ipv6:1; 219 u8 hash_type:2; 220 u8 filter_tid:1; 221 u8 filter_hit:1; 222 u8 channel:2; 223 #endif 224 __be16 qid; 225 __be32 hash_val; 226 }; 227 228 struct work_request_hdr { 229 __be32 wr_hi; 230 __be32 wr_mid; 231 __be64 wr_lo; 232 }; 233 234 /* wr_hi fields */ 235 #define WR_OP_S 24 236 #define WR_OP_V(x) ((__u64)(x) << WR_OP_S) 237 238 #define WR_HDR struct work_request_hdr wr 239 240 /* option 0 fields */ 241 #define TX_CHAN_S 2 242 #define TX_CHAN_V(x) ((x) << TX_CHAN_S) 243 244 #define ULP_MODE_S 8 245 #define ULP_MODE_V(x) ((x) << ULP_MODE_S) 246 247 #define RCV_BUFSIZ_S 12 248 #define RCV_BUFSIZ_M 0x3FFU 249 #define RCV_BUFSIZ_V(x) ((x) << RCV_BUFSIZ_S) 250 251 #define SMAC_SEL_S 28 252 #define SMAC_SEL_V(x) ((__u64)(x) << SMAC_SEL_S) 253 254 #define L2T_IDX_S 36 255 #define L2T_IDX_V(x) ((__u64)(x) << L2T_IDX_S) 256 257 #define WND_SCALE_S 50 258 #define WND_SCALE_V(x) ((__u64)(x) << WND_SCALE_S) 259 260 #define KEEP_ALIVE_S 54 261 #define KEEP_ALIVE_V(x) ((__u64)(x) << KEEP_ALIVE_S) 262 #define KEEP_ALIVE_F KEEP_ALIVE_V(1ULL) 263 264 #define MSS_IDX_S 60 265 #define MSS_IDX_M 0xF 266 #define MSS_IDX_V(x) ((__u64)(x) << MSS_IDX_S) 267 #define MSS_IDX_G(x) (((x) >> MSS_IDX_S) & MSS_IDX_M) 268 269 /* option 2 fields */ 270 #define RSS_QUEUE_S 0 271 #define RSS_QUEUE_M 0x3FF 272 #define RSS_QUEUE_V(x) ((x) << RSS_QUEUE_S) 273 #define RSS_QUEUE_G(x) (((x) >> RSS_QUEUE_S) & RSS_QUEUE_M) 274 275 #define RSS_QUEUE_VALID_S 10 276 #define RSS_QUEUE_VALID_V(x) ((x) << RSS_QUEUE_VALID_S) 277 #define RSS_QUEUE_VALID_F RSS_QUEUE_VALID_V(1U) 278 279 #define RX_FC_DISABLE_S 20 280 #define RX_FC_DISABLE_V(x) ((x) << RX_FC_DISABLE_S) 281 #define RX_FC_DISABLE_F RX_FC_DISABLE_V(1U) 282 283 #define RX_FC_VALID_S 22 284 #define RX_FC_VALID_V(x) ((x) << RX_FC_VALID_S) 285 #define RX_FC_VALID_F RX_FC_VALID_V(1U) 286 287 #define RX_CHANNEL_S 26 288 #define RX_CHANNEL_V(x) ((x) << RX_CHANNEL_S) 289 #define RX_CHANNEL_F RX_CHANNEL_V(1U) 290 291 #define WND_SCALE_EN_S 28 292 #define WND_SCALE_EN_V(x) ((x) << WND_SCALE_EN_S) 293 #define WND_SCALE_EN_F WND_SCALE_EN_V(1U) 294 295 #define T5_OPT_2_VALID_S 31 296 #define T5_OPT_2_VALID_V(x) ((x) << T5_OPT_2_VALID_S) 297 #define T5_OPT_2_VALID_F T5_OPT_2_VALID_V(1U) 298 299 struct cpl_pass_open_req { 300 WR_HDR; 301 union opcode_tid ot; 302 __be16 local_port; 303 __be16 peer_port; 304 __be32 local_ip; 305 __be32 peer_ip; 306 __be64 opt0; 307 __be64 opt1; 308 }; 309 310 /* option 0 fields */ 311 #define NO_CONG_S 4 312 #define NO_CONG_V(x) ((x) << NO_CONG_S) 313 #define NO_CONG_F NO_CONG_V(1U) 314 315 #define DELACK_S 5 316 #define DELACK_V(x) ((x) << DELACK_S) 317 #define DELACK_F DELACK_V(1U) 318 319 #define NON_OFFLOAD_S 7 320 #define NON_OFFLOAD_V(x) ((x) << NON_OFFLOAD_S) 321 #define NON_OFFLOAD_F NON_OFFLOAD_V(1U) 322 323 #define DSCP_S 22 324 #define DSCP_M 0x3F 325 #define DSCP_V(x) ((x) << DSCP_S) 326 #define DSCP_G(x) (((x) >> DSCP_S) & DSCP_M) 327 328 #define TCAM_BYPASS_S 48 329 #define TCAM_BYPASS_V(x) ((__u64)(x) << TCAM_BYPASS_S) 330 #define TCAM_BYPASS_F TCAM_BYPASS_V(1ULL) 331 332 #define NAGLE_S 49 333 #define NAGLE_V(x) ((__u64)(x) << NAGLE_S) 334 #define NAGLE_F NAGLE_V(1ULL) 335 336 /* option 1 fields */ 337 #define SYN_RSS_ENABLE_S 0 338 #define SYN_RSS_ENABLE_V(x) ((x) << SYN_RSS_ENABLE_S) 339 #define SYN_RSS_ENABLE_F SYN_RSS_ENABLE_V(1U) 340 341 #define SYN_RSS_QUEUE_S 2 342 #define SYN_RSS_QUEUE_V(x) ((x) << SYN_RSS_QUEUE_S) 343 344 #define CONN_POLICY_S 22 345 #define CONN_POLICY_V(x) ((x) << CONN_POLICY_S) 346 347 struct cpl_pass_open_req6 { 348 WR_HDR; 349 union opcode_tid ot; 350 __be16 local_port; 351 __be16 peer_port; 352 __be64 local_ip_hi; 353 __be64 local_ip_lo; 354 __be64 peer_ip_hi; 355 __be64 peer_ip_lo; 356 __be64 opt0; 357 __be64 opt1; 358 }; 359 360 struct cpl_pass_open_rpl { 361 union opcode_tid ot; 362 u8 rsvd[3]; 363 u8 status; 364 }; 365 366 struct tcp_options { 367 __be16 mss; 368 __u8 wsf; 369 #if defined(__LITTLE_ENDIAN_BITFIELD) 370 __u8:4; 371 __u8 unknown:1; 372 __u8:1; 373 __u8 sack:1; 374 __u8 tstamp:1; 375 #else 376 __u8 tstamp:1; 377 __u8 sack:1; 378 __u8:1; 379 __u8 unknown:1; 380 __u8:4; 381 #endif 382 }; 383 384 struct cpl_pass_accept_req { 385 union opcode_tid ot; 386 __be16 rsvd; 387 __be16 len; 388 __be32 hdr_len; 389 __be16 vlan; 390 __be16 l2info; 391 __be32 tos_stid; 392 struct tcp_options tcpopt; 393 }; 394 395 /* cpl_pass_accept_req.hdr_len fields */ 396 #define SYN_RX_CHAN_S 0 397 #define SYN_RX_CHAN_M 0xF 398 #define SYN_RX_CHAN_V(x) ((x) << SYN_RX_CHAN_S) 399 #define SYN_RX_CHAN_G(x) (((x) >> SYN_RX_CHAN_S) & SYN_RX_CHAN_M) 400 401 #define TCP_HDR_LEN_S 10 402 #define TCP_HDR_LEN_M 0x3F 403 #define TCP_HDR_LEN_V(x) ((x) << TCP_HDR_LEN_S) 404 #define TCP_HDR_LEN_G(x) (((x) >> TCP_HDR_LEN_S) & TCP_HDR_LEN_M) 405 406 #define IP_HDR_LEN_S 16 407 #define IP_HDR_LEN_M 0x3FF 408 #define IP_HDR_LEN_V(x) ((x) << IP_HDR_LEN_S) 409 #define IP_HDR_LEN_G(x) (((x) >> IP_HDR_LEN_S) & IP_HDR_LEN_M) 410 411 #define ETH_HDR_LEN_S 26 412 #define ETH_HDR_LEN_M 0x1F 413 #define ETH_HDR_LEN_V(x) ((x) << ETH_HDR_LEN_S) 414 #define ETH_HDR_LEN_G(x) (((x) >> ETH_HDR_LEN_S) & ETH_HDR_LEN_M) 415 416 /* cpl_pass_accept_req.l2info fields */ 417 #define SYN_MAC_IDX_S 0 418 #define SYN_MAC_IDX_M 0x1FF 419 #define SYN_MAC_IDX_V(x) ((x) << SYN_MAC_IDX_S) 420 #define SYN_MAC_IDX_G(x) (((x) >> SYN_MAC_IDX_S) & SYN_MAC_IDX_M) 421 422 #define SYN_XACT_MATCH_S 9 423 #define SYN_XACT_MATCH_V(x) ((x) << SYN_XACT_MATCH_S) 424 #define SYN_XACT_MATCH_F SYN_XACT_MATCH_V(1U) 425 426 #define SYN_INTF_S 12 427 #define SYN_INTF_M 0xF 428 #define SYN_INTF_V(x) ((x) << SYN_INTF_S) 429 #define SYN_INTF_G(x) (((x) >> SYN_INTF_S) & SYN_INTF_M) 430 431 enum { /* TCP congestion control algorithms */ 432 CONG_ALG_RENO, 433 CONG_ALG_TAHOE, 434 CONG_ALG_NEWRENO, 435 CONG_ALG_HIGHSPEED 436 }; 437 438 #define CONG_CNTRL_S 14 439 #define CONG_CNTRL_M 0x3 440 #define CONG_CNTRL_V(x) ((x) << CONG_CNTRL_S) 441 #define CONG_CNTRL_G(x) (((x) >> CONG_CNTRL_S) & CONG_CNTRL_M) 442 443 #define T5_ISS_S 18 444 #define T5_ISS_V(x) ((x) << T5_ISS_S) 445 #define T5_ISS_F T5_ISS_V(1U) 446 447 struct cpl_pass_accept_rpl { 448 WR_HDR; 449 union opcode_tid ot; 450 __be32 opt2; 451 __be64 opt0; 452 }; 453 454 /* option 2 fields */ 455 #define RX_COALESCE_VALID_S 11 456 #define RX_COALESCE_VALID_V(x) ((x) << RX_COALESCE_VALID_S) 457 #define RX_COALESCE_VALID_F RX_COALESCE_VALID_V(1U) 458 459 #define RX_COALESCE_S 12 460 #define RX_COALESCE_V(x) ((x) << RX_COALESCE_S) 461 462 #define PACE_S 16 463 #define PACE_V(x) ((x) << PACE_S) 464 465 #define TX_QUEUE_S 23 466 #define TX_QUEUE_M 0x7 467 #define TX_QUEUE_V(x) ((x) << TX_QUEUE_S) 468 #define TX_QUEUE_G(x) (((x) >> TX_QUEUE_S) & TX_QUEUE_M) 469 470 #define CCTRL_ECN_S 27 471 #define CCTRL_ECN_V(x) ((x) << CCTRL_ECN_S) 472 #define CCTRL_ECN_F CCTRL_ECN_V(1U) 473 474 #define TSTAMPS_EN_S 29 475 #define TSTAMPS_EN_V(x) ((x) << TSTAMPS_EN_S) 476 #define TSTAMPS_EN_F TSTAMPS_EN_V(1U) 477 478 #define SACK_EN_S 30 479 #define SACK_EN_V(x) ((x) << SACK_EN_S) 480 #define SACK_EN_F SACK_EN_V(1U) 481 482 struct cpl_t5_pass_accept_rpl { 483 WR_HDR; 484 union opcode_tid ot; 485 __be32 opt2; 486 __be64 opt0; 487 __be32 iss; 488 __be32 rsvd; 489 }; 490 491 struct cpl_act_open_req { 492 WR_HDR; 493 union opcode_tid ot; 494 __be16 local_port; 495 __be16 peer_port; 496 __be32 local_ip; 497 __be32 peer_ip; 498 __be64 opt0; 499 __be32 params; 500 __be32 opt2; 501 }; 502 503 #define FILTER_TUPLE_S 24 504 #define FILTER_TUPLE_M 0xFFFFFFFFFF 505 #define FILTER_TUPLE_V(x) ((x) << FILTER_TUPLE_S) 506 #define FILTER_TUPLE_G(x) (((x) >> FILTER_TUPLE_S) & FILTER_TUPLE_M) 507 struct cpl_t5_act_open_req { 508 WR_HDR; 509 union opcode_tid ot; 510 __be16 local_port; 511 __be16 peer_port; 512 __be32 local_ip; 513 __be32 peer_ip; 514 __be64 opt0; 515 __be32 rsvd; 516 __be32 opt2; 517 __be64 params; 518 }; 519 520 struct cpl_t6_act_open_req { 521 WR_HDR; 522 union opcode_tid ot; 523 __be16 local_port; 524 __be16 peer_port; 525 __be32 local_ip; 526 __be32 peer_ip; 527 __be64 opt0; 528 __be32 rsvd; 529 __be32 opt2; 530 __be64 params; 531 __be32 rsvd2; 532 __be32 opt3; 533 }; 534 535 struct cpl_act_open_req6 { 536 WR_HDR; 537 union opcode_tid ot; 538 __be16 local_port; 539 __be16 peer_port; 540 __be64 local_ip_hi; 541 __be64 local_ip_lo; 542 __be64 peer_ip_hi; 543 __be64 peer_ip_lo; 544 __be64 opt0; 545 __be32 params; 546 __be32 opt2; 547 }; 548 549 struct cpl_t5_act_open_req6 { 550 WR_HDR; 551 union opcode_tid ot; 552 __be16 local_port; 553 __be16 peer_port; 554 __be64 local_ip_hi; 555 __be64 local_ip_lo; 556 __be64 peer_ip_hi; 557 __be64 peer_ip_lo; 558 __be64 opt0; 559 __be32 rsvd; 560 __be32 opt2; 561 __be64 params; 562 }; 563 564 struct cpl_t6_act_open_req6 { 565 WR_HDR; 566 union opcode_tid ot; 567 __be16 local_port; 568 __be16 peer_port; 569 __be64 local_ip_hi; 570 __be64 local_ip_lo; 571 __be64 peer_ip_hi; 572 __be64 peer_ip_lo; 573 __be64 opt0; 574 __be32 rsvd; 575 __be32 opt2; 576 __be64 params; 577 __be32 rsvd2; 578 __be32 opt3; 579 }; 580 581 struct cpl_act_open_rpl { 582 union opcode_tid ot; 583 __be32 atid_status; 584 }; 585 586 /* cpl_act_open_rpl.atid_status fields */ 587 #define AOPEN_STATUS_S 0 588 #define AOPEN_STATUS_M 0xFF 589 #define AOPEN_STATUS_G(x) (((x) >> AOPEN_STATUS_S) & AOPEN_STATUS_M) 590 591 #define AOPEN_ATID_S 8 592 #define AOPEN_ATID_M 0xFFFFFF 593 #define AOPEN_ATID_G(x) (((x) >> AOPEN_ATID_S) & AOPEN_ATID_M) 594 595 struct cpl_pass_establish { 596 union opcode_tid ot; 597 __be32 rsvd; 598 __be32 tos_stid; 599 __be16 mac_idx; 600 __be16 tcp_opt; 601 __be32 snd_isn; 602 __be32 rcv_isn; 603 }; 604 605 /* cpl_pass_establish.tos_stid fields */ 606 #define PASS_OPEN_TID_S 0 607 #define PASS_OPEN_TID_M 0xFFFFFF 608 #define PASS_OPEN_TID_V(x) ((x) << PASS_OPEN_TID_S) 609 #define PASS_OPEN_TID_G(x) (((x) >> PASS_OPEN_TID_S) & PASS_OPEN_TID_M) 610 611 #define PASS_OPEN_TOS_S 24 612 #define PASS_OPEN_TOS_M 0xFF 613 #define PASS_OPEN_TOS_V(x) ((x) << PASS_OPEN_TOS_S) 614 #define PASS_OPEN_TOS_G(x) (((x) >> PASS_OPEN_TOS_S) & PASS_OPEN_TOS_M) 615 616 /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */ 617 #define TCPOPT_WSCALE_OK_S 5 618 #define TCPOPT_WSCALE_OK_M 0x1 619 #define TCPOPT_WSCALE_OK_G(x) \ 620 (((x) >> TCPOPT_WSCALE_OK_S) & TCPOPT_WSCALE_OK_M) 621 622 #define TCPOPT_SACK_S 6 623 #define TCPOPT_SACK_M 0x1 624 #define TCPOPT_SACK_G(x) (((x) >> TCPOPT_SACK_S) & TCPOPT_SACK_M) 625 626 #define TCPOPT_TSTAMP_S 7 627 #define TCPOPT_TSTAMP_M 0x1 628 #define TCPOPT_TSTAMP_G(x) (((x) >> TCPOPT_TSTAMP_S) & TCPOPT_TSTAMP_M) 629 630 #define TCPOPT_SND_WSCALE_S 8 631 #define TCPOPT_SND_WSCALE_M 0xF 632 #define TCPOPT_SND_WSCALE_G(x) \ 633 (((x) >> TCPOPT_SND_WSCALE_S) & TCPOPT_SND_WSCALE_M) 634 635 #define TCPOPT_MSS_S 12 636 #define TCPOPT_MSS_M 0xF 637 #define TCPOPT_MSS_G(x) (((x) >> TCPOPT_MSS_S) & TCPOPT_MSS_M) 638 639 #define T6_TCP_HDR_LEN_S 8 640 #define T6_TCP_HDR_LEN_V(x) ((x) << T6_TCP_HDR_LEN_S) 641 #define T6_TCP_HDR_LEN_G(x) (((x) >> T6_TCP_HDR_LEN_S) & TCP_HDR_LEN_M) 642 643 #define T6_IP_HDR_LEN_S 14 644 #define T6_IP_HDR_LEN_V(x) ((x) << T6_IP_HDR_LEN_S) 645 #define T6_IP_HDR_LEN_G(x) (((x) >> T6_IP_HDR_LEN_S) & IP_HDR_LEN_M) 646 647 #define T6_ETH_HDR_LEN_S 24 648 #define T6_ETH_HDR_LEN_M 0xFF 649 #define T6_ETH_HDR_LEN_V(x) ((x) << T6_ETH_HDR_LEN_S) 650 #define T6_ETH_HDR_LEN_G(x) (((x) >> T6_ETH_HDR_LEN_S) & T6_ETH_HDR_LEN_M) 651 652 struct cpl_act_establish { 653 union opcode_tid ot; 654 __be32 rsvd; 655 __be32 tos_atid; 656 __be16 mac_idx; 657 __be16 tcp_opt; 658 __be32 snd_isn; 659 __be32 rcv_isn; 660 }; 661 662 struct cpl_get_tcb { 663 WR_HDR; 664 union opcode_tid ot; 665 __be16 reply_ctrl; 666 __be16 cookie; 667 }; 668 669 /* cpl_get_tcb.reply_ctrl fields */ 670 #define QUEUENO_S 0 671 #define QUEUENO_V(x) ((x) << QUEUENO_S) 672 673 #define REPLY_CHAN_S 14 674 #define REPLY_CHAN_V(x) ((x) << REPLY_CHAN_S) 675 #define REPLY_CHAN_F REPLY_CHAN_V(1U) 676 677 #define NO_REPLY_S 15 678 #define NO_REPLY_V(x) ((x) << NO_REPLY_S) 679 #define NO_REPLY_F NO_REPLY_V(1U) 680 681 struct cpl_set_tcb_field { 682 WR_HDR; 683 union opcode_tid ot; 684 __be16 reply_ctrl; 685 __be16 word_cookie; 686 __be64 mask; 687 __be64 val; 688 }; 689 690 /* cpl_set_tcb_field.word_cookie fields */ 691 #define TCB_WORD_S 0 692 #define TCB_WORD_V(x) ((x) << TCB_WORD_S) 693 694 #define TCB_COOKIE_S 5 695 #define TCB_COOKIE_M 0x7 696 #define TCB_COOKIE_V(x) ((x) << TCB_COOKIE_S) 697 #define TCB_COOKIE_G(x) (((x) >> TCB_COOKIE_S) & TCB_COOKIE_M) 698 699 struct cpl_set_tcb_rpl { 700 union opcode_tid ot; 701 __be16 rsvd; 702 u8 cookie; 703 u8 status; 704 __be64 oldval; 705 }; 706 707 struct cpl_close_con_req { 708 WR_HDR; 709 union opcode_tid ot; 710 __be32 rsvd; 711 }; 712 713 struct cpl_close_con_rpl { 714 union opcode_tid ot; 715 u8 rsvd[3]; 716 u8 status; 717 __be32 snd_nxt; 718 __be32 rcv_nxt; 719 }; 720 721 struct cpl_close_listsvr_req { 722 WR_HDR; 723 union opcode_tid ot; 724 __be16 reply_ctrl; 725 __be16 rsvd; 726 }; 727 728 /* additional cpl_close_listsvr_req.reply_ctrl field */ 729 #define LISTSVR_IPV6_S 14 730 #define LISTSVR_IPV6_V(x) ((x) << LISTSVR_IPV6_S) 731 #define LISTSVR_IPV6_F LISTSVR_IPV6_V(1U) 732 733 struct cpl_close_listsvr_rpl { 734 union opcode_tid ot; 735 u8 rsvd[3]; 736 u8 status; 737 }; 738 739 struct cpl_abort_req_rss { 740 union opcode_tid ot; 741 u8 rsvd[3]; 742 u8 status; 743 }; 744 745 struct cpl_abort_req { 746 WR_HDR; 747 union opcode_tid ot; 748 __be32 rsvd0; 749 u8 rsvd1; 750 u8 cmd; 751 u8 rsvd2[6]; 752 }; 753 754 struct cpl_abort_rpl_rss { 755 union opcode_tid ot; 756 u8 rsvd[3]; 757 u8 status; 758 }; 759 760 struct cpl_abort_rpl { 761 WR_HDR; 762 union opcode_tid ot; 763 __be32 rsvd0; 764 u8 rsvd1; 765 u8 cmd; 766 u8 rsvd2[6]; 767 }; 768 769 struct cpl_peer_close { 770 union opcode_tid ot; 771 __be32 rcv_nxt; 772 }; 773 774 struct cpl_tid_release { 775 WR_HDR; 776 union opcode_tid ot; 777 __be32 rsvd; 778 }; 779 780 struct cpl_tx_pkt_core { 781 __be32 ctrl0; 782 __be16 pack; 783 __be16 len; 784 __be64 ctrl1; 785 }; 786 787 struct cpl_tx_pkt { 788 WR_HDR; 789 struct cpl_tx_pkt_core c; 790 }; 791 792 #define cpl_tx_pkt_xt cpl_tx_pkt 793 794 /* cpl_tx_pkt_core.ctrl0 fields */ 795 #define TXPKT_VF_S 0 796 #define TXPKT_VF_V(x) ((x) << TXPKT_VF_S) 797 798 #define TXPKT_PF_S 8 799 #define TXPKT_PF_V(x) ((x) << TXPKT_PF_S) 800 801 #define TXPKT_VF_VLD_S 11 802 #define TXPKT_VF_VLD_V(x) ((x) << TXPKT_VF_VLD_S) 803 #define TXPKT_VF_VLD_F TXPKT_VF_VLD_V(1U) 804 805 #define TXPKT_OVLAN_IDX_S 12 806 #define TXPKT_OVLAN_IDX_V(x) ((x) << TXPKT_OVLAN_IDX_S) 807 808 #define TXPKT_T5_OVLAN_IDX_S 12 809 #define TXPKT_T5_OVLAN_IDX_V(x) ((x) << TXPKT_T5_OVLAN_IDX_S) 810 811 #define TXPKT_INTF_S 16 812 #define TXPKT_INTF_V(x) ((x) << TXPKT_INTF_S) 813 814 #define TXPKT_INS_OVLAN_S 21 815 #define TXPKT_INS_OVLAN_V(x) ((x) << TXPKT_INS_OVLAN_S) 816 #define TXPKT_INS_OVLAN_F TXPKT_INS_OVLAN_V(1U) 817 818 #define TXPKT_TSTAMP_S 23 819 #define TXPKT_TSTAMP_V(x) ((x) << TXPKT_TSTAMP_S) 820 #define TXPKT_TSTAMP_F TXPKT_TSTAMP_V(1ULL) 821 822 #define TXPKT_OPCODE_S 24 823 #define TXPKT_OPCODE_V(x) ((x) << TXPKT_OPCODE_S) 824 825 /* cpl_tx_pkt_core.ctrl1 fields */ 826 #define TXPKT_CSUM_END_S 12 827 #define TXPKT_CSUM_END_V(x) ((x) << TXPKT_CSUM_END_S) 828 829 #define TXPKT_CSUM_START_S 20 830 #define TXPKT_CSUM_START_V(x) ((x) << TXPKT_CSUM_START_S) 831 832 #define TXPKT_IPHDR_LEN_S 20 833 #define TXPKT_IPHDR_LEN_V(x) ((__u64)(x) << TXPKT_IPHDR_LEN_S) 834 835 #define TXPKT_CSUM_LOC_S 30 836 #define TXPKT_CSUM_LOC_V(x) ((__u64)(x) << TXPKT_CSUM_LOC_S) 837 838 #define TXPKT_ETHHDR_LEN_S 34 839 #define TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << TXPKT_ETHHDR_LEN_S) 840 841 #define T6_TXPKT_ETHHDR_LEN_S 32 842 #define T6_TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << T6_TXPKT_ETHHDR_LEN_S) 843 844 #define TXPKT_CSUM_TYPE_S 40 845 #define TXPKT_CSUM_TYPE_V(x) ((__u64)(x) << TXPKT_CSUM_TYPE_S) 846 847 #define TXPKT_VLAN_S 44 848 #define TXPKT_VLAN_V(x) ((__u64)(x) << TXPKT_VLAN_S) 849 850 #define TXPKT_VLAN_VLD_S 60 851 #define TXPKT_VLAN_VLD_V(x) ((__u64)(x) << TXPKT_VLAN_VLD_S) 852 #define TXPKT_VLAN_VLD_F TXPKT_VLAN_VLD_V(1ULL) 853 854 #define TXPKT_IPCSUM_DIS_S 62 855 #define TXPKT_IPCSUM_DIS_V(x) ((__u64)(x) << TXPKT_IPCSUM_DIS_S) 856 #define TXPKT_IPCSUM_DIS_F TXPKT_IPCSUM_DIS_V(1ULL) 857 858 #define TXPKT_L4CSUM_DIS_S 63 859 #define TXPKT_L4CSUM_DIS_V(x) ((__u64)(x) << TXPKT_L4CSUM_DIS_S) 860 #define TXPKT_L4CSUM_DIS_F TXPKT_L4CSUM_DIS_V(1ULL) 861 862 struct cpl_tx_pkt_lso_core { 863 __be32 lso_ctrl; 864 __be16 ipid_ofst; 865 __be16 mss; 866 __be32 seqno_offset; 867 __be32 len; 868 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 869 }; 870 871 /* cpl_tx_pkt_lso_core.lso_ctrl fields */ 872 #define LSO_TCPHDR_LEN_S 0 873 #define LSO_TCPHDR_LEN_V(x) ((x) << LSO_TCPHDR_LEN_S) 874 875 #define LSO_IPHDR_LEN_S 4 876 #define LSO_IPHDR_LEN_V(x) ((x) << LSO_IPHDR_LEN_S) 877 878 #define LSO_ETHHDR_LEN_S 16 879 #define LSO_ETHHDR_LEN_V(x) ((x) << LSO_ETHHDR_LEN_S) 880 881 #define LSO_IPV6_S 20 882 #define LSO_IPV6_V(x) ((x) << LSO_IPV6_S) 883 #define LSO_IPV6_F LSO_IPV6_V(1U) 884 885 #define LSO_LAST_SLICE_S 22 886 #define LSO_LAST_SLICE_V(x) ((x) << LSO_LAST_SLICE_S) 887 #define LSO_LAST_SLICE_F LSO_LAST_SLICE_V(1U) 888 889 #define LSO_FIRST_SLICE_S 23 890 #define LSO_FIRST_SLICE_V(x) ((x) << LSO_FIRST_SLICE_S) 891 #define LSO_FIRST_SLICE_F LSO_FIRST_SLICE_V(1U) 892 893 #define LSO_OPCODE_S 24 894 #define LSO_OPCODE_V(x) ((x) << LSO_OPCODE_S) 895 896 #define LSO_T5_XFER_SIZE_S 0 897 #define LSO_T5_XFER_SIZE_V(x) ((x) << LSO_T5_XFER_SIZE_S) 898 899 struct cpl_tx_pkt_lso { 900 WR_HDR; 901 struct cpl_tx_pkt_lso_core c; 902 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 903 }; 904 905 struct cpl_iscsi_hdr { 906 union opcode_tid ot; 907 __be16 pdu_len_ddp; 908 __be16 len; 909 __be32 seq; 910 __be16 urg; 911 u8 rsvd; 912 u8 status; 913 }; 914 915 /* cpl_iscsi_hdr.pdu_len_ddp fields */ 916 #define ISCSI_PDU_LEN_S 0 917 #define ISCSI_PDU_LEN_M 0x7FFF 918 #define ISCSI_PDU_LEN_V(x) ((x) << ISCSI_PDU_LEN_S) 919 #define ISCSI_PDU_LEN_G(x) (((x) >> ISCSI_PDU_LEN_S) & ISCSI_PDU_LEN_M) 920 921 #define ISCSI_DDP_S 15 922 #define ISCSI_DDP_V(x) ((x) << ISCSI_DDP_S) 923 #define ISCSI_DDP_F ISCSI_DDP_V(1U) 924 925 struct cpl_rx_data_ddp { 926 union opcode_tid ot; 927 __be16 urg; 928 __be16 len; 929 __be32 seq; 930 union { 931 __be32 nxt_seq; 932 __be32 ddp_report; 933 }; 934 __be32 ulp_crc; 935 __be32 ddpvld; 936 }; 937 938 #define cpl_rx_iscsi_ddp cpl_rx_data_ddp 939 940 struct cpl_iscsi_data { 941 union opcode_tid ot; 942 __u8 rsvd0[2]; 943 __be16 len; 944 __be32 seq; 945 __be16 urg; 946 __u8 rsvd1; 947 __u8 status; 948 }; 949 950 struct cpl_rx_iscsi_cmp { 951 union opcode_tid ot; 952 __be16 pdu_len_ddp; 953 __be16 len; 954 __be32 seq; 955 __be16 urg; 956 __u8 rsvd; 957 __u8 status; 958 __be32 ulp_crc; 959 __be32 ddpvld; 960 }; 961 962 struct cpl_tx_data_iso { 963 __be32 op_to_scsi; 964 __u8 reserved1; 965 __u8 ahs_len; 966 __be16 mpdu; 967 __be32 burst_size; 968 __be32 len; 969 __be32 reserved2_seglen_offset; 970 __be32 datasn_offset; 971 __be32 buffer_offset; 972 __be32 reserved3; 973 974 /* encapsulated CPL_TX_DATA follows here */ 975 }; 976 977 /* cpl_tx_data_iso.op_to_scsi fields */ 978 #define CPL_TX_DATA_ISO_OP_S 24 979 #define CPL_TX_DATA_ISO_OP_M 0xff 980 #define CPL_TX_DATA_ISO_OP_V(x) ((x) << CPL_TX_DATA_ISO_OP_S) 981 #define CPL_TX_DATA_ISO_OP_G(x) \ 982 (((x) >> CPL_TX_DATA_ISO_OP_S) & CPL_TX_DATA_ISO_OP_M) 983 984 #define CPL_TX_DATA_ISO_FIRST_S 23 985 #define CPL_TX_DATA_ISO_FIRST_M 0x1 986 #define CPL_TX_DATA_ISO_FIRST_V(x) ((x) << CPL_TX_DATA_ISO_FIRST_S) 987 #define CPL_TX_DATA_ISO_FIRST_G(x) \ 988 (((x) >> CPL_TX_DATA_ISO_FIRST_S) & CPL_TX_DATA_ISO_FIRST_M) 989 #define CPL_TX_DATA_ISO_FIRST_F CPL_TX_DATA_ISO_FIRST_V(1U) 990 991 #define CPL_TX_DATA_ISO_LAST_S 22 992 #define CPL_TX_DATA_ISO_LAST_M 0x1 993 #define CPL_TX_DATA_ISO_LAST_V(x) ((x) << CPL_TX_DATA_ISO_LAST_S) 994 #define CPL_TX_DATA_ISO_LAST_G(x) \ 995 (((x) >> CPL_TX_DATA_ISO_LAST_S) & CPL_TX_DATA_ISO_LAST_M) 996 #define CPL_TX_DATA_ISO_LAST_F CPL_TX_DATA_ISO_LAST_V(1U) 997 998 #define CPL_TX_DATA_ISO_CPLHDRLEN_S 21 999 #define CPL_TX_DATA_ISO_CPLHDRLEN_M 0x1 1000 #define CPL_TX_DATA_ISO_CPLHDRLEN_V(x) ((x) << CPL_TX_DATA_ISO_CPLHDRLEN_S) 1001 #define CPL_TX_DATA_ISO_CPLHDRLEN_G(x) \ 1002 (((x) >> CPL_TX_DATA_ISO_CPLHDRLEN_S) & CPL_TX_DATA_ISO_CPLHDRLEN_M) 1003 #define CPL_TX_DATA_ISO_CPLHDRLEN_F CPL_TX_DATA_ISO_CPLHDRLEN_V(1U) 1004 1005 #define CPL_TX_DATA_ISO_HDRCRC_S 20 1006 #define CPL_TX_DATA_ISO_HDRCRC_M 0x1 1007 #define CPL_TX_DATA_ISO_HDRCRC_V(x) ((x) << CPL_TX_DATA_ISO_HDRCRC_S) 1008 #define CPL_TX_DATA_ISO_HDRCRC_G(x) \ 1009 (((x) >> CPL_TX_DATA_ISO_HDRCRC_S) & CPL_TX_DATA_ISO_HDRCRC_M) 1010 #define CPL_TX_DATA_ISO_HDRCRC_F CPL_TX_DATA_ISO_HDRCRC_V(1U) 1011 1012 #define CPL_TX_DATA_ISO_PLDCRC_S 19 1013 #define CPL_TX_DATA_ISO_PLDCRC_M 0x1 1014 #define CPL_TX_DATA_ISO_PLDCRC_V(x) ((x) << CPL_TX_DATA_ISO_PLDCRC_S) 1015 #define CPL_TX_DATA_ISO_PLDCRC_G(x) \ 1016 (((x) >> CPL_TX_DATA_ISO_PLDCRC_S) & CPL_TX_DATA_ISO_PLDCRC_M) 1017 #define CPL_TX_DATA_ISO_PLDCRC_F CPL_TX_DATA_ISO_PLDCRC_V(1U) 1018 1019 #define CPL_TX_DATA_ISO_IMMEDIATE_S 18 1020 #define CPL_TX_DATA_ISO_IMMEDIATE_M 0x1 1021 #define CPL_TX_DATA_ISO_IMMEDIATE_V(x) ((x) << CPL_TX_DATA_ISO_IMMEDIATE_S) 1022 #define CPL_TX_DATA_ISO_IMMEDIATE_G(x) \ 1023 (((x) >> CPL_TX_DATA_ISO_IMMEDIATE_S) & CPL_TX_DATA_ISO_IMMEDIATE_M) 1024 #define CPL_TX_DATA_ISO_IMMEDIATE_F CPL_TX_DATA_ISO_IMMEDIATE_V(1U) 1025 1026 #define CPL_TX_DATA_ISO_SCSI_S 16 1027 #define CPL_TX_DATA_ISO_SCSI_M 0x3 1028 #define CPL_TX_DATA_ISO_SCSI_V(x) ((x) << CPL_TX_DATA_ISO_SCSI_S) 1029 #define CPL_TX_DATA_ISO_SCSI_G(x) \ 1030 (((x) >> CPL_TX_DATA_ISO_SCSI_S) & CPL_TX_DATA_ISO_SCSI_M) 1031 1032 /* cpl_tx_data_iso.reserved2_seglen_offset fields */ 1033 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_S 0 1034 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_M 0xffffff 1035 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_V(x) \ 1036 ((x) << CPL_TX_DATA_ISO_SEGLEN_OFFSET_S) 1037 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_G(x) \ 1038 (((x) >> CPL_TX_DATA_ISO_SEGLEN_OFFSET_S) & \ 1039 CPL_TX_DATA_ISO_SEGLEN_OFFSET_M) 1040 1041 struct cpl_rx_data { 1042 union opcode_tid ot; 1043 __be16 rsvd; 1044 __be16 len; 1045 __be32 seq; 1046 __be16 urg; 1047 #if defined(__LITTLE_ENDIAN_BITFIELD) 1048 u8 dack_mode:2; 1049 u8 psh:1; 1050 u8 heartbeat:1; 1051 u8 ddp_off:1; 1052 u8 :3; 1053 #else 1054 u8 :3; 1055 u8 ddp_off:1; 1056 u8 heartbeat:1; 1057 u8 psh:1; 1058 u8 dack_mode:2; 1059 #endif 1060 u8 status; 1061 }; 1062 1063 struct cpl_rx_data_ack { 1064 WR_HDR; 1065 union opcode_tid ot; 1066 __be32 credit_dack; 1067 }; 1068 1069 /* cpl_rx_data_ack.ack_seq fields */ 1070 #define RX_CREDITS_S 0 1071 #define RX_CREDITS_V(x) ((x) << RX_CREDITS_S) 1072 1073 #define RX_FORCE_ACK_S 28 1074 #define RX_FORCE_ACK_V(x) ((x) << RX_FORCE_ACK_S) 1075 #define RX_FORCE_ACK_F RX_FORCE_ACK_V(1U) 1076 1077 #define RX_DACK_MODE_S 29 1078 #define RX_DACK_MODE_M 0x3 1079 #define RX_DACK_MODE_V(x) ((x) << RX_DACK_MODE_S) 1080 #define RX_DACK_MODE_G(x) (((x) >> RX_DACK_MODE_S) & RX_DACK_MODE_M) 1081 1082 #define RX_DACK_CHANGE_S 31 1083 #define RX_DACK_CHANGE_V(x) ((x) << RX_DACK_CHANGE_S) 1084 #define RX_DACK_CHANGE_F RX_DACK_CHANGE_V(1U) 1085 1086 struct cpl_rx_pkt { 1087 struct rss_header rsshdr; 1088 u8 opcode; 1089 #if defined(__LITTLE_ENDIAN_BITFIELD) 1090 u8 iff:4; 1091 u8 csum_calc:1; 1092 u8 ipmi_pkt:1; 1093 u8 vlan_ex:1; 1094 u8 ip_frag:1; 1095 #else 1096 u8 ip_frag:1; 1097 u8 vlan_ex:1; 1098 u8 ipmi_pkt:1; 1099 u8 csum_calc:1; 1100 u8 iff:4; 1101 #endif 1102 __be16 csum; 1103 __be16 vlan; 1104 __be16 len; 1105 __be32 l2info; 1106 __be16 hdr_len; 1107 __be16 err_vec; 1108 }; 1109 1110 #define RX_T6_ETHHDR_LEN_M 0xFF 1111 #define RX_T6_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_T6_ETHHDR_LEN_M) 1112 1113 #define RXF_PSH_S 20 1114 #define RXF_PSH_V(x) ((x) << RXF_PSH_S) 1115 #define RXF_PSH_F RXF_PSH_V(1U) 1116 1117 #define RXF_SYN_S 21 1118 #define RXF_SYN_V(x) ((x) << RXF_SYN_S) 1119 #define RXF_SYN_F RXF_SYN_V(1U) 1120 1121 #define RXF_UDP_S 22 1122 #define RXF_UDP_V(x) ((x) << RXF_UDP_S) 1123 #define RXF_UDP_F RXF_UDP_V(1U) 1124 1125 #define RXF_TCP_S 23 1126 #define RXF_TCP_V(x) ((x) << RXF_TCP_S) 1127 #define RXF_TCP_F RXF_TCP_V(1U) 1128 1129 #define RXF_IP_S 24 1130 #define RXF_IP_V(x) ((x) << RXF_IP_S) 1131 #define RXF_IP_F RXF_IP_V(1U) 1132 1133 #define RXF_IP6_S 25 1134 #define RXF_IP6_V(x) ((x) << RXF_IP6_S) 1135 #define RXF_IP6_F RXF_IP6_V(1U) 1136 1137 #define RXF_SYN_COOKIE_S 26 1138 #define RXF_SYN_COOKIE_V(x) ((x) << RXF_SYN_COOKIE_S) 1139 #define RXF_SYN_COOKIE_F RXF_SYN_COOKIE_V(1U) 1140 1141 #define RXF_FCOE_S 26 1142 #define RXF_FCOE_V(x) ((x) << RXF_FCOE_S) 1143 #define RXF_FCOE_F RXF_FCOE_V(1U) 1144 1145 #define RXF_LRO_S 27 1146 #define RXF_LRO_V(x) ((x) << RXF_LRO_S) 1147 #define RXF_LRO_F RXF_LRO_V(1U) 1148 1149 /* rx_pkt.l2info fields */ 1150 #define RX_ETHHDR_LEN_S 0 1151 #define RX_ETHHDR_LEN_M 0x1F 1152 #define RX_ETHHDR_LEN_V(x) ((x) << RX_ETHHDR_LEN_S) 1153 #define RX_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_ETHHDR_LEN_M) 1154 1155 #define RX_T5_ETHHDR_LEN_S 0 1156 #define RX_T5_ETHHDR_LEN_M 0x3F 1157 #define RX_T5_ETHHDR_LEN_V(x) ((x) << RX_T5_ETHHDR_LEN_S) 1158 #define RX_T5_ETHHDR_LEN_G(x) (((x) >> RX_T5_ETHHDR_LEN_S) & RX_T5_ETHHDR_LEN_M) 1159 1160 #define RX_MACIDX_S 8 1161 #define RX_MACIDX_M 0x1FF 1162 #define RX_MACIDX_V(x) ((x) << RX_MACIDX_S) 1163 #define RX_MACIDX_G(x) (((x) >> RX_MACIDX_S) & RX_MACIDX_M) 1164 1165 #define RXF_SYN_S 21 1166 #define RXF_SYN_V(x) ((x) << RXF_SYN_S) 1167 #define RXF_SYN_F RXF_SYN_V(1U) 1168 1169 #define RX_CHAN_S 28 1170 #define RX_CHAN_M 0xF 1171 #define RX_CHAN_V(x) ((x) << RX_CHAN_S) 1172 #define RX_CHAN_G(x) (((x) >> RX_CHAN_S) & RX_CHAN_M) 1173 1174 /* rx_pkt.hdr_len fields */ 1175 #define RX_TCPHDR_LEN_S 0 1176 #define RX_TCPHDR_LEN_M 0x3F 1177 #define RX_TCPHDR_LEN_V(x) ((x) << RX_TCPHDR_LEN_S) 1178 #define RX_TCPHDR_LEN_G(x) (((x) >> RX_TCPHDR_LEN_S) & RX_TCPHDR_LEN_M) 1179 1180 #define RX_IPHDR_LEN_S 6 1181 #define RX_IPHDR_LEN_M 0x3FF 1182 #define RX_IPHDR_LEN_V(x) ((x) << RX_IPHDR_LEN_S) 1183 #define RX_IPHDR_LEN_G(x) (((x) >> RX_IPHDR_LEN_S) & RX_IPHDR_LEN_M) 1184 1185 /* rx_pkt.err_vec fields */ 1186 #define RXERR_CSUM_S 13 1187 #define RXERR_CSUM_V(x) ((x) << RXERR_CSUM_S) 1188 #define RXERR_CSUM_F RXERR_CSUM_V(1U) 1189 1190 #define T6_COMPR_RXERR_LEN_S 1 1191 #define T6_COMPR_RXERR_LEN_V(x) ((x) << T6_COMPR_RXERR_LEN_S) 1192 #define T6_COMPR_RXERR_LEN_F T6_COMPR_RXERR_LEN_V(1U) 1193 1194 #define T6_COMPR_RXERR_VEC_S 0 1195 #define T6_COMPR_RXERR_VEC_M 0x3F 1196 #define T6_COMPR_RXERR_VEC_V(x) ((x) << T6_COMPR_RXERR_LEN_S) 1197 #define T6_COMPR_RXERR_VEC_G(x) \ 1198 (((x) >> T6_COMPR_RXERR_VEC_S) & T6_COMPR_RXERR_VEC_M) 1199 1200 /* Logical OR of RX_ERROR_CSUM, RX_ERROR_CSIP */ 1201 #define T6_COMPR_RXERR_SUM_S 4 1202 #define T6_COMPR_RXERR_SUM_V(x) ((x) << T6_COMPR_RXERR_SUM_S) 1203 #define T6_COMPR_RXERR_SUM_F T6_COMPR_RXERR_SUM_V(1U) 1204 1205 struct cpl_trace_pkt { 1206 u8 opcode; 1207 u8 intf; 1208 #if defined(__LITTLE_ENDIAN_BITFIELD) 1209 u8 runt:4; 1210 u8 filter_hit:4; 1211 u8 :6; 1212 u8 err:1; 1213 u8 trunc:1; 1214 #else 1215 u8 filter_hit:4; 1216 u8 runt:4; 1217 u8 trunc:1; 1218 u8 err:1; 1219 u8 :6; 1220 #endif 1221 __be16 rsvd; 1222 __be16 len; 1223 __be64 tstamp; 1224 }; 1225 1226 struct cpl_t5_trace_pkt { 1227 __u8 opcode; 1228 __u8 intf; 1229 #if defined(__LITTLE_ENDIAN_BITFIELD) 1230 __u8 runt:4; 1231 __u8 filter_hit:4; 1232 __u8:6; 1233 __u8 err:1; 1234 __u8 trunc:1; 1235 #else 1236 __u8 filter_hit:4; 1237 __u8 runt:4; 1238 __u8 trunc:1; 1239 __u8 err:1; 1240 __u8:6; 1241 #endif 1242 __be16 rsvd; 1243 __be16 len; 1244 __be64 tstamp; 1245 __be64 rsvd1; 1246 }; 1247 1248 struct cpl_l2t_write_req { 1249 WR_HDR; 1250 union opcode_tid ot; 1251 __be16 params; 1252 __be16 l2t_idx; 1253 __be16 vlan; 1254 u8 dst_mac[6]; 1255 }; 1256 1257 /* cpl_l2t_write_req.params fields */ 1258 #define L2T_W_INFO_S 2 1259 #define L2T_W_INFO_V(x) ((x) << L2T_W_INFO_S) 1260 1261 #define L2T_W_PORT_S 8 1262 #define L2T_W_PORT_V(x) ((x) << L2T_W_PORT_S) 1263 1264 #define L2T_W_NOREPLY_S 15 1265 #define L2T_W_NOREPLY_V(x) ((x) << L2T_W_NOREPLY_S) 1266 #define L2T_W_NOREPLY_F L2T_W_NOREPLY_V(1U) 1267 1268 #define CPL_L2T_VLAN_NONE 0xfff 1269 1270 struct cpl_l2t_write_rpl { 1271 union opcode_tid ot; 1272 u8 status; 1273 u8 rsvd[3]; 1274 }; 1275 1276 struct cpl_smt_write_req { 1277 WR_HDR; 1278 union opcode_tid ot; 1279 __be32 params; 1280 __be16 pfvf1; 1281 u8 src_mac1[6]; 1282 __be16 pfvf0; 1283 u8 src_mac0[6]; 1284 }; 1285 1286 struct cpl_t6_smt_write_req { 1287 WR_HDR; 1288 union opcode_tid ot; 1289 __be32 params; 1290 __be64 tag; 1291 __be16 pfvf0; 1292 u8 src_mac0[6]; 1293 __be32 local_ip; 1294 __be32 rsvd; 1295 }; 1296 1297 struct cpl_smt_write_rpl { 1298 union opcode_tid ot; 1299 u8 status; 1300 u8 rsvd[3]; 1301 }; 1302 1303 /* cpl_smt_{read,write}_req.params fields */ 1304 #define SMTW_OVLAN_IDX_S 16 1305 #define SMTW_OVLAN_IDX_V(x) ((x) << SMTW_OVLAN_IDX_S) 1306 1307 #define SMTW_IDX_S 20 1308 #define SMTW_IDX_V(x) ((x) << SMTW_IDX_S) 1309 1310 #define SMTW_NORPL_S 31 1311 #define SMTW_NORPL_V(x) ((x) << SMTW_NORPL_S) 1312 #define SMTW_NORPL_F SMTW_NORPL_V(1U) 1313 1314 struct cpl_rdma_terminate { 1315 union opcode_tid ot; 1316 __be16 rsvd; 1317 __be16 len; 1318 }; 1319 1320 struct cpl_sge_egr_update { 1321 __be32 opcode_qid; 1322 __be16 cidx; 1323 __be16 pidx; 1324 }; 1325 1326 /* cpl_sge_egr_update.ot fields */ 1327 #define EGR_QID_S 0 1328 #define EGR_QID_M 0x1FFFF 1329 #define EGR_QID_G(x) (((x) >> EGR_QID_S) & EGR_QID_M) 1330 1331 /* cpl_fw*.type values */ 1332 enum { 1333 FW_TYPE_CMD_RPL = 0, 1334 FW_TYPE_WR_RPL = 1, 1335 FW_TYPE_CQE = 2, 1336 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3, 1337 FW_TYPE_RSSCPL = 4, 1338 }; 1339 1340 struct cpl_fw4_pld { 1341 u8 opcode; 1342 u8 rsvd0[3]; 1343 u8 type; 1344 u8 rsvd1; 1345 __be16 len; 1346 __be64 data; 1347 __be64 rsvd2; 1348 }; 1349 1350 struct cpl_fw6_pld { 1351 u8 opcode; 1352 u8 rsvd[5]; 1353 __be16 len; 1354 __be64 data[4]; 1355 }; 1356 1357 struct cpl_fw4_msg { 1358 u8 opcode; 1359 u8 type; 1360 __be16 rsvd0; 1361 __be32 rsvd1; 1362 __be64 data[2]; 1363 }; 1364 1365 struct cpl_fw4_ack { 1366 union opcode_tid ot; 1367 u8 credits; 1368 u8 rsvd0[2]; 1369 u8 seq_vld; 1370 __be32 snd_nxt; 1371 __be32 snd_una; 1372 __be64 rsvd1; 1373 }; 1374 1375 enum { 1376 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1, /* seqn valid */ 1377 CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */ 1378 CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */ 1379 }; 1380 1381 struct cpl_fw6_msg { 1382 u8 opcode; 1383 u8 type; 1384 __be16 rsvd0; 1385 __be32 rsvd1; 1386 __be64 data[4]; 1387 }; 1388 1389 /* cpl_fw6_msg.type values */ 1390 enum { 1391 FW6_TYPE_CMD_RPL = 0, 1392 FW6_TYPE_WR_RPL = 1, 1393 FW6_TYPE_CQE = 2, 1394 FW6_TYPE_OFLD_CONNECTION_WR_RPL = 3, 1395 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL, 1396 }; 1397 1398 struct cpl_fw6_msg_ofld_connection_wr_rpl { 1399 __u64 cookie; 1400 __be32 tid; /* or atid in case of active failure */ 1401 __u8 t_state; 1402 __u8 retval; 1403 __u8 rsvd[2]; 1404 }; 1405 1406 struct cpl_tx_data { 1407 union opcode_tid ot; 1408 __be32 len; 1409 __be32 rsvd; 1410 __be32 flags; 1411 }; 1412 1413 /* cpl_tx_data.flags field */ 1414 #define TX_FORCE_S 13 1415 #define TX_FORCE_V(x) ((x) << TX_FORCE_S) 1416 1417 #define T6_TX_FORCE_S 20 1418 #define T6_TX_FORCE_V(x) ((x) << T6_TX_FORCE_S) 1419 #define T6_TX_FORCE_F T6_TX_FORCE_V(1U) 1420 1421 enum { 1422 ULP_TX_MEM_READ = 2, 1423 ULP_TX_MEM_WRITE = 3, 1424 ULP_TX_PKT = 4 1425 }; 1426 1427 enum { 1428 ULP_TX_SC_NOOP = 0x80, 1429 ULP_TX_SC_IMM = 0x81, 1430 ULP_TX_SC_DSGL = 0x82, 1431 ULP_TX_SC_ISGL = 0x83 1432 }; 1433 1434 #define ULPTX_CMD_S 24 1435 #define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S) 1436 1437 struct ulptx_sge_pair { 1438 __be32 len[2]; 1439 __be64 addr[2]; 1440 }; 1441 1442 struct ulptx_sgl { 1443 __be32 cmd_nsge; 1444 __be32 len0; 1445 __be64 addr0; 1446 struct ulptx_sge_pair sge[0]; 1447 }; 1448 1449 struct ulptx_idata { 1450 __be32 cmd_more; 1451 __be32 len; 1452 }; 1453 1454 struct ulp_txpkt { 1455 __be32 cmd_dest; 1456 __be32 len; 1457 }; 1458 1459 #define ULPTX_CMD_S 24 1460 #define ULPTX_CMD_M 0xFF 1461 #define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S) 1462 1463 #define ULPTX_NSGE_S 0 1464 #define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S) 1465 1466 #define ULPTX_MORE_S 23 1467 #define ULPTX_MORE_V(x) ((x) << ULPTX_MORE_S) 1468 #define ULPTX_MORE_F ULPTX_MORE_V(1U) 1469 1470 #define ULP_TXPKT_DEST_S 16 1471 #define ULP_TXPKT_DEST_M 0x3 1472 #define ULP_TXPKT_DEST_V(x) ((x) << ULP_TXPKT_DEST_S) 1473 1474 #define ULP_TXPKT_FID_S 4 1475 #define ULP_TXPKT_FID_M 0x7ff 1476 #define ULP_TXPKT_FID_V(x) ((x) << ULP_TXPKT_FID_S) 1477 1478 #define ULP_TXPKT_RO_S 3 1479 #define ULP_TXPKT_RO_V(x) ((x) << ULP_TXPKT_RO_S) 1480 #define ULP_TXPKT_RO_F ULP_TXPKT_RO_V(1U) 1481 1482 #define ULP_TX_SC_MORE_S 23 1483 #define ULP_TX_SC_MORE_V(x) ((x) << ULP_TX_SC_MORE_S) 1484 #define ULP_TX_SC_MORE_F ULP_TX_SC_MORE_V(1U) 1485 1486 struct ulp_mem_io { 1487 WR_HDR; 1488 __be32 cmd; 1489 __be32 len16; /* command length */ 1490 __be32 dlen; /* data length in 32-byte units */ 1491 __be32 lock_addr; 1492 }; 1493 1494 #define ULP_MEMIO_LOCK_S 31 1495 #define ULP_MEMIO_LOCK_V(x) ((x) << ULP_MEMIO_LOCK_S) 1496 #define ULP_MEMIO_LOCK_F ULP_MEMIO_LOCK_V(1U) 1497 1498 /* additional ulp_mem_io.cmd fields */ 1499 #define ULP_MEMIO_ORDER_S 23 1500 #define ULP_MEMIO_ORDER_V(x) ((x) << ULP_MEMIO_ORDER_S) 1501 #define ULP_MEMIO_ORDER_F ULP_MEMIO_ORDER_V(1U) 1502 1503 #define T5_ULP_MEMIO_IMM_S 23 1504 #define T5_ULP_MEMIO_IMM_V(x) ((x) << T5_ULP_MEMIO_IMM_S) 1505 #define T5_ULP_MEMIO_IMM_F T5_ULP_MEMIO_IMM_V(1U) 1506 1507 #define T5_ULP_MEMIO_ORDER_S 22 1508 #define T5_ULP_MEMIO_ORDER_V(x) ((x) << T5_ULP_MEMIO_ORDER_S) 1509 #define T5_ULP_MEMIO_ORDER_F T5_ULP_MEMIO_ORDER_V(1U) 1510 1511 #define T5_ULP_MEMIO_FID_S 4 1512 #define T5_ULP_MEMIO_FID_M 0x7ff 1513 #define T5_ULP_MEMIO_FID_V(x) ((x) << T5_ULP_MEMIO_FID_S) 1514 1515 /* ulp_mem_io.lock_addr fields */ 1516 #define ULP_MEMIO_ADDR_S 0 1517 #define ULP_MEMIO_ADDR_V(x) ((x) << ULP_MEMIO_ADDR_S) 1518 1519 /* ulp_mem_io.dlen fields */ 1520 #define ULP_MEMIO_DATA_LEN_S 0 1521 #define ULP_MEMIO_DATA_LEN_V(x) ((x) << ULP_MEMIO_DATA_LEN_S) 1522 1523 #define ULPTX_NSGE_S 0 1524 #define ULPTX_NSGE_M 0xFFFF 1525 #define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S) 1526 #define ULPTX_NSGE_G(x) (((x) >> ULPTX_NSGE_S) & ULPTX_NSGE_M) 1527 1528 struct ulptx_sc_memrd { 1529 __be32 cmd_to_len; 1530 __be32 addr; 1531 }; 1532 1533 #define ULP_TXPKT_DATAMODIFY_S 23 1534 #define ULP_TXPKT_DATAMODIFY_M 0x1 1535 #define ULP_TXPKT_DATAMODIFY_V(x) ((x) << ULP_TXPKT_DATAMODIFY_S) 1536 #define ULP_TXPKT_DATAMODIFY_G(x) \ 1537 (((x) >> ULP_TXPKT_DATAMODIFY_S) & ULP_TXPKT_DATAMODIFY__M) 1538 #define ULP_TXPKT_DATAMODIFY_F ULP_TXPKT_DATAMODIFY_V(1U) 1539 1540 #define ULP_TXPKT_CHANNELID_S 22 1541 #define ULP_TXPKT_CHANNELID_M 0x1 1542 #define ULP_TXPKT_CHANNELID_V(x) ((x) << ULP_TXPKT_CHANNELID_S) 1543 #define ULP_TXPKT_CHANNELID_G(x) \ 1544 (((x) >> ULP_TXPKT_CHANNELID_S) & ULP_TXPKT_CHANNELID_M) 1545 #define ULP_TXPKT_CHANNELID_F ULP_TXPKT_CHANNELID_V(1U) 1546 1547 #define SCMD_SEQ_NO_CTRL_S 29 1548 #define SCMD_SEQ_NO_CTRL_M 0x3 1549 #define SCMD_SEQ_NO_CTRL_V(x) ((x) << SCMD_SEQ_NO_CTRL_S) 1550 #define SCMD_SEQ_NO_CTRL_G(x) \ 1551 (((x) >> SCMD_SEQ_NO_CTRL_S) & SCMD_SEQ_NO_CTRL_M) 1552 1553 /* StsFieldPrsnt- Status field at the end of the TLS PDU */ 1554 #define SCMD_STATUS_PRESENT_S 28 1555 #define SCMD_STATUS_PRESENT_M 0x1 1556 #define SCMD_STATUS_PRESENT_V(x) ((x) << SCMD_STATUS_PRESENT_S) 1557 #define SCMD_STATUS_PRESENT_G(x) \ 1558 (((x) >> SCMD_STATUS_PRESENT_S) & SCMD_STATUS_PRESENT_M) 1559 #define SCMD_STATUS_PRESENT_F SCMD_STATUS_PRESENT_V(1U) 1560 1561 /* ProtoVersion - Protocol Version 0: 1.2, 1:1.1, 2:DTLS, 3:Generic, 1562 * 3-15: Reserved. 1563 */ 1564 #define SCMD_PROTO_VERSION_S 24 1565 #define SCMD_PROTO_VERSION_M 0xf 1566 #define SCMD_PROTO_VERSION_V(x) ((x) << SCMD_PROTO_VERSION_S) 1567 #define SCMD_PROTO_VERSION_G(x) \ 1568 (((x) >> SCMD_PROTO_VERSION_S) & SCMD_PROTO_VERSION_M) 1569 1570 /* EncDecCtrl - Encryption/Decryption Control. 0: Encrypt, 1: Decrypt */ 1571 #define SCMD_ENC_DEC_CTRL_S 23 1572 #define SCMD_ENC_DEC_CTRL_M 0x1 1573 #define SCMD_ENC_DEC_CTRL_V(x) ((x) << SCMD_ENC_DEC_CTRL_S) 1574 #define SCMD_ENC_DEC_CTRL_G(x) \ 1575 (((x) >> SCMD_ENC_DEC_CTRL_S) & SCMD_ENC_DEC_CTRL_M) 1576 #define SCMD_ENC_DEC_CTRL_F SCMD_ENC_DEC_CTRL_V(1U) 1577 1578 /* CipherAuthSeqCtrl - Cipher Authentication Sequence Control. */ 1579 #define SCMD_CIPH_AUTH_SEQ_CTRL_S 22 1580 #define SCMD_CIPH_AUTH_SEQ_CTRL_M 0x1 1581 #define SCMD_CIPH_AUTH_SEQ_CTRL_V(x) \ 1582 ((x) << SCMD_CIPH_AUTH_SEQ_CTRL_S) 1583 #define SCMD_CIPH_AUTH_SEQ_CTRL_G(x) \ 1584 (((x) >> SCMD_CIPH_AUTH_SEQ_CTRL_S) & SCMD_CIPH_AUTH_SEQ_CTRL_M) 1585 #define SCMD_CIPH_AUTH_SEQ_CTRL_F SCMD_CIPH_AUTH_SEQ_CTRL_V(1U) 1586 1587 /* CiphMode - Cipher Mode. 0: NOP, 1:AES-CBC, 2:AES-GCM, 3:AES-CTR, 1588 * 4:Generic-AES, 5-15: Reserved. 1589 */ 1590 #define SCMD_CIPH_MODE_S 18 1591 #define SCMD_CIPH_MODE_M 0xf 1592 #define SCMD_CIPH_MODE_V(x) ((x) << SCMD_CIPH_MODE_S) 1593 #define SCMD_CIPH_MODE_G(x) \ 1594 (((x) >> SCMD_CIPH_MODE_S) & SCMD_CIPH_MODE_M) 1595 1596 /* AuthMode - Auth Mode. 0: NOP, 1:SHA1, 2:SHA2-224, 3:SHA2-256 1597 * 4-15: Reserved 1598 */ 1599 #define SCMD_AUTH_MODE_S 14 1600 #define SCMD_AUTH_MODE_M 0xf 1601 #define SCMD_AUTH_MODE_V(x) ((x) << SCMD_AUTH_MODE_S) 1602 #define SCMD_AUTH_MODE_G(x) \ 1603 (((x) >> SCMD_AUTH_MODE_S) & SCMD_AUTH_MODE_M) 1604 1605 /* HmacCtrl - HMAC Control. 0:NOP, 1:No truncation, 2:Support HMAC Truncation 1606 * per RFC 4366, 3:IPSec 96 bits, 4-7:Reserved 1607 */ 1608 #define SCMD_HMAC_CTRL_S 11 1609 #define SCMD_HMAC_CTRL_M 0x7 1610 #define SCMD_HMAC_CTRL_V(x) ((x) << SCMD_HMAC_CTRL_S) 1611 #define SCMD_HMAC_CTRL_G(x) \ 1612 (((x) >> SCMD_HMAC_CTRL_S) & SCMD_HMAC_CTRL_M) 1613 1614 /* IvSize - IV size in units of 2 bytes */ 1615 #define SCMD_IV_SIZE_S 7 1616 #define SCMD_IV_SIZE_M 0xf 1617 #define SCMD_IV_SIZE_V(x) ((x) << SCMD_IV_SIZE_S) 1618 #define SCMD_IV_SIZE_G(x) \ 1619 (((x) >> SCMD_IV_SIZE_S) & SCMD_IV_SIZE_M) 1620 1621 /* NumIVs - Number of IVs */ 1622 #define SCMD_NUM_IVS_S 0 1623 #define SCMD_NUM_IVS_M 0x7f 1624 #define SCMD_NUM_IVS_V(x) ((x) << SCMD_NUM_IVS_S) 1625 #define SCMD_NUM_IVS_G(x) \ 1626 (((x) >> SCMD_NUM_IVS_S) & SCMD_NUM_IVS_M) 1627 1628 /* EnbDbgId - If this is enabled upper 20 (63:44) bits if SeqNumber 1629 * (below) are used as Cid (connection id for debug status), these 1630 * bits are padded to zero for forming the 64 bit 1631 * sequence number for TLS 1632 */ 1633 #define SCMD_ENB_DBGID_S 31 1634 #define SCMD_ENB_DBGID_M 0x1 1635 #define SCMD_ENB_DBGID_V(x) ((x) << SCMD_ENB_DBGID_S) 1636 #define SCMD_ENB_DBGID_G(x) \ 1637 (((x) >> SCMD_ENB_DBGID_S) & SCMD_ENB_DBGID_M) 1638 1639 /* IV generation in SW. */ 1640 #define SCMD_IV_GEN_CTRL_S 30 1641 #define SCMD_IV_GEN_CTRL_M 0x1 1642 #define SCMD_IV_GEN_CTRL_V(x) ((x) << SCMD_IV_GEN_CTRL_S) 1643 #define SCMD_IV_GEN_CTRL_G(x) \ 1644 (((x) >> SCMD_IV_GEN_CTRL_S) & SCMD_IV_GEN_CTRL_M) 1645 #define SCMD_IV_GEN_CTRL_F SCMD_IV_GEN_CTRL_V(1U) 1646 1647 /* More frags */ 1648 #define SCMD_MORE_FRAGS_S 20 1649 #define SCMD_MORE_FRAGS_M 0x1 1650 #define SCMD_MORE_FRAGS_V(x) ((x) << SCMD_MORE_FRAGS_S) 1651 #define SCMD_MORE_FRAGS_G(x) (((x) >> SCMD_MORE_FRAGS_S) & SCMD_MORE_FRAGS_M) 1652 1653 /*last frag */ 1654 #define SCMD_LAST_FRAG_S 19 1655 #define SCMD_LAST_FRAG_M 0x1 1656 #define SCMD_LAST_FRAG_V(x) ((x) << SCMD_LAST_FRAG_S) 1657 #define SCMD_LAST_FRAG_G(x) (((x) >> SCMD_LAST_FRAG_S) & SCMD_LAST_FRAG_M) 1658 1659 /* TlsCompPdu */ 1660 #define SCMD_TLS_COMPPDU_S 18 1661 #define SCMD_TLS_COMPPDU_M 0x1 1662 #define SCMD_TLS_COMPPDU_V(x) ((x) << SCMD_TLS_COMPPDU_S) 1663 #define SCMD_TLS_COMPPDU_G(x) (((x) >> SCMD_TLS_COMPPDU_S) & SCMD_TLS_COMPPDU_M) 1664 1665 /* KeyCntxtInline - Key context inline after the scmd OR PayloadOnly*/ 1666 #define SCMD_KEY_CTX_INLINE_S 17 1667 #define SCMD_KEY_CTX_INLINE_M 0x1 1668 #define SCMD_KEY_CTX_INLINE_V(x) ((x) << SCMD_KEY_CTX_INLINE_S) 1669 #define SCMD_KEY_CTX_INLINE_G(x) \ 1670 (((x) >> SCMD_KEY_CTX_INLINE_S) & SCMD_KEY_CTX_INLINE_M) 1671 #define SCMD_KEY_CTX_INLINE_F SCMD_KEY_CTX_INLINE_V(1U) 1672 1673 /* TLSFragEnable - 0: Host created TLS PDUs, 1: TLS Framgmentation in ASIC */ 1674 #define SCMD_TLS_FRAG_ENABLE_S 16 1675 #define SCMD_TLS_FRAG_ENABLE_M 0x1 1676 #define SCMD_TLS_FRAG_ENABLE_V(x) ((x) << SCMD_TLS_FRAG_ENABLE_S) 1677 #define SCMD_TLS_FRAG_ENABLE_G(x) \ 1678 (((x) >> SCMD_TLS_FRAG_ENABLE_S) & SCMD_TLS_FRAG_ENABLE_M) 1679 #define SCMD_TLS_FRAG_ENABLE_F SCMD_TLS_FRAG_ENABLE_V(1U) 1680 1681 /* MacOnly - Only send the MAC and discard PDU. This is valid for hash only 1682 * modes, in this case TLS_TX will drop the PDU and only 1683 * send back the MAC bytes. 1684 */ 1685 #define SCMD_MAC_ONLY_S 15 1686 #define SCMD_MAC_ONLY_M 0x1 1687 #define SCMD_MAC_ONLY_V(x) ((x) << SCMD_MAC_ONLY_S) 1688 #define SCMD_MAC_ONLY_G(x) \ 1689 (((x) >> SCMD_MAC_ONLY_S) & SCMD_MAC_ONLY_M) 1690 #define SCMD_MAC_ONLY_F SCMD_MAC_ONLY_V(1U) 1691 1692 /* AadIVDrop - Drop the AAD and IV fields. Useful in protocols 1693 * which have complex AAD and IV formations Eg:AES-CCM 1694 */ 1695 #define SCMD_AADIVDROP_S 14 1696 #define SCMD_AADIVDROP_M 0x1 1697 #define SCMD_AADIVDROP_V(x) ((x) << SCMD_AADIVDROP_S) 1698 #define SCMD_AADIVDROP_G(x) \ 1699 (((x) >> SCMD_AADIVDROP_S) & SCMD_AADIVDROP_M) 1700 #define SCMD_AADIVDROP_F SCMD_AADIVDROP_V(1U) 1701 1702 /* HdrLength - Length of all headers excluding TLS header 1703 * present before start of crypto PDU/payload. 1704 */ 1705 #define SCMD_HDR_LEN_S 0 1706 #define SCMD_HDR_LEN_M 0x3fff 1707 #define SCMD_HDR_LEN_V(x) ((x) << SCMD_HDR_LEN_S) 1708 #define SCMD_HDR_LEN_G(x) \ 1709 (((x) >> SCMD_HDR_LEN_S) & SCMD_HDR_LEN_M) 1710 1711 struct cpl_tx_sec_pdu { 1712 __be32 op_ivinsrtofst; 1713 __be32 pldlen; 1714 __be32 aadstart_cipherstop_hi; 1715 __be32 cipherstop_lo_authinsert; 1716 __be32 seqno_numivs; 1717 __be32 ivgen_hdrlen; 1718 __be64 scmd1; 1719 }; 1720 1721 #define CPL_TX_SEC_PDU_OPCODE_S 24 1722 #define CPL_TX_SEC_PDU_OPCODE_M 0xff 1723 #define CPL_TX_SEC_PDU_OPCODE_V(x) ((x) << CPL_TX_SEC_PDU_OPCODE_S) 1724 #define CPL_TX_SEC_PDU_OPCODE_G(x) \ 1725 (((x) >> CPL_TX_SEC_PDU_OPCODE_S) & CPL_TX_SEC_PDU_OPCODE_M) 1726 1727 /* RX Channel Id */ 1728 #define CPL_TX_SEC_PDU_RXCHID_S 22 1729 #define CPL_TX_SEC_PDU_RXCHID_M 0x1 1730 #define CPL_TX_SEC_PDU_RXCHID_V(x) ((x) << CPL_TX_SEC_PDU_RXCHID_S) 1731 #define CPL_TX_SEC_PDU_RXCHID_G(x) \ 1732 (((x) >> CPL_TX_SEC_PDU_RXCHID_S) & CPL_TX_SEC_PDU_RXCHID_M) 1733 #define CPL_TX_SEC_PDU_RXCHID_F CPL_TX_SEC_PDU_RXCHID_V(1U) 1734 1735 /* Ack Follows */ 1736 #define CPL_TX_SEC_PDU_ACKFOLLOWS_S 21 1737 #define CPL_TX_SEC_PDU_ACKFOLLOWS_M 0x1 1738 #define CPL_TX_SEC_PDU_ACKFOLLOWS_V(x) ((x) << CPL_TX_SEC_PDU_ACKFOLLOWS_S) 1739 #define CPL_TX_SEC_PDU_ACKFOLLOWS_G(x) \ 1740 (((x) >> CPL_TX_SEC_PDU_ACKFOLLOWS_S) & CPL_TX_SEC_PDU_ACKFOLLOWS_M) 1741 #define CPL_TX_SEC_PDU_ACKFOLLOWS_F CPL_TX_SEC_PDU_ACKFOLLOWS_V(1U) 1742 1743 /* Loopback bit in cpl_tx_sec_pdu */ 1744 #define CPL_TX_SEC_PDU_ULPTXLPBK_S 20 1745 #define CPL_TX_SEC_PDU_ULPTXLPBK_M 0x1 1746 #define CPL_TX_SEC_PDU_ULPTXLPBK_V(x) ((x) << CPL_TX_SEC_PDU_ULPTXLPBK_S) 1747 #define CPL_TX_SEC_PDU_ULPTXLPBK_G(x) \ 1748 (((x) >> CPL_TX_SEC_PDU_ULPTXLPBK_S) & CPL_TX_SEC_PDU_ULPTXLPBK_M) 1749 #define CPL_TX_SEC_PDU_ULPTXLPBK_F CPL_TX_SEC_PDU_ULPTXLPBK_V(1U) 1750 1751 /* Length of cpl header encapsulated */ 1752 #define CPL_TX_SEC_PDU_CPLLEN_S 16 1753 #define CPL_TX_SEC_PDU_CPLLEN_M 0xf 1754 #define CPL_TX_SEC_PDU_CPLLEN_V(x) ((x) << CPL_TX_SEC_PDU_CPLLEN_S) 1755 #define CPL_TX_SEC_PDU_CPLLEN_G(x) \ 1756 (((x) >> CPL_TX_SEC_PDU_CPLLEN_S) & CPL_TX_SEC_PDU_CPLLEN_M) 1757 1758 /* PlaceHolder */ 1759 #define CPL_TX_SEC_PDU_PLACEHOLDER_S 10 1760 #define CPL_TX_SEC_PDU_PLACEHOLDER_M 0x1 1761 #define CPL_TX_SEC_PDU_PLACEHOLDER_V(x) ((x) << CPL_TX_SEC_PDU_PLACEHOLDER_S) 1762 #define CPL_TX_SEC_PDU_PLACEHOLDER_G(x) \ 1763 (((x) >> CPL_TX_SEC_PDU_PLACEHOLDER_S) & \ 1764 CPL_TX_SEC_PDU_PLACEHOLDER_M) 1765 1766 /* IvInsrtOffset: Insertion location for IV */ 1767 #define CPL_TX_SEC_PDU_IVINSRTOFST_S 0 1768 #define CPL_TX_SEC_PDU_IVINSRTOFST_M 0x3ff 1769 #define CPL_TX_SEC_PDU_IVINSRTOFST_V(x) ((x) << CPL_TX_SEC_PDU_IVINSRTOFST_S) 1770 #define CPL_TX_SEC_PDU_IVINSRTOFST_G(x) \ 1771 (((x) >> CPL_TX_SEC_PDU_IVINSRTOFST_S) & \ 1772 CPL_TX_SEC_PDU_IVINSRTOFST_M) 1773 1774 /* AadStartOffset: Offset in bytes for AAD start from 1775 * the first byte following the pkt headers (0-255 bytes) 1776 */ 1777 #define CPL_TX_SEC_PDU_AADSTART_S 24 1778 #define CPL_TX_SEC_PDU_AADSTART_M 0xff 1779 #define CPL_TX_SEC_PDU_AADSTART_V(x) ((x) << CPL_TX_SEC_PDU_AADSTART_S) 1780 #define CPL_TX_SEC_PDU_AADSTART_G(x) \ 1781 (((x) >> CPL_TX_SEC_PDU_AADSTART_S) & \ 1782 CPL_TX_SEC_PDU_AADSTART_M) 1783 1784 /* AadStopOffset: offset in bytes for AAD stop/end from the first byte following 1785 * the pkt headers (0-511 bytes) 1786 */ 1787 #define CPL_TX_SEC_PDU_AADSTOP_S 15 1788 #define CPL_TX_SEC_PDU_AADSTOP_M 0x1ff 1789 #define CPL_TX_SEC_PDU_AADSTOP_V(x) ((x) << CPL_TX_SEC_PDU_AADSTOP_S) 1790 #define CPL_TX_SEC_PDU_AADSTOP_G(x) \ 1791 (((x) >> CPL_TX_SEC_PDU_AADSTOP_S) & CPL_TX_SEC_PDU_AADSTOP_M) 1792 1793 /* CipherStartOffset: offset in bytes for encryption/decryption start from the 1794 * first byte following the pkt headers (0-1023 bytes) 1795 */ 1796 #define CPL_TX_SEC_PDU_CIPHERSTART_S 5 1797 #define CPL_TX_SEC_PDU_CIPHERSTART_M 0x3ff 1798 #define CPL_TX_SEC_PDU_CIPHERSTART_V(x) ((x) << CPL_TX_SEC_PDU_CIPHERSTART_S) 1799 #define CPL_TX_SEC_PDU_CIPHERSTART_G(x) \ 1800 (((x) >> CPL_TX_SEC_PDU_CIPHERSTART_S) & \ 1801 CPL_TX_SEC_PDU_CIPHERSTART_M) 1802 1803 /* CipherStopOffset: offset in bytes for encryption/decryption end 1804 * from end of the payload of this command (0-511 bytes) 1805 */ 1806 #define CPL_TX_SEC_PDU_CIPHERSTOP_HI_S 0 1807 #define CPL_TX_SEC_PDU_CIPHERSTOP_HI_M 0x1f 1808 #define CPL_TX_SEC_PDU_CIPHERSTOP_HI_V(x) \ 1809 ((x) << CPL_TX_SEC_PDU_CIPHERSTOP_HI_S) 1810 #define CPL_TX_SEC_PDU_CIPHERSTOP_HI_G(x) \ 1811 (((x) >> CPL_TX_SEC_PDU_CIPHERSTOP_HI_S) & \ 1812 CPL_TX_SEC_PDU_CIPHERSTOP_HI_M) 1813 1814 #define CPL_TX_SEC_PDU_CIPHERSTOP_LO_S 28 1815 #define CPL_TX_SEC_PDU_CIPHERSTOP_LO_M 0xf 1816 #define CPL_TX_SEC_PDU_CIPHERSTOP_LO_V(x) \ 1817 ((x) << CPL_TX_SEC_PDU_CIPHERSTOP_LO_S) 1818 #define CPL_TX_SEC_PDU_CIPHERSTOP_LO_G(x) \ 1819 (((x) >> CPL_TX_SEC_PDU_CIPHERSTOP_LO_S) & \ 1820 CPL_TX_SEC_PDU_CIPHERSTOP_LO_M) 1821 1822 /* AuthStartOffset: offset in bytes for authentication start from 1823 * the first byte following the pkt headers (0-1023) 1824 */ 1825 #define CPL_TX_SEC_PDU_AUTHSTART_S 18 1826 #define CPL_TX_SEC_PDU_AUTHSTART_M 0x3ff 1827 #define CPL_TX_SEC_PDU_AUTHSTART_V(x) ((x) << CPL_TX_SEC_PDU_AUTHSTART_S) 1828 #define CPL_TX_SEC_PDU_AUTHSTART_G(x) \ 1829 (((x) >> CPL_TX_SEC_PDU_AUTHSTART_S) & \ 1830 CPL_TX_SEC_PDU_AUTHSTART_M) 1831 1832 /* AuthStopOffset: offset in bytes for authentication 1833 * end from end of the payload of this command (0-511 Bytes) 1834 */ 1835 #define CPL_TX_SEC_PDU_AUTHSTOP_S 9 1836 #define CPL_TX_SEC_PDU_AUTHSTOP_M 0x1ff 1837 #define CPL_TX_SEC_PDU_AUTHSTOP_V(x) ((x) << CPL_TX_SEC_PDU_AUTHSTOP_S) 1838 #define CPL_TX_SEC_PDU_AUTHSTOP_G(x) \ 1839 (((x) >> CPL_TX_SEC_PDU_AUTHSTOP_S) & \ 1840 CPL_TX_SEC_PDU_AUTHSTOP_M) 1841 1842 /* AuthInsrtOffset: offset in bytes for authentication insertion 1843 * from end of the payload of this command (0-511 bytes) 1844 */ 1845 #define CPL_TX_SEC_PDU_AUTHINSERT_S 0 1846 #define CPL_TX_SEC_PDU_AUTHINSERT_M 0x1ff 1847 #define CPL_TX_SEC_PDU_AUTHINSERT_V(x) ((x) << CPL_TX_SEC_PDU_AUTHINSERT_S) 1848 #define CPL_TX_SEC_PDU_AUTHINSERT_G(x) \ 1849 (((x) >> CPL_TX_SEC_PDU_AUTHINSERT_S) & \ 1850 CPL_TX_SEC_PDU_AUTHINSERT_M) 1851 1852 struct cpl_rx_phys_dsgl { 1853 __be32 op_to_tid; 1854 __be32 pcirlxorder_to_noofsgentr; 1855 struct rss_header rss_hdr_int; 1856 }; 1857 1858 #define CPL_RX_PHYS_DSGL_OPCODE_S 24 1859 #define CPL_RX_PHYS_DSGL_OPCODE_M 0xff 1860 #define CPL_RX_PHYS_DSGL_OPCODE_V(x) ((x) << CPL_RX_PHYS_DSGL_OPCODE_S) 1861 #define CPL_RX_PHYS_DSGL_OPCODE_G(x) \ 1862 (((x) >> CPL_RX_PHYS_DSGL_OPCODE_S) & CPL_RX_PHYS_DSGL_OPCODE_M) 1863 1864 #define CPL_RX_PHYS_DSGL_ISRDMA_S 23 1865 #define CPL_RX_PHYS_DSGL_ISRDMA_M 0x1 1866 #define CPL_RX_PHYS_DSGL_ISRDMA_V(x) ((x) << CPL_RX_PHYS_DSGL_ISRDMA_S) 1867 #define CPL_RX_PHYS_DSGL_ISRDMA_G(x) \ 1868 (((x) >> CPL_RX_PHYS_DSGL_ISRDMA_S) & CPL_RX_PHYS_DSGL_ISRDMA_M) 1869 #define CPL_RX_PHYS_DSGL_ISRDMA_F CPL_RX_PHYS_DSGL_ISRDMA_V(1U) 1870 1871 #define CPL_RX_PHYS_DSGL_RSVD1_S 20 1872 #define CPL_RX_PHYS_DSGL_RSVD1_M 0x7 1873 #define CPL_RX_PHYS_DSGL_RSVD1_V(x) ((x) << CPL_RX_PHYS_DSGL_RSVD1_S) 1874 #define CPL_RX_PHYS_DSGL_RSVD1_G(x) \ 1875 (((x) >> CPL_RX_PHYS_DSGL_RSVD1_S) & \ 1876 CPL_RX_PHYS_DSGL_RSVD1_M) 1877 1878 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_S 31 1879 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_M 0x1 1880 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_V(x) \ 1881 ((x) << CPL_RX_PHYS_DSGL_PCIRLXORDER_S) 1882 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_G(x) \ 1883 (((x) >> CPL_RX_PHYS_DSGL_PCIRLXORDER_S) & \ 1884 CPL_RX_PHYS_DSGL_PCIRLXORDER_M) 1885 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_F CPL_RX_PHYS_DSGL_PCIRLXORDER_V(1U) 1886 1887 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_S 30 1888 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_M 0x1 1889 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_V(x) \ 1890 ((x) << CPL_RX_PHYS_DSGL_PCINOSNOOP_S) 1891 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_G(x) \ 1892 (((x) >> CPL_RX_PHYS_DSGL_PCINOSNOOP_S) & \ 1893 CPL_RX_PHYS_DSGL_PCINOSNOOP_M) 1894 1895 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_F CPL_RX_PHYS_DSGL_PCINOSNOOP_V(1U) 1896 1897 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_S 29 1898 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_M 0x1 1899 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_V(x) \ 1900 ((x) << CPL_RX_PHYS_DSGL_PCITPHNTENB_S) 1901 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_G(x) \ 1902 (((x) >> CPL_RX_PHYS_DSGL_PCITPHNTENB_S) & \ 1903 CPL_RX_PHYS_DSGL_PCITPHNTENB_M) 1904 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_F CPL_RX_PHYS_DSGL_PCITPHNTENB_V(1U) 1905 1906 #define CPL_RX_PHYS_DSGL_PCITPHNT_S 27 1907 #define CPL_RX_PHYS_DSGL_PCITPHNT_M 0x3 1908 #define CPL_RX_PHYS_DSGL_PCITPHNT_V(x) ((x) << CPL_RX_PHYS_DSGL_PCITPHNT_S) 1909 #define CPL_RX_PHYS_DSGL_PCITPHNT_G(x) \ 1910 (((x) >> CPL_RX_PHYS_DSGL_PCITPHNT_S) & \ 1911 CPL_RX_PHYS_DSGL_PCITPHNT_M) 1912 1913 #define CPL_RX_PHYS_DSGL_DCAID_S 16 1914 #define CPL_RX_PHYS_DSGL_DCAID_M 0x7ff 1915 #define CPL_RX_PHYS_DSGL_DCAID_V(x) ((x) << CPL_RX_PHYS_DSGL_DCAID_S) 1916 #define CPL_RX_PHYS_DSGL_DCAID_G(x) \ 1917 (((x) >> CPL_RX_PHYS_DSGL_DCAID_S) & \ 1918 CPL_RX_PHYS_DSGL_DCAID_M) 1919 1920 #define CPL_RX_PHYS_DSGL_NOOFSGENTR_S 0 1921 #define CPL_RX_PHYS_DSGL_NOOFSGENTR_M 0xffff 1922 #define CPL_RX_PHYS_DSGL_NOOFSGENTR_V(x) \ 1923 ((x) << CPL_RX_PHYS_DSGL_NOOFSGENTR_S) 1924 #define CPL_RX_PHYS_DSGL_NOOFSGENTR_G(x) \ 1925 (((x) >> CPL_RX_PHYS_DSGL_NOOFSGENTR_S) & \ 1926 CPL_RX_PHYS_DSGL_NOOFSGENTR_M) 1927 1928 struct cpl_rx_mps_pkt { 1929 __be32 op_to_r1_hi; 1930 __be32 r1_lo_length; 1931 }; 1932 1933 #define CPL_RX_MPS_PKT_OP_S 24 1934 #define CPL_RX_MPS_PKT_OP_M 0xff 1935 #define CPL_RX_MPS_PKT_OP_V(x) ((x) << CPL_RX_MPS_PKT_OP_S) 1936 #define CPL_RX_MPS_PKT_OP_G(x) \ 1937 (((x) >> CPL_RX_MPS_PKT_OP_S) & CPL_RX_MPS_PKT_OP_M) 1938 1939 #define CPL_RX_MPS_PKT_TYPE_S 20 1940 #define CPL_RX_MPS_PKT_TYPE_M 0xf 1941 #define CPL_RX_MPS_PKT_TYPE_V(x) ((x) << CPL_RX_MPS_PKT_TYPE_S) 1942 #define CPL_RX_MPS_PKT_TYPE_G(x) \ 1943 (((x) >> CPL_RX_MPS_PKT_TYPE_S) & CPL_RX_MPS_PKT_TYPE_M) 1944 1945 enum { 1946 X_CPL_RX_MPS_PKT_TYPE_PAUSE = 1 << 0, 1947 X_CPL_RX_MPS_PKT_TYPE_PPP = 1 << 1, 1948 X_CPL_RX_MPS_PKT_TYPE_QFC = 1 << 2, 1949 X_CPL_RX_MPS_PKT_TYPE_PTP = 1 << 3 1950 }; 1951 #endif /* __T4_MSG_H */ 1952