1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __T4_MSG_H 36 #define __T4_MSG_H 37 38 #include <linux/types.h> 39 40 enum { 41 CPL_PASS_OPEN_REQ = 0x1, 42 CPL_PASS_ACCEPT_RPL = 0x2, 43 CPL_ACT_OPEN_REQ = 0x3, 44 CPL_SET_TCB_FIELD = 0x5, 45 CPL_GET_TCB = 0x6, 46 CPL_CLOSE_CON_REQ = 0x8, 47 CPL_CLOSE_LISTSRV_REQ = 0x9, 48 CPL_ABORT_REQ = 0xA, 49 CPL_ABORT_RPL = 0xB, 50 CPL_RX_DATA_ACK = 0xD, 51 CPL_TX_PKT = 0xE, 52 CPL_L2T_WRITE_REQ = 0x12, 53 CPL_TID_RELEASE = 0x1A, 54 55 CPL_CLOSE_LISTSRV_RPL = 0x20, 56 CPL_L2T_WRITE_RPL = 0x23, 57 CPL_PASS_OPEN_RPL = 0x24, 58 CPL_ACT_OPEN_RPL = 0x25, 59 CPL_PEER_CLOSE = 0x26, 60 CPL_ABORT_REQ_RSS = 0x2B, 61 CPL_ABORT_RPL_RSS = 0x2D, 62 63 CPL_CLOSE_CON_RPL = 0x32, 64 CPL_ISCSI_HDR = 0x33, 65 CPL_RDMA_CQE = 0x35, 66 CPL_RDMA_CQE_READ_RSP = 0x36, 67 CPL_RDMA_CQE_ERR = 0x37, 68 CPL_RX_DATA = 0x39, 69 CPL_SET_TCB_RPL = 0x3A, 70 CPL_RX_PKT = 0x3B, 71 CPL_RX_DDP_COMPLETE = 0x3F, 72 73 CPL_ACT_ESTABLISH = 0x40, 74 CPL_PASS_ESTABLISH = 0x41, 75 CPL_RX_DATA_DDP = 0x42, 76 CPL_PASS_ACCEPT_REQ = 0x44, 77 CPL_TRACE_PKT_T5 = 0x48, 78 CPL_RX_ISCSI_DDP = 0x49, 79 80 CPL_RDMA_READ_REQ = 0x60, 81 82 CPL_PASS_OPEN_REQ6 = 0x81, 83 CPL_ACT_OPEN_REQ6 = 0x83, 84 85 CPL_RDMA_TERMINATE = 0xA2, 86 CPL_RDMA_WRITE = 0xA4, 87 CPL_SGE_EGR_UPDATE = 0xA5, 88 89 CPL_TRACE_PKT = 0xB0, 90 CPL_ISCSI_DATA = 0xB2, 91 92 CPL_FW4_MSG = 0xC0, 93 CPL_FW4_PLD = 0xC1, 94 CPL_FW4_ACK = 0xC3, 95 96 CPL_FW6_MSG = 0xE0, 97 CPL_FW6_PLD = 0xE1, 98 CPL_TX_PKT_LSO = 0xED, 99 CPL_TX_PKT_XT = 0xEE, 100 101 NUM_CPL_CMDS 102 }; 103 104 enum CPL_error { 105 CPL_ERR_NONE = 0, 106 CPL_ERR_TCAM_FULL = 3, 107 CPL_ERR_BAD_LENGTH = 15, 108 CPL_ERR_BAD_ROUTE = 18, 109 CPL_ERR_CONN_RESET = 20, 110 CPL_ERR_CONN_EXIST_SYNRECV = 21, 111 CPL_ERR_CONN_EXIST = 22, 112 CPL_ERR_ARP_MISS = 23, 113 CPL_ERR_BAD_SYN = 24, 114 CPL_ERR_CONN_TIMEDOUT = 30, 115 CPL_ERR_XMIT_TIMEDOUT = 31, 116 CPL_ERR_PERSIST_TIMEDOUT = 32, 117 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 118 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 119 CPL_ERR_RTX_NEG_ADVICE = 35, 120 CPL_ERR_PERSIST_NEG_ADVICE = 36, 121 CPL_ERR_KEEPALV_NEG_ADVICE = 37, 122 CPL_ERR_ABORT_FAILED = 42, 123 CPL_ERR_IWARP_FLM = 50, 124 }; 125 126 enum { 127 ULP_MODE_NONE = 0, 128 ULP_MODE_ISCSI = 2, 129 ULP_MODE_RDMA = 4, 130 ULP_MODE_TCPDDP = 5, 131 ULP_MODE_FCOE = 6, 132 }; 133 134 enum { 135 ULP_CRC_HEADER = 1 << 0, 136 ULP_CRC_DATA = 1 << 1 137 }; 138 139 enum { 140 CPL_ABORT_SEND_RST = 0, 141 CPL_ABORT_NO_RST, 142 }; 143 144 enum { /* TX_PKT_XT checksum types */ 145 TX_CSUM_TCP = 0, 146 TX_CSUM_UDP = 1, 147 TX_CSUM_CRC16 = 4, 148 TX_CSUM_CRC32 = 5, 149 TX_CSUM_CRC32C = 6, 150 TX_CSUM_FCOE = 7, 151 TX_CSUM_TCPIP = 8, 152 TX_CSUM_UDPIP = 9, 153 TX_CSUM_TCPIP6 = 10, 154 TX_CSUM_UDPIP6 = 11, 155 TX_CSUM_IP = 12, 156 }; 157 158 union opcode_tid { 159 __be32 opcode_tid; 160 u8 opcode; 161 }; 162 163 #define CPL_OPCODE(x) ((x) << 24) 164 #define G_CPL_OPCODE(x) (((x) >> 24) & 0xFF) 165 #define MK_OPCODE_TID(opcode, tid) (CPL_OPCODE(opcode) | (tid)) 166 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 167 #define GET_TID(cmd) (ntohl(OPCODE_TID(cmd)) & 0xFFFFFF) 168 169 /* partitioning of TID fields that also carry a queue id */ 170 #define GET_TID_TID(x) ((x) & 0x3fff) 171 #define GET_TID_QID(x) (((x) >> 14) & 0x3ff) 172 #define TID_QID(x) ((x) << 14) 173 174 struct rss_header { 175 u8 opcode; 176 #if defined(__LITTLE_ENDIAN_BITFIELD) 177 u8 channel:2; 178 u8 filter_hit:1; 179 u8 filter_tid:1; 180 u8 hash_type:2; 181 u8 ipv6:1; 182 u8 send2fw:1; 183 #else 184 u8 send2fw:1; 185 u8 ipv6:1; 186 u8 hash_type:2; 187 u8 filter_tid:1; 188 u8 filter_hit:1; 189 u8 channel:2; 190 #endif 191 __be16 qid; 192 __be32 hash_val; 193 }; 194 195 struct work_request_hdr { 196 __be32 wr_hi; 197 __be32 wr_mid; 198 __be64 wr_lo; 199 }; 200 201 /* wr_hi fields */ 202 #define S_WR_OP 24 203 #define V_WR_OP(x) ((__u64)(x) << S_WR_OP) 204 205 #define WR_HDR struct work_request_hdr wr 206 207 /* option 0 fields */ 208 #define S_MSS_IDX 60 209 #define M_MSS_IDX 0xF 210 #define V_MSS_IDX(x) ((__u64)(x) << S_MSS_IDX) 211 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX) 212 213 /* option 2 fields */ 214 #define S_RSS_QUEUE 0 215 #define M_RSS_QUEUE 0x3FF 216 #define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE) 217 #define G_RSS_QUEUE(x) (((x) >> S_RSS_QUEUE) & M_RSS_QUEUE) 218 219 struct cpl_pass_open_req { 220 WR_HDR; 221 union opcode_tid ot; 222 __be16 local_port; 223 __be16 peer_port; 224 __be32 local_ip; 225 __be32 peer_ip; 226 __be64 opt0; 227 #define TX_CHAN(x) ((x) << 2) 228 #define NO_CONG(x) ((x) << 4) 229 #define DELACK(x) ((x) << 5) 230 #define ULP_MODE(x) ((x) << 8) 231 #define RCV_BUFSIZ(x) ((x) << 12) 232 #define RCV_BUFSIZ_MASK 0x3FFU 233 #define DSCP(x) ((x) << 22) 234 #define SMAC_SEL(x) ((u64)(x) << 28) 235 #define L2T_IDX(x) ((u64)(x) << 36) 236 #define TCAM_BYPASS(x) ((u64)(x) << 48) 237 #define NAGLE(x) ((u64)(x) << 49) 238 #define WND_SCALE(x) ((u64)(x) << 50) 239 #define KEEP_ALIVE(x) ((u64)(x) << 54) 240 #define MSS_IDX(x) ((u64)(x) << 60) 241 __be64 opt1; 242 #define SYN_RSS_ENABLE (1 << 0) 243 #define SYN_RSS_QUEUE(x) ((x) << 2) 244 #define CONN_POLICY_ASK (1 << 22) 245 }; 246 247 struct cpl_pass_open_req6 { 248 WR_HDR; 249 union opcode_tid ot; 250 __be16 local_port; 251 __be16 peer_port; 252 __be64 local_ip_hi; 253 __be64 local_ip_lo; 254 __be64 peer_ip_hi; 255 __be64 peer_ip_lo; 256 __be64 opt0; 257 __be64 opt1; 258 }; 259 260 struct cpl_pass_open_rpl { 261 union opcode_tid ot; 262 u8 rsvd[3]; 263 u8 status; 264 }; 265 266 struct cpl_pass_accept_rpl { 267 WR_HDR; 268 union opcode_tid ot; 269 __be32 opt2; 270 #define RSS_QUEUE(x) ((x) << 0) 271 #define RSS_QUEUE_VALID (1 << 10) 272 #define RX_COALESCE_VALID(x) ((x) << 11) 273 #define RX_COALESCE(x) ((x) << 12) 274 #define PACE(x) ((x) << 16) 275 #define RX_FC_VALID ((1U) << 19) 276 #define RX_FC_DISABLE ((1U) << 20) 277 #define TX_QUEUE(x) ((x) << 23) 278 #define RX_CHANNEL(x) ((x) << 26) 279 #define CCTRL_ECN(x) ((x) << 27) 280 #define WND_SCALE_EN(x) ((x) << 28) 281 #define TSTAMPS_EN(x) ((x) << 29) 282 #define SACK_EN(x) ((x) << 30) 283 #define T5_OPT_2_VALID ((1U) << 31) 284 __be64 opt0; 285 }; 286 287 struct cpl_t5_pass_accept_rpl { 288 WR_HDR; 289 union opcode_tid ot; 290 __be32 opt2; 291 __be64 opt0; 292 __be32 iss; 293 __be32 rsvd; 294 }; 295 296 struct cpl_act_open_req { 297 WR_HDR; 298 union opcode_tid ot; 299 __be16 local_port; 300 __be16 peer_port; 301 __be32 local_ip; 302 __be32 peer_ip; 303 __be64 opt0; 304 __be32 params; 305 __be32 opt2; 306 }; 307 308 #define S_FILTER_TUPLE 24 309 #define M_FILTER_TUPLE 0xFFFFFFFFFF 310 #define V_FILTER_TUPLE(x) ((x) << S_FILTER_TUPLE) 311 #define G_FILTER_TUPLE(x) (((x) >> S_FILTER_TUPLE) & M_FILTER_TUPLE) 312 struct cpl_t5_act_open_req { 313 WR_HDR; 314 union opcode_tid ot; 315 __be16 local_port; 316 __be16 peer_port; 317 __be32 local_ip; 318 __be32 peer_ip; 319 __be64 opt0; 320 __be32 rsvd; 321 __be32 opt2; 322 __be64 params; 323 }; 324 325 struct cpl_act_open_req6 { 326 WR_HDR; 327 union opcode_tid ot; 328 __be16 local_port; 329 __be16 peer_port; 330 __be64 local_ip_hi; 331 __be64 local_ip_lo; 332 __be64 peer_ip_hi; 333 __be64 peer_ip_lo; 334 __be64 opt0; 335 __be32 params; 336 __be32 opt2; 337 }; 338 339 struct cpl_t5_act_open_req6 { 340 WR_HDR; 341 union opcode_tid ot; 342 __be16 local_port; 343 __be16 peer_port; 344 __be64 local_ip_hi; 345 __be64 local_ip_lo; 346 __be64 peer_ip_hi; 347 __be64 peer_ip_lo; 348 __be64 opt0; 349 __be32 rsvd; 350 __be32 opt2; 351 __be64 params; 352 }; 353 354 struct cpl_act_open_rpl { 355 union opcode_tid ot; 356 __be32 atid_status; 357 #define GET_AOPEN_STATUS(x) ((x) & 0xff) 358 #define GET_AOPEN_ATID(x) (((x) >> 8) & 0xffffff) 359 }; 360 361 struct cpl_pass_establish { 362 union opcode_tid ot; 363 __be32 rsvd; 364 __be32 tos_stid; 365 #define PASS_OPEN_TID(x) ((x) << 0) 366 #define PASS_OPEN_TOS(x) ((x) << 24) 367 #define GET_PASS_OPEN_TID(x) (((x) >> 0) & 0xFFFFFF) 368 #define GET_POPEN_TID(x) ((x) & 0xffffff) 369 #define GET_POPEN_TOS(x) (((x) >> 24) & 0xff) 370 __be16 mac_idx; 371 __be16 tcp_opt; 372 #define GET_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1) 373 #define GET_TCPOPT_SACK(x) (((x) >> 6) & 1) 374 #define GET_TCPOPT_TSTAMP(x) (((x) >> 7) & 1) 375 #define GET_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf) 376 #define GET_TCPOPT_MSS(x) (((x) >> 12) & 0xf) 377 __be32 snd_isn; 378 __be32 rcv_isn; 379 }; 380 381 struct cpl_act_establish { 382 union opcode_tid ot; 383 __be32 rsvd; 384 __be32 tos_atid; 385 __be16 mac_idx; 386 __be16 tcp_opt; 387 __be32 snd_isn; 388 __be32 rcv_isn; 389 }; 390 391 struct cpl_get_tcb { 392 WR_HDR; 393 union opcode_tid ot; 394 __be16 reply_ctrl; 395 #define QUEUENO(x) ((x) << 0) 396 #define REPLY_CHAN(x) ((x) << 14) 397 #define NO_REPLY(x) ((x) << 15) 398 __be16 cookie; 399 }; 400 401 struct cpl_set_tcb_field { 402 WR_HDR; 403 union opcode_tid ot; 404 __be16 reply_ctrl; 405 __be16 word_cookie; 406 #define TCB_WORD(x) ((x) << 0) 407 #define TCB_COOKIE(x) ((x) << 5) 408 #define GET_TCB_COOKIE(x) (((x) >> 5) & 7) 409 __be64 mask; 410 __be64 val; 411 }; 412 413 struct cpl_set_tcb_rpl { 414 union opcode_tid ot; 415 __be16 rsvd; 416 u8 cookie; 417 u8 status; 418 __be64 oldval; 419 }; 420 421 struct cpl_close_con_req { 422 WR_HDR; 423 union opcode_tid ot; 424 __be32 rsvd; 425 }; 426 427 struct cpl_close_con_rpl { 428 union opcode_tid ot; 429 u8 rsvd[3]; 430 u8 status; 431 __be32 snd_nxt; 432 __be32 rcv_nxt; 433 }; 434 435 struct cpl_close_listsvr_req { 436 WR_HDR; 437 union opcode_tid ot; 438 __be16 reply_ctrl; 439 #define LISTSVR_IPV6(x) ((x) << 14) 440 __be16 rsvd; 441 }; 442 443 struct cpl_close_listsvr_rpl { 444 union opcode_tid ot; 445 u8 rsvd[3]; 446 u8 status; 447 }; 448 449 struct cpl_abort_req_rss { 450 union opcode_tid ot; 451 u8 rsvd[3]; 452 u8 status; 453 }; 454 455 struct cpl_abort_req { 456 WR_HDR; 457 union opcode_tid ot; 458 __be32 rsvd0; 459 u8 rsvd1; 460 u8 cmd; 461 u8 rsvd2[6]; 462 }; 463 464 struct cpl_abort_rpl_rss { 465 union opcode_tid ot; 466 u8 rsvd[3]; 467 u8 status; 468 }; 469 470 struct cpl_abort_rpl { 471 WR_HDR; 472 union opcode_tid ot; 473 __be32 rsvd0; 474 u8 rsvd1; 475 u8 cmd; 476 u8 rsvd2[6]; 477 }; 478 479 struct cpl_peer_close { 480 union opcode_tid ot; 481 __be32 rcv_nxt; 482 }; 483 484 struct cpl_tid_release { 485 WR_HDR; 486 union opcode_tid ot; 487 __be32 rsvd; 488 }; 489 490 struct cpl_tx_pkt_core { 491 __be32 ctrl0; 492 #define TXPKT_VF(x) ((x) << 0) 493 #define TXPKT_PF(x) ((x) << 8) 494 #define TXPKT_VF_VLD (1 << 11) 495 #define TXPKT_OVLAN_IDX(x) ((x) << 12) 496 #define TXPKT_INTF(x) ((x) << 16) 497 #define TXPKT_INS_OVLAN (1 << 21) 498 #define TXPKT_OPCODE(x) ((x) << 24) 499 __be16 pack; 500 __be16 len; 501 __be64 ctrl1; 502 #define TXPKT_CSUM_END(x) ((x) << 12) 503 #define TXPKT_CSUM_START(x) ((x) << 20) 504 #define TXPKT_IPHDR_LEN(x) ((u64)(x) << 20) 505 #define TXPKT_CSUM_LOC(x) ((u64)(x) << 30) 506 #define TXPKT_ETHHDR_LEN(x) ((u64)(x) << 34) 507 #define TXPKT_CSUM_TYPE(x) ((u64)(x) << 40) 508 #define TXPKT_VLAN(x) ((u64)(x) << 44) 509 #define TXPKT_VLAN_VLD (1ULL << 60) 510 #define TXPKT_IPCSUM_DIS (1ULL << 62) 511 #define TXPKT_L4CSUM_DIS (1ULL << 63) 512 }; 513 514 struct cpl_tx_pkt { 515 WR_HDR; 516 struct cpl_tx_pkt_core c; 517 }; 518 519 #define cpl_tx_pkt_xt cpl_tx_pkt 520 521 struct cpl_tx_pkt_lso_core { 522 __be32 lso_ctrl; 523 #define LSO_TCPHDR_LEN(x) ((x) << 0) 524 #define LSO_IPHDR_LEN(x) ((x) << 4) 525 #define LSO_ETHHDR_LEN(x) ((x) << 16) 526 #define LSO_IPV6(x) ((x) << 20) 527 #define LSO_LAST_SLICE (1 << 22) 528 #define LSO_FIRST_SLICE (1 << 23) 529 #define LSO_OPCODE(x) ((x) << 24) 530 #define LSO_T5_XFER_SIZE(x) ((x) << 0) 531 __be16 ipid_ofst; 532 __be16 mss; 533 __be32 seqno_offset; 534 __be32 len; 535 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 536 }; 537 538 struct cpl_tx_pkt_lso { 539 WR_HDR; 540 struct cpl_tx_pkt_lso_core c; 541 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 542 }; 543 544 struct cpl_iscsi_hdr { 545 union opcode_tid ot; 546 __be16 pdu_len_ddp; 547 #define ISCSI_PDU_LEN(x) ((x) & 0x7FFF) 548 #define ISCSI_DDP (1 << 15) 549 __be16 len; 550 __be32 seq; 551 __be16 urg; 552 u8 rsvd; 553 u8 status; 554 }; 555 556 struct cpl_rx_data { 557 union opcode_tid ot; 558 __be16 rsvd; 559 __be16 len; 560 __be32 seq; 561 __be16 urg; 562 #if defined(__LITTLE_ENDIAN_BITFIELD) 563 u8 dack_mode:2; 564 u8 psh:1; 565 u8 heartbeat:1; 566 u8 ddp_off:1; 567 u8 :3; 568 #else 569 u8 :3; 570 u8 ddp_off:1; 571 u8 heartbeat:1; 572 u8 psh:1; 573 u8 dack_mode:2; 574 #endif 575 u8 status; 576 }; 577 578 struct cpl_rx_data_ack { 579 WR_HDR; 580 union opcode_tid ot; 581 __be32 credit_dack; 582 #define RX_CREDITS(x) ((x) << 0) 583 #define RX_FORCE_ACK(x) ((x) << 28) 584 }; 585 586 struct cpl_rx_pkt { 587 struct rss_header rsshdr; 588 u8 opcode; 589 #if defined(__LITTLE_ENDIAN_BITFIELD) 590 u8 iff:4; 591 u8 csum_calc:1; 592 u8 ipmi_pkt:1; 593 u8 vlan_ex:1; 594 u8 ip_frag:1; 595 #else 596 u8 ip_frag:1; 597 u8 vlan_ex:1; 598 u8 ipmi_pkt:1; 599 u8 csum_calc:1; 600 u8 iff:4; 601 #endif 602 __be16 csum; 603 __be16 vlan; 604 __be16 len; 605 __be32 l2info; 606 #define RXF_UDP (1 << 22) 607 #define RXF_TCP (1 << 23) 608 #define RXF_IP (1 << 24) 609 #define RXF_IP6 (1 << 25) 610 __be16 hdr_len; 611 __be16 err_vec; 612 }; 613 614 /* rx_pkt.l2info fields */ 615 #define S_RX_ETHHDR_LEN 0 616 #define M_RX_ETHHDR_LEN 0x1F 617 #define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN) 618 #define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN) 619 620 #define S_RX_T5_ETHHDR_LEN 0 621 #define M_RX_T5_ETHHDR_LEN 0x3F 622 #define V_RX_T5_ETHHDR_LEN(x) ((x) << S_RX_T5_ETHHDR_LEN) 623 #define G_RX_T5_ETHHDR_LEN(x) (((x) >> S_RX_T5_ETHHDR_LEN) & M_RX_T5_ETHHDR_LEN) 624 625 #define S_RX_MACIDX 8 626 #define M_RX_MACIDX 0x1FF 627 #define V_RX_MACIDX(x) ((x) << S_RX_MACIDX) 628 #define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX) 629 630 #define S_RXF_SYN 21 631 #define V_RXF_SYN(x) ((x) << S_RXF_SYN) 632 #define F_RXF_SYN V_RXF_SYN(1U) 633 634 #define S_RX_CHAN 28 635 #define M_RX_CHAN 0xF 636 #define V_RX_CHAN(x) ((x) << S_RX_CHAN) 637 #define G_RX_CHAN(x) (((x) >> S_RX_CHAN) & M_RX_CHAN) 638 639 /* rx_pkt.hdr_len fields */ 640 #define S_RX_TCPHDR_LEN 0 641 #define M_RX_TCPHDR_LEN 0x3F 642 #define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN) 643 #define G_RX_TCPHDR_LEN(x) (((x) >> S_RX_TCPHDR_LEN) & M_RX_TCPHDR_LEN) 644 645 #define S_RX_IPHDR_LEN 6 646 #define M_RX_IPHDR_LEN 0x3FF 647 #define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN) 648 #define G_RX_IPHDR_LEN(x) (((x) >> S_RX_IPHDR_LEN) & M_RX_IPHDR_LEN) 649 650 struct cpl_trace_pkt { 651 u8 opcode; 652 u8 intf; 653 #if defined(__LITTLE_ENDIAN_BITFIELD) 654 u8 runt:4; 655 u8 filter_hit:4; 656 u8 :6; 657 u8 err:1; 658 u8 trunc:1; 659 #else 660 u8 filter_hit:4; 661 u8 runt:4; 662 u8 trunc:1; 663 u8 err:1; 664 u8 :6; 665 #endif 666 __be16 rsvd; 667 __be16 len; 668 __be64 tstamp; 669 }; 670 671 struct cpl_t5_trace_pkt { 672 __u8 opcode; 673 __u8 intf; 674 #if defined(__LITTLE_ENDIAN_BITFIELD) 675 __u8 runt:4; 676 __u8 filter_hit:4; 677 __u8:6; 678 __u8 err:1; 679 __u8 trunc:1; 680 #else 681 __u8 filter_hit:4; 682 __u8 runt:4; 683 __u8 trunc:1; 684 __u8 err:1; 685 __u8:6; 686 #endif 687 __be16 rsvd; 688 __be16 len; 689 __be64 tstamp; 690 __be64 rsvd1; 691 }; 692 693 struct cpl_l2t_write_req { 694 WR_HDR; 695 union opcode_tid ot; 696 __be16 params; 697 #define L2T_W_INFO(x) ((x) << 2) 698 #define L2T_W_PORT(x) ((x) << 8) 699 #define L2T_W_NOREPLY(x) ((x) << 15) 700 __be16 l2t_idx; 701 __be16 vlan; 702 u8 dst_mac[6]; 703 }; 704 705 struct cpl_l2t_write_rpl { 706 union opcode_tid ot; 707 u8 status; 708 u8 rsvd[3]; 709 }; 710 711 struct cpl_rdma_terminate { 712 union opcode_tid ot; 713 __be16 rsvd; 714 __be16 len; 715 }; 716 717 struct cpl_sge_egr_update { 718 __be32 opcode_qid; 719 #define EGR_QID(x) ((x) & 0x1FFFF) 720 __be16 cidx; 721 __be16 pidx; 722 }; 723 724 /* cpl_fw*.type values */ 725 enum { 726 FW_TYPE_CMD_RPL = 0, 727 FW_TYPE_WR_RPL = 1, 728 FW_TYPE_CQE = 2, 729 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3, 730 FW_TYPE_RSSCPL = 4, 731 }; 732 733 struct cpl_fw4_pld { 734 u8 opcode; 735 u8 rsvd0[3]; 736 u8 type; 737 u8 rsvd1; 738 __be16 len; 739 __be64 data; 740 __be64 rsvd2; 741 }; 742 743 struct cpl_fw6_pld { 744 u8 opcode; 745 u8 rsvd[5]; 746 __be16 len; 747 __be64 data[4]; 748 }; 749 750 struct cpl_fw4_msg { 751 u8 opcode; 752 u8 type; 753 __be16 rsvd0; 754 __be32 rsvd1; 755 __be64 data[2]; 756 }; 757 758 struct cpl_fw4_ack { 759 union opcode_tid ot; 760 u8 credits; 761 u8 rsvd0[2]; 762 u8 seq_vld; 763 __be32 snd_nxt; 764 __be32 snd_una; 765 __be64 rsvd1; 766 }; 767 768 struct cpl_fw6_msg { 769 u8 opcode; 770 u8 type; 771 __be16 rsvd0; 772 __be32 rsvd1; 773 __be64 data[4]; 774 }; 775 776 /* cpl_fw6_msg.type values */ 777 enum { 778 FW6_TYPE_CMD_RPL = 0, 779 FW6_TYPE_WR_RPL = 1, 780 FW6_TYPE_CQE = 2, 781 FW6_TYPE_OFLD_CONNECTION_WR_RPL = 3, 782 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL, 783 }; 784 785 struct cpl_fw6_msg_ofld_connection_wr_rpl { 786 __u64 cookie; 787 __be32 tid; /* or atid in case of active failure */ 788 __u8 t_state; 789 __u8 retval; 790 __u8 rsvd[2]; 791 }; 792 793 enum { 794 ULP_TX_MEM_READ = 2, 795 ULP_TX_MEM_WRITE = 3, 796 ULP_TX_PKT = 4 797 }; 798 799 enum { 800 ULP_TX_SC_NOOP = 0x80, 801 ULP_TX_SC_IMM = 0x81, 802 ULP_TX_SC_DSGL = 0x82, 803 ULP_TX_SC_ISGL = 0x83 804 }; 805 806 struct ulptx_sge_pair { 807 __be32 len[2]; 808 __be64 addr[2]; 809 }; 810 811 struct ulptx_sgl { 812 __be32 cmd_nsge; 813 #define ULPTX_CMD(x) ((x) << 24) 814 #define ULPTX_NSGE(x) ((x) << 0) 815 #define ULPTX_MORE (1U << 23) 816 __be32 len0; 817 __be64 addr0; 818 struct ulptx_sge_pair sge[0]; 819 }; 820 821 struct ulp_mem_io { 822 WR_HDR; 823 __be32 cmd; 824 #define ULP_MEMIO_ORDER(x) ((x) << 23) 825 __be32 len16; /* command length */ 826 __be32 dlen; /* data length in 32-byte units */ 827 #define ULP_MEMIO_DATA_LEN(x) ((x) << 0) 828 __be32 lock_addr; 829 #define ULP_MEMIO_ADDR(x) ((x) << 0) 830 #define ULP_MEMIO_LOCK(x) ((x) << 31) 831 }; 832 833 #define S_T5_ULP_MEMIO_IMM 23 834 #define V_T5_ULP_MEMIO_IMM(x) ((x) << S_T5_ULP_MEMIO_IMM) 835 #define F_T5_ULP_MEMIO_IMM V_T5_ULP_MEMIO_IMM(1U) 836 837 #define S_T5_ULP_MEMIO_ORDER 22 838 #define V_T5_ULP_MEMIO_ORDER(x) ((x) << S_T5_ULP_MEMIO_ORDER) 839 #define F_T5_ULP_MEMIO_ORDER V_T5_ULP_MEMIO_ORDER(1U) 840 841 #endif /* __T4_MSG_H */ 842