1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __T4_HW_H 36 #define __T4_HW_H 37 38 #include <linux/types.h> 39 40 enum { 41 NCHAN = 4, /* # of HW channels */ 42 MAX_MTU = 9600, /* max MAC MTU, excluding header + FCS */ 43 EEPROMSIZE = 17408, /* Serial EEPROM physical size */ 44 EEPROMVSIZE = 32768, /* Serial EEPROM virtual address space size */ 45 EEPROMPFSIZE = 1024, /* EEPROM writable area size for PFn, n>0 */ 46 RSS_NENTRIES = 2048, /* # of entries in RSS mapping table */ 47 TCB_SIZE = 128, /* TCB size */ 48 NMTUS = 16, /* size of MTU table */ 49 NCCTRL_WIN = 32, /* # of congestion control windows */ 50 NTX_SCHED = 8, /* # of HW Tx scheduling queues */ 51 PM_NSTATS = 5, /* # of PM stats */ 52 T6_PM_NSTATS = 7, /* # of PM stats in T6 */ 53 MBOX_LEN = 64, /* mailbox size in bytes */ 54 TRACE_LEN = 112, /* length of trace data and mask */ 55 FILTER_OPT_LEN = 36, /* filter tuple width for optional components */ 56 }; 57 58 enum { 59 CIM_NUM_IBQ = 6, /* # of CIM IBQs */ 60 CIM_NUM_OBQ = 6, /* # of CIM OBQs */ 61 CIM_NUM_OBQ_T5 = 8, /* # of CIM OBQs for T5 adapter */ 62 CIMLA_SIZE = 2048, /* # of 32-bit words in CIM LA */ 63 CIM_PIFLA_SIZE = 64, /* # of 192-bit words in CIM PIF LA */ 64 CIM_MALA_SIZE = 64, /* # of 160-bit words in CIM MA LA */ 65 CIM_IBQ_SIZE = 128, /* # of 128-bit words in a CIM IBQ */ 66 CIM_OBQ_SIZE = 128, /* # of 128-bit words in a CIM OBQ */ 67 TPLA_SIZE = 128, /* # of 64-bit words in TP LA */ 68 ULPRX_LA_SIZE = 512, /* # of 256-bit words in ULP_RX LA */ 69 }; 70 71 /* SGE context types */ 72 enum ctxt_type { 73 CTXT_FLM = 2, 74 CTXT_CNM, 75 }; 76 77 enum { 78 SF_PAGE_SIZE = 256, /* serial flash page size */ 79 SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */ 80 }; 81 82 enum { RSP_TYPE_FLBUF, RSP_TYPE_CPL, RSP_TYPE_INTR }; /* response entry types */ 83 84 enum { MBOX_OWNER_NONE, MBOX_OWNER_FW, MBOX_OWNER_DRV }; /* mailbox owners */ 85 86 enum { 87 SGE_MAX_WR_LEN = 512, /* max WR size in bytes */ 88 SGE_CTXT_SIZE = 24, /* size of SGE context */ 89 SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */ 90 SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */ 91 SGE_MAX_IQ_SIZE = 65520, 92 93 SGE_TIMER_RSTRT_CNTR = 6, /* restart RX packet threshold counter */ 94 SGE_TIMER_UPD_CIDX = 7, /* update cidx only */ 95 96 SGE_EQ_IDXSIZE = 64, /* egress queue pidx/cidx unit size */ 97 98 SGE_INTRDST_PCI = 0, /* interrupt destination is PCI-E */ 99 SGE_INTRDST_IQ = 1, /* destination is an ingress queue */ 100 101 SGE_UPDATEDEL_NONE = 0, /* ingress queue pidx update delivery */ 102 SGE_UPDATEDEL_INTR = 1, /* interrupt */ 103 SGE_UPDATEDEL_STPG = 2, /* status page */ 104 SGE_UPDATEDEL_BOTH = 3, /* interrupt and status page */ 105 106 SGE_HOSTFCMODE_NONE = 0, /* egress queue cidx updates */ 107 SGE_HOSTFCMODE_IQ = 1, /* sent to ingress queue */ 108 SGE_HOSTFCMODE_STPG = 2, /* sent to status page */ 109 SGE_HOSTFCMODE_BOTH = 3, /* ingress queue and status page */ 110 111 SGE_FETCHBURSTMIN_16B = 0,/* egress queue descriptor fetch minimum */ 112 SGE_FETCHBURSTMIN_32B = 1, 113 SGE_FETCHBURSTMIN_64B = 2, 114 SGE_FETCHBURSTMIN_128B = 3, 115 116 SGE_FETCHBURSTMAX_64B = 0,/* egress queue descriptor fetch maximum */ 117 SGE_FETCHBURSTMAX_128B = 1, 118 SGE_FETCHBURSTMAX_256B = 2, 119 SGE_FETCHBURSTMAX_512B = 3, 120 121 SGE_CIDXFLUSHTHRESH_1 = 0,/* egress queue cidx flush threshold */ 122 SGE_CIDXFLUSHTHRESH_2 = 1, 123 SGE_CIDXFLUSHTHRESH_4 = 2, 124 SGE_CIDXFLUSHTHRESH_8 = 3, 125 SGE_CIDXFLUSHTHRESH_16 = 4, 126 SGE_CIDXFLUSHTHRESH_32 = 5, 127 SGE_CIDXFLUSHTHRESH_64 = 6, 128 SGE_CIDXFLUSHTHRESH_128 = 7, 129 130 SGE_INGPADBOUNDARY_SHIFT = 5,/* ingress queue pad boundary */ 131 }; 132 133 /* PCI-e memory window access */ 134 enum pcie_memwin { 135 MEMWIN_NIC = 0, 136 MEMWIN_RSVD1 = 1, 137 MEMWIN_RSVD2 = 2, 138 MEMWIN_RDMA = 3, 139 MEMWIN_RSVD4 = 4, 140 MEMWIN_FOISCSI = 5, 141 MEMWIN_CSIOSTOR = 6, 142 MEMWIN_RSVD7 = 7, 143 }; 144 145 struct sge_qstat { /* data written to SGE queue status entries */ 146 __be32 qid; 147 __be16 cidx; 148 __be16 pidx; 149 }; 150 151 /* 152 * Structure for last 128 bits of response descriptors 153 */ 154 struct rsp_ctrl { 155 __be32 hdrbuflen_pidx; 156 __be32 pldbuflen_qid; 157 union { 158 u8 type_gen; 159 __be64 last_flit; 160 }; 161 }; 162 163 #define RSPD_NEWBUF_S 31 164 #define RSPD_NEWBUF_V(x) ((x) << RSPD_NEWBUF_S) 165 #define RSPD_NEWBUF_F RSPD_NEWBUF_V(1U) 166 167 #define RSPD_LEN_S 0 168 #define RSPD_LEN_M 0x7fffffff 169 #define RSPD_LEN_G(x) (((x) >> RSPD_LEN_S) & RSPD_LEN_M) 170 171 #define RSPD_QID_S RSPD_LEN_S 172 #define RSPD_QID_M RSPD_LEN_M 173 #define RSPD_QID_G(x) RSPD_LEN_G(x) 174 175 #define RSPD_GEN_S 7 176 177 #define RSPD_TYPE_S 4 178 #define RSPD_TYPE_M 0x3 179 #define RSPD_TYPE_G(x) (((x) >> RSPD_TYPE_S) & RSPD_TYPE_M) 180 181 /* Rx queue interrupt deferral fields: counter enable and timer index */ 182 #define QINTR_CNT_EN_S 0 183 #define QINTR_CNT_EN_V(x) ((x) << QINTR_CNT_EN_S) 184 #define QINTR_CNT_EN_F QINTR_CNT_EN_V(1U) 185 186 #define QINTR_TIMER_IDX_S 1 187 #define QINTR_TIMER_IDX_M 0x7 188 #define QINTR_TIMER_IDX_V(x) ((x) << QINTR_TIMER_IDX_S) 189 #define QINTR_TIMER_IDX_G(x) (((x) >> QINTR_TIMER_IDX_S) & QINTR_TIMER_IDX_M) 190 191 /* 192 * Flash layout. 193 */ 194 #define FLASH_START(start) ((start) * SF_SEC_SIZE) 195 #define FLASH_MAX_SIZE(nsecs) ((nsecs) * SF_SEC_SIZE) 196 197 enum { 198 /* 199 * Various Expansion-ROM boot images, etc. 200 */ 201 FLASH_EXP_ROM_START_SEC = 0, 202 FLASH_EXP_ROM_NSECS = 6, 203 FLASH_EXP_ROM_START = FLASH_START(FLASH_EXP_ROM_START_SEC), 204 FLASH_EXP_ROM_MAX_SIZE = FLASH_MAX_SIZE(FLASH_EXP_ROM_NSECS), 205 206 /* 207 * iSCSI Boot Firmware Table (iBFT) and other driver-related 208 * parameters ... 209 */ 210 FLASH_IBFT_START_SEC = 6, 211 FLASH_IBFT_NSECS = 1, 212 FLASH_IBFT_START = FLASH_START(FLASH_IBFT_START_SEC), 213 FLASH_IBFT_MAX_SIZE = FLASH_MAX_SIZE(FLASH_IBFT_NSECS), 214 215 /* 216 * Boot configuration data. 217 */ 218 FLASH_BOOTCFG_START_SEC = 7, 219 FLASH_BOOTCFG_NSECS = 1, 220 FLASH_BOOTCFG_START = FLASH_START(FLASH_BOOTCFG_START_SEC), 221 FLASH_BOOTCFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_BOOTCFG_NSECS), 222 223 /* 224 * Location of firmware image in FLASH. 225 */ 226 FLASH_FW_START_SEC = 8, 227 FLASH_FW_NSECS = 16, 228 FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC), 229 FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS), 230 231 /* Location of bootstrap firmware image in FLASH. 232 */ 233 FLASH_FWBOOTSTRAP_START_SEC = 27, 234 FLASH_FWBOOTSTRAP_NSECS = 1, 235 FLASH_FWBOOTSTRAP_START = FLASH_START(FLASH_FWBOOTSTRAP_START_SEC), 236 FLASH_FWBOOTSTRAP_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FWBOOTSTRAP_NSECS), 237 238 /* 239 * iSCSI persistent/crash information. 240 */ 241 FLASH_ISCSI_CRASH_START_SEC = 29, 242 FLASH_ISCSI_CRASH_NSECS = 1, 243 FLASH_ISCSI_CRASH_START = FLASH_START(FLASH_ISCSI_CRASH_START_SEC), 244 FLASH_ISCSI_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_ISCSI_CRASH_NSECS), 245 246 /* 247 * FCoE persistent/crash information. 248 */ 249 FLASH_FCOE_CRASH_START_SEC = 30, 250 FLASH_FCOE_CRASH_NSECS = 1, 251 FLASH_FCOE_CRASH_START = FLASH_START(FLASH_FCOE_CRASH_START_SEC), 252 FLASH_FCOE_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FCOE_CRASH_NSECS), 253 254 /* 255 * Location of Firmware Configuration File in FLASH. Since the FPGA 256 * "FLASH" is smaller we need to store the Configuration File in a 257 * different location -- which will overlap the end of the firmware 258 * image if firmware ever gets that large ... 259 */ 260 FLASH_CFG_START_SEC = 31, 261 FLASH_CFG_NSECS = 1, 262 FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC), 263 FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS), 264 265 /* We don't support FLASH devices which can't support the full 266 * standard set of sections which we need for normal 267 * operations. 268 */ 269 FLASH_MIN_SIZE = FLASH_CFG_START + FLASH_CFG_MAX_SIZE, 270 271 FLASH_FPGA_CFG_START_SEC = 15, 272 FLASH_FPGA_CFG_START = FLASH_START(FLASH_FPGA_CFG_START_SEC), 273 274 /* 275 * Sectors 32-63 are reserved for FLASH failover. 276 */ 277 }; 278 279 #undef FLASH_START 280 #undef FLASH_MAX_SIZE 281 282 #define SGE_TIMESTAMP_S 0 283 #define SGE_TIMESTAMP_M 0xfffffffffffffffULL 284 #define SGE_TIMESTAMP_V(x) ((__u64)(x) << SGE_TIMESTAMP_S) 285 #define SGE_TIMESTAMP_G(x) (((__u64)(x) >> SGE_TIMESTAMP_S) & SGE_TIMESTAMP_M) 286 287 #endif /* __T4_HW_H */ 288